mbed library sources modified for open wear
Dependents: openwear-lifelogger-example
Fork of mbed-src by
targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_rcc_ex.h@310:6188e0254baa, 2014-09-16 (annotated)
- Committer:
- janekm
- Date:
- Tue Sep 16 22:42:01 2014 +0000
- Revision:
- 310:6188e0254baa
- Parent:
- 181:a4cbdfbbd2f4
N/A
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
mbed_official | 181:a4cbdfbbd2f4 | 1 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 2 | ****************************************************************************** |
mbed_official | 181:a4cbdfbbd2f4 | 3 | * @file stm32l0xx_hal_rcc_ex.h |
mbed_official | 181:a4cbdfbbd2f4 | 4 | * @author MCD Application Team |
mbed_official | 181:a4cbdfbbd2f4 | 5 | * @version V1.0.0 |
mbed_official | 181:a4cbdfbbd2f4 | 6 | * @date 22-April-2014 |
mbed_official | 181:a4cbdfbbd2f4 | 7 | * @brief Header file of RCC HAL Extension module. |
mbed_official | 181:a4cbdfbbd2f4 | 8 | ****************************************************************************** |
mbed_official | 181:a4cbdfbbd2f4 | 9 | * @attention |
mbed_official | 181:a4cbdfbbd2f4 | 10 | * |
mbed_official | 181:a4cbdfbbd2f4 | 11 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
mbed_official | 181:a4cbdfbbd2f4 | 12 | * |
mbed_official | 181:a4cbdfbbd2f4 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
mbed_official | 181:a4cbdfbbd2f4 | 14 | * are permitted provided that the following conditions are met: |
mbed_official | 181:a4cbdfbbd2f4 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
mbed_official | 181:a4cbdfbbd2f4 | 16 | * this list of conditions and the following disclaimer. |
mbed_official | 181:a4cbdfbbd2f4 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
mbed_official | 181:a4cbdfbbd2f4 | 18 | * this list of conditions and the following disclaimer in the documentation |
mbed_official | 181:a4cbdfbbd2f4 | 19 | * and/or other materials provided with the distribution. |
mbed_official | 181:a4cbdfbbd2f4 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
mbed_official | 181:a4cbdfbbd2f4 | 21 | * may be used to endorse or promote products derived from this software |
mbed_official | 181:a4cbdfbbd2f4 | 22 | * without specific prior written permission. |
mbed_official | 181:a4cbdfbbd2f4 | 23 | * |
mbed_official | 181:a4cbdfbbd2f4 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
mbed_official | 181:a4cbdfbbd2f4 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
mbed_official | 181:a4cbdfbbd2f4 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
mbed_official | 181:a4cbdfbbd2f4 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
mbed_official | 181:a4cbdfbbd2f4 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
mbed_official | 181:a4cbdfbbd2f4 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
mbed_official | 181:a4cbdfbbd2f4 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
mbed_official | 181:a4cbdfbbd2f4 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
mbed_official | 181:a4cbdfbbd2f4 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
mbed_official | 181:a4cbdfbbd2f4 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
mbed_official | 181:a4cbdfbbd2f4 | 34 | * |
mbed_official | 181:a4cbdfbbd2f4 | 35 | ****************************************************************************** |
mbed_official | 181:a4cbdfbbd2f4 | 36 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 37 | |
mbed_official | 181:a4cbdfbbd2f4 | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
mbed_official | 181:a4cbdfbbd2f4 | 39 | #ifndef __STM32L0xx_HAL_RCC_EX_H |
mbed_official | 181:a4cbdfbbd2f4 | 40 | #define __STM32L0xx_HAL_RCC_EX_H |
mbed_official | 181:a4cbdfbbd2f4 | 41 | |
mbed_official | 181:a4cbdfbbd2f4 | 42 | #ifdef __cplusplus |
mbed_official | 181:a4cbdfbbd2f4 | 43 | extern "C" { |
mbed_official | 181:a4cbdfbbd2f4 | 44 | #endif |
mbed_official | 181:a4cbdfbbd2f4 | 45 | |
mbed_official | 181:a4cbdfbbd2f4 | 46 | /* Includes ------------------------------------------------------------------*/ |
mbed_official | 181:a4cbdfbbd2f4 | 47 | #include "stm32l0xx_hal_def.h" |
mbed_official | 181:a4cbdfbbd2f4 | 48 | |
mbed_official | 181:a4cbdfbbd2f4 | 49 | /** @addtogroup STM32L0xx_HAL_Driver |
mbed_official | 181:a4cbdfbbd2f4 | 50 | * @{ |
mbed_official | 181:a4cbdfbbd2f4 | 51 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 52 | |
mbed_official | 181:a4cbdfbbd2f4 | 53 | /** @addtogroup RCCEx |
mbed_official | 181:a4cbdfbbd2f4 | 54 | * @{ |
mbed_official | 181:a4cbdfbbd2f4 | 55 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 56 | |
mbed_official | 181:a4cbdfbbd2f4 | 57 | /* Exported types ------------------------------------------------------------*/ |
mbed_official | 181:a4cbdfbbd2f4 | 58 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 59 | * @brief RCC extended clocks structure definition |
mbed_official | 181:a4cbdfbbd2f4 | 60 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 61 | #if !defined(STM32L051xx) && !defined(STM32L061xx) |
mbed_official | 181:a4cbdfbbd2f4 | 62 | typedef struct |
mbed_official | 181:a4cbdfbbd2f4 | 63 | { |
mbed_official | 181:a4cbdfbbd2f4 | 64 | uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. |
mbed_official | 181:a4cbdfbbd2f4 | 65 | This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ |
mbed_official | 181:a4cbdfbbd2f4 | 66 | uint32_t Usart1ClockSelection; /*!< USART1 clock source |
mbed_official | 181:a4cbdfbbd2f4 | 67 | This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ |
mbed_official | 181:a4cbdfbbd2f4 | 68 | |
mbed_official | 181:a4cbdfbbd2f4 | 69 | uint32_t Usart2ClockSelection; /*!< USART2 clock source |
mbed_official | 181:a4cbdfbbd2f4 | 70 | This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ |
mbed_official | 181:a4cbdfbbd2f4 | 71 | |
mbed_official | 181:a4cbdfbbd2f4 | 72 | uint32_t Lpuart1ClockSelection; /*!< LPUART1 clock source |
mbed_official | 181:a4cbdfbbd2f4 | 73 | This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */ |
mbed_official | 181:a4cbdfbbd2f4 | 74 | |
mbed_official | 181:a4cbdfbbd2f4 | 75 | uint32_t I2c1ClockSelection; /*!< I2C1 clock source |
mbed_official | 181:a4cbdfbbd2f4 | 76 | This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ |
mbed_official | 181:a4cbdfbbd2f4 | 77 | |
mbed_official | 181:a4cbdfbbd2f4 | 78 | uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection |
mbed_official | 181:a4cbdfbbd2f4 | 79 | This parameter can be a value of @ref RCCEx_RTC_Clock_Source */ |
mbed_official | 181:a4cbdfbbd2f4 | 80 | |
mbed_official | 181:a4cbdfbbd2f4 | 81 | uint32_t UsbClockSelection; /*!< Specifies USB and RNG Clock Selection |
mbed_official | 181:a4cbdfbbd2f4 | 82 | This parameter can be a value of @ref RCCEx_USB_Clock_Source */ |
mbed_official | 181:a4cbdfbbd2f4 | 83 | |
mbed_official | 181:a4cbdfbbd2f4 | 84 | uint32_t LptimClockSelection; /*!< LPTIM1 clock source |
mbed_official | 181:a4cbdfbbd2f4 | 85 | This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ |
mbed_official | 181:a4cbdfbbd2f4 | 86 | |
mbed_official | 181:a4cbdfbbd2f4 | 87 | }RCC_PeriphCLKInitTypeDef; |
mbed_official | 181:a4cbdfbbd2f4 | 88 | #endif /* !(STM32L051xx) && !(STM32L061xx) */ |
mbed_official | 181:a4cbdfbbd2f4 | 89 | |
mbed_official | 181:a4cbdfbbd2f4 | 90 | #if defined(STM32L051xx) || defined(STM32L061xx) |
mbed_official | 181:a4cbdfbbd2f4 | 91 | typedef struct |
mbed_official | 181:a4cbdfbbd2f4 | 92 | { |
mbed_official | 181:a4cbdfbbd2f4 | 93 | uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. |
mbed_official | 181:a4cbdfbbd2f4 | 94 | This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ |
mbed_official | 181:a4cbdfbbd2f4 | 95 | uint32_t Usart1ClockSelection; /*!< USART1 clock source |
mbed_official | 181:a4cbdfbbd2f4 | 96 | This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ |
mbed_official | 181:a4cbdfbbd2f4 | 97 | |
mbed_official | 181:a4cbdfbbd2f4 | 98 | uint32_t Usart2ClockSelection; /*!< USART2 clock source |
mbed_official | 181:a4cbdfbbd2f4 | 99 | This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ |
mbed_official | 181:a4cbdfbbd2f4 | 100 | |
mbed_official | 181:a4cbdfbbd2f4 | 101 | uint32_t Lpuart1ClockSelection; /*!< LPUART1 clock source |
mbed_official | 181:a4cbdfbbd2f4 | 102 | This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */ |
mbed_official | 181:a4cbdfbbd2f4 | 103 | |
mbed_official | 181:a4cbdfbbd2f4 | 104 | uint32_t I2c1ClockSelection; /*!< I2C1 clock source |
mbed_official | 181:a4cbdfbbd2f4 | 105 | This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ |
mbed_official | 181:a4cbdfbbd2f4 | 106 | |
mbed_official | 181:a4cbdfbbd2f4 | 107 | uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection |
mbed_official | 181:a4cbdfbbd2f4 | 108 | This parameter can be a value of @ref RCCEx_RTC_Clock_Source */ |
mbed_official | 181:a4cbdfbbd2f4 | 109 | |
mbed_official | 181:a4cbdfbbd2f4 | 110 | uint32_t LptimClockSelection; /*!< LPTIM1 clock source |
mbed_official | 181:a4cbdfbbd2f4 | 111 | This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ |
mbed_official | 181:a4cbdfbbd2f4 | 112 | |
mbed_official | 181:a4cbdfbbd2f4 | 113 | }RCC_PeriphCLKInitTypeDef; |
mbed_official | 181:a4cbdfbbd2f4 | 114 | #endif /* STM32L051xx || STM32L061xx */ |
mbed_official | 181:a4cbdfbbd2f4 | 115 | |
mbed_official | 181:a4cbdfbbd2f4 | 116 | #if !defined(STM32L051xx) && !defined(STM32L061xx) |
mbed_official | 181:a4cbdfbbd2f4 | 117 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 118 | * @brief RCC CRS Status structures definition |
mbed_official | 181:a4cbdfbbd2f4 | 119 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 120 | typedef enum |
mbed_official | 181:a4cbdfbbd2f4 | 121 | { |
mbed_official | 181:a4cbdfbbd2f4 | 122 | RCC_CRS_NONE = 0x00, |
mbed_official | 181:a4cbdfbbd2f4 | 123 | RCC_CRS_TIMEOUT = 0x01, |
mbed_official | 181:a4cbdfbbd2f4 | 124 | RCC_CRS_SYNCOK = 0x02, |
mbed_official | 181:a4cbdfbbd2f4 | 125 | RCC_CRS_SYNCWARM = 0x04, |
mbed_official | 181:a4cbdfbbd2f4 | 126 | RCC_CRS_SYNCERR = 0x08, |
mbed_official | 181:a4cbdfbbd2f4 | 127 | RCC_CRS_SYNCMISS = 0x10, |
mbed_official | 181:a4cbdfbbd2f4 | 128 | RCC_CRS_TRIMOV = 0x20 |
mbed_official | 181:a4cbdfbbd2f4 | 129 | } RCC_CRSStatusTypeDef; |
mbed_official | 181:a4cbdfbbd2f4 | 130 | |
mbed_official | 181:a4cbdfbbd2f4 | 131 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 132 | * @brief RCC_CRS Init structure definition |
mbed_official | 181:a4cbdfbbd2f4 | 133 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 134 | typedef struct |
mbed_official | 181:a4cbdfbbd2f4 | 135 | { |
mbed_official | 181:a4cbdfbbd2f4 | 136 | uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal. |
mbed_official | 181:a4cbdfbbd2f4 | 137 | This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */ |
mbed_official | 181:a4cbdfbbd2f4 | 138 | |
mbed_official | 181:a4cbdfbbd2f4 | 139 | uint32_t Source; /*!< Specifies the SYNC signal source. |
mbed_official | 181:a4cbdfbbd2f4 | 140 | This parameter can be a value of @ref RCCEx_CRS_SynchroSource */ |
mbed_official | 181:a4cbdfbbd2f4 | 141 | |
mbed_official | 181:a4cbdfbbd2f4 | 142 | uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source. |
mbed_official | 181:a4cbdfbbd2f4 | 143 | This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */ |
mbed_official | 181:a4cbdfbbd2f4 | 144 | |
mbed_official | 181:a4cbdfbbd2f4 | 145 | uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event. |
mbed_official | 181:a4cbdfbbd2f4 | 146 | It can be calculated in using macro __HAL_RCC_CRS_CALCULATE_RELOADVALUE(_FTARGET_, _FSYNC_) |
mbed_official | 181:a4cbdfbbd2f4 | 147 | This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/ |
mbed_official | 181:a4cbdfbbd2f4 | 148 | |
mbed_official | 181:a4cbdfbbd2f4 | 149 | uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value. |
mbed_official | 181:a4cbdfbbd2f4 | 150 | This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */ |
mbed_official | 181:a4cbdfbbd2f4 | 151 | |
mbed_official | 181:a4cbdfbbd2f4 | 152 | uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator. |
mbed_official | 181:a4cbdfbbd2f4 | 153 | This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */ |
mbed_official | 181:a4cbdfbbd2f4 | 154 | |
mbed_official | 181:a4cbdfbbd2f4 | 155 | }RCC_CRSInitTypeDef; |
mbed_official | 181:a4cbdfbbd2f4 | 156 | |
mbed_official | 181:a4cbdfbbd2f4 | 157 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 158 | * @brief RCC_CRS Synchronization structure definition |
mbed_official | 181:a4cbdfbbd2f4 | 159 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 160 | typedef struct |
mbed_official | 181:a4cbdfbbd2f4 | 161 | { |
mbed_official | 181:a4cbdfbbd2f4 | 162 | uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value. |
mbed_official | 181:a4cbdfbbd2f4 | 163 | This parameter must be a number between 0 and 0xFFFF*/ |
mbed_official | 181:a4cbdfbbd2f4 | 164 | |
mbed_official | 181:a4cbdfbbd2f4 | 165 | uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming. |
mbed_official | 181:a4cbdfbbd2f4 | 166 | This parameter must be a number between 0 and 0x3F */ |
mbed_official | 181:a4cbdfbbd2f4 | 167 | |
mbed_official | 181:a4cbdfbbd2f4 | 168 | uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter |
mbed_official | 181:a4cbdfbbd2f4 | 169 | value latched in the time of the last SYNC event. |
mbed_official | 181:a4cbdfbbd2f4 | 170 | This parameter must be a number between 0 and 0xFFFF */ |
mbed_official | 181:a4cbdfbbd2f4 | 171 | |
mbed_official | 181:a4cbdfbbd2f4 | 172 | uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the |
mbed_official | 181:a4cbdfbbd2f4 | 173 | frequency error counter latched in the time of the last SYNC event. |
mbed_official | 181:a4cbdfbbd2f4 | 174 | It shows whether the actual frequency is below or above the target. |
mbed_official | 181:a4cbdfbbd2f4 | 175 | This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/ |
mbed_official | 181:a4cbdfbbd2f4 | 176 | |
mbed_official | 181:a4cbdfbbd2f4 | 177 | }RCC_CRSSynchroInfoTypeDef; |
mbed_official | 181:a4cbdfbbd2f4 | 178 | #endif /* !(STM32L051xx ) && !(STM32L061xx ) */ |
mbed_official | 181:a4cbdfbbd2f4 | 179 | |
mbed_official | 181:a4cbdfbbd2f4 | 180 | /* Exported constants --------------------------------------------------------*/ |
mbed_official | 181:a4cbdfbbd2f4 | 181 | /** @defgroup RCCEx_Exported_Constants |
mbed_official | 181:a4cbdfbbd2f4 | 182 | * @{ |
mbed_official | 181:a4cbdfbbd2f4 | 183 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 184 | |
mbed_official | 181:a4cbdfbbd2f4 | 185 | /** @defgroup RCCEx_Periph_Clock_Selection |
mbed_official | 181:a4cbdfbbd2f4 | 186 | * @{ |
mbed_official | 181:a4cbdfbbd2f4 | 187 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 188 | #if !defined(STM32L051xx) && !defined(STM32L061xx) |
mbed_official | 181:a4cbdfbbd2f4 | 189 | #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001) |
mbed_official | 181:a4cbdfbbd2f4 | 190 | #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002) |
mbed_official | 181:a4cbdfbbd2f4 | 191 | #define RCC_PERIPHCLK_LPUART1 ((uint32_t)0x00000004) |
mbed_official | 181:a4cbdfbbd2f4 | 192 | #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000008) |
mbed_official | 181:a4cbdfbbd2f4 | 193 | #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000010) |
mbed_official | 181:a4cbdfbbd2f4 | 194 | #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020) |
mbed_official | 181:a4cbdfbbd2f4 | 195 | #define RCC_PERIPHCLK_USB ((uint32_t)0x00000040) |
mbed_official | 181:a4cbdfbbd2f4 | 196 | #define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000080) |
mbed_official | 181:a4cbdfbbd2f4 | 197 | |
mbed_official | 181:a4cbdfbbd2f4 | 198 | |
mbed_official | 181:a4cbdfbbd2f4 | 199 | #define IS_RCC_PERIPHCLK(CLK) ((CLK) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \ |
mbed_official | 181:a4cbdfbbd2f4 | 200 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \ |
mbed_official | 181:a4cbdfbbd2f4 | 201 | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1)) |
mbed_official | 181:a4cbdfbbd2f4 | 202 | #endif /* !(STM32L051xx) && !(STM32L061xx) */ |
mbed_official | 181:a4cbdfbbd2f4 | 203 | |
mbed_official | 181:a4cbdfbbd2f4 | 204 | #if defined(STM32L051xx) || defined(STM32L061xx) |
mbed_official | 181:a4cbdfbbd2f4 | 205 | #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001) |
mbed_official | 181:a4cbdfbbd2f4 | 206 | #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002) |
mbed_official | 181:a4cbdfbbd2f4 | 207 | #define RCC_PERIPHCLK_LPUART1 ((uint32_t)0x00000004) |
mbed_official | 181:a4cbdfbbd2f4 | 208 | #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000008) |
mbed_official | 181:a4cbdfbbd2f4 | 209 | #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000010) |
mbed_official | 181:a4cbdfbbd2f4 | 210 | #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020) |
mbed_official | 181:a4cbdfbbd2f4 | 211 | #define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000080) |
mbed_official | 181:a4cbdfbbd2f4 | 212 | |
mbed_official | 181:a4cbdfbbd2f4 | 213 | |
mbed_official | 181:a4cbdfbbd2f4 | 214 | #define IS_RCC_PERIPHCLK(CLK) ((CLK) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \ |
mbed_official | 181:a4cbdfbbd2f4 | 215 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \ |
mbed_official | 181:a4cbdfbbd2f4 | 216 | RCC_PERIPHCLK_LPTIM1)) |
mbed_official | 181:a4cbdfbbd2f4 | 217 | #endif /* !(STM32L051xx) && !(STM32L061xx) */ |
mbed_official | 181:a4cbdfbbd2f4 | 218 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 219 | * @} |
mbed_official | 181:a4cbdfbbd2f4 | 220 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 221 | |
mbed_official | 181:a4cbdfbbd2f4 | 222 | /** @defgroup RCCEx_USART1_Clock_Source |
mbed_official | 181:a4cbdfbbd2f4 | 223 | * @{ |
mbed_official | 181:a4cbdfbbd2f4 | 224 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 225 | #define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000) |
mbed_official | 181:a4cbdfbbd2f4 | 226 | #define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0 |
mbed_official | 181:a4cbdfbbd2f4 | 227 | #define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1 |
mbed_official | 181:a4cbdfbbd2f4 | 228 | #define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1) |
mbed_official | 181:a4cbdfbbd2f4 | 229 | #define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \ |
mbed_official | 181:a4cbdfbbd2f4 | 230 | ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \ |
mbed_official | 181:a4cbdfbbd2f4 | 231 | ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \ |
mbed_official | 181:a4cbdfbbd2f4 | 232 | ((SOURCE) == RCC_USART1CLKSOURCE_HSI)) |
mbed_official | 181:a4cbdfbbd2f4 | 233 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 234 | * @} |
mbed_official | 181:a4cbdfbbd2f4 | 235 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 236 | |
mbed_official | 181:a4cbdfbbd2f4 | 237 | /** @defgroup RCCEx_USART2_Clock_Source |
mbed_official | 181:a4cbdfbbd2f4 | 238 | * @{ |
mbed_official | 181:a4cbdfbbd2f4 | 239 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 240 | #define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000) |
mbed_official | 181:a4cbdfbbd2f4 | 241 | #define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0 |
mbed_official | 181:a4cbdfbbd2f4 | 242 | #define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1 |
mbed_official | 181:a4cbdfbbd2f4 | 243 | #define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1) |
mbed_official | 181:a4cbdfbbd2f4 | 244 | #define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) || \ |
mbed_official | 181:a4cbdfbbd2f4 | 245 | ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \ |
mbed_official | 181:a4cbdfbbd2f4 | 246 | ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \ |
mbed_official | 181:a4cbdfbbd2f4 | 247 | ((SOURCE) == RCC_USART2CLKSOURCE_HSI)) |
mbed_official | 181:a4cbdfbbd2f4 | 248 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 249 | * @} |
mbed_official | 181:a4cbdfbbd2f4 | 250 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 251 | |
mbed_official | 181:a4cbdfbbd2f4 | 252 | /** @defgroup RCCEx_LPUART_Clock_Source |
mbed_official | 181:a4cbdfbbd2f4 | 253 | * @{ |
mbed_official | 181:a4cbdfbbd2f4 | 254 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 255 | #define RCC_LPUART1CLKSOURCE_PCLK1 ((uint32_t)0x00000000) |
mbed_official | 181:a4cbdfbbd2f4 | 256 | #define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0 |
mbed_official | 181:a4cbdfbbd2f4 | 257 | #define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 |
mbed_official | 181:a4cbdfbbd2f4 | 258 | #define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1) |
mbed_official | 181:a4cbdfbbd2f4 | 259 | #define IS_RCC_LPUART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPUART1CLKSOURCE_PCLK1) || \ |
mbed_official | 181:a4cbdfbbd2f4 | 260 | ((SOURCE) == RCC_LPUART1CLKSOURCE_SYSCLK) || \ |
mbed_official | 181:a4cbdfbbd2f4 | 261 | ((SOURCE) == RCC_LPUART1CLKSOURCE_LSE) || \ |
mbed_official | 181:a4cbdfbbd2f4 | 262 | ((SOURCE) == RCC_LPUART1CLKSOURCE_HSI)) |
mbed_official | 181:a4cbdfbbd2f4 | 263 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 264 | * @} |
mbed_official | 181:a4cbdfbbd2f4 | 265 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 266 | |
mbed_official | 181:a4cbdfbbd2f4 | 267 | /** @defgroup RCCEx_I2C1_Clock_Source |
mbed_official | 181:a4cbdfbbd2f4 | 268 | * @{ |
mbed_official | 181:a4cbdfbbd2f4 | 269 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 270 | #define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000) |
mbed_official | 181:a4cbdfbbd2f4 | 271 | #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0 |
mbed_official | 181:a4cbdfbbd2f4 | 272 | #define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1 |
mbed_official | 181:a4cbdfbbd2f4 | 273 | #define IS_RCC_I2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C1CLKSOURCE_PCLK1) || \ |
mbed_official | 181:a4cbdfbbd2f4 | 274 | ((SOURCE) == RCC_I2C1CLKSOURCE_SYSCLK)|| \ |
mbed_official | 181:a4cbdfbbd2f4 | 275 | ((SOURCE) == RCC_I2C1CLKSOURCE_HSI)) |
mbed_official | 181:a4cbdfbbd2f4 | 276 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 277 | * @} |
mbed_official | 181:a4cbdfbbd2f4 | 278 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 279 | |
mbed_official | 181:a4cbdfbbd2f4 | 280 | /** @defgroup RCCEx_TIM_PRescaler_Selection |
mbed_official | 181:a4cbdfbbd2f4 | 281 | * @{ |
mbed_official | 181:a4cbdfbbd2f4 | 282 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 283 | #define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00) |
mbed_official | 181:a4cbdfbbd2f4 | 284 | #define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01) |
mbed_official | 181:a4cbdfbbd2f4 | 285 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 286 | * @} |
mbed_official | 181:a4cbdfbbd2f4 | 287 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 288 | |
mbed_official | 181:a4cbdfbbd2f4 | 289 | #if !defined(STM32L051xx) && !defined(STM32L061xx) |
mbed_official | 181:a4cbdfbbd2f4 | 290 | /** @defgroup RCCEx_USB_Clock_Source |
mbed_official | 181:a4cbdfbbd2f4 | 291 | * @{ |
mbed_official | 181:a4cbdfbbd2f4 | 292 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 293 | #define RCC_USBCLKSOURCE_HSI48 RCC_CCIPR_HSI48SEL |
mbed_official | 181:a4cbdfbbd2f4 | 294 | #define RCC_USBCLKSOURCE_PLLCLK ((uint32_t)0x00000000) |
mbed_official | 181:a4cbdfbbd2f4 | 295 | |
mbed_official | 181:a4cbdfbbd2f4 | 296 | #define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_HSI48) || \ |
mbed_official | 181:a4cbdfbbd2f4 | 297 | ((SOURCE) == RCC_USBCLKSOURCE_PLLCLK)) |
mbed_official | 181:a4cbdfbbd2f4 | 298 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 299 | * @} |
mbed_official | 181:a4cbdfbbd2f4 | 300 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 301 | |
mbed_official | 181:a4cbdfbbd2f4 | 302 | /** @defgroup RCCEx_RNG_Clock_Source |
mbed_official | 181:a4cbdfbbd2f4 | 303 | * @{ |
mbed_official | 181:a4cbdfbbd2f4 | 304 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 305 | #define RCC_RNGCLKSOURCE_HSI48 RCC_CCIPR_HSI48SEL |
mbed_official | 181:a4cbdfbbd2f4 | 306 | #define RCC_RNGCLKSOURCE_PLLCLK ((uint32_t)0x00000000) |
mbed_official | 181:a4cbdfbbd2f4 | 307 | |
mbed_official | 181:a4cbdfbbd2f4 | 308 | #define IS_RCC_RNGCLKSOURCE(SOURCE) (((SOURCE) == RCC_RNGCLKSOURCE_HSI48) || \ |
mbed_official | 181:a4cbdfbbd2f4 | 309 | ((SOURCE) == RCC_RNGCLKSOURCE_PLLCLK)) |
mbed_official | 181:a4cbdfbbd2f4 | 310 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 311 | * @} |
mbed_official | 181:a4cbdfbbd2f4 | 312 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 313 | |
mbed_official | 181:a4cbdfbbd2f4 | 314 | /** @defgroup RCCEx_HSI48M_Clock_Source |
mbed_official | 181:a4cbdfbbd2f4 | 315 | * @{ |
mbed_official | 181:a4cbdfbbd2f4 | 316 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 317 | |
mbed_official | 181:a4cbdfbbd2f4 | 318 | #define RCC_HSI48M_PLL ((uint32_t)0x00000000) |
mbed_official | 181:a4cbdfbbd2f4 | 319 | #define RCC_HSI48M_RC48 RCC_CCIPR_HSI48SEL |
mbed_official | 181:a4cbdfbbd2f4 | 320 | |
mbed_official | 181:a4cbdfbbd2f4 | 321 | #define IS_RCC_HSI48MCLKSOURCE(HSI48MCLK) (((HSI48MCLK) == RCC_HSI48M_PLL) || ((HSI48MCLK) == RCC_HSI48M_RC48)) |
mbed_official | 181:a4cbdfbbd2f4 | 322 | |
mbed_official | 181:a4cbdfbbd2f4 | 323 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 324 | * @} |
mbed_official | 181:a4cbdfbbd2f4 | 325 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 326 | #endif /* !(STM32L051xx ) && !(STM32L061xx ) */ |
mbed_official | 181:a4cbdfbbd2f4 | 327 | |
mbed_official | 181:a4cbdfbbd2f4 | 328 | /** @defgroup RCCEx_LPTIM1_Clock_Source |
mbed_official | 181:a4cbdfbbd2f4 | 329 | * @{ |
mbed_official | 181:a4cbdfbbd2f4 | 330 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 331 | #define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000) |
mbed_official | 181:a4cbdfbbd2f4 | 332 | #define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0 |
mbed_official | 181:a4cbdfbbd2f4 | 333 | #define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1 |
mbed_official | 181:a4cbdfbbd2f4 | 334 | #define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL |
mbed_official | 181:a4cbdfbbd2f4 | 335 | |
mbed_official | 181:a4cbdfbbd2f4 | 336 | #define IS_RCC_LPTIMCLK(LPTIMCLK) (((LPTIMCLK) == RCC_LPTIM1CLKSOURCE_PCLK) || \ |
mbed_official | 181:a4cbdfbbd2f4 | 337 | ((LPTIMCLK) == RCC_LPTIM1CLKSOURCE_LSI) || \ |
mbed_official | 181:a4cbdfbbd2f4 | 338 | ((LPTIMCLK) == RCC_LPTIM1CLKSOURCE_HSI) || \ |
mbed_official | 181:a4cbdfbbd2f4 | 339 | ((LPTIMCLK) == RCC_LPTIM1CLKSOURCE_LSE)) |
mbed_official | 181:a4cbdfbbd2f4 | 340 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 341 | * @} |
mbed_official | 181:a4cbdfbbd2f4 | 342 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 343 | |
mbed_official | 181:a4cbdfbbd2f4 | 344 | /** @defgroup RCCEx_StopWakeUp_Clock |
mbed_official | 181:a4cbdfbbd2f4 | 345 | * @{ |
mbed_official | 181:a4cbdfbbd2f4 | 346 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 347 | |
mbed_official | 181:a4cbdfbbd2f4 | 348 | #define RCC_StopWakeUpClock_MSI ((uint32_t)0x00) |
mbed_official | 181:a4cbdfbbd2f4 | 349 | #define RCC_StopWakeUpClock_HSI RCC_CFGR_STOPWUCK |
mbed_official | 181:a4cbdfbbd2f4 | 350 | |
mbed_official | 181:a4cbdfbbd2f4 | 351 | #define IS_RCC_STOPWAKEUP_CLOCK(SOURCE) (((SOURCE) == RCC_StopWakeUpClock_MSI) || \ |
mbed_official | 181:a4cbdfbbd2f4 | 352 | ((SOURCE) == RCC_StopWakeUpClock_HSI)) |
mbed_official | 181:a4cbdfbbd2f4 | 353 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 354 | * @} |
mbed_official | 181:a4cbdfbbd2f4 | 355 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 356 | |
mbed_official | 181:a4cbdfbbd2f4 | 357 | /** @defgroup RCCEx_LSEDrive_Configuration |
mbed_official | 181:a4cbdfbbd2f4 | 358 | * @{ |
mbed_official | 181:a4cbdfbbd2f4 | 359 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 360 | |
mbed_official | 181:a4cbdfbbd2f4 | 361 | #define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000) |
mbed_official | 181:a4cbdfbbd2f4 | 362 | #define RCC_LSEDRIVE_MEDIUMLOW RCC_CSR_LSEDRV_0 |
mbed_official | 181:a4cbdfbbd2f4 | 363 | #define RCC_LSEDRIVE_MEDIUMHIGH RCC_CSR_LSEDRV_1 |
mbed_official | 181:a4cbdfbbd2f4 | 364 | #define RCC_LSEDRIVE_HIGH RCC_CSR_LSEDRV |
mbed_official | 181:a4cbdfbbd2f4 | 365 | #define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDRIVE_LOW) || ((DRIVE) == RCC_LSEDRIVE_MEDIUMLOW) || \ |
mbed_official | 181:a4cbdfbbd2f4 | 366 | ((DRIVE) == RCC_LSEDRIVE_MEDIUMHIGH) || ((DRIVE) == RCC_LSEDRIVE_HIGH)) |
mbed_official | 181:a4cbdfbbd2f4 | 367 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 368 | * @} |
mbed_official | 181:a4cbdfbbd2f4 | 369 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 370 | |
mbed_official | 181:a4cbdfbbd2f4 | 371 | #if !defined(STM32L051xx) && !defined(STM32L061xx) |
mbed_official | 181:a4cbdfbbd2f4 | 372 | /** @defgroup RCCEx_CRS_SynchroSource |
mbed_official | 181:a4cbdfbbd2f4 | 373 | * @{ |
mbed_official | 181:a4cbdfbbd2f4 | 374 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 375 | #define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00) /*!< Synchro Signal source GPIO */ |
mbed_official | 181:a4cbdfbbd2f4 | 376 | #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ |
mbed_official | 181:a4cbdfbbd2f4 | 377 | #define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ |
mbed_official | 181:a4cbdfbbd2f4 | 378 | |
mbed_official | 181:a4cbdfbbd2f4 | 379 | #define IS_RCC_CRS_SYNC_SOURCE(_SOURCE_) (((_SOURCE_) == RCC_CRS_SYNC_SOURCE_GPIO) || \ |
mbed_official | 181:a4cbdfbbd2f4 | 380 | ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_LSE) ||\ |
mbed_official | 181:a4cbdfbbd2f4 | 381 | ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_USB)) |
mbed_official | 181:a4cbdfbbd2f4 | 382 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 383 | * @} |
mbed_official | 181:a4cbdfbbd2f4 | 384 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 385 | |
mbed_official | 181:a4cbdfbbd2f4 | 386 | /** @defgroup RCCEx_CRS_SynchroDivider |
mbed_official | 181:a4cbdfbbd2f4 | 387 | * @{ |
mbed_official | 181:a4cbdfbbd2f4 | 388 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 389 | #define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00) /*!< Synchro Signal not divided (default) */ |
mbed_official | 181:a4cbdfbbd2f4 | 390 | #define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ |
mbed_official | 181:a4cbdfbbd2f4 | 391 | #define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ |
mbed_official | 181:a4cbdfbbd2f4 | 392 | #define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ |
mbed_official | 181:a4cbdfbbd2f4 | 393 | #define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ |
mbed_official | 181:a4cbdfbbd2f4 | 394 | #define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ |
mbed_official | 181:a4cbdfbbd2f4 | 395 | #define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ |
mbed_official | 181:a4cbdfbbd2f4 | 396 | #define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ |
mbed_official | 181:a4cbdfbbd2f4 | 397 | |
mbed_official | 181:a4cbdfbbd2f4 | 398 | #define IS_RCC_CRS_SYNC_DIV(_DIV_) (((_DIV_) == RCC_CRS_SYNC_DIV1) || ((_DIV_) == RCC_CRS_SYNC_DIV2) ||\ |
mbed_official | 181:a4cbdfbbd2f4 | 399 | ((_DIV_) == RCC_CRS_SYNC_DIV4) || ((_DIV_) == RCC_CRS_SYNC_DIV8) || \ |
mbed_official | 181:a4cbdfbbd2f4 | 400 | ((_DIV_) == RCC_CRS_SYNC_DIV16) || ((_DIV_) == RCC_CRS_SYNC_DIV32) || \ |
mbed_official | 181:a4cbdfbbd2f4 | 401 | ((_DIV_) == RCC_CRS_SYNC_DIV64) || ((_DIV_) == RCC_CRS_SYNC_DIV128)) |
mbed_official | 181:a4cbdfbbd2f4 | 402 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 403 | * @} |
mbed_official | 181:a4cbdfbbd2f4 | 404 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 405 | |
mbed_official | 181:a4cbdfbbd2f4 | 406 | /** @defgroup RCCEx_CRS_SynchroPolarity |
mbed_official | 181:a4cbdfbbd2f4 | 407 | * @{ |
mbed_official | 181:a4cbdfbbd2f4 | 408 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 409 | #define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00) /*!< Synchro Active on rising edge (default) */ |
mbed_official | 181:a4cbdfbbd2f4 | 410 | #define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ |
mbed_official | 181:a4cbdfbbd2f4 | 411 | |
mbed_official | 181:a4cbdfbbd2f4 | 412 | #define IS_RCC_CRS_SYNC_POLARITY(_POLARITY_) (((_POLARITY_) == RCC_CRS_SYNC_POLARITY_RISING) || \ |
mbed_official | 181:a4cbdfbbd2f4 | 413 | ((_POLARITY_) == RCC_CRS_SYNC_POLARITY_FALLING)) |
mbed_official | 181:a4cbdfbbd2f4 | 414 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 415 | * @} |
mbed_official | 181:a4cbdfbbd2f4 | 416 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 417 | |
mbed_official | 181:a4cbdfbbd2f4 | 418 | /** @defgroup RCCEx_CRS_ReloadValueDefault |
mbed_official | 181:a4cbdfbbd2f4 | 419 | * @{ |
mbed_official | 181:a4cbdfbbd2f4 | 420 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 421 | #define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7F) /*!< The reset value of the RELOAD field corresponds |
mbed_official | 181:a4cbdfbbd2f4 | 422 | to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */ |
mbed_official | 181:a4cbdfbbd2f4 | 423 | |
mbed_official | 181:a4cbdfbbd2f4 | 424 | #define IS_RCC_CRS_RELOADVALUE(_VALUE_) (((_VALUE_) <= 0xFFFF)) |
mbed_official | 181:a4cbdfbbd2f4 | 425 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 426 | * @} |
mbed_official | 181:a4cbdfbbd2f4 | 427 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 428 | |
mbed_official | 181:a4cbdfbbd2f4 | 429 | /** @defgroup RCCEx_CRS_ErrorLimitDefault |
mbed_official | 181:a4cbdfbbd2f4 | 430 | * @{ |
mbed_official | 181:a4cbdfbbd2f4 | 431 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 432 | #define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22) /*!< Default Frequency error limit */ |
mbed_official | 181:a4cbdfbbd2f4 | 433 | |
mbed_official | 181:a4cbdfbbd2f4 | 434 | #define IS_RCC_CRS_ERRORLIMIT(_VALUE_) (((_VALUE_) <= 0xFF)) |
mbed_official | 181:a4cbdfbbd2f4 | 435 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 436 | * @} |
mbed_official | 181:a4cbdfbbd2f4 | 437 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 438 | |
mbed_official | 181:a4cbdfbbd2f4 | 439 | /** @defgroup RCCEx_CRS_HSI48CalibrationDefault |
mbed_official | 181:a4cbdfbbd2f4 | 440 | * @{ |
mbed_official | 181:a4cbdfbbd2f4 | 441 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 442 | #define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x20) /*!< The default value is 32, which corresponds to the middle of the trimming interval. |
mbed_official | 181:a4cbdfbbd2f4 | 443 | The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value |
mbed_official | 181:a4cbdfbbd2f4 | 444 | corresponds to a higher output frequency */ |
mbed_official | 181:a4cbdfbbd2f4 | 445 | |
mbed_official | 181:a4cbdfbbd2f4 | 446 | #define IS_RCC_CRS_HSI48CALIBRATION(_VALUE_) (((_VALUE_) <= 0x3F)) |
mbed_official | 181:a4cbdfbbd2f4 | 447 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 448 | * @} |
mbed_official | 181:a4cbdfbbd2f4 | 449 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 450 | |
mbed_official | 181:a4cbdfbbd2f4 | 451 | /** @defgroup RCCEx_CRS_FreqErrorDirection |
mbed_official | 181:a4cbdfbbd2f4 | 452 | * @{ |
mbed_official | 181:a4cbdfbbd2f4 | 453 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 454 | #define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00) /*!< Upcounting direction, the actual frequency is above the target */ |
mbed_official | 181:a4cbdfbbd2f4 | 455 | #define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */ |
mbed_official | 181:a4cbdfbbd2f4 | 456 | |
mbed_official | 181:a4cbdfbbd2f4 | 457 | #define IS_RCC_CRS_FREQERRORDIR(_DIR_) (((_DIR_) == RCC_CRS_FREQERRORDIR_UP) || \ |
mbed_official | 181:a4cbdfbbd2f4 | 458 | ((_DIR_) == RCC_CRS_FREQERRORDIR_DOWN)) |
mbed_official | 181:a4cbdfbbd2f4 | 459 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 460 | * @} |
mbed_official | 181:a4cbdfbbd2f4 | 461 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 462 | |
mbed_official | 181:a4cbdfbbd2f4 | 463 | /** @defgroup RCCEx_CRS_Interrupt_Sources |
mbed_official | 181:a4cbdfbbd2f4 | 464 | * @{ |
mbed_official | 181:a4cbdfbbd2f4 | 465 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 466 | #define RCC_CRS_IT_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK */ |
mbed_official | 181:a4cbdfbbd2f4 | 467 | #define RCC_CRS_IT_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning */ |
mbed_official | 181:a4cbdfbbd2f4 | 468 | #define RCC_CRS_IT_ERR CRS_ISR_ERRF /*!< error */ |
mbed_official | 181:a4cbdfbbd2f4 | 469 | #define RCC_CRS_IT_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC */ |
mbed_official | 181:a4cbdfbbd2f4 | 470 | #define RCC_CRS_IT_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ |
mbed_official | 181:a4cbdfbbd2f4 | 471 | #define RCC_CRS_IT_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ |
mbed_official | 181:a4cbdfbbd2f4 | 472 | #define RCC_CRS_IT_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ |
mbed_official | 181:a4cbdfbbd2f4 | 473 | |
mbed_official | 181:a4cbdfbbd2f4 | 474 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 475 | * @} |
mbed_official | 181:a4cbdfbbd2f4 | 476 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 477 | |
mbed_official | 181:a4cbdfbbd2f4 | 478 | /** @defgroup RCCEx_CRS_Flags |
mbed_official | 181:a4cbdfbbd2f4 | 479 | * @{ |
mbed_official | 181:a4cbdfbbd2f4 | 480 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 481 | #define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /* SYNC event OK flag */ |
mbed_official | 181:a4cbdfbbd2f4 | 482 | #define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /* SYNC warning flag */ |
mbed_official | 181:a4cbdfbbd2f4 | 483 | #define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /* Error flag */ |
mbed_official | 181:a4cbdfbbd2f4 | 484 | #define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /* Expected SYNC flag */ |
mbed_official | 181:a4cbdfbbd2f4 | 485 | #define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ |
mbed_official | 181:a4cbdfbbd2f4 | 486 | #define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ |
mbed_official | 181:a4cbdfbbd2f4 | 487 | #define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ |
mbed_official | 181:a4cbdfbbd2f4 | 488 | |
mbed_official | 181:a4cbdfbbd2f4 | 489 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 490 | * @} |
mbed_official | 181:a4cbdfbbd2f4 | 491 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 492 | |
mbed_official | 181:a4cbdfbbd2f4 | 493 | #endif /* !(STM32L051xx ) && !(STM32L061xx ) */ |
mbed_official | 181:a4cbdfbbd2f4 | 494 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 495 | * @} |
mbed_official | 181:a4cbdfbbd2f4 | 496 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 497 | |
mbed_official | 181:a4cbdfbbd2f4 | 498 | /* Exported macro ------------------------------------------------------------*/ |
mbed_official | 181:a4cbdfbbd2f4 | 499 | /** @defgroup RCCEx_Exported_Macros |
mbed_official | 181:a4cbdfbbd2f4 | 500 | * @{ |
mbed_official | 181:a4cbdfbbd2f4 | 501 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 502 | |
mbed_official | 181:a4cbdfbbd2f4 | 503 | /** @brief Enable or disable the AHB peripheral clock. |
mbed_official | 181:a4cbdfbbd2f4 | 504 | * @note After reset, the peripheral clock (used for registers read/write access) |
mbed_official | 181:a4cbdfbbd2f4 | 505 | * is disabled and the application software has to enable this clock before |
mbed_official | 181:a4cbdfbbd2f4 | 506 | * using it. |
mbed_official | 181:a4cbdfbbd2f4 | 507 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 508 | |
mbed_official | 181:a4cbdfbbd2f4 | 509 | #if defined(STM32L062xx) || defined(STM32L063xx) |
mbed_official | 181:a4cbdfbbd2f4 | 510 | #define __CRYP_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_CRYPEN)) |
mbed_official | 181:a4cbdfbbd2f4 | 511 | #define __CRYP_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_CRYPEN)) |
mbed_official | 181:a4cbdfbbd2f4 | 512 | #endif /* STM32L062xx || STM32L063xx */ |
mbed_official | 181:a4cbdfbbd2f4 | 513 | |
mbed_official | 181:a4cbdfbbd2f4 | 514 | #if !defined(STM32L051xx) && !defined(STM32L061xx) |
mbed_official | 181:a4cbdfbbd2f4 | 515 | #define __TSC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_TSCEN)) |
mbed_official | 181:a4cbdfbbd2f4 | 516 | #define __TSC_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_TSCEN)) |
mbed_official | 181:a4cbdfbbd2f4 | 517 | |
mbed_official | 181:a4cbdfbbd2f4 | 518 | #define __RNG_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_RNGEN)) |
mbed_official | 181:a4cbdfbbd2f4 | 519 | #define __RNG_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_RNGEN)) |
mbed_official | 181:a4cbdfbbd2f4 | 520 | #endif /* !(STM32L051xx ) && !(STM32L061xx ) */ |
mbed_official | 181:a4cbdfbbd2f4 | 521 | |
mbed_official | 181:a4cbdfbbd2f4 | 522 | /** @brief Enable or disable the APB1 peripheral clock. |
mbed_official | 181:a4cbdfbbd2f4 | 523 | * @note After reset, the peripheral clock (used for registers read/write access) |
mbed_official | 181:a4cbdfbbd2f4 | 524 | * is disabled and the application software has to enable this clock before |
mbed_official | 181:a4cbdfbbd2f4 | 525 | * using it. |
mbed_official | 181:a4cbdfbbd2f4 | 526 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 527 | |
mbed_official | 181:a4cbdfbbd2f4 | 528 | #if !defined(STM32L051xx) && !defined(STM32L061xx) |
mbed_official | 181:a4cbdfbbd2f4 | 529 | #define __USB_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USBEN)) |
mbed_official | 181:a4cbdfbbd2f4 | 530 | #define __USB_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_USBEN)) |
mbed_official | 181:a4cbdfbbd2f4 | 531 | #endif /* !(STM32L051xx ) && !(STM32L061xx ) */ |
mbed_official | 181:a4cbdfbbd2f4 | 532 | |
mbed_official | 181:a4cbdfbbd2f4 | 533 | #if !defined(STM32L051xx) && !defined(STM32L061xx) |
mbed_official | 181:a4cbdfbbd2f4 | 534 | #define __CRS_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CRSEN)) |
mbed_official | 181:a4cbdfbbd2f4 | 535 | #define __CRS_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CRSEN)) |
mbed_official | 181:a4cbdfbbd2f4 | 536 | #endif /* !(STM32L051xx ) && !(STM32L061xx ) */ |
mbed_official | 181:a4cbdfbbd2f4 | 537 | |
mbed_official | 181:a4cbdfbbd2f4 | 538 | |
mbed_official | 181:a4cbdfbbd2f4 | 539 | #if defined(STM32L053xx) || defined(STM32L063xx) |
mbed_official | 181:a4cbdfbbd2f4 | 540 | #define __LCD_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_LCDEN)) |
mbed_official | 181:a4cbdfbbd2f4 | 541 | #define __LCD_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LCDEN)) |
mbed_official | 181:a4cbdfbbd2f4 | 542 | #endif /* STM32L053xx || STM32L063xx */ |
mbed_official | 181:a4cbdfbbd2f4 | 543 | |
mbed_official | 181:a4cbdfbbd2f4 | 544 | #if defined(STM32L053xx) || defined(STM32L063xx) || \ |
mbed_official | 181:a4cbdfbbd2f4 | 545 | defined(STM32L052xx) || defined(STM32L062xx) || \ |
mbed_official | 181:a4cbdfbbd2f4 | 546 | defined(STM32L051xx) || defined(STM32L061xx) |
mbed_official | 181:a4cbdfbbd2f4 | 547 | #define __TIM2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN)) |
mbed_official | 181:a4cbdfbbd2f4 | 548 | #define __TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN)) |
mbed_official | 181:a4cbdfbbd2f4 | 549 | #define __SPI2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI2EN)) |
mbed_official | 181:a4cbdfbbd2f4 | 550 | #define __USART2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART2EN)) |
mbed_official | 181:a4cbdfbbd2f4 | 551 | #define __LPUART1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_LPUART1EN)) |
mbed_official | 181:a4cbdfbbd2f4 | 552 | #define __I2C1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C1EN)) |
mbed_official | 181:a4cbdfbbd2f4 | 553 | #define __I2C2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C2EN)) |
mbed_official | 181:a4cbdfbbd2f4 | 554 | #define __DAC_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DACEN)) |
mbed_official | 181:a4cbdfbbd2f4 | 555 | #define __LPTIM1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_LPTIM1EN)) |
mbed_official | 181:a4cbdfbbd2f4 | 556 | |
mbed_official | 181:a4cbdfbbd2f4 | 557 | #define __TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM2EN)) |
mbed_official | 181:a4cbdfbbd2f4 | 558 | #define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM6EN)) |
mbed_official | 181:a4cbdfbbd2f4 | 559 | #define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_SPI2EN)) |
mbed_official | 181:a4cbdfbbd2f4 | 560 | #define __USART2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_USART2EN)) |
mbed_official | 181:a4cbdfbbd2f4 | 561 | #define __LPUART1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPUART1EN)) |
mbed_official | 181:a4cbdfbbd2f4 | 562 | #define __I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C1EN)) |
mbed_official | 181:a4cbdfbbd2f4 | 563 | #define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C2EN)) |
mbed_official | 181:a4cbdfbbd2f4 | 564 | #define __DAC_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_DACEN)) |
mbed_official | 181:a4cbdfbbd2f4 | 565 | #define __LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPTIM1EN)) |
mbed_official | 181:a4cbdfbbd2f4 | 566 | #endif /* STM32L051xx || STM32L061xx || */ |
mbed_official | 181:a4cbdfbbd2f4 | 567 | /* STM32L052xx || STM32L062xx || */ |
mbed_official | 181:a4cbdfbbd2f4 | 568 | /* STM32L053xx || STM32L063xx || */ |
mbed_official | 181:a4cbdfbbd2f4 | 569 | |
mbed_official | 181:a4cbdfbbd2f4 | 570 | /** @brief Enable or disable the APB2 peripheral clock. |
mbed_official | 181:a4cbdfbbd2f4 | 571 | * @note After reset, the peripheral clock (used for registers read/write access) |
mbed_official | 181:a4cbdfbbd2f4 | 572 | * is disabled and the application software has to enable this clock before |
mbed_official | 181:a4cbdfbbd2f4 | 573 | * using it. |
mbed_official | 181:a4cbdfbbd2f4 | 574 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 575 | |
mbed_official | 181:a4cbdfbbd2f4 | 576 | #if defined(STM32L053xx) || defined(STM32L063xx) || \ |
mbed_official | 181:a4cbdfbbd2f4 | 577 | defined(STM32L052xx) || defined(STM32L062xx) || \ |
mbed_official | 181:a4cbdfbbd2f4 | 578 | defined(STM32L051xx) || defined(STM32L061xx) |
mbed_official | 181:a4cbdfbbd2f4 | 579 | #define __TIM21_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM21EN)) |
mbed_official | 181:a4cbdfbbd2f4 | 580 | #define __TIM22_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM22EN)) |
mbed_official | 181:a4cbdfbbd2f4 | 581 | #define __FIREWALL_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_MIFIEN)) |
mbed_official | 181:a4cbdfbbd2f4 | 582 | #define __ADC1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC1EN)) |
mbed_official | 181:a4cbdfbbd2f4 | 583 | #define __SPI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI1EN)) |
mbed_official | 181:a4cbdfbbd2f4 | 584 | #define __USART1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART1EN)) |
mbed_official | 181:a4cbdfbbd2f4 | 585 | |
mbed_official | 181:a4cbdfbbd2f4 | 586 | #define __TIM21_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_TIM21EN)) |
mbed_official | 181:a4cbdfbbd2f4 | 587 | #define __TIM22_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_TIM22EN)) |
mbed_official | 181:a4cbdfbbd2f4 | 588 | #define __FIREWALL_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_MIFIEN)) |
mbed_official | 181:a4cbdfbbd2f4 | 589 | #define __ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_ADC1EN)) |
mbed_official | 181:a4cbdfbbd2f4 | 590 | #define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_SPI1EN)) |
mbed_official | 181:a4cbdfbbd2f4 | 591 | #define __USART1_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_USART1EN)) |
mbed_official | 181:a4cbdfbbd2f4 | 592 | #endif /* STM32L051xx || STM32L061xx || */ |
mbed_official | 181:a4cbdfbbd2f4 | 593 | /* STM32L052xx || STM32L062xx || */ |
mbed_official | 181:a4cbdfbbd2f4 | 594 | /* STM32L053xx || STM32L063xx || */ |
mbed_official | 181:a4cbdfbbd2f4 | 595 | |
mbed_official | 181:a4cbdfbbd2f4 | 596 | /** @brief Force or release AHB peripheral reset. |
mbed_official | 181:a4cbdfbbd2f4 | 597 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 598 | #if defined(STM32L062xx) || defined(STM32L063xx) |
mbed_official | 181:a4cbdfbbd2f4 | 599 | #define __CRYP_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_CRYPRST)) |
mbed_official | 181:a4cbdfbbd2f4 | 600 | #define __CRYP_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_CRYPRST)) |
mbed_official | 181:a4cbdfbbd2f4 | 601 | #endif /* STM32L062xx || STM32L063xx */ |
mbed_official | 181:a4cbdfbbd2f4 | 602 | |
mbed_official | 181:a4cbdfbbd2f4 | 603 | #if !defined(STM32L051xx) && !defined(STM32L061xx) |
mbed_official | 181:a4cbdfbbd2f4 | 604 | #define __TSC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_TSCRST)) |
mbed_official | 181:a4cbdfbbd2f4 | 605 | #define __TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_TSCRST)) |
mbed_official | 181:a4cbdfbbd2f4 | 606 | #define __RNG_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_RNGRST)) |
mbed_official | 181:a4cbdfbbd2f4 | 607 | #define __RNG_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_RNGRST)) |
mbed_official | 181:a4cbdfbbd2f4 | 608 | #endif /* !(STM32L051xx ) && !(STM32L061xx ) */ |
mbed_official | 181:a4cbdfbbd2f4 | 609 | |
mbed_official | 181:a4cbdfbbd2f4 | 610 | /** @brief Force or release APB1 peripheral reset. |
mbed_official | 181:a4cbdfbbd2f4 | 611 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 612 | #if defined(STM32L053xx) || defined(STM32L063xx) || \ |
mbed_official | 181:a4cbdfbbd2f4 | 613 | defined(STM32L052xx) || defined(STM32L062xx) || \ |
mbed_official | 181:a4cbdfbbd2f4 | 614 | defined(STM32L051xx) || defined(STM32L061xx) |
mbed_official | 181:a4cbdfbbd2f4 | 615 | #define __TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) |
mbed_official | 181:a4cbdfbbd2f4 | 616 | #define __TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) |
mbed_official | 181:a4cbdfbbd2f4 | 617 | #define __LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST)) |
mbed_official | 181:a4cbdfbbd2f4 | 618 | #define __I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) |
mbed_official | 181:a4cbdfbbd2f4 | 619 | #define __I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) |
mbed_official | 181:a4cbdfbbd2f4 | 620 | #define __USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) |
mbed_official | 181:a4cbdfbbd2f4 | 621 | #define __LPUART1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPUART1RST)) |
mbed_official | 181:a4cbdfbbd2f4 | 622 | #define __SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) |
mbed_official | 181:a4cbdfbbd2f4 | 623 | #define __DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) |
mbed_official | 181:a4cbdfbbd2f4 | 624 | |
mbed_official | 181:a4cbdfbbd2f4 | 625 | #define __TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM2RST)) |
mbed_official | 181:a4cbdfbbd2f4 | 626 | #define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM6RST)) |
mbed_official | 181:a4cbdfbbd2f4 | 627 | #define __LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPTIM1RST)) |
mbed_official | 181:a4cbdfbbd2f4 | 628 | #define __I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C1RST)) |
mbed_official | 181:a4cbdfbbd2f4 | 629 | #define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C2RST)) |
mbed_official | 181:a4cbdfbbd2f4 | 630 | #define __USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USART2RST)) |
mbed_official | 181:a4cbdfbbd2f4 | 631 | #define __LPUART1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPUART1RST)) |
mbed_official | 181:a4cbdfbbd2f4 | 632 | #define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_SPI2RST)) |
mbed_official | 181:a4cbdfbbd2f4 | 633 | #define __DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_DACRST)) |
mbed_official | 181:a4cbdfbbd2f4 | 634 | #endif /* STM32L051xx || STM32L061xx || */ |
mbed_official | 181:a4cbdfbbd2f4 | 635 | /* STM32L052xx || STM32L062xx || */ |
mbed_official | 181:a4cbdfbbd2f4 | 636 | /* STM32L053xx || STM32L063xx || */ |
mbed_official | 181:a4cbdfbbd2f4 | 637 | |
mbed_official | 181:a4cbdfbbd2f4 | 638 | #if !defined(STM32L051xx) && !defined(STM32L061xx) |
mbed_official | 181:a4cbdfbbd2f4 | 639 | #define __USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST)) |
mbed_official | 181:a4cbdfbbd2f4 | 640 | #define __USB_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USBRST)) |
mbed_official | 181:a4cbdfbbd2f4 | 641 | #endif /* !(STM32L051xx ) && !(STM32L061xx ) */ |
mbed_official | 181:a4cbdfbbd2f4 | 642 | |
mbed_official | 181:a4cbdfbbd2f4 | 643 | #if !defined(STM32L051xx) && !defined(STM32L061xx) |
mbed_official | 181:a4cbdfbbd2f4 | 644 | #define __CRS_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CRSRST)) |
mbed_official | 181:a4cbdfbbd2f4 | 645 | #define __CRS_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CRSRST)) |
mbed_official | 181:a4cbdfbbd2f4 | 646 | #endif /* !(STM32L051xx ) && !(STM32L061xx ) */ |
mbed_official | 181:a4cbdfbbd2f4 | 647 | |
mbed_official | 181:a4cbdfbbd2f4 | 648 | #if defined(STM32L053xx) || defined(STM32L063xx) |
mbed_official | 181:a4cbdfbbd2f4 | 649 | #define __LCD_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LCDRST)) |
mbed_official | 181:a4cbdfbbd2f4 | 650 | #define __LCD_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LCDRST)) |
mbed_official | 181:a4cbdfbbd2f4 | 651 | #endif /* STM32L053xx || STM32L063xx */ |
mbed_official | 181:a4cbdfbbd2f4 | 652 | |
mbed_official | 181:a4cbdfbbd2f4 | 653 | /** @brief Force or release APB2 peripheral reset. |
mbed_official | 181:a4cbdfbbd2f4 | 654 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 655 | #if defined(STM32L053xx) || defined(STM32L063xx) || \ |
mbed_official | 181:a4cbdfbbd2f4 | 656 | defined(STM32L052xx) || defined(STM32L062xx) || \ |
mbed_official | 181:a4cbdfbbd2f4 | 657 | defined(STM32L051xx) || defined(STM32L061xx) |
mbed_official | 181:a4cbdfbbd2f4 | 658 | #define __USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) |
mbed_official | 181:a4cbdfbbd2f4 | 659 | #define __ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST)) |
mbed_official | 181:a4cbdfbbd2f4 | 660 | #define __SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) |
mbed_official | 181:a4cbdfbbd2f4 | 661 | #define __TIM21_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM21RST)) |
mbed_official | 181:a4cbdfbbd2f4 | 662 | #define __TIM22_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM22RST)) |
mbed_official | 181:a4cbdfbbd2f4 | 663 | |
mbed_official | 181:a4cbdfbbd2f4 | 664 | #define __USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_USART1RST)) |
mbed_official | 181:a4cbdfbbd2f4 | 665 | #define __ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_ADC1RST)) |
mbed_official | 181:a4cbdfbbd2f4 | 666 | #define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_SPI1RST)) |
mbed_official | 181:a4cbdfbbd2f4 | 667 | #define __TIM21_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_TIM21RST)) |
mbed_official | 181:a4cbdfbbd2f4 | 668 | #define __TIM22_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_TIM22RST)) |
mbed_official | 181:a4cbdfbbd2f4 | 669 | #endif /* STM32L051xx || STM32L061xx || */ |
mbed_official | 181:a4cbdfbbd2f4 | 670 | /* STM32L052xx || STM32L062xx || */ |
mbed_official | 181:a4cbdfbbd2f4 | 671 | /* STM32L053xx || STM32L063xx || */ |
mbed_official | 181:a4cbdfbbd2f4 | 672 | |
mbed_official | 181:a4cbdfbbd2f4 | 673 | /** @brief Enable or disable the AHB peripheral clock during Low Power (Sleep) mode. |
mbed_official | 181:a4cbdfbbd2f4 | 674 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
mbed_official | 181:a4cbdfbbd2f4 | 675 | * power consumption. |
mbed_official | 181:a4cbdfbbd2f4 | 676 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
mbed_official | 181:a4cbdfbbd2f4 | 677 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
mbed_official | 181:a4cbdfbbd2f4 | 678 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 679 | |
mbed_official | 181:a4cbdfbbd2f4 | 680 | #if !defined(STM32L051xx) && !defined(STM32L061xx) |
mbed_official | 181:a4cbdfbbd2f4 | 681 | #define __TSC_CLK_SLEEP_ENABLE() (RCC->AHBSMENR |= (RCC_AHBSMENR_TSCSMEN)) |
mbed_official | 181:a4cbdfbbd2f4 | 682 | #define __RNG_CLK_SLEEP_ENABLE() (RCC->AHBSMENR |= (RCC_AHBSMENR_RNGSMEN)) |
mbed_official | 181:a4cbdfbbd2f4 | 683 | #define __TSC_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_TSCSMEN)) |
mbed_official | 181:a4cbdfbbd2f4 | 684 | #define __RNG_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_RNGSMEN)) |
mbed_official | 181:a4cbdfbbd2f4 | 685 | #endif /* !(STM32L051xx ) && !(STM32L061xx ) */ |
mbed_official | 181:a4cbdfbbd2f4 | 686 | |
mbed_official | 181:a4cbdfbbd2f4 | 687 | #if defined(STM32L062xx) || defined(STM32L063xx) |
mbed_official | 181:a4cbdfbbd2f4 | 688 | #define __CRYP_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBSMENR_CRYPSMEN)) |
mbed_official | 181:a4cbdfbbd2f4 | 689 | #define __CRYP_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~ (RCC_AHBSMENR_CRYPSMEN)) |
mbed_official | 181:a4cbdfbbd2f4 | 690 | #endif /* STM32L062xx || STM32L063xx */ |
mbed_official | 181:a4cbdfbbd2f4 | 691 | |
mbed_official | 181:a4cbdfbbd2f4 | 692 | |
mbed_official | 181:a4cbdfbbd2f4 | 693 | /** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. |
mbed_official | 181:a4cbdfbbd2f4 | 694 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
mbed_official | 181:a4cbdfbbd2f4 | 695 | * power consumption. |
mbed_official | 181:a4cbdfbbd2f4 | 696 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
mbed_official | 181:a4cbdfbbd2f4 | 697 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
mbed_official | 181:a4cbdfbbd2f4 | 698 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 699 | |
mbed_official | 181:a4cbdfbbd2f4 | 700 | #if defined(STM32L053xx) || defined(STM32L063xx) || \ |
mbed_official | 181:a4cbdfbbd2f4 | 701 | defined(STM32L052xx) || defined(STM32L062xx) || \ |
mbed_official | 181:a4cbdfbbd2f4 | 702 | defined(STM32L051xx) || defined(STM32L061xx) |
mbed_official | 181:a4cbdfbbd2f4 | 703 | #define __TIM2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_TIM2SMEN)) |
mbed_official | 181:a4cbdfbbd2f4 | 704 | #define __TIM6_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_TIM6SMEN)) |
mbed_official | 181:a4cbdfbbd2f4 | 705 | #define __SPI2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_SPI2SMEN)) |
mbed_official | 181:a4cbdfbbd2f4 | 706 | #define __USART2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_USART2SMEN)) |
mbed_official | 181:a4cbdfbbd2f4 | 707 | #define __LPUART1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_LPUART1SMEN)) |
mbed_official | 181:a4cbdfbbd2f4 | 708 | #define __I2C1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_I2C1SMEN)) |
mbed_official | 181:a4cbdfbbd2f4 | 709 | #define __I2C2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_I2C2SMEN)) |
mbed_official | 181:a4cbdfbbd2f4 | 710 | #define __DAC_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_DACSMEN)) |
mbed_official | 181:a4cbdfbbd2f4 | 711 | #define __LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_LPTIM1SMEN)) |
mbed_official | 181:a4cbdfbbd2f4 | 712 | |
mbed_official | 181:a4cbdfbbd2f4 | 713 | #define __TIM2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM2SMEN)) |
mbed_official | 181:a4cbdfbbd2f4 | 714 | #define __TIM6_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM6SMEN)) |
mbed_official | 181:a4cbdfbbd2f4 | 715 | #define __SPI2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_SPI2SMEN)) |
mbed_official | 181:a4cbdfbbd2f4 | 716 | #define __USART2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_USART2SMEN)) |
mbed_official | 181:a4cbdfbbd2f4 | 717 | #define __LPUART1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_LPUART1SMEN)) |
mbed_official | 181:a4cbdfbbd2f4 | 718 | #define __I2C1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_I2C1SMEN)) |
mbed_official | 181:a4cbdfbbd2f4 | 719 | #define __I2C2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_I2C2SMEN)) |
mbed_official | 181:a4cbdfbbd2f4 | 720 | #define __DAC_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_DACSMEN)) |
mbed_official | 181:a4cbdfbbd2f4 | 721 | #define __LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_LPTIM1SMEN)) |
mbed_official | 181:a4cbdfbbd2f4 | 722 | #endif /* STM32L051xx || STM32L061xx || */ |
mbed_official | 181:a4cbdfbbd2f4 | 723 | /* STM32L052xx || STM32L062xx || */ |
mbed_official | 181:a4cbdfbbd2f4 | 724 | /* STM32L053xx || STM32L063xx || */ |
mbed_official | 181:a4cbdfbbd2f4 | 725 | |
mbed_official | 181:a4cbdfbbd2f4 | 726 | #if !defined(STM32L051xx) && !defined(STM32L061xx) |
mbed_official | 181:a4cbdfbbd2f4 | 727 | #define __USB_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_USBSMEN)) |
mbed_official | 181:a4cbdfbbd2f4 | 728 | #define __USB_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_USBSMEN)) |
mbed_official | 181:a4cbdfbbd2f4 | 729 | |
mbed_official | 181:a4cbdfbbd2f4 | 730 | #define __CRS_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_CRSSMEN)) |
mbed_official | 181:a4cbdfbbd2f4 | 731 | #define __CRS_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_CRSSMEN)) |
mbed_official | 181:a4cbdfbbd2f4 | 732 | #endif /* !(STM32L051xx ) && !(STM32L061xx ) */ |
mbed_official | 181:a4cbdfbbd2f4 | 733 | |
mbed_official | 181:a4cbdfbbd2f4 | 734 | #if defined(STM32L053xx) || defined(STM32L063xx) |
mbed_official | 181:a4cbdfbbd2f4 | 735 | #define __LCD_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_LCDSMEN)) |
mbed_official | 181:a4cbdfbbd2f4 | 736 | #define __LCD_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_LCDSMEN)) |
mbed_official | 181:a4cbdfbbd2f4 | 737 | #endif /* STM32L053xx || STM32L063xx */ |
mbed_official | 181:a4cbdfbbd2f4 | 738 | |
mbed_official | 181:a4cbdfbbd2f4 | 739 | /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. |
mbed_official | 181:a4cbdfbbd2f4 | 740 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
mbed_official | 181:a4cbdfbbd2f4 | 741 | * power consumption. |
mbed_official | 181:a4cbdfbbd2f4 | 742 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
mbed_official | 181:a4cbdfbbd2f4 | 743 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
mbed_official | 181:a4cbdfbbd2f4 | 744 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 745 | #if defined(STM32L053xx) || defined(STM32L063xx) || \ |
mbed_official | 181:a4cbdfbbd2f4 | 746 | defined(STM32L052xx) || defined(STM32L062xx) || \ |
mbed_official | 181:a4cbdfbbd2f4 | 747 | defined(STM32L051xx) || defined(STM32L061xx) |
mbed_official | 181:a4cbdfbbd2f4 | 748 | #define __TIM21_CLK_SLEEP_ENABLE() (RCC->APB2SMENR |= (RCC_APB2SMENR_TIM21SMEN)) |
mbed_official | 181:a4cbdfbbd2f4 | 749 | #define __TIM22_CLK_SLEEP_ENABLE() (RCC->APB2SMENR |= (RCC_APB2SMENR_TIM22SMEN)) |
mbed_official | 181:a4cbdfbbd2f4 | 750 | #define __ADC1_CLK_SLEEP_ENABLE() (RCC->APB2SMENR |= (RCC_APB2SMENR_ADC1SMEN)) |
mbed_official | 181:a4cbdfbbd2f4 | 751 | #define __SPI1_CLK_SLEEP_ENABLE() (RCC->APB2SMENR |= (RCC_APB2SMENR_SPI1SMEN)) |
mbed_official | 181:a4cbdfbbd2f4 | 752 | #define __USART1_CLK_SLEEP_ENABLE() (RCC->APB2SMENR |= (RCC_APB2SMENR_USART1SMEN)) |
mbed_official | 181:a4cbdfbbd2f4 | 753 | |
mbed_official | 181:a4cbdfbbd2f4 | 754 | #define __TIM21_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_TIM21SMEN)) |
mbed_official | 181:a4cbdfbbd2f4 | 755 | #define __TIM22_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_TIM22SMEN)) |
mbed_official | 181:a4cbdfbbd2f4 | 756 | #define __ADC1_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_ADC1SMEN)) |
mbed_official | 181:a4cbdfbbd2f4 | 757 | #define __SPI1_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_SPI1SMEN)) |
mbed_official | 181:a4cbdfbbd2f4 | 758 | #define __USART1_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_USART1SMEN)) |
mbed_official | 181:a4cbdfbbd2f4 | 759 | #endif /* STM32L051xx || STM32L061xx || */ |
mbed_official | 181:a4cbdfbbd2f4 | 760 | /* STM32L052xx || STM32L062xx || */ |
mbed_official | 181:a4cbdfbbd2f4 | 761 | /* STM32L053xx || STM32L063xx || */ |
mbed_official | 181:a4cbdfbbd2f4 | 762 | |
mbed_official | 181:a4cbdfbbd2f4 | 763 | /** @brief macro to configure the I2C1 clock (I2C1CLK). |
mbed_official | 181:a4cbdfbbd2f4 | 764 | * |
mbed_official | 181:a4cbdfbbd2f4 | 765 | * @param __I2C1CLKSource__: specifies the I2C1 clock source. |
mbed_official | 181:a4cbdfbbd2f4 | 766 | * This parameter can be one of the following values: |
mbed_official | 181:a4cbdfbbd2f4 | 767 | * @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock |
mbed_official | 181:a4cbdfbbd2f4 | 768 | * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock |
mbed_official | 181:a4cbdfbbd2f4 | 769 | * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock |
mbed_official | 181:a4cbdfbbd2f4 | 770 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 771 | #define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSource__) \ |
mbed_official | 181:a4cbdfbbd2f4 | 772 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (uint32_t)(__I2C1CLKSource__)) |
mbed_official | 181:a4cbdfbbd2f4 | 773 | |
mbed_official | 181:a4cbdfbbd2f4 | 774 | /** @brief macro to get the I2C1 clock source. |
mbed_official | 181:a4cbdfbbd2f4 | 775 | * @retval The clock source can be one of the following values: |
mbed_official | 181:a4cbdfbbd2f4 | 776 | * @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock |
mbed_official | 181:a4cbdfbbd2f4 | 777 | * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock |
mbed_official | 181:a4cbdfbbd2f4 | 778 | * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock |
mbed_official | 181:a4cbdfbbd2f4 | 779 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 780 | #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL))) |
mbed_official | 181:a4cbdfbbd2f4 | 781 | |
mbed_official | 181:a4cbdfbbd2f4 | 782 | /** @brief macro to configure the USART1 clock (USART1CLK). |
mbed_official | 181:a4cbdfbbd2f4 | 783 | * |
mbed_official | 181:a4cbdfbbd2f4 | 784 | * @param __USART1CLKSource__: specifies the USART1 clock source. |
mbed_official | 181:a4cbdfbbd2f4 | 785 | * This parameter can be one of the following values: |
mbed_official | 181:a4cbdfbbd2f4 | 786 | * @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock |
mbed_official | 181:a4cbdfbbd2f4 | 787 | * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock |
mbed_official | 181:a4cbdfbbd2f4 | 788 | * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock |
mbed_official | 181:a4cbdfbbd2f4 | 789 | * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock |
mbed_official | 181:a4cbdfbbd2f4 | 790 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 791 | #define __HAL_RCC_USART1_CONFIG(__USART1CLKSource__) \ |
mbed_official | 181:a4cbdfbbd2f4 | 792 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (uint32_t)(__USART1CLKSource__)) |
mbed_official | 181:a4cbdfbbd2f4 | 793 | |
mbed_official | 181:a4cbdfbbd2f4 | 794 | /** @brief macro to get the USART1 clock source. |
mbed_official | 181:a4cbdfbbd2f4 | 795 | * @retval The clock source can be one of the following values: |
mbed_official | 181:a4cbdfbbd2f4 | 796 | * @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock |
mbed_official | 181:a4cbdfbbd2f4 | 797 | * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock |
mbed_official | 181:a4cbdfbbd2f4 | 798 | * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock |
mbed_official | 181:a4cbdfbbd2f4 | 799 | * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock |
mbed_official | 181:a4cbdfbbd2f4 | 800 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 801 | #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL))) |
mbed_official | 181:a4cbdfbbd2f4 | 802 | |
mbed_official | 181:a4cbdfbbd2f4 | 803 | /** @brief macro to configure the USART2 clock (USART2CLK). |
mbed_official | 181:a4cbdfbbd2f4 | 804 | * |
mbed_official | 181:a4cbdfbbd2f4 | 805 | * @param __USART2CLKSource__: specifies the USART2 clock source. |
mbed_official | 181:a4cbdfbbd2f4 | 806 | * This parameter can be one of the following values: |
mbed_official | 181:a4cbdfbbd2f4 | 807 | * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock |
mbed_official | 181:a4cbdfbbd2f4 | 808 | * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock |
mbed_official | 181:a4cbdfbbd2f4 | 809 | * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock |
mbed_official | 181:a4cbdfbbd2f4 | 810 | * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock |
mbed_official | 181:a4cbdfbbd2f4 | 811 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 812 | #define __HAL_RCC_USART2_CONFIG(__USART2CLKSource__) \ |
mbed_official | 181:a4cbdfbbd2f4 | 813 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (uint32_t)(__USART2CLKSource__)) |
mbed_official | 181:a4cbdfbbd2f4 | 814 | |
mbed_official | 181:a4cbdfbbd2f4 | 815 | /** @brief macro to get the USART2 clock source. |
mbed_official | 181:a4cbdfbbd2f4 | 816 | * @retval The clock source can be one of the following values: |
mbed_official | 181:a4cbdfbbd2f4 | 817 | * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock |
mbed_official | 181:a4cbdfbbd2f4 | 818 | * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock |
mbed_official | 181:a4cbdfbbd2f4 | 819 | * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock |
mbed_official | 181:a4cbdfbbd2f4 | 820 | * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock |
mbed_official | 181:a4cbdfbbd2f4 | 821 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 822 | #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL))) |
mbed_official | 181:a4cbdfbbd2f4 | 823 | |
mbed_official | 181:a4cbdfbbd2f4 | 824 | /** @brief macro to configure the LPUART1 clock (LPUART1CLK). |
mbed_official | 181:a4cbdfbbd2f4 | 825 | * |
mbed_official | 181:a4cbdfbbd2f4 | 826 | * @param __LPUART1CLKSource__: specifies the LPUART1 clock source. |
mbed_official | 181:a4cbdfbbd2f4 | 827 | * This parameter can be one of the following values: |
mbed_official | 181:a4cbdfbbd2f4 | 828 | * @arg RCC_LPUART1CLKSOURCE_PCLK1: PCLK1 selected as LPUART1 clock |
mbed_official | 181:a4cbdfbbd2f4 | 829 | * @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock |
mbed_official | 181:a4cbdfbbd2f4 | 830 | * @arg RCC_LPUART1CLKSOURCE_SYSCLK: System Clock selected as LPUART1 clock |
mbed_official | 181:a4cbdfbbd2f4 | 831 | * @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock |
mbed_official | 181:a4cbdfbbd2f4 | 832 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 833 | #define __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) \ |
mbed_official | 181:a4cbdfbbd2f4 | 834 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__)) |
mbed_official | 181:a4cbdfbbd2f4 | 835 | |
mbed_official | 181:a4cbdfbbd2f4 | 836 | /** @brief macro to get the LPUART1 clock source. |
mbed_official | 181:a4cbdfbbd2f4 | 837 | * @retval The clock source can be one of the following values: |
mbed_official | 181:a4cbdfbbd2f4 | 838 | * @arg RCC_LPUART1CLKSOURCE_PCLK1: PCLK1 selected as LPUART1 clock |
mbed_official | 181:a4cbdfbbd2f4 | 839 | * @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock |
mbed_official | 181:a4cbdfbbd2f4 | 840 | * @arg RCC_LPUART1CLKSOURCE_SYSCLK: System Clock selected as LPUART1 clock |
mbed_official | 181:a4cbdfbbd2f4 | 841 | * @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock |
mbed_official | 181:a4cbdfbbd2f4 | 842 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 843 | #define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL))) |
mbed_official | 181:a4cbdfbbd2f4 | 844 | |
mbed_official | 181:a4cbdfbbd2f4 | 845 | /** @brief macro to configure the LPTIM1 clock (LPTIM1CLK). |
mbed_official | 181:a4cbdfbbd2f4 | 846 | * |
mbed_official | 181:a4cbdfbbd2f4 | 847 | * @param __LPTIM1CLKSource__: specifies the LPTIM1 clock source. |
mbed_official | 181:a4cbdfbbd2f4 | 848 | * This parameter can be one of the following values: |
mbed_official | 181:a4cbdfbbd2f4 | 849 | * @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPTIM1 clock |
mbed_official | 181:a4cbdfbbd2f4 | 850 | * @arg RCC_LPTIM1CLKSOURCE_LSI : HSI selected as LPTIM1 clock |
mbed_official | 181:a4cbdfbbd2f4 | 851 | * @arg RCC_LPTIM1CLKSOURCE_HSI : LSI selected as LPTIM1 clock |
mbed_official | 181:a4cbdfbbd2f4 | 852 | * @arg RCC_LPTIM1CLKSOURCE_LSE : LSE selected as LPTIM1 clock |
mbed_official | 181:a4cbdfbbd2f4 | 853 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 854 | #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) \ |
mbed_official | 181:a4cbdfbbd2f4 | 855 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__)) |
mbed_official | 181:a4cbdfbbd2f4 | 856 | |
mbed_official | 181:a4cbdfbbd2f4 | 857 | /** @brief macro to get the LPTIM1 clock source. |
mbed_official | 181:a4cbdfbbd2f4 | 858 | * @retval The clock source can be one of the following values: |
mbed_official | 181:a4cbdfbbd2f4 | 859 | * @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPUART1 clock |
mbed_official | 181:a4cbdfbbd2f4 | 860 | * @arg RCC_LPTIM1CLKSOURCE_LSI : HSI selected as LPUART1 clock |
mbed_official | 181:a4cbdfbbd2f4 | 861 | * @arg RCC_LPTIM1CLKSOURCE_HSI : System Clock selected as LPUART1 clock |
mbed_official | 181:a4cbdfbbd2f4 | 862 | * @arg RCC_LPTIM1CLKSOURCE_LSE : LSE selected as LPUART1 clock |
mbed_official | 181:a4cbdfbbd2f4 | 863 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 864 | #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL))) |
mbed_official | 181:a4cbdfbbd2f4 | 865 | |
mbed_official | 181:a4cbdfbbd2f4 | 866 | #if !defined(STM32L051xx) && !defined(STM32L061xx) |
mbed_official | 181:a4cbdfbbd2f4 | 867 | /** @brief Macro to configure the USB clock (USBCLK). |
mbed_official | 181:a4cbdfbbd2f4 | 868 | * @param __USBCLKSource__: specifies the USB clock source. |
mbed_official | 181:a4cbdfbbd2f4 | 869 | * This parameter can be one of the following values: |
mbed_official | 181:a4cbdfbbd2f4 | 870 | * @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock |
mbed_official | 181:a4cbdfbbd2f4 | 871 | * @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock |
mbed_official | 181:a4cbdfbbd2f4 | 872 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 873 | #define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \ |
mbed_official | 181:a4cbdfbbd2f4 | 874 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, (uint32_t)(__USBCLKSource__)) |
mbed_official | 181:a4cbdfbbd2f4 | 875 | |
mbed_official | 181:a4cbdfbbd2f4 | 876 | /** @brief Macro to get the USB clock source. |
mbed_official | 181:a4cbdfbbd2f4 | 877 | * @retval The clock source can be one of the following values: |
mbed_official | 181:a4cbdfbbd2f4 | 878 | * @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock |
mbed_official | 181:a4cbdfbbd2f4 | 879 | * @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock |
mbed_official | 181:a4cbdfbbd2f4 | 880 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 881 | #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_HSI48SEL))) |
mbed_official | 181:a4cbdfbbd2f4 | 882 | |
mbed_official | 181:a4cbdfbbd2f4 | 883 | /** @brief Macro to configure the RNG clock (RNGCLK). |
mbed_official | 181:a4cbdfbbd2f4 | 884 | * @param __RNGCLKSource__: specifies the USB clock source. |
mbed_official | 181:a4cbdfbbd2f4 | 885 | * This parameter can be one of the following values: |
mbed_official | 181:a4cbdfbbd2f4 | 886 | * @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock |
mbed_official | 181:a4cbdfbbd2f4 | 887 | * @arg RCC_RNGCLKSOURCE_PLLCLK: PLL Clock selected as RNG clock |
mbed_official | 181:a4cbdfbbd2f4 | 888 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 889 | #define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) \ |
mbed_official | 181:a4cbdfbbd2f4 | 890 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, (uint32_t)(__RNGCLKSource__)) |
mbed_official | 181:a4cbdfbbd2f4 | 891 | |
mbed_official | 181:a4cbdfbbd2f4 | 892 | /** @brief Macro to get the RNG clock source. |
mbed_official | 181:a4cbdfbbd2f4 | 893 | * @retval The clock source can be one of the following values: |
mbed_official | 181:a4cbdfbbd2f4 | 894 | * @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock |
mbed_official | 181:a4cbdfbbd2f4 | 895 | * @arg RCC_RNGCLKSOURCE_PLLCLK: PLL Clock selected as RNG clock |
mbed_official | 181:a4cbdfbbd2f4 | 896 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 897 | #define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_HSI48SEL))) |
mbed_official | 181:a4cbdfbbd2f4 | 898 | |
mbed_official | 181:a4cbdfbbd2f4 | 899 | /** @brief macro to select the HSI48M clock source |
mbed_official | 181:a4cbdfbbd2f4 | 900 | * @note This macro can be replaced by either __HAL_RCC_RNG_CONFIG or |
mbed_official | 181:a4cbdfbbd2f4 | 901 | * __HAL_RCC_USB_CONFIG to configure respectively RNG or UBS clock sources. |
mbed_official | 181:a4cbdfbbd2f4 | 902 | * |
mbed_official | 181:a4cbdfbbd2f4 | 903 | * @param __HSI48MCLKSource__: specifies the HSI48M clock source dedicated for |
mbed_official | 181:a4cbdfbbd2f4 | 904 | * USB an RNG peripherals. |
mbed_official | 181:a4cbdfbbd2f4 | 905 | * This parameter can be one of the following values: |
mbed_official | 181:a4cbdfbbd2f4 | 906 | * @arg RCC_HSI48M_PLL: A dedicated 48MHZ PLL output. |
mbed_official | 181:a4cbdfbbd2f4 | 907 | * @arg RCC_HSI48M_RC48: 48MHZ issued from internal HSI48 oscillator. |
mbed_official | 181:a4cbdfbbd2f4 | 908 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 909 | #define __HAL_RCC_HSI48M_CONFIG(__HSI48MCLKSource__) \ |
mbed_official | 181:a4cbdfbbd2f4 | 910 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, (uint32_t)(__HSI48MCLKSource__)) |
mbed_official | 181:a4cbdfbbd2f4 | 911 | |
mbed_official | 181:a4cbdfbbd2f4 | 912 | /** @brief macro to get the HSI48M clock source. |
mbed_official | 181:a4cbdfbbd2f4 | 913 | * @note This macro can be replaced by either __HAL_RCC_GET_RNG_SOURCE or |
mbed_official | 181:a4cbdfbbd2f4 | 914 | * __HAL_RCC_GET_USB_SOURCE to get respectively RNG or UBS clock sources. |
mbed_official | 181:a4cbdfbbd2f4 | 915 | * @retval The clock source can be one of the following values: |
mbed_official | 181:a4cbdfbbd2f4 | 916 | * @arg RCC_HSI48M_PLL: A dedicated 48MHZ PLL output. |
mbed_official | 181:a4cbdfbbd2f4 | 917 | * @arg RCC_HSI48M_RC48: 48MHZ issued from internal HSI48 oscillator. |
mbed_official | 181:a4cbdfbbd2f4 | 918 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 919 | #define __HAL_RCC_GET_HSI48M_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_HSI48SEL))) |
mbed_official | 181:a4cbdfbbd2f4 | 920 | #endif /* !(STM32L051xx ) && !(STM32L061xx ) */ |
mbed_official | 181:a4cbdfbbd2f4 | 921 | |
mbed_official | 181:a4cbdfbbd2f4 | 922 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 923 | * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI) |
mbed_official | 181:a4cbdfbbd2f4 | 924 | * in STOP mode to be quickly available as kernel clock for USART and I2C. |
mbed_official | 181:a4cbdfbbd2f4 | 925 | * @note The Enable of this function has not effect on the HSION bit. |
mbed_official | 181:a4cbdfbbd2f4 | 926 | * This parameter can be: ENABLE or DISABLE. |
mbed_official | 181:a4cbdfbbd2f4 | 927 | * @retval None |
mbed_official | 181:a4cbdfbbd2f4 | 928 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 929 | #define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON) |
mbed_official | 181:a4cbdfbbd2f4 | 930 | #define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON) |
mbed_official | 181:a4cbdfbbd2f4 | 931 | |
mbed_official | 181:a4cbdfbbd2f4 | 932 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 933 | * @brief Macro to configures the External Low Speed oscillator (LSE) drive capability. |
mbed_official | 181:a4cbdfbbd2f4 | 934 | * @param RCC_LSEDrive: specifies the new state of the LSE drive capability. |
mbed_official | 181:a4cbdfbbd2f4 | 935 | * This parameter can be one of the following values: |
mbed_official | 181:a4cbdfbbd2f4 | 936 | * @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability. |
mbed_official | 181:a4cbdfbbd2f4 | 937 | * @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability. |
mbed_official | 181:a4cbdfbbd2f4 | 938 | * @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability. |
mbed_official | 181:a4cbdfbbd2f4 | 939 | * @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability. |
mbed_official | 181:a4cbdfbbd2f4 | 940 | * @retval None |
mbed_official | 181:a4cbdfbbd2f4 | 941 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 942 | #define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDrive__) (MODIFY_REG(RCC->CSR,\ |
mbed_official | 181:a4cbdfbbd2f4 | 943 | RCC_CSR_LSEDRV, (uint32_t)(__RCC_LSEDrive__) )) |
mbed_official | 181:a4cbdfbbd2f4 | 944 | |
mbed_official | 181:a4cbdfbbd2f4 | 945 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 946 | * @brief Macro to configures the wake up from stop clock. |
mbed_official | 181:a4cbdfbbd2f4 | 947 | * @param RCC_STOPWUCLK: specifies the clock source used after wake up from stop |
mbed_official | 181:a4cbdfbbd2f4 | 948 | * This parameter can be one of the following values: |
mbed_official | 181:a4cbdfbbd2f4 | 949 | * @arg RCC_StopWakeUpClock_MSI: MSI selected as system clock source |
mbed_official | 181:a4cbdfbbd2f4 | 950 | * @arg RCC_StopWakeUpClock_HSI: HSI selected as system clock source |
mbed_official | 181:a4cbdfbbd2f4 | 951 | * @retval None |
mbed_official | 181:a4cbdfbbd2f4 | 952 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 953 | #define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__RCC_STOPWUCLK__) (MODIFY_REG(RCC->CFGR,\ |
mbed_official | 181:a4cbdfbbd2f4 | 954 | RCC_CFGR_STOPWUCK, (uint32_t)(__RCC_STOPWUCLK__) )) |
mbed_official | 181:a4cbdfbbd2f4 | 955 | |
mbed_official | 181:a4cbdfbbd2f4 | 956 | #if !defined(STM32L051xx) && !defined(STM32L061xx) |
mbed_official | 181:a4cbdfbbd2f4 | 957 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 958 | * @brief Enables the specified CRS interrupts. |
mbed_official | 181:a4cbdfbbd2f4 | 959 | * @param __INTERRUPT__: specifies the CRS interrupt sources to be enabled. |
mbed_official | 181:a4cbdfbbd2f4 | 960 | * This parameter can be any combination of the following values: |
mbed_official | 181:a4cbdfbbd2f4 | 961 | * @arg RCC_CRS_IT_SYNCOK |
mbed_official | 181:a4cbdfbbd2f4 | 962 | * @arg RCC_CRS_IT_SYNCWARN |
mbed_official | 181:a4cbdfbbd2f4 | 963 | * @arg RCC_CRS_IT_ERR |
mbed_official | 181:a4cbdfbbd2f4 | 964 | * @arg RCC_CRS_IT_ESYNC |
mbed_official | 181:a4cbdfbbd2f4 | 965 | * @retval None |
mbed_official | 181:a4cbdfbbd2f4 | 966 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 967 | #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) (CRS->CR |= (__INTERRUPT__)) |
mbed_official | 181:a4cbdfbbd2f4 | 968 | |
mbed_official | 181:a4cbdfbbd2f4 | 969 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 970 | * @brief Disables the specified CRS interrupts. |
mbed_official | 181:a4cbdfbbd2f4 | 971 | * @param __INTERRUPT__: specifies the CRS interrupt sources to be disabled. |
mbed_official | 181:a4cbdfbbd2f4 | 972 | * This parameter can be any combination of the following values: |
mbed_official | 181:a4cbdfbbd2f4 | 973 | * @arg RCC_CRS_IT_SYNCOK |
mbed_official | 181:a4cbdfbbd2f4 | 974 | * @arg RCC_CRS_IT_SYNCWARN |
mbed_official | 181:a4cbdfbbd2f4 | 975 | * @arg RCC_CRS_IT_ERR |
mbed_official | 181:a4cbdfbbd2f4 | 976 | * @arg RCC_CRS_IT_ESYNC |
mbed_official | 181:a4cbdfbbd2f4 | 977 | * @retval None |
mbed_official | 181:a4cbdfbbd2f4 | 978 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 979 | #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) (CRS->CR &= ~(__INTERRUPT__)) |
mbed_official | 181:a4cbdfbbd2f4 | 980 | |
mbed_official | 181:a4cbdfbbd2f4 | 981 | /** @brief Check the CRS's interrupt has occurred or not. |
mbed_official | 181:a4cbdfbbd2f4 | 982 | * @param __INTERRUPT__: specifies the CRS interrupt source to check. |
mbed_official | 181:a4cbdfbbd2f4 | 983 | * This parameter can be one of the following values: |
mbed_official | 181:a4cbdfbbd2f4 | 984 | * @arg RCC_CRS_IT_SYNCOK |
mbed_official | 181:a4cbdfbbd2f4 | 985 | * @arg RCC_CRS_IT_SYNCWARN |
mbed_official | 181:a4cbdfbbd2f4 | 986 | * @arg RCC_CRS_IT_ERR |
mbed_official | 181:a4cbdfbbd2f4 | 987 | * @arg RCC_CRS_IT_ESYNC |
mbed_official | 181:a4cbdfbbd2f4 | 988 | * @retval The new state of __INTERRUPT__ (SET or RESET). |
mbed_official | 181:a4cbdfbbd2f4 | 989 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 990 | #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((CRS->CR & (__INTERRUPT__))? SET : RESET) |
mbed_official | 181:a4cbdfbbd2f4 | 991 | |
mbed_official | 181:a4cbdfbbd2f4 | 992 | /** @brief Clear the CRS's interrupt pending bits |
mbed_official | 181:a4cbdfbbd2f4 | 993 | * bits to clear the selected interrupt pending bits. |
mbed_official | 181:a4cbdfbbd2f4 | 994 | * @param __INTERRUPT__: specifies the interrupt pending bit to clear. |
mbed_official | 181:a4cbdfbbd2f4 | 995 | * This parameter can be any combination of the following values: |
mbed_official | 181:a4cbdfbbd2f4 | 996 | * @arg RCC_CRS_IT_SYNCOK |
mbed_official | 181:a4cbdfbbd2f4 | 997 | * @arg RCC_CRS_IT_SYNCWARN |
mbed_official | 181:a4cbdfbbd2f4 | 998 | * @arg RCC_CRS_IT_ERR |
mbed_official | 181:a4cbdfbbd2f4 | 999 | * @arg RCC_CRS_IT_ESYNC |
mbed_official | 181:a4cbdfbbd2f4 | 1000 | * @arg RCC_CRS_IT_TRIMOVF |
mbed_official | 181:a4cbdfbbd2f4 | 1001 | * @arg RCC_CRS_IT_SYNCERR |
mbed_official | 181:a4cbdfbbd2f4 | 1002 | * @arg RCC_CRS_IT_SYNCMISS |
mbed_official | 181:a4cbdfbbd2f4 | 1003 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 1004 | /* CRS IT Error Mask */ |
mbed_official | 181:a4cbdfbbd2f4 | 1005 | #define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)) |
mbed_official | 181:a4cbdfbbd2f4 | 1006 | |
mbed_official | 181:a4cbdfbbd2f4 | 1007 | #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) ((((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK)!= 0) ? (CRS->ICR |= CRS_ICR_ERRC) : \ |
mbed_official | 181:a4cbdfbbd2f4 | 1008 | (CRS->ICR |= (__INTERRUPT__))) |
mbed_official | 181:a4cbdfbbd2f4 | 1009 | |
mbed_official | 181:a4cbdfbbd2f4 | 1010 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 1011 | * @brief Checks whether the specified CRS flag is set or not. |
mbed_official | 181:a4cbdfbbd2f4 | 1012 | * @param _FLAG_: specifies the flag to check. |
mbed_official | 181:a4cbdfbbd2f4 | 1013 | * This parameter can be one of the following values: |
mbed_official | 181:a4cbdfbbd2f4 | 1014 | * @arg RCC_CRS_FLAG_SYNCOK |
mbed_official | 181:a4cbdfbbd2f4 | 1015 | * @arg RCC_CRS_FLAG_SYNCWARN |
mbed_official | 181:a4cbdfbbd2f4 | 1016 | * @arg RCC_CRS_FLAG_ERR |
mbed_official | 181:a4cbdfbbd2f4 | 1017 | * @arg RCC_CRS_FLAG_ESYNC |
mbed_official | 181:a4cbdfbbd2f4 | 1018 | * @arg RCC_CRS_FLAG_TRIMOVF |
mbed_official | 181:a4cbdfbbd2f4 | 1019 | * @arg RCC_CRS_FLAG_SYNCERR |
mbed_official | 181:a4cbdfbbd2f4 | 1020 | * @arg RCC_CRS_FLAG_SYNCMISS |
mbed_official | 181:a4cbdfbbd2f4 | 1021 | * @retval The new state of _FLAG_ (TRUE or FALSE). |
mbed_official | 181:a4cbdfbbd2f4 | 1022 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 1023 | #define __HAL_RCC_CRS_GET_FLAG(_FLAG_) ((CRS->ISR & (_FLAG_)) == (_FLAG_)) |
mbed_official | 181:a4cbdfbbd2f4 | 1024 | |
mbed_official | 181:a4cbdfbbd2f4 | 1025 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 1026 | * @brief Clears the CRS specified FLAG. |
mbed_official | 181:a4cbdfbbd2f4 | 1027 | * @param _FLAG_: specifies the flag to clear. |
mbed_official | 181:a4cbdfbbd2f4 | 1028 | * This parameter can be one of the following values: |
mbed_official | 181:a4cbdfbbd2f4 | 1029 | * @arg RCC_CRS_FLAG_SYNCOK |
mbed_official | 181:a4cbdfbbd2f4 | 1030 | * @arg RCC_CRS_FLAG_SYNCWARN |
mbed_official | 181:a4cbdfbbd2f4 | 1031 | * @arg RCC_CRS_FLAG_ERR |
mbed_official | 181:a4cbdfbbd2f4 | 1032 | * @arg RCC_CRS_FLAG_ESYNC |
mbed_official | 181:a4cbdfbbd2f4 | 1033 | * @arg RCC_CRS_FLAG_TRIMOVF |
mbed_official | 181:a4cbdfbbd2f4 | 1034 | * @arg RCC_CRS_FLAG_SYNCERR |
mbed_official | 181:a4cbdfbbd2f4 | 1035 | * @arg RCC_CRS_FLAG_SYNCMISS |
mbed_official | 181:a4cbdfbbd2f4 | 1036 | * @retval None |
mbed_official | 181:a4cbdfbbd2f4 | 1037 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 1038 | |
mbed_official | 181:a4cbdfbbd2f4 | 1039 | /* CRS Flag Error Mask */ |
mbed_official | 181:a4cbdfbbd2f4 | 1040 | #define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)) |
mbed_official | 181:a4cbdfbbd2f4 | 1041 | |
mbed_official | 181:a4cbdfbbd2f4 | 1042 | #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) ((((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK)!= 0) ? (CRS->ICR |= CRS_ICR_ERRC) : \ |
mbed_official | 181:a4cbdfbbd2f4 | 1043 | (CRS->ICR |= (__FLAG__))) |
mbed_official | 181:a4cbdfbbd2f4 | 1044 | |
mbed_official | 181:a4cbdfbbd2f4 | 1045 | |
mbed_official | 181:a4cbdfbbd2f4 | 1046 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 1047 | * @brief Enables the oscillator clock for frequency error counter. |
mbed_official | 181:a4cbdfbbd2f4 | 1048 | * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. |
mbed_official | 181:a4cbdfbbd2f4 | 1049 | * @param None |
mbed_official | 181:a4cbdfbbd2f4 | 1050 | * @retval None |
mbed_official | 181:a4cbdfbbd2f4 | 1051 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 1052 | #define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER() (CRS->CR |= CRS_CR_CEN) |
mbed_official | 181:a4cbdfbbd2f4 | 1053 | |
mbed_official | 181:a4cbdfbbd2f4 | 1054 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 1055 | * @brief Disables the oscillator clock for frequency error counter. |
mbed_official | 181:a4cbdfbbd2f4 | 1056 | * @param None |
mbed_official | 181:a4cbdfbbd2f4 | 1057 | * @retval None |
mbed_official | 181:a4cbdfbbd2f4 | 1058 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 1059 | #define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER() (CRS->CR &= ~CRS_CR_CEN) |
mbed_official | 181:a4cbdfbbd2f4 | 1060 | |
mbed_official | 181:a4cbdfbbd2f4 | 1061 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 1062 | * @brief Enables the automatic hardware adjustment of TRIM bits. |
mbed_official | 181:a4cbdfbbd2f4 | 1063 | * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. |
mbed_official | 181:a4cbdfbbd2f4 | 1064 | * @param None |
mbed_official | 181:a4cbdfbbd2f4 | 1065 | * @retval None |
mbed_official | 181:a4cbdfbbd2f4 | 1066 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 1067 | #define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB() (CRS->CR |= CRS_CR_AUTOTRIMEN) |
mbed_official | 181:a4cbdfbbd2f4 | 1068 | |
mbed_official | 181:a4cbdfbbd2f4 | 1069 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 1070 | * @brief Enables or disables the automatic hardware adjustment of TRIM bits. |
mbed_official | 181:a4cbdfbbd2f4 | 1071 | * @param None |
mbed_official | 181:a4cbdfbbd2f4 | 1072 | * @retval None |
mbed_official | 181:a4cbdfbbd2f4 | 1073 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 1074 | #define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB() (CRS->CR &= ~CRS_CR_AUTOTRIMEN) |
mbed_official | 181:a4cbdfbbd2f4 | 1075 | |
mbed_official | 181:a4cbdfbbd2f4 | 1076 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 1077 | * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies |
mbed_official | 181:a4cbdfbbd2f4 | 1078 | * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency |
mbed_official | 181:a4cbdfbbd2f4 | 1079 | * of the synchronization source after prescaling. It is then decreased by one in order to |
mbed_official | 181:a4cbdfbbd2f4 | 1080 | * reach the expected synchronization on the zero value. The formula is the following: |
mbed_official | 181:a4cbdfbbd2f4 | 1081 | * RELOAD = (fTARGET / fSYNC) -1 |
mbed_official | 181:a4cbdfbbd2f4 | 1082 | * @param _FTARGET_ Target frequency (value in Hz) |
mbed_official | 181:a4cbdfbbd2f4 | 1083 | * @param _FSYNC_ Synchronization signal frequency (value in Hz) |
mbed_official | 181:a4cbdfbbd2f4 | 1084 | * @retval None |
mbed_official | 181:a4cbdfbbd2f4 | 1085 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 1086 | #define __HAL_RCC_CRS_CALCULATE_RELOADVALUE(_FTARGET_, _FSYNC_) (((_FTARGET_) / (_FSYNC_)) - 1) |
mbed_official | 181:a4cbdfbbd2f4 | 1087 | |
mbed_official | 181:a4cbdfbbd2f4 | 1088 | #endif /* !(STM32L051xx) && !(STM32L061xx) */ |
mbed_official | 181:a4cbdfbbd2f4 | 1089 | |
mbed_official | 181:a4cbdfbbd2f4 | 1090 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 1091 | * @} |
mbed_official | 181:a4cbdfbbd2f4 | 1092 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 1093 | |
mbed_official | 181:a4cbdfbbd2f4 | 1094 | |
mbed_official | 181:a4cbdfbbd2f4 | 1095 | /* Exported functions --------------------------------------------------------*/ |
mbed_official | 181:a4cbdfbbd2f4 | 1096 | HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); |
mbed_official | 181:a4cbdfbbd2f4 | 1097 | void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); |
mbed_official | 181:a4cbdfbbd2f4 | 1098 | void HAL_RCCEx_EnableLSECSS(void); |
mbed_official | 181:a4cbdfbbd2f4 | 1099 | void HAL_RCCEx_DisableLSECSS(void); |
mbed_official | 181:a4cbdfbbd2f4 | 1100 | #if !defined(STM32L051xx) && !defined(STM32L061xx) |
mbed_official | 181:a4cbdfbbd2f4 | 1101 | void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit); |
mbed_official | 181:a4cbdfbbd2f4 | 1102 | void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); |
mbed_official | 181:a4cbdfbbd2f4 | 1103 | void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); |
mbed_official | 181:a4cbdfbbd2f4 | 1104 | RCC_CRSStatusTypeDef HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); |
mbed_official | 181:a4cbdfbbd2f4 | 1105 | #endif /* !(STM32L051xx) && !(STM32L061xx) */ |
mbed_official | 181:a4cbdfbbd2f4 | 1106 | |
mbed_official | 181:a4cbdfbbd2f4 | 1107 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 1108 | * @} |
mbed_official | 181:a4cbdfbbd2f4 | 1109 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 1110 | |
mbed_official | 181:a4cbdfbbd2f4 | 1111 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 1112 | * @} |
mbed_official | 181:a4cbdfbbd2f4 | 1113 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 1114 | |
mbed_official | 181:a4cbdfbbd2f4 | 1115 | #ifdef __cplusplus |
mbed_official | 181:a4cbdfbbd2f4 | 1116 | } |
mbed_official | 181:a4cbdfbbd2f4 | 1117 | #endif |
mbed_official | 181:a4cbdfbbd2f4 | 1118 | |
mbed_official | 181:a4cbdfbbd2f4 | 1119 | #endif /* __STM32L0xx_HAL_RCC_EX_H */ |
mbed_official | 181:a4cbdfbbd2f4 | 1120 | |
mbed_official | 181:a4cbdfbbd2f4 | 1121 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |