Janek Mann
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targets/cmsis/TARGET_STM/TARGET_NUCLEO_F411RE/stm32f4xx_hal_dma.h@310:6188e0254baa, 2014-09-16 (annotated)
- Committer:
- janekm
- Date:
- Tue Sep 16 22:42:01 2014 +0000
- Revision:
- 310:6188e0254baa
- Parent:
- 235:685d5f11838f
N/A
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 235:685d5f11838f | 1 | /** |
| mbed_official | 235:685d5f11838f | 2 | ****************************************************************************** |
| mbed_official | 235:685d5f11838f | 3 | * @file stm32f4xx_hal_dma.h |
| mbed_official | 235:685d5f11838f | 4 | * @author MCD Application Team |
| mbed_official | 235:685d5f11838f | 5 | * @version V1.1.0 |
| mbed_official | 235:685d5f11838f | 6 | * @date 19-June-2014 |
| mbed_official | 235:685d5f11838f | 7 | * @brief Header file of DMA HAL module. |
| mbed_official | 235:685d5f11838f | 8 | ****************************************************************************** |
| mbed_official | 235:685d5f11838f | 9 | * @attention |
| mbed_official | 235:685d5f11838f | 10 | * |
| mbed_official | 235:685d5f11838f | 11 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
| mbed_official | 235:685d5f11838f | 12 | * |
| mbed_official | 235:685d5f11838f | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| mbed_official | 235:685d5f11838f | 14 | * are permitted provided that the following conditions are met: |
| mbed_official | 235:685d5f11838f | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| mbed_official | 235:685d5f11838f | 16 | * this list of conditions and the following disclaimer. |
| mbed_official | 235:685d5f11838f | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| mbed_official | 235:685d5f11838f | 18 | * this list of conditions and the following disclaimer in the documentation |
| mbed_official | 235:685d5f11838f | 19 | * and/or other materials provided with the distribution. |
| mbed_official | 235:685d5f11838f | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| mbed_official | 235:685d5f11838f | 21 | * may be used to endorse or promote products derived from this software |
| mbed_official | 235:685d5f11838f | 22 | * without specific prior written permission. |
| mbed_official | 235:685d5f11838f | 23 | * |
| mbed_official | 235:685d5f11838f | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| mbed_official | 235:685d5f11838f | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| mbed_official | 235:685d5f11838f | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| mbed_official | 235:685d5f11838f | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| mbed_official | 235:685d5f11838f | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| mbed_official | 235:685d5f11838f | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| mbed_official | 235:685d5f11838f | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| mbed_official | 235:685d5f11838f | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| mbed_official | 235:685d5f11838f | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| mbed_official | 235:685d5f11838f | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 235:685d5f11838f | 34 | * |
| mbed_official | 235:685d5f11838f | 35 | ****************************************************************************** |
| mbed_official | 235:685d5f11838f | 36 | */ |
| mbed_official | 235:685d5f11838f | 37 | |
| mbed_official | 235:685d5f11838f | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| mbed_official | 235:685d5f11838f | 39 | #ifndef __STM32F4xx_HAL_DMA_H |
| mbed_official | 235:685d5f11838f | 40 | #define __STM32F4xx_HAL_DMA_H |
| mbed_official | 235:685d5f11838f | 41 | |
| mbed_official | 235:685d5f11838f | 42 | #ifdef __cplusplus |
| mbed_official | 235:685d5f11838f | 43 | extern "C" { |
| mbed_official | 235:685d5f11838f | 44 | #endif |
| mbed_official | 235:685d5f11838f | 45 | |
| mbed_official | 235:685d5f11838f | 46 | /* Includes ------------------------------------------------------------------*/ |
| mbed_official | 235:685d5f11838f | 47 | #include "stm32f4xx_hal_def.h" |
| mbed_official | 235:685d5f11838f | 48 | |
| mbed_official | 235:685d5f11838f | 49 | /** @addtogroup STM32F4xx_HAL_Driver |
| mbed_official | 235:685d5f11838f | 50 | * @{ |
| mbed_official | 235:685d5f11838f | 51 | */ |
| mbed_official | 235:685d5f11838f | 52 | |
| mbed_official | 235:685d5f11838f | 53 | /** @addtogroup DMA |
| mbed_official | 235:685d5f11838f | 54 | * @{ |
| mbed_official | 235:685d5f11838f | 55 | */ |
| mbed_official | 235:685d5f11838f | 56 | |
| mbed_official | 235:685d5f11838f | 57 | /* Exported types ------------------------------------------------------------*/ |
| mbed_official | 235:685d5f11838f | 58 | |
| mbed_official | 235:685d5f11838f | 59 | /** |
| mbed_official | 235:685d5f11838f | 60 | * @brief DMA Configuration Structure definition |
| mbed_official | 235:685d5f11838f | 61 | */ |
| mbed_official | 235:685d5f11838f | 62 | typedef struct |
| mbed_official | 235:685d5f11838f | 63 | { |
| mbed_official | 235:685d5f11838f | 64 | uint32_t Channel; /*!< Specifies the channel used for the specified stream. |
| mbed_official | 235:685d5f11838f | 65 | This parameter can be a value of @ref DMA_Channel_selection */ |
| mbed_official | 235:685d5f11838f | 66 | |
| mbed_official | 235:685d5f11838f | 67 | uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, |
| mbed_official | 235:685d5f11838f | 68 | from memory to memory or from peripheral to memory. |
| mbed_official | 235:685d5f11838f | 69 | This parameter can be a value of @ref DMA_Data_transfer_direction */ |
| mbed_official | 235:685d5f11838f | 70 | |
| mbed_official | 235:685d5f11838f | 71 | uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. |
| mbed_official | 235:685d5f11838f | 72 | This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ |
| mbed_official | 235:685d5f11838f | 73 | |
| mbed_official | 235:685d5f11838f | 74 | uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. |
| mbed_official | 235:685d5f11838f | 75 | This parameter can be a value of @ref DMA_Memory_incremented_mode */ |
| mbed_official | 235:685d5f11838f | 76 | |
| mbed_official | 235:685d5f11838f | 77 | uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. |
| mbed_official | 235:685d5f11838f | 78 | This parameter can be a value of @ref DMA_Peripheral_data_size */ |
| mbed_official | 235:685d5f11838f | 79 | |
| mbed_official | 235:685d5f11838f | 80 | uint32_t MemDataAlignment; /*!< Specifies the Memory data width. |
| mbed_official | 235:685d5f11838f | 81 | This parameter can be a value of @ref DMA_Memory_data_size */ |
| mbed_official | 235:685d5f11838f | 82 | |
| mbed_official | 235:685d5f11838f | 83 | uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx. |
| mbed_official | 235:685d5f11838f | 84 | This parameter can be a value of @ref DMA_mode |
| mbed_official | 235:685d5f11838f | 85 | @note The circular buffer mode cannot be used if the memory-to-memory |
| mbed_official | 235:685d5f11838f | 86 | data transfer is configured on the selected Stream */ |
| mbed_official | 235:685d5f11838f | 87 | |
| mbed_official | 235:685d5f11838f | 88 | uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx. |
| mbed_official | 235:685d5f11838f | 89 | This parameter can be a value of @ref DMA_Priority_level */ |
| mbed_official | 235:685d5f11838f | 90 | |
| mbed_official | 235:685d5f11838f | 91 | uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream. |
| mbed_official | 235:685d5f11838f | 92 | This parameter can be a value of @ref DMA_FIFO_direct_mode |
| mbed_official | 235:685d5f11838f | 93 | @note The Direct mode (FIFO mode disabled) cannot be used if the |
| mbed_official | 235:685d5f11838f | 94 | memory-to-memory data transfer is configured on the selected stream */ |
| mbed_official | 235:685d5f11838f | 95 | |
| mbed_official | 235:685d5f11838f | 96 | uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level. |
| mbed_official | 235:685d5f11838f | 97 | This parameter can be a value of @ref DMA_FIFO_threshold_level */ |
| mbed_official | 235:685d5f11838f | 98 | |
| mbed_official | 235:685d5f11838f | 99 | uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. |
| mbed_official | 235:685d5f11838f | 100 | It specifies the amount of data to be transferred in a single non interruptable |
| mbed_official | 235:685d5f11838f | 101 | transaction. |
| mbed_official | 235:685d5f11838f | 102 | This parameter can be a value of @ref DMA_Memory_burst |
| mbed_official | 235:685d5f11838f | 103 | @note The burst mode is possible only if the address Increment mode is enabled. */ |
| mbed_official | 235:685d5f11838f | 104 | |
| mbed_official | 235:685d5f11838f | 105 | uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. |
| mbed_official | 235:685d5f11838f | 106 | It specifies the amount of data to be transferred in a single non interruptable |
| mbed_official | 235:685d5f11838f | 107 | transaction. |
| mbed_official | 235:685d5f11838f | 108 | This parameter can be a value of @ref DMA_Peripheral_burst |
| mbed_official | 235:685d5f11838f | 109 | @note The burst mode is possible only if the address Increment mode is enabled. */ |
| mbed_official | 235:685d5f11838f | 110 | }DMA_InitTypeDef; |
| mbed_official | 235:685d5f11838f | 111 | |
| mbed_official | 235:685d5f11838f | 112 | /** |
| mbed_official | 235:685d5f11838f | 113 | * @brief HAL DMA State structures definition |
| mbed_official | 235:685d5f11838f | 114 | */ |
| mbed_official | 235:685d5f11838f | 115 | typedef enum |
| mbed_official | 235:685d5f11838f | 116 | { |
| mbed_official | 235:685d5f11838f | 117 | HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */ |
| mbed_official | 235:685d5f11838f | 118 | HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */ |
| mbed_official | 235:685d5f11838f | 119 | HAL_DMA_STATE_READY_MEM0 = 0x11, /*!< DMA Mem0 process success */ |
| mbed_official | 235:685d5f11838f | 120 | HAL_DMA_STATE_READY_MEM1 = 0x21, /*!< DMA Mem1 process success */ |
| mbed_official | 235:685d5f11838f | 121 | HAL_DMA_STATE_READY_HALF_MEM0 = 0x31, /*!< DMA Mem0 Half process success */ |
| mbed_official | 235:685d5f11838f | 122 | HAL_DMA_STATE_READY_HALF_MEM1 = 0x41, /*!< DMA Mem1 Half process success */ |
| mbed_official | 235:685d5f11838f | 123 | HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */ |
| mbed_official | 235:685d5f11838f | 124 | HAL_DMA_STATE_BUSY_MEM0 = 0x12, /*!< DMA Mem0 process is ongoing */ |
| mbed_official | 235:685d5f11838f | 125 | HAL_DMA_STATE_BUSY_MEM1 = 0x22, /*!< DMA Mem1 process is ongoing */ |
| mbed_official | 235:685d5f11838f | 126 | HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */ |
| mbed_official | 235:685d5f11838f | 127 | HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */ |
| mbed_official | 235:685d5f11838f | 128 | }HAL_DMA_StateTypeDef; |
| mbed_official | 235:685d5f11838f | 129 | |
| mbed_official | 235:685d5f11838f | 130 | /** |
| mbed_official | 235:685d5f11838f | 131 | * @brief HAL DMA Error Code structure definition |
| mbed_official | 235:685d5f11838f | 132 | */ |
| mbed_official | 235:685d5f11838f | 133 | typedef enum |
| mbed_official | 235:685d5f11838f | 134 | { |
| mbed_official | 235:685d5f11838f | 135 | HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */ |
| mbed_official | 235:685d5f11838f | 136 | HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */ |
| mbed_official | 235:685d5f11838f | 137 | }HAL_DMA_LevelCompleteTypeDef; |
| mbed_official | 235:685d5f11838f | 138 | |
| mbed_official | 235:685d5f11838f | 139 | /** |
| mbed_official | 235:685d5f11838f | 140 | * @brief DMA handle Structure definition |
| mbed_official | 235:685d5f11838f | 141 | */ |
| mbed_official | 235:685d5f11838f | 142 | typedef struct __DMA_HandleTypeDef |
| mbed_official | 235:685d5f11838f | 143 | { |
| mbed_official | 235:685d5f11838f | 144 | DMA_Stream_TypeDef *Instance; /*!< Register base address */ |
| mbed_official | 235:685d5f11838f | 145 | |
| mbed_official | 235:685d5f11838f | 146 | DMA_InitTypeDef Init; /*!< DMA communication parameters */ |
| mbed_official | 235:685d5f11838f | 147 | |
| mbed_official | 235:685d5f11838f | 148 | HAL_LockTypeDef Lock; /*!< DMA locking object */ |
| mbed_official | 235:685d5f11838f | 149 | |
| mbed_official | 235:685d5f11838f | 150 | __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ |
| mbed_official | 235:685d5f11838f | 151 | |
| mbed_official | 235:685d5f11838f | 152 | void *Parent; /*!< Parent object state */ |
| mbed_official | 235:685d5f11838f | 153 | |
| mbed_official | 235:685d5f11838f | 154 | void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ |
| mbed_official | 235:685d5f11838f | 155 | |
| mbed_official | 235:685d5f11838f | 156 | void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ |
| mbed_official | 235:685d5f11838f | 157 | |
| mbed_official | 235:685d5f11838f | 158 | void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */ |
| mbed_official | 235:685d5f11838f | 159 | |
| mbed_official | 235:685d5f11838f | 160 | void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ |
| mbed_official | 235:685d5f11838f | 161 | |
| mbed_official | 235:685d5f11838f | 162 | __IO uint32_t ErrorCode; /*!< DMA Error code */ |
| mbed_official | 235:685d5f11838f | 163 | }DMA_HandleTypeDef; |
| mbed_official | 235:685d5f11838f | 164 | |
| mbed_official | 235:685d5f11838f | 165 | /* Exported constants --------------------------------------------------------*/ |
| mbed_official | 235:685d5f11838f | 166 | |
| mbed_official | 235:685d5f11838f | 167 | /** @defgroup DMA_Exported_Constants |
| mbed_official | 235:685d5f11838f | 168 | * @{ |
| mbed_official | 235:685d5f11838f | 169 | */ |
| mbed_official | 235:685d5f11838f | 170 | |
| mbed_official | 235:685d5f11838f | 171 | /** @defgroup DMA_Error_Code |
| mbed_official | 235:685d5f11838f | 172 | * @{ |
| mbed_official | 235:685d5f11838f | 173 | */ |
| mbed_official | 235:685d5f11838f | 174 | #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ |
| mbed_official | 235:685d5f11838f | 175 | #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */ |
| mbed_official | 235:685d5f11838f | 176 | #define HAL_DMA_ERROR_FE ((uint32_t)0x00000002) /*!< FIFO error */ |
| mbed_official | 235:685d5f11838f | 177 | #define HAL_DMA_ERROR_DME ((uint32_t)0x00000004) /*!< Direct Mode error */ |
| mbed_official | 235:685d5f11838f | 178 | #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */ |
| mbed_official | 235:685d5f11838f | 179 | /** |
| mbed_official | 235:685d5f11838f | 180 | * @} |
| mbed_official | 235:685d5f11838f | 181 | */ |
| mbed_official | 235:685d5f11838f | 182 | |
| mbed_official | 235:685d5f11838f | 183 | /** @defgroup DMA_Channel_selection |
| mbed_official | 235:685d5f11838f | 184 | * @{ |
| mbed_official | 235:685d5f11838f | 185 | */ |
| mbed_official | 235:685d5f11838f | 186 | #define DMA_CHANNEL_0 ((uint32_t)0x00000000) /*!< DMA Channel 0 */ |
| mbed_official | 235:685d5f11838f | 187 | #define DMA_CHANNEL_1 ((uint32_t)0x02000000) /*!< DMA Channel 1 */ |
| mbed_official | 235:685d5f11838f | 188 | #define DMA_CHANNEL_2 ((uint32_t)0x04000000) /*!< DMA Channel 2 */ |
| mbed_official | 235:685d5f11838f | 189 | #define DMA_CHANNEL_3 ((uint32_t)0x06000000) /*!< DMA Channel 3 */ |
| mbed_official | 235:685d5f11838f | 190 | #define DMA_CHANNEL_4 ((uint32_t)0x08000000) /*!< DMA Channel 4 */ |
| mbed_official | 235:685d5f11838f | 191 | #define DMA_CHANNEL_5 ((uint32_t)0x0A000000) /*!< DMA Channel 5 */ |
| mbed_official | 235:685d5f11838f | 192 | #define DMA_CHANNEL_6 ((uint32_t)0x0C000000) /*!< DMA Channel 6 */ |
| mbed_official | 235:685d5f11838f | 193 | #define DMA_CHANNEL_7 ((uint32_t)0x0E000000) /*!< DMA Channel 7 */ |
| mbed_official | 235:685d5f11838f | 194 | |
| mbed_official | 235:685d5f11838f | 195 | #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \ |
| mbed_official | 235:685d5f11838f | 196 | ((CHANNEL) == DMA_CHANNEL_1) || \ |
| mbed_official | 235:685d5f11838f | 197 | ((CHANNEL) == DMA_CHANNEL_2) || \ |
| mbed_official | 235:685d5f11838f | 198 | ((CHANNEL) == DMA_CHANNEL_3) || \ |
| mbed_official | 235:685d5f11838f | 199 | ((CHANNEL) == DMA_CHANNEL_4) || \ |
| mbed_official | 235:685d5f11838f | 200 | ((CHANNEL) == DMA_CHANNEL_5) || \ |
| mbed_official | 235:685d5f11838f | 201 | ((CHANNEL) == DMA_CHANNEL_6) || \ |
| mbed_official | 235:685d5f11838f | 202 | ((CHANNEL) == DMA_CHANNEL_7)) |
| mbed_official | 235:685d5f11838f | 203 | /** |
| mbed_official | 235:685d5f11838f | 204 | * @} |
| mbed_official | 235:685d5f11838f | 205 | */ |
| mbed_official | 235:685d5f11838f | 206 | |
| mbed_official | 235:685d5f11838f | 207 | /** @defgroup DMA_Data_transfer_direction |
| mbed_official | 235:685d5f11838f | 208 | * @{ |
| mbed_official | 235:685d5f11838f | 209 | */ |
| mbed_official | 235:685d5f11838f | 210 | #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */ |
| mbed_official | 235:685d5f11838f | 211 | #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */ |
| mbed_official | 235:685d5f11838f | 212 | #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */ |
| mbed_official | 235:685d5f11838f | 213 | |
| mbed_official | 235:685d5f11838f | 214 | #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ |
| mbed_official | 235:685d5f11838f | 215 | ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ |
| mbed_official | 235:685d5f11838f | 216 | ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) |
| mbed_official | 235:685d5f11838f | 217 | /** |
| mbed_official | 235:685d5f11838f | 218 | * @} |
| mbed_official | 235:685d5f11838f | 219 | */ |
| mbed_official | 235:685d5f11838f | 220 | |
| mbed_official | 235:685d5f11838f | 221 | /** @defgroup DMA_Data_buffer_size |
| mbed_official | 235:685d5f11838f | 222 | * @{ |
| mbed_official | 235:685d5f11838f | 223 | */ |
| mbed_official | 235:685d5f11838f | 224 | #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) |
| mbed_official | 235:685d5f11838f | 225 | /** |
| mbed_official | 235:685d5f11838f | 226 | * @} |
| mbed_official | 235:685d5f11838f | 227 | */ |
| mbed_official | 235:685d5f11838f | 228 | |
| mbed_official | 235:685d5f11838f | 229 | /** @defgroup DMA_Peripheral_incremented_mode |
| mbed_official | 235:685d5f11838f | 230 | * @{ |
| mbed_official | 235:685d5f11838f | 231 | */ |
| mbed_official | 235:685d5f11838f | 232 | #define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */ |
| mbed_official | 235:685d5f11838f | 233 | #define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode disable */ |
| mbed_official | 235:685d5f11838f | 234 | |
| mbed_official | 235:685d5f11838f | 235 | #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ |
| mbed_official | 235:685d5f11838f | 236 | ((STATE) == DMA_PINC_DISABLE)) |
| mbed_official | 235:685d5f11838f | 237 | /** |
| mbed_official | 235:685d5f11838f | 238 | * @} |
| mbed_official | 235:685d5f11838f | 239 | */ |
| mbed_official | 235:685d5f11838f | 240 | |
| mbed_official | 235:685d5f11838f | 241 | /** @defgroup DMA_Memory_incremented_mode |
| mbed_official | 235:685d5f11838f | 242 | * @{ |
| mbed_official | 235:685d5f11838f | 243 | */ |
| mbed_official | 235:685d5f11838f | 244 | #define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */ |
| mbed_official | 235:685d5f11838f | 245 | #define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode disable */ |
| mbed_official | 235:685d5f11838f | 246 | |
| mbed_official | 235:685d5f11838f | 247 | #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ |
| mbed_official | 235:685d5f11838f | 248 | ((STATE) == DMA_MINC_DISABLE)) |
| mbed_official | 235:685d5f11838f | 249 | /** |
| mbed_official | 235:685d5f11838f | 250 | * @} |
| mbed_official | 235:685d5f11838f | 251 | */ |
| mbed_official | 235:685d5f11838f | 252 | |
| mbed_official | 235:685d5f11838f | 253 | /** @defgroup DMA_Peripheral_data_size |
| mbed_official | 235:685d5f11838f | 254 | * @{ |
| mbed_official | 235:685d5f11838f | 255 | */ |
| mbed_official | 235:685d5f11838f | 256 | #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment: Byte */ |
| mbed_official | 235:685d5f11838f | 257 | #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */ |
| mbed_official | 235:685d5f11838f | 258 | #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */ |
| mbed_official | 235:685d5f11838f | 259 | |
| mbed_official | 235:685d5f11838f | 260 | #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ |
| mbed_official | 235:685d5f11838f | 261 | ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ |
| mbed_official | 235:685d5f11838f | 262 | ((SIZE) == DMA_PDATAALIGN_WORD)) |
| mbed_official | 235:685d5f11838f | 263 | /** |
| mbed_official | 235:685d5f11838f | 264 | * @} |
| mbed_official | 235:685d5f11838f | 265 | */ |
| mbed_official | 235:685d5f11838f | 266 | |
| mbed_official | 235:685d5f11838f | 267 | |
| mbed_official | 235:685d5f11838f | 268 | /** @defgroup DMA_Memory_data_size |
| mbed_official | 235:685d5f11838f | 269 | * @{ |
| mbed_official | 235:685d5f11838f | 270 | */ |
| mbed_official | 235:685d5f11838f | 271 | #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment: Byte */ |
| mbed_official | 235:685d5f11838f | 272 | #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */ |
| mbed_official | 235:685d5f11838f | 273 | #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */ |
| mbed_official | 235:685d5f11838f | 274 | |
| mbed_official | 235:685d5f11838f | 275 | #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ |
| mbed_official | 235:685d5f11838f | 276 | ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ |
| mbed_official | 235:685d5f11838f | 277 | ((SIZE) == DMA_MDATAALIGN_WORD )) |
| mbed_official | 235:685d5f11838f | 278 | /** |
| mbed_official | 235:685d5f11838f | 279 | * @} |
| mbed_official | 235:685d5f11838f | 280 | */ |
| mbed_official | 235:685d5f11838f | 281 | |
| mbed_official | 235:685d5f11838f | 282 | /** @defgroup DMA_mode |
| mbed_official | 235:685d5f11838f | 283 | * @{ |
| mbed_official | 235:685d5f11838f | 284 | */ |
| mbed_official | 235:685d5f11838f | 285 | #define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */ |
| mbed_official | 235:685d5f11838f | 286 | #define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */ |
| mbed_official | 235:685d5f11838f | 287 | #define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */ |
| mbed_official | 235:685d5f11838f | 288 | |
| mbed_official | 235:685d5f11838f | 289 | #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ |
| mbed_official | 235:685d5f11838f | 290 | ((MODE) == DMA_CIRCULAR) || \ |
| mbed_official | 235:685d5f11838f | 291 | ((MODE) == DMA_PFCTRL)) |
| mbed_official | 235:685d5f11838f | 292 | /** |
| mbed_official | 235:685d5f11838f | 293 | * @} |
| mbed_official | 235:685d5f11838f | 294 | */ |
| mbed_official | 235:685d5f11838f | 295 | |
| mbed_official | 235:685d5f11838f | 296 | /** @defgroup DMA_Priority_level |
| mbed_official | 235:685d5f11838f | 297 | * @{ |
| mbed_official | 235:685d5f11838f | 298 | */ |
| mbed_official | 235:685d5f11838f | 299 | #define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level: Low */ |
| mbed_official | 235:685d5f11838f | 300 | #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */ |
| mbed_official | 235:685d5f11838f | 301 | #define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */ |
| mbed_official | 235:685d5f11838f | 302 | #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */ |
| mbed_official | 235:685d5f11838f | 303 | |
| mbed_official | 235:685d5f11838f | 304 | #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ |
| mbed_official | 235:685d5f11838f | 305 | ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ |
| mbed_official | 235:685d5f11838f | 306 | ((PRIORITY) == DMA_PRIORITY_HIGH) || \ |
| mbed_official | 235:685d5f11838f | 307 | ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) |
| mbed_official | 235:685d5f11838f | 308 | /** |
| mbed_official | 235:685d5f11838f | 309 | * @} |
| mbed_official | 235:685d5f11838f | 310 | */ |
| mbed_official | 235:685d5f11838f | 311 | |
| mbed_official | 235:685d5f11838f | 312 | /** @defgroup DMA_FIFO_direct_mode |
| mbed_official | 235:685d5f11838f | 313 | * @{ |
| mbed_official | 235:685d5f11838f | 314 | */ |
| mbed_official | 235:685d5f11838f | 315 | #define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000) /*!< FIFO mode disable */ |
| mbed_official | 235:685d5f11838f | 316 | #define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */ |
| mbed_official | 235:685d5f11838f | 317 | |
| mbed_official | 235:685d5f11838f | 318 | #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \ |
| mbed_official | 235:685d5f11838f | 319 | ((STATE) == DMA_FIFOMODE_ENABLE)) |
| mbed_official | 235:685d5f11838f | 320 | /** |
| mbed_official | 235:685d5f11838f | 321 | * @} |
| mbed_official | 235:685d5f11838f | 322 | */ |
| mbed_official | 235:685d5f11838f | 323 | |
| mbed_official | 235:685d5f11838f | 324 | /** @defgroup DMA_FIFO_threshold_level |
| mbed_official | 235:685d5f11838f | 325 | * @{ |
| mbed_official | 235:685d5f11838f | 326 | */ |
| mbed_official | 235:685d5f11838f | 327 | #define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000) /*!< FIFO threshold 1 quart full configuration */ |
| mbed_official | 235:685d5f11838f | 328 | #define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */ |
| mbed_official | 235:685d5f11838f | 329 | #define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */ |
| mbed_official | 235:685d5f11838f | 330 | #define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */ |
| mbed_official | 235:685d5f11838f | 331 | |
| mbed_official | 235:685d5f11838f | 332 | #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \ |
| mbed_official | 235:685d5f11838f | 333 | ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \ |
| mbed_official | 235:685d5f11838f | 334 | ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \ |
| mbed_official | 235:685d5f11838f | 335 | ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL)) |
| mbed_official | 235:685d5f11838f | 336 | /** |
| mbed_official | 235:685d5f11838f | 337 | * @} |
| mbed_official | 235:685d5f11838f | 338 | */ |
| mbed_official | 235:685d5f11838f | 339 | |
| mbed_official | 235:685d5f11838f | 340 | /** @defgroup DMA_Memory_burst |
| mbed_official | 235:685d5f11838f | 341 | * @{ |
| mbed_official | 235:685d5f11838f | 342 | */ |
| mbed_official | 235:685d5f11838f | 343 | #define DMA_MBURST_SINGLE ((uint32_t)0x00000000) |
| mbed_official | 235:685d5f11838f | 344 | #define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0) |
| mbed_official | 235:685d5f11838f | 345 | #define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1) |
| mbed_official | 235:685d5f11838f | 346 | #define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST) |
| mbed_official | 235:685d5f11838f | 347 | |
| mbed_official | 235:685d5f11838f | 348 | #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \ |
| mbed_official | 235:685d5f11838f | 349 | ((BURST) == DMA_MBURST_INC4) || \ |
| mbed_official | 235:685d5f11838f | 350 | ((BURST) == DMA_MBURST_INC8) || \ |
| mbed_official | 235:685d5f11838f | 351 | ((BURST) == DMA_MBURST_INC16)) |
| mbed_official | 235:685d5f11838f | 352 | /** |
| mbed_official | 235:685d5f11838f | 353 | * @} |
| mbed_official | 235:685d5f11838f | 354 | */ |
| mbed_official | 235:685d5f11838f | 355 | |
| mbed_official | 235:685d5f11838f | 356 | /** @defgroup DMA_Peripheral_burst |
| mbed_official | 235:685d5f11838f | 357 | * @{ |
| mbed_official | 235:685d5f11838f | 358 | */ |
| mbed_official | 235:685d5f11838f | 359 | #define DMA_PBURST_SINGLE ((uint32_t)0x00000000) |
| mbed_official | 235:685d5f11838f | 360 | #define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0) |
| mbed_official | 235:685d5f11838f | 361 | #define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1) |
| mbed_official | 235:685d5f11838f | 362 | #define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST) |
| mbed_official | 235:685d5f11838f | 363 | |
| mbed_official | 235:685d5f11838f | 364 | #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \ |
| mbed_official | 235:685d5f11838f | 365 | ((BURST) == DMA_PBURST_INC4) || \ |
| mbed_official | 235:685d5f11838f | 366 | ((BURST) == DMA_PBURST_INC8) || \ |
| mbed_official | 235:685d5f11838f | 367 | ((BURST) == DMA_PBURST_INC16)) |
| mbed_official | 235:685d5f11838f | 368 | /** |
| mbed_official | 235:685d5f11838f | 369 | * @} |
| mbed_official | 235:685d5f11838f | 370 | */ |
| mbed_official | 235:685d5f11838f | 371 | |
| mbed_official | 235:685d5f11838f | 372 | /** @defgroup DMA_interrupt_enable_definitions |
| mbed_official | 235:685d5f11838f | 373 | * @{ |
| mbed_official | 235:685d5f11838f | 374 | */ |
| mbed_official | 235:685d5f11838f | 375 | #define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE) |
| mbed_official | 235:685d5f11838f | 376 | #define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE) |
| mbed_official | 235:685d5f11838f | 377 | #define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE) |
| mbed_official | 235:685d5f11838f | 378 | #define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE) |
| mbed_official | 235:685d5f11838f | 379 | #define DMA_IT_FE ((uint32_t)0x00000080) |
| mbed_official | 235:685d5f11838f | 380 | /** |
| mbed_official | 235:685d5f11838f | 381 | * @} |
| mbed_official | 235:685d5f11838f | 382 | */ |
| mbed_official | 235:685d5f11838f | 383 | |
| mbed_official | 235:685d5f11838f | 384 | /** @defgroup DMA_flag_definitions |
| mbed_official | 235:685d5f11838f | 385 | * @{ |
| mbed_official | 235:685d5f11838f | 386 | */ |
| mbed_official | 235:685d5f11838f | 387 | #define DMA_FLAG_FEIF0_4 ((uint32_t)0x00800001) |
| mbed_official | 235:685d5f11838f | 388 | #define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00800004) |
| mbed_official | 235:685d5f11838f | 389 | #define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008) |
| mbed_official | 235:685d5f11838f | 390 | #define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010) |
| mbed_official | 235:685d5f11838f | 391 | #define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020) |
| mbed_official | 235:685d5f11838f | 392 | #define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040) |
| mbed_official | 235:685d5f11838f | 393 | #define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100) |
| mbed_official | 235:685d5f11838f | 394 | #define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200) |
| mbed_official | 235:685d5f11838f | 395 | #define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400) |
| mbed_official | 235:685d5f11838f | 396 | #define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800) |
| mbed_official | 235:685d5f11838f | 397 | #define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000) |
| mbed_official | 235:685d5f11838f | 398 | #define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000) |
| mbed_official | 235:685d5f11838f | 399 | #define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000) |
| mbed_official | 235:685d5f11838f | 400 | #define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000) |
| mbed_official | 235:685d5f11838f | 401 | #define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000) |
| mbed_official | 235:685d5f11838f | 402 | #define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000) |
| mbed_official | 235:685d5f11838f | 403 | #define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000) |
| mbed_official | 235:685d5f11838f | 404 | #define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000) |
| mbed_official | 235:685d5f11838f | 405 | #define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000) |
| mbed_official | 235:685d5f11838f | 406 | #define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000) |
| mbed_official | 235:685d5f11838f | 407 | /** |
| mbed_official | 235:685d5f11838f | 408 | * @} |
| mbed_official | 235:685d5f11838f | 409 | */ |
| mbed_official | 235:685d5f11838f | 410 | |
| mbed_official | 235:685d5f11838f | 411 | /** |
| mbed_official | 235:685d5f11838f | 412 | * @} |
| mbed_official | 235:685d5f11838f | 413 | */ |
| mbed_official | 235:685d5f11838f | 414 | |
| mbed_official | 235:685d5f11838f | 415 | /* Exported macro ------------------------------------------------------------*/ |
| mbed_official | 235:685d5f11838f | 416 | |
| mbed_official | 235:685d5f11838f | 417 | /** @brief Reset DMA handle state |
| mbed_official | 235:685d5f11838f | 418 | * @param __HANDLE__: specifies the DMA handle. |
| mbed_official | 235:685d5f11838f | 419 | * @retval None |
| mbed_official | 235:685d5f11838f | 420 | */ |
| mbed_official | 235:685d5f11838f | 421 | #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) |
| mbed_official | 235:685d5f11838f | 422 | |
| mbed_official | 235:685d5f11838f | 423 | /** |
| mbed_official | 235:685d5f11838f | 424 | * @brief Return the current DMA Stream FIFO filled level. |
| mbed_official | 235:685d5f11838f | 425 | * @param __HANDLE__: DMA handle |
| mbed_official | 235:685d5f11838f | 426 | * @retval The FIFO filling state. |
| mbed_official | 235:685d5f11838f | 427 | * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full |
| mbed_official | 235:685d5f11838f | 428 | * and not empty. |
| mbed_official | 235:685d5f11838f | 429 | * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full. |
| mbed_official | 235:685d5f11838f | 430 | * - DMA_FIFOStatus_HalfFull: if more than 1 half-full. |
| mbed_official | 235:685d5f11838f | 431 | * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full. |
| mbed_official | 235:685d5f11838f | 432 | * - DMA_FIFOStatus_Empty: when FIFO is empty |
| mbed_official | 235:685d5f11838f | 433 | * - DMA_FIFOStatus_Full: when FIFO is full |
| mbed_official | 235:685d5f11838f | 434 | */ |
| mbed_official | 235:685d5f11838f | 435 | #define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS))) |
| mbed_official | 235:685d5f11838f | 436 | |
| mbed_official | 235:685d5f11838f | 437 | /** |
| mbed_official | 235:685d5f11838f | 438 | * @brief Enable the specified DMA Stream. |
| mbed_official | 235:685d5f11838f | 439 | * @param __HANDLE__: DMA handle |
| mbed_official | 235:685d5f11838f | 440 | * @retval None |
| mbed_official | 235:685d5f11838f | 441 | */ |
| mbed_official | 235:685d5f11838f | 442 | #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN) |
| mbed_official | 235:685d5f11838f | 443 | |
| mbed_official | 235:685d5f11838f | 444 | /** |
| mbed_official | 235:685d5f11838f | 445 | * @brief Disable the specified DMA Stream. |
| mbed_official | 235:685d5f11838f | 446 | * @param __HANDLE__: DMA handle |
| mbed_official | 235:685d5f11838f | 447 | * @retval None |
| mbed_official | 235:685d5f11838f | 448 | */ |
| mbed_official | 235:685d5f11838f | 449 | #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN) |
| mbed_official | 235:685d5f11838f | 450 | |
| mbed_official | 235:685d5f11838f | 451 | /* Interrupt & Flag management */ |
| mbed_official | 235:685d5f11838f | 452 | |
| mbed_official | 235:685d5f11838f | 453 | /** |
| mbed_official | 235:685d5f11838f | 454 | * @brief Return the current DMA Stream transfer complete flag. |
| mbed_official | 235:685d5f11838f | 455 | * @param __HANDLE__: DMA handle |
| mbed_official | 235:685d5f11838f | 456 | * @retval The specified transfer complete flag index. |
| mbed_official | 235:685d5f11838f | 457 | */ |
| mbed_official | 235:685d5f11838f | 458 | #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ |
| mbed_official | 235:685d5f11838f | 459 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\ |
| mbed_official | 235:685d5f11838f | 460 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\ |
| mbed_official | 235:685d5f11838f | 461 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\ |
| mbed_official | 235:685d5f11838f | 462 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\ |
| mbed_official | 235:685d5f11838f | 463 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\ |
| mbed_official | 235:685d5f11838f | 464 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\ |
| mbed_official | 235:685d5f11838f | 465 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\ |
| mbed_official | 235:685d5f11838f | 466 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\ |
| mbed_official | 235:685d5f11838f | 467 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\ |
| mbed_official | 235:685d5f11838f | 468 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\ |
| mbed_official | 235:685d5f11838f | 469 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\ |
| mbed_official | 235:685d5f11838f | 470 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\ |
| mbed_official | 235:685d5f11838f | 471 | DMA_FLAG_TCIF3_7) |
| mbed_official | 235:685d5f11838f | 472 | |
| mbed_official | 235:685d5f11838f | 473 | /** |
| mbed_official | 235:685d5f11838f | 474 | * @brief Return the current DMA Stream half transfer complete flag. |
| mbed_official | 235:685d5f11838f | 475 | * @param __HANDLE__: DMA handle |
| mbed_official | 235:685d5f11838f | 476 | * @retval The specified half transfer complete flag index. |
| mbed_official | 235:685d5f11838f | 477 | */ |
| mbed_official | 235:685d5f11838f | 478 | #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ |
| mbed_official | 235:685d5f11838f | 479 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\ |
| mbed_official | 235:685d5f11838f | 480 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\ |
| mbed_official | 235:685d5f11838f | 481 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\ |
| mbed_official | 235:685d5f11838f | 482 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\ |
| mbed_official | 235:685d5f11838f | 483 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\ |
| mbed_official | 235:685d5f11838f | 484 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\ |
| mbed_official | 235:685d5f11838f | 485 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\ |
| mbed_official | 235:685d5f11838f | 486 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\ |
| mbed_official | 235:685d5f11838f | 487 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\ |
| mbed_official | 235:685d5f11838f | 488 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\ |
| mbed_official | 235:685d5f11838f | 489 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\ |
| mbed_official | 235:685d5f11838f | 490 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\ |
| mbed_official | 235:685d5f11838f | 491 | DMA_FLAG_HTIF3_7) |
| mbed_official | 235:685d5f11838f | 492 | |
| mbed_official | 235:685d5f11838f | 493 | /** |
| mbed_official | 235:685d5f11838f | 494 | * @brief Return the current DMA Stream transfer error flag. |
| mbed_official | 235:685d5f11838f | 495 | * @param __HANDLE__: DMA handle |
| mbed_official | 235:685d5f11838f | 496 | * @retval The specified transfer error flag index. |
| mbed_official | 235:685d5f11838f | 497 | */ |
| mbed_official | 235:685d5f11838f | 498 | #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ |
| mbed_official | 235:685d5f11838f | 499 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\ |
| mbed_official | 235:685d5f11838f | 500 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\ |
| mbed_official | 235:685d5f11838f | 501 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\ |
| mbed_official | 235:685d5f11838f | 502 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\ |
| mbed_official | 235:685d5f11838f | 503 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\ |
| mbed_official | 235:685d5f11838f | 504 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\ |
| mbed_official | 235:685d5f11838f | 505 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\ |
| mbed_official | 235:685d5f11838f | 506 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\ |
| mbed_official | 235:685d5f11838f | 507 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\ |
| mbed_official | 235:685d5f11838f | 508 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\ |
| mbed_official | 235:685d5f11838f | 509 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\ |
| mbed_official | 235:685d5f11838f | 510 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\ |
| mbed_official | 235:685d5f11838f | 511 | DMA_FLAG_TEIF3_7) |
| mbed_official | 235:685d5f11838f | 512 | |
| mbed_official | 235:685d5f11838f | 513 | /** |
| mbed_official | 235:685d5f11838f | 514 | * @brief Return the current DMA Stream FIFO error flag. |
| mbed_official | 235:685d5f11838f | 515 | * @param __HANDLE__: DMA handle |
| mbed_official | 235:685d5f11838f | 516 | * @retval The specified FIFO error flag index. |
| mbed_official | 235:685d5f11838f | 517 | */ |
| mbed_official | 235:685d5f11838f | 518 | #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\ |
| mbed_official | 235:685d5f11838f | 519 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\ |
| mbed_official | 235:685d5f11838f | 520 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\ |
| mbed_official | 235:685d5f11838f | 521 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\ |
| mbed_official | 235:685d5f11838f | 522 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\ |
| mbed_official | 235:685d5f11838f | 523 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\ |
| mbed_official | 235:685d5f11838f | 524 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\ |
| mbed_official | 235:685d5f11838f | 525 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\ |
| mbed_official | 235:685d5f11838f | 526 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\ |
| mbed_official | 235:685d5f11838f | 527 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\ |
| mbed_official | 235:685d5f11838f | 528 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\ |
| mbed_official | 235:685d5f11838f | 529 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\ |
| mbed_official | 235:685d5f11838f | 530 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\ |
| mbed_official | 235:685d5f11838f | 531 | DMA_FLAG_FEIF3_7) |
| mbed_official | 235:685d5f11838f | 532 | |
| mbed_official | 235:685d5f11838f | 533 | /** |
| mbed_official | 235:685d5f11838f | 534 | * @brief Return the current DMA Stream direct mode error flag. |
| mbed_official | 235:685d5f11838f | 535 | * @param __HANDLE__: DMA handle |
| mbed_official | 235:685d5f11838f | 536 | * @retval The specified direct mode error flag index. |
| mbed_official | 235:685d5f11838f | 537 | */ |
| mbed_official | 235:685d5f11838f | 538 | #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\ |
| mbed_official | 235:685d5f11838f | 539 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\ |
| mbed_official | 235:685d5f11838f | 540 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\ |
| mbed_official | 235:685d5f11838f | 541 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\ |
| mbed_official | 235:685d5f11838f | 542 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\ |
| mbed_official | 235:685d5f11838f | 543 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\ |
| mbed_official | 235:685d5f11838f | 544 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\ |
| mbed_official | 235:685d5f11838f | 545 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\ |
| mbed_official | 235:685d5f11838f | 546 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\ |
| mbed_official | 235:685d5f11838f | 547 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\ |
| mbed_official | 235:685d5f11838f | 548 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\ |
| mbed_official | 235:685d5f11838f | 549 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\ |
| mbed_official | 235:685d5f11838f | 550 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\ |
| mbed_official | 235:685d5f11838f | 551 | DMA_FLAG_DMEIF3_7) |
| mbed_official | 235:685d5f11838f | 552 | |
| mbed_official | 235:685d5f11838f | 553 | /** |
| mbed_official | 235:685d5f11838f | 554 | * @brief Get the DMA Stream pending flags. |
| mbed_official | 235:685d5f11838f | 555 | * @param __HANDLE__: DMA handle |
| mbed_official | 235:685d5f11838f | 556 | * @param __FLAG__: Get the specified flag. |
| mbed_official | 235:685d5f11838f | 557 | * This parameter can be any combination of the following values: |
| mbed_official | 235:685d5f11838f | 558 | * @arg DMA_FLAG_TCIFx: Transfer complete flag. |
| mbed_official | 235:685d5f11838f | 559 | * @arg DMA_FLAG_HTIFx: Half transfer complete flag. |
| mbed_official | 235:685d5f11838f | 560 | * @arg DMA_FLAG_TEIFx: Transfer error flag. |
| mbed_official | 235:685d5f11838f | 561 | * @arg DMA_FLAG_DMEIFx: Direct mode error flag. |
| mbed_official | 235:685d5f11838f | 562 | * @arg DMA_FLAG_FEIFx: FIFO error flag. |
| mbed_official | 235:685d5f11838f | 563 | * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. |
| mbed_official | 235:685d5f11838f | 564 | * @retval The state of FLAG (SET or RESET). |
| mbed_official | 235:685d5f11838f | 565 | */ |
| mbed_official | 235:685d5f11838f | 566 | #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ |
| mbed_official | 235:685d5f11838f | 567 | (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\ |
| mbed_official | 235:685d5f11838f | 568 | ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\ |
| mbed_official | 235:685d5f11838f | 569 | ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__))) |
| mbed_official | 235:685d5f11838f | 570 | |
| mbed_official | 235:685d5f11838f | 571 | /** |
| mbed_official | 235:685d5f11838f | 572 | * @brief Clear the DMA Stream pending flags. |
| mbed_official | 235:685d5f11838f | 573 | * @param __HANDLE__: DMA handle |
| mbed_official | 235:685d5f11838f | 574 | * @param __FLAG__: specifies the flag to clear. |
| mbed_official | 235:685d5f11838f | 575 | * This parameter can be any combination of the following values: |
| mbed_official | 235:685d5f11838f | 576 | * @arg DMA_FLAG_TCIFx: Transfer complete flag. |
| mbed_official | 235:685d5f11838f | 577 | * @arg DMA_FLAG_HTIFx: Half transfer complete flag. |
| mbed_official | 235:685d5f11838f | 578 | * @arg DMA_FLAG_TEIFx: Transfer error flag. |
| mbed_official | 235:685d5f11838f | 579 | * @arg DMA_FLAG_DMEIFx: Direct mode error flag. |
| mbed_official | 235:685d5f11838f | 580 | * @arg DMA_FLAG_FEIFx: FIFO error flag. |
| mbed_official | 235:685d5f11838f | 581 | * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. |
| mbed_official | 235:685d5f11838f | 582 | * @retval None |
| mbed_official | 235:685d5f11838f | 583 | */ |
| mbed_official | 235:685d5f11838f | 584 | #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ |
| mbed_official | 235:685d5f11838f | 585 | (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\ |
| mbed_official | 235:685d5f11838f | 586 | ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\ |
| mbed_official | 235:685d5f11838f | 587 | ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__))) |
| mbed_official | 235:685d5f11838f | 588 | |
| mbed_official | 235:685d5f11838f | 589 | /** |
| mbed_official | 235:685d5f11838f | 590 | * @brief Enable the specified DMA Stream interrupts. |
| mbed_official | 235:685d5f11838f | 591 | * @param __HANDLE__: DMA handle |
| mbed_official | 235:685d5f11838f | 592 | * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. |
| mbed_official | 235:685d5f11838f | 593 | * This parameter can be any combination of the following values: |
| mbed_official | 235:685d5f11838f | 594 | * @arg DMA_IT_TC: Transfer complete interrupt mask. |
| mbed_official | 235:685d5f11838f | 595 | * @arg DMA_IT_HT: Half transfer complete interrupt mask. |
| mbed_official | 235:685d5f11838f | 596 | * @arg DMA_IT_TE: Transfer error interrupt mask. |
| mbed_official | 235:685d5f11838f | 597 | * @arg DMA_IT_FE: FIFO error interrupt mask. |
| mbed_official | 235:685d5f11838f | 598 | * @arg DMA_IT_DME: Direct mode error interrupt. |
| mbed_official | 235:685d5f11838f | 599 | * @retval None |
| mbed_official | 235:685d5f11838f | 600 | */ |
| mbed_official | 235:685d5f11838f | 601 | #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ |
| mbed_official | 235:685d5f11838f | 602 | ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__))) |
| mbed_official | 235:685d5f11838f | 603 | |
| mbed_official | 235:685d5f11838f | 604 | /** |
| mbed_official | 235:685d5f11838f | 605 | * @brief Disable the specified DMA Stream interrupts. |
| mbed_official | 235:685d5f11838f | 606 | * @param __HANDLE__: DMA handle |
| mbed_official | 235:685d5f11838f | 607 | * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. |
| mbed_official | 235:685d5f11838f | 608 | * This parameter can be any combination of the following values: |
| mbed_official | 235:685d5f11838f | 609 | * @arg DMA_IT_TC: Transfer complete interrupt mask. |
| mbed_official | 235:685d5f11838f | 610 | * @arg DMA_IT_HT: Half transfer complete interrupt mask. |
| mbed_official | 235:685d5f11838f | 611 | * @arg DMA_IT_TE: Transfer error interrupt mask. |
| mbed_official | 235:685d5f11838f | 612 | * @arg DMA_IT_FE: FIFO error interrupt mask. |
| mbed_official | 235:685d5f11838f | 613 | * @arg DMA_IT_DME: Direct mode error interrupt. |
| mbed_official | 235:685d5f11838f | 614 | * @retval None |
| mbed_official | 235:685d5f11838f | 615 | */ |
| mbed_official | 235:685d5f11838f | 616 | #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ |
| mbed_official | 235:685d5f11838f | 617 | ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__))) |
| mbed_official | 235:685d5f11838f | 618 | |
| mbed_official | 235:685d5f11838f | 619 | /** |
| mbed_official | 235:685d5f11838f | 620 | * @brief Check whether the specified DMA Stream interrupt has occurred or not. |
| mbed_official | 235:685d5f11838f | 621 | * @param __HANDLE__: DMA handle |
| mbed_official | 235:685d5f11838f | 622 | * @param __INTERRUPT__: specifies the DMA interrupt source to check. |
| mbed_official | 235:685d5f11838f | 623 | * This parameter can be one of the following values: |
| mbed_official | 235:685d5f11838f | 624 | * @arg DMA_IT_TC: Transfer complete interrupt mask. |
| mbed_official | 235:685d5f11838f | 625 | * @arg DMA_IT_HT: Half transfer complete interrupt mask. |
| mbed_official | 235:685d5f11838f | 626 | * @arg DMA_IT_TE: Transfer error interrupt mask. |
| mbed_official | 235:685d5f11838f | 627 | * @arg DMA_IT_FE: FIFO error interrupt mask. |
| mbed_official | 235:685d5f11838f | 628 | * @arg DMA_IT_DME: Direct mode error interrupt. |
| mbed_official | 235:685d5f11838f | 629 | * @retval The state of DMA_IT. |
| mbed_official | 235:685d5f11838f | 630 | */ |
| mbed_official | 235:685d5f11838f | 631 | #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ |
| mbed_official | 235:685d5f11838f | 632 | ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \ |
| mbed_official | 235:685d5f11838f | 633 | ((__HANDLE__)->Instance->FCR & (__INTERRUPT__))) |
| mbed_official | 235:685d5f11838f | 634 | |
| mbed_official | 235:685d5f11838f | 635 | /** |
| mbed_official | 235:685d5f11838f | 636 | * @brief Writes the number of data units to be transferred on the DMA Stream. |
| mbed_official | 235:685d5f11838f | 637 | * @param __HANDLE__: DMA handle |
| mbed_official | 235:685d5f11838f | 638 | * @param __COUNTER__: Number of data units to be transferred (from 0 to 65535) |
| mbed_official | 235:685d5f11838f | 639 | * Number of data items depends only on the Peripheral data format. |
| mbed_official | 235:685d5f11838f | 640 | * |
| mbed_official | 235:685d5f11838f | 641 | * @note If Peripheral data format is Bytes: number of data units is equal |
| mbed_official | 235:685d5f11838f | 642 | * to total number of bytes to be transferred. |
| mbed_official | 235:685d5f11838f | 643 | * |
| mbed_official | 235:685d5f11838f | 644 | * @note If Peripheral data format is Half-Word: number of data units is |
| mbed_official | 235:685d5f11838f | 645 | * equal to total number of bytes to be transferred / 2. |
| mbed_official | 235:685d5f11838f | 646 | * |
| mbed_official | 235:685d5f11838f | 647 | * @note If Peripheral data format is Word: number of data units is equal |
| mbed_official | 235:685d5f11838f | 648 | * to total number of bytes to be transferred / 4. |
| mbed_official | 235:685d5f11838f | 649 | * |
| mbed_official | 235:685d5f11838f | 650 | * @retval The number of remaining data units in the current DMAy Streamx transfer. |
| mbed_official | 235:685d5f11838f | 651 | */ |
| mbed_official | 235:685d5f11838f | 652 | #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__)) |
| mbed_official | 235:685d5f11838f | 653 | |
| mbed_official | 235:685d5f11838f | 654 | /** |
| mbed_official | 235:685d5f11838f | 655 | * @brief Returns the number of remaining data units in the current DMAy Streamx transfer. |
| mbed_official | 235:685d5f11838f | 656 | * @param __HANDLE__: DMA handle |
| mbed_official | 235:685d5f11838f | 657 | * |
| mbed_official | 235:685d5f11838f | 658 | * @retval The number of remaining data units in the current DMA Stream transfer. |
| mbed_official | 235:685d5f11838f | 659 | */ |
| mbed_official | 235:685d5f11838f | 660 | #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR) |
| mbed_official | 235:685d5f11838f | 661 | |
| mbed_official | 235:685d5f11838f | 662 | |
| mbed_official | 235:685d5f11838f | 663 | /* Include DMA HAL Extension module */ |
| mbed_official | 235:685d5f11838f | 664 | #include "stm32f4xx_hal_dma_ex.h" |
| mbed_official | 235:685d5f11838f | 665 | |
| mbed_official | 235:685d5f11838f | 666 | /* Exported functions --------------------------------------------------------*/ |
| mbed_official | 235:685d5f11838f | 667 | |
| mbed_official | 235:685d5f11838f | 668 | /* Initialization and de-initialization functions *****************************/ |
| mbed_official | 235:685d5f11838f | 669 | HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); |
| mbed_official | 235:685d5f11838f | 670 | HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); |
| mbed_official | 235:685d5f11838f | 671 | |
| mbed_official | 235:685d5f11838f | 672 | /* IO operation functions *****************************************************/ |
| mbed_official | 235:685d5f11838f | 673 | HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); |
| mbed_official | 235:685d5f11838f | 674 | HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); |
| mbed_official | 235:685d5f11838f | 675 | HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); |
| mbed_official | 235:685d5f11838f | 676 | HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout); |
| mbed_official | 235:685d5f11838f | 677 | void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); |
| mbed_official | 235:685d5f11838f | 678 | |
| mbed_official | 235:685d5f11838f | 679 | /* Peripheral State and Error functions ***************************************/ |
| mbed_official | 235:685d5f11838f | 680 | HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); |
| mbed_official | 235:685d5f11838f | 681 | uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); |
| mbed_official | 235:685d5f11838f | 682 | |
| mbed_official | 235:685d5f11838f | 683 | /** |
| mbed_official | 235:685d5f11838f | 684 | * @} |
| mbed_official | 235:685d5f11838f | 685 | */ |
| mbed_official | 235:685d5f11838f | 686 | |
| mbed_official | 235:685d5f11838f | 687 | /** |
| mbed_official | 235:685d5f11838f | 688 | * @} |
| mbed_official | 235:685d5f11838f | 689 | */ |
| mbed_official | 235:685d5f11838f | 690 | |
| mbed_official | 235:685d5f11838f | 691 | #ifdef __cplusplus |
| mbed_official | 235:685d5f11838f | 692 | } |
| mbed_official | 235:685d5f11838f | 693 | #endif |
| mbed_official | 235:685d5f11838f | 694 | |
| mbed_official | 235:685d5f11838f | 695 | #endif /* __STM32F4xx_HAL_DMA_H */ |
| mbed_official | 235:685d5f11838f | 696 | |
| mbed_official | 235:685d5f11838f | 697 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |