mbed library sources modified for open wear
Dependents: openwear-lifelogger-example
Fork of mbed-src by
targets/cmsis/TARGET_STM/TARGET_NUCLEO_F334R8/stm32f3xx_hal_rcc.h@310:6188e0254baa, 2014-09-16 (annotated)
- Committer:
- janekm
- Date:
- Tue Sep 16 22:42:01 2014 +0000
- Revision:
- 310:6188e0254baa
- Parent:
- 237:f3da66175598
N/A
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
mbed_official | 237:f3da66175598 | 1 | /** |
mbed_official | 237:f3da66175598 | 2 | ****************************************************************************** |
mbed_official | 237:f3da66175598 | 3 | * @file stm32f3xx_hal_rcc.h |
mbed_official | 237:f3da66175598 | 4 | * @author MCD Application Team |
mbed_official | 237:f3da66175598 | 5 | * @version V1.0.1 |
mbed_official | 237:f3da66175598 | 6 | * @date 18-June-2014 |
mbed_official | 237:f3da66175598 | 7 | * @brief Header file of RCC HAL module. |
mbed_official | 237:f3da66175598 | 8 | ****************************************************************************** |
mbed_official | 237:f3da66175598 | 9 | * @attention |
mbed_official | 237:f3da66175598 | 10 | * |
mbed_official | 237:f3da66175598 | 11 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
mbed_official | 237:f3da66175598 | 12 | * |
mbed_official | 237:f3da66175598 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
mbed_official | 237:f3da66175598 | 14 | * are permitted provided that the following conditions are met: |
mbed_official | 237:f3da66175598 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
mbed_official | 237:f3da66175598 | 16 | * this list of conditions and the following disclaimer. |
mbed_official | 237:f3da66175598 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
mbed_official | 237:f3da66175598 | 18 | * this list of conditions and the following disclaimer in the documentation |
mbed_official | 237:f3da66175598 | 19 | * and/or other materials provided with the distribution. |
mbed_official | 237:f3da66175598 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
mbed_official | 237:f3da66175598 | 21 | * may be used to endorse or promote products derived from this software |
mbed_official | 237:f3da66175598 | 22 | * without specific prior written permission. |
mbed_official | 237:f3da66175598 | 23 | * |
mbed_official | 237:f3da66175598 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
mbed_official | 237:f3da66175598 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
mbed_official | 237:f3da66175598 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
mbed_official | 237:f3da66175598 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
mbed_official | 237:f3da66175598 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
mbed_official | 237:f3da66175598 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
mbed_official | 237:f3da66175598 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
mbed_official | 237:f3da66175598 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
mbed_official | 237:f3da66175598 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
mbed_official | 237:f3da66175598 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
mbed_official | 237:f3da66175598 | 34 | * |
mbed_official | 237:f3da66175598 | 35 | ****************************************************************************** |
mbed_official | 237:f3da66175598 | 36 | */ |
mbed_official | 237:f3da66175598 | 37 | |
mbed_official | 237:f3da66175598 | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
mbed_official | 237:f3da66175598 | 39 | #ifndef __STM32F3xx_HAL_RCC_H |
mbed_official | 237:f3da66175598 | 40 | #define __STM32F3xx_HAL_RCC_H |
mbed_official | 237:f3da66175598 | 41 | |
mbed_official | 237:f3da66175598 | 42 | #ifdef __cplusplus |
mbed_official | 237:f3da66175598 | 43 | extern "C" { |
mbed_official | 237:f3da66175598 | 44 | #endif |
mbed_official | 237:f3da66175598 | 45 | |
mbed_official | 237:f3da66175598 | 46 | /* Includes ------------------------------------------------------------------*/ |
mbed_official | 237:f3da66175598 | 47 | #include "stm32f3xx_hal_def.h" |
mbed_official | 237:f3da66175598 | 48 | |
mbed_official | 237:f3da66175598 | 49 | /** @addtogroup STM32F3xx_HAL_Driver |
mbed_official | 237:f3da66175598 | 50 | * @{ |
mbed_official | 237:f3da66175598 | 51 | */ |
mbed_official | 237:f3da66175598 | 52 | |
mbed_official | 237:f3da66175598 | 53 | /** @addtogroup RCC |
mbed_official | 237:f3da66175598 | 54 | * @{ |
mbed_official | 237:f3da66175598 | 55 | */ |
mbed_official | 237:f3da66175598 | 56 | |
mbed_official | 237:f3da66175598 | 57 | /* Exported types ------------------------------------------------------------*/ |
mbed_official | 237:f3da66175598 | 58 | |
mbed_official | 237:f3da66175598 | 59 | /** |
mbed_official | 237:f3da66175598 | 60 | * @brief RCC PLL configuration structure definition |
mbed_official | 237:f3da66175598 | 61 | */ |
mbed_official | 237:f3da66175598 | 62 | typedef struct |
mbed_official | 237:f3da66175598 | 63 | { |
mbed_official | 237:f3da66175598 | 64 | uint32_t PLLState; /*!< PLLState: The new state of the PLL. |
mbed_official | 237:f3da66175598 | 65 | This parameter can be a value of @ref RCC_PLL_Config */ |
mbed_official | 237:f3da66175598 | 66 | |
mbed_official | 237:f3da66175598 | 67 | uint32_t PLLSource; /*!< PLLSource: PLL entry clock source. |
mbed_official | 237:f3da66175598 | 68 | This parameter must be a value of @ref RCC_PLL_Clock_Source */ |
mbed_official | 237:f3da66175598 | 69 | |
mbed_official | 237:f3da66175598 | 70 | uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock |
mbed_official | 237:f3da66175598 | 71 | This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/ |
mbed_official | 237:f3da66175598 | 72 | |
mbed_official | 237:f3da66175598 | 73 | }RCC_PLLInitTypeDef; |
mbed_official | 237:f3da66175598 | 74 | |
mbed_official | 237:f3da66175598 | 75 | /** |
mbed_official | 237:f3da66175598 | 76 | * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition |
mbed_official | 237:f3da66175598 | 77 | */ |
mbed_official | 237:f3da66175598 | 78 | typedef struct |
mbed_official | 237:f3da66175598 | 79 | { |
mbed_official | 237:f3da66175598 | 80 | uint32_t OscillatorType; /*!< The oscillators to be configured. |
mbed_official | 237:f3da66175598 | 81 | This parameter can be a value of @ref RCC_Oscillator_Type */ |
mbed_official | 237:f3da66175598 | 82 | |
mbed_official | 237:f3da66175598 | 83 | uint32_t HSEState; /*!< The new state of the HSE. |
mbed_official | 237:f3da66175598 | 84 | This parameter can be a value of @ref RCC_HSE_Config */ |
mbed_official | 237:f3da66175598 | 85 | |
mbed_official | 237:f3da66175598 | 86 | uint32_t HSEPredivValue; /*!< The HSE predivision factor value. |
mbed_official | 237:f3da66175598 | 87 | This parameter can be a value of @ref RCC_HSE_Predivision_Factor */ |
mbed_official | 237:f3da66175598 | 88 | |
mbed_official | 237:f3da66175598 | 89 | uint32_t LSEState; /*!< The new state of the LSE. |
mbed_official | 237:f3da66175598 | 90 | This parameter can be a value of @ref RCC_LSE_Config */ |
mbed_official | 237:f3da66175598 | 91 | |
mbed_official | 237:f3da66175598 | 92 | uint32_t HSIState; /*!< The new state of the HSI. |
mbed_official | 237:f3da66175598 | 93 | This parameter can be a value of @ref RCC_HSI_Config */ |
mbed_official | 237:f3da66175598 | 94 | |
mbed_official | 237:f3da66175598 | 95 | uint32_t HSICalibrationValue; /*!< The calibration trimming value. |
mbed_official | 237:f3da66175598 | 96 | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ |
mbed_official | 237:f3da66175598 | 97 | |
mbed_official | 237:f3da66175598 | 98 | uint32_t LSIState; /*!< The new state of the LSI. |
mbed_official | 237:f3da66175598 | 99 | This parameter can be a value of @ref RCC_LSI_Config */ |
mbed_official | 237:f3da66175598 | 100 | |
mbed_official | 237:f3da66175598 | 101 | RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ |
mbed_official | 237:f3da66175598 | 102 | |
mbed_official | 237:f3da66175598 | 103 | }RCC_OscInitTypeDef; |
mbed_official | 237:f3da66175598 | 104 | |
mbed_official | 237:f3da66175598 | 105 | /** |
mbed_official | 237:f3da66175598 | 106 | * @brief RCC System, AHB and APB busses clock configuration structure definition |
mbed_official | 237:f3da66175598 | 107 | */ |
mbed_official | 237:f3da66175598 | 108 | typedef struct |
mbed_official | 237:f3da66175598 | 109 | { |
mbed_official | 237:f3da66175598 | 110 | uint32_t ClockType; /*!< The clock to be configured. |
mbed_official | 237:f3da66175598 | 111 | This parameter can be a value of @ref RCC_System_Clock_Type */ |
mbed_official | 237:f3da66175598 | 112 | |
mbed_official | 237:f3da66175598 | 113 | uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock. |
mbed_official | 237:f3da66175598 | 114 | This parameter can be a value of @ref RCC_System_Clock_Source */ |
mbed_official | 237:f3da66175598 | 115 | |
mbed_official | 237:f3da66175598 | 116 | uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). |
mbed_official | 237:f3da66175598 | 117 | This parameter can be a value of @ref RCC_AHB_Clock_Source */ |
mbed_official | 237:f3da66175598 | 118 | |
mbed_official | 237:f3da66175598 | 119 | uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). |
mbed_official | 237:f3da66175598 | 120 | This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ |
mbed_official | 237:f3da66175598 | 121 | |
mbed_official | 237:f3da66175598 | 122 | uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). |
mbed_official | 237:f3da66175598 | 123 | This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ |
mbed_official | 237:f3da66175598 | 124 | |
mbed_official | 237:f3da66175598 | 125 | }RCC_ClkInitTypeDef; |
mbed_official | 237:f3da66175598 | 126 | |
mbed_official | 237:f3da66175598 | 127 | /* Exported constants --------------------------------------------------------*/ |
mbed_official | 237:f3da66175598 | 128 | /** @defgroup RCC_Exported_Constants |
mbed_official | 237:f3da66175598 | 129 | * @{ |
mbed_official | 237:f3da66175598 | 130 | */ |
mbed_official | 237:f3da66175598 | 131 | |
mbed_official | 237:f3da66175598 | 132 | /** @defgroup RCC_BitAddress_AliasRegion |
mbed_official | 237:f3da66175598 | 133 | * @brief RCC registers bit address in the alias region |
mbed_official | 237:f3da66175598 | 134 | * @{ |
mbed_official | 237:f3da66175598 | 135 | */ |
mbed_official | 237:f3da66175598 | 136 | #define RCC_OFFSET (RCC_BASE - PERIPH_BASE) |
mbed_official | 237:f3da66175598 | 137 | /* --- CR Register ---*/ |
mbed_official | 237:f3da66175598 | 138 | #define RCC_CR_OFFSET (RCC_OFFSET + 0x00) |
mbed_official | 237:f3da66175598 | 139 | /* Alias word address of HSION bit */ |
mbed_official | 237:f3da66175598 | 140 | #define HSION_BitNumber 0 |
mbed_official | 237:f3da66175598 | 141 | #define CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (HSION_BitNumber * 4)) |
mbed_official | 237:f3da66175598 | 142 | /* Alias word address of HSEON bit */ |
mbed_official | 237:f3da66175598 | 143 | #define HSEON_BitNumber 16 |
mbed_official | 237:f3da66175598 | 144 | #define CR_HSEON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (HSEON_BitNumber * 4)) |
mbed_official | 237:f3da66175598 | 145 | /* Alias word address of CSSON bit */ |
mbed_official | 237:f3da66175598 | 146 | #define CSSON_BitNumber 19 |
mbed_official | 237:f3da66175598 | 147 | #define CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (CSSON_BitNumber * 4)) |
mbed_official | 237:f3da66175598 | 148 | /* Alias word address of PLLON bit */ |
mbed_official | 237:f3da66175598 | 149 | #define PLLON_BitNumber 24 |
mbed_official | 237:f3da66175598 | 150 | #define CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (PLLON_BitNumber * 4)) |
mbed_official | 237:f3da66175598 | 151 | |
mbed_official | 237:f3da66175598 | 152 | /* --- CFGR Register ---*/ |
mbed_official | 237:f3da66175598 | 153 | #define RCC_CFGR_OFFSET (RCC_OFFSET + 0x04) |
mbed_official | 237:f3da66175598 | 154 | /* Alias word address of PLLSRC bit */ |
mbed_official | 237:f3da66175598 | 155 | #define PLLSRC_BitNumber 16 |
mbed_official | 237:f3da66175598 | 156 | #define CFGR_PLLSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (PLLSRC_BitNumber * 4)) |
mbed_official | 237:f3da66175598 | 157 | |
mbed_official | 237:f3da66175598 | 158 | /* --- CIR Register ---*/ |
mbed_official | 237:f3da66175598 | 159 | #define RCC_CIR_OFFSET (RCC_OFFSET + 0x08) |
mbed_official | 237:f3da66175598 | 160 | |
mbed_official | 237:f3da66175598 | 161 | /* --- BDCR Register ---*/ |
mbed_official | 237:f3da66175598 | 162 | #define RCC_BDCR_OFFSET (RCC_OFFSET + 0x20) |
mbed_official | 237:f3da66175598 | 163 | /* Alias word address of LSEON bit */ |
mbed_official | 237:f3da66175598 | 164 | #define LSEON_BitNumber 0 |
mbed_official | 237:f3da66175598 | 165 | #define BDCR_LSEON_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (LSEON_BitNumber * 4)) |
mbed_official | 237:f3da66175598 | 166 | /* Alias word address of RTCEN bit */ |
mbed_official | 237:f3da66175598 | 167 | #define RTCEN_BitNumber 15 |
mbed_official | 237:f3da66175598 | 168 | #define BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4)) |
mbed_official | 237:f3da66175598 | 169 | /* Alias word address of BDRST bit */ |
mbed_official | 237:f3da66175598 | 170 | #define BDRST_BitNumber 16 |
mbed_official | 237:f3da66175598 | 171 | #define BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (BDRST_BitNumber * 4)) |
mbed_official | 237:f3da66175598 | 172 | |
mbed_official | 237:f3da66175598 | 173 | /* --- CSR Register ---*/ |
mbed_official | 237:f3da66175598 | 174 | #define RCC_CSR_OFFSET (RCC_OFFSET + 0x24) |
mbed_official | 237:f3da66175598 | 175 | /* Alias word address of LSION bit */ |
mbed_official | 237:f3da66175598 | 176 | #define LSION_BitNumber 0 |
mbed_official | 237:f3da66175598 | 177 | #define CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32) + (LSION_BitNumber * 4)) |
mbed_official | 237:f3da66175598 | 178 | /* Alias word address of RMVF bit */ |
mbed_official | 237:f3da66175598 | 179 | #define RMVF_BitNumber 24 |
mbed_official | 237:f3da66175598 | 180 | #define CSR_RMVF_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32) + (RMVF_BitNumber * 4)) |
mbed_official | 237:f3da66175598 | 181 | |
mbed_official | 237:f3da66175598 | 182 | /* CR register byte 2 (Bits[23:16]) base address */ |
mbed_official | 237:f3da66175598 | 183 | #define CR_BYTE2_ADDRESS (PERIPH_BASE + RCC_CR_OFFSET + 0x02) |
mbed_official | 237:f3da66175598 | 184 | |
mbed_official | 237:f3da66175598 | 185 | /* CIR register byte 1 (Bits[15:8]) base address */ |
mbed_official | 237:f3da66175598 | 186 | #define CIR_BYTE1_ADDRESS (PERIPH_BASE + RCC_CIR_OFFSET + 0x01) |
mbed_official | 237:f3da66175598 | 187 | |
mbed_official | 237:f3da66175598 | 188 | /* CIR register byte 2 (Bits[23:16]) base address */ |
mbed_official | 237:f3da66175598 | 189 | #define CIR_BYTE2_ADDRESS (PERIPH_BASE + RCC_CIR_OFFSET + 0x02) |
mbed_official | 237:f3da66175598 | 190 | |
mbed_official | 237:f3da66175598 | 191 | /* CSR register byte 1 (Bits[15:8]) base address */ |
mbed_official | 237:f3da66175598 | 192 | #define CSR_BYTE1_ADDRESS (PERIPH_BASE + RCC_CSR_OFFSET + 0x01) |
mbed_official | 237:f3da66175598 | 193 | |
mbed_official | 237:f3da66175598 | 194 | /* BDCR register byte 0 (Bits[7:0] base address */ |
mbed_official | 237:f3da66175598 | 195 | #define BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET) |
mbed_official | 237:f3da66175598 | 196 | |
mbed_official | 237:f3da66175598 | 197 | /* LSE state change timeout */ |
mbed_official | 237:f3da66175598 | 198 | #define LSE_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */ |
mbed_official | 237:f3da66175598 | 199 | |
mbed_official | 237:f3da66175598 | 200 | /* Disable Backup domain write protection state change timeout */ |
mbed_official | 237:f3da66175598 | 201 | #define DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ |
mbed_official | 237:f3da66175598 | 202 | /** |
mbed_official | 237:f3da66175598 | 203 | * @} |
mbed_official | 237:f3da66175598 | 204 | */ |
mbed_official | 237:f3da66175598 | 205 | |
mbed_official | 237:f3da66175598 | 206 | /** @defgroup RCC_Oscillator_Type |
mbed_official | 237:f3da66175598 | 207 | * @{ |
mbed_official | 237:f3da66175598 | 208 | */ |
mbed_official | 237:f3da66175598 | 209 | #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000) |
mbed_official | 237:f3da66175598 | 210 | #define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001) |
mbed_official | 237:f3da66175598 | 211 | #define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002) |
mbed_official | 237:f3da66175598 | 212 | #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004) |
mbed_official | 237:f3da66175598 | 213 | #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008) |
mbed_official | 237:f3da66175598 | 214 | |
mbed_official | 237:f3da66175598 | 215 | #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \ |
mbed_official | 237:f3da66175598 | 216 | (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ |
mbed_official | 237:f3da66175598 | 217 | (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ |
mbed_official | 237:f3da66175598 | 218 | (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ |
mbed_official | 237:f3da66175598 | 219 | (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) |
mbed_official | 237:f3da66175598 | 220 | /** |
mbed_official | 237:f3da66175598 | 221 | * @} |
mbed_official | 237:f3da66175598 | 222 | */ |
mbed_official | 237:f3da66175598 | 223 | |
mbed_official | 237:f3da66175598 | 224 | /** @defgroup RCC_HSE_Config |
mbed_official | 237:f3da66175598 | 225 | * @{ |
mbed_official | 237:f3da66175598 | 226 | */ |
mbed_official | 237:f3da66175598 | 227 | #define RCC_HSE_OFF ((uint32_t)0x00000000) |
mbed_official | 237:f3da66175598 | 228 | #define RCC_HSE_ON ((uint32_t)0x00000001) |
mbed_official | 237:f3da66175598 | 229 | #define RCC_HSE_BYPASS ((uint32_t)0x00000005) |
mbed_official | 237:f3da66175598 | 230 | |
mbed_official | 237:f3da66175598 | 231 | #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ |
mbed_official | 237:f3da66175598 | 232 | ((HSE) == RCC_HSE_BYPASS)) |
mbed_official | 237:f3da66175598 | 233 | /** |
mbed_official | 237:f3da66175598 | 234 | * @} |
mbed_official | 237:f3da66175598 | 235 | */ |
mbed_official | 237:f3da66175598 | 236 | |
mbed_official | 237:f3da66175598 | 237 | /** @defgroup RCC_HSE_Predivision_Factor |
mbed_official | 237:f3da66175598 | 238 | * @{ |
mbed_official | 237:f3da66175598 | 239 | */ |
mbed_official | 237:f3da66175598 | 240 | |
mbed_official | 237:f3da66175598 | 241 | #define RCC_HSE_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1 |
mbed_official | 237:f3da66175598 | 242 | #define RCC_HSE_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2 |
mbed_official | 237:f3da66175598 | 243 | #define RCC_HSE_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3 |
mbed_official | 237:f3da66175598 | 244 | #define RCC_HSE_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4 |
mbed_official | 237:f3da66175598 | 245 | #define RCC_HSE_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5 |
mbed_official | 237:f3da66175598 | 246 | #define RCC_HSE_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6 |
mbed_official | 237:f3da66175598 | 247 | #define RCC_HSE_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7 |
mbed_official | 237:f3da66175598 | 248 | #define RCC_HSE_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8 |
mbed_official | 237:f3da66175598 | 249 | #define RCC_HSE_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9 |
mbed_official | 237:f3da66175598 | 250 | #define RCC_HSE_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10 |
mbed_official | 237:f3da66175598 | 251 | #define RCC_HSE_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11 |
mbed_official | 237:f3da66175598 | 252 | #define RCC_HSE_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12 |
mbed_official | 237:f3da66175598 | 253 | #define RCC_HSE_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13 |
mbed_official | 237:f3da66175598 | 254 | #define RCC_HSE_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14 |
mbed_official | 237:f3da66175598 | 255 | #define RCC_HSE_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15 |
mbed_official | 237:f3da66175598 | 256 | #define RCC_HSE_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16 |
mbed_official | 237:f3da66175598 | 257 | |
mbed_official | 237:f3da66175598 | 258 | #define IS_RCC_HSE_PREDIV(DIV) (((DIV) == RCC_HSE_PREDIV_DIV1) || ((DIV) == RCC_HSE_PREDIV_DIV2) || \ |
mbed_official | 237:f3da66175598 | 259 | ((DIV) == RCC_HSE_PREDIV_DIV3) || ((DIV) == RCC_HSE_PREDIV_DIV4) || \ |
mbed_official | 237:f3da66175598 | 260 | ((DIV) == RCC_HSE_PREDIV_DIV5) || ((DIV) == RCC_HSE_PREDIV_DIV6) || \ |
mbed_official | 237:f3da66175598 | 261 | ((DIV) == RCC_HSE_PREDIV_DIV7) || ((DIV) == RCC_HSE_PREDIV_DIV8) || \ |
mbed_official | 237:f3da66175598 | 262 | ((DIV) == RCC_HSE_PREDIV_DIV9) || ((DIV) == RCC_HSE_PREDIV_DIV10) || \ |
mbed_official | 237:f3da66175598 | 263 | ((DIV) == RCC_HSE_PREDIV_DIV11) || ((DIV) == RCC_HSE_PREDIV_DIV12) || \ |
mbed_official | 237:f3da66175598 | 264 | ((DIV) == RCC_HSE_PREDIV_DIV13) || ((DIV) == RCC_HSE_PREDIV_DIV14) || \ |
mbed_official | 237:f3da66175598 | 265 | ((DIV) == RCC_HSE_PREDIV_DIV15) || ((DIV) == RCC_HSE_PREDIV_DIV16)) |
mbed_official | 237:f3da66175598 | 266 | |
mbed_official | 237:f3da66175598 | 267 | /** |
mbed_official | 237:f3da66175598 | 268 | * @} |
mbed_official | 237:f3da66175598 | 269 | */ |
mbed_official | 237:f3da66175598 | 270 | |
mbed_official | 237:f3da66175598 | 271 | /** @defgroup RCC_LSE_Config |
mbed_official | 237:f3da66175598 | 272 | * @{ |
mbed_official | 237:f3da66175598 | 273 | */ |
mbed_official | 237:f3da66175598 | 274 | #define RCC_LSE_OFF ((uint32_t)0x00000000) |
mbed_official | 237:f3da66175598 | 275 | #define RCC_LSE_ON ((uint32_t)0x00000001) |
mbed_official | 237:f3da66175598 | 276 | #define RCC_LSE_BYPASS ((uint32_t)0x00000005) |
mbed_official | 237:f3da66175598 | 277 | |
mbed_official | 237:f3da66175598 | 278 | #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ |
mbed_official | 237:f3da66175598 | 279 | ((LSE) == RCC_LSE_BYPASS)) |
mbed_official | 237:f3da66175598 | 280 | /** |
mbed_official | 237:f3da66175598 | 281 | * @} |
mbed_official | 237:f3da66175598 | 282 | */ |
mbed_official | 237:f3da66175598 | 283 | |
mbed_official | 237:f3da66175598 | 284 | /** @defgroup RCC_HSI_Config |
mbed_official | 237:f3da66175598 | 285 | * @{ |
mbed_official | 237:f3da66175598 | 286 | */ |
mbed_official | 237:f3da66175598 | 287 | #define RCC_HSI_OFF ((uint32_t)0x00000000) |
mbed_official | 237:f3da66175598 | 288 | #define RCC_HSI_ON ((uint32_t)0x00000001) |
mbed_official | 237:f3da66175598 | 289 | |
mbed_official | 237:f3da66175598 | 290 | #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON)) |
mbed_official | 237:f3da66175598 | 291 | /** |
mbed_official | 237:f3da66175598 | 292 | * @} |
mbed_official | 237:f3da66175598 | 293 | */ |
mbed_official | 237:f3da66175598 | 294 | |
mbed_official | 237:f3da66175598 | 295 | /** @defgroup RCC_LSI_Config |
mbed_official | 237:f3da66175598 | 296 | * @{ |
mbed_official | 237:f3da66175598 | 297 | */ |
mbed_official | 237:f3da66175598 | 298 | #define RCC_LSI_OFF ((uint32_t)0x00000000) |
mbed_official | 237:f3da66175598 | 299 | #define RCC_LSI_ON ((uint32_t)0x00000001) |
mbed_official | 237:f3da66175598 | 300 | |
mbed_official | 237:f3da66175598 | 301 | #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON)) |
mbed_official | 237:f3da66175598 | 302 | /** |
mbed_official | 237:f3da66175598 | 303 | * @} |
mbed_official | 237:f3da66175598 | 304 | */ |
mbed_official | 237:f3da66175598 | 305 | |
mbed_official | 237:f3da66175598 | 306 | /** @defgroup RCC_PLL_Config |
mbed_official | 237:f3da66175598 | 307 | * @{ |
mbed_official | 237:f3da66175598 | 308 | */ |
mbed_official | 237:f3da66175598 | 309 | #define RCC_PLL_NONE ((uint32_t)0x00000000) |
mbed_official | 237:f3da66175598 | 310 | #define RCC_PLL_OFF ((uint32_t)0x00000001) |
mbed_official | 237:f3da66175598 | 311 | #define RCC_PLL_ON ((uint32_t)0x00000002) |
mbed_official | 237:f3da66175598 | 312 | |
mbed_official | 237:f3da66175598 | 313 | #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON)) |
mbed_official | 237:f3da66175598 | 314 | /** |
mbed_official | 237:f3da66175598 | 315 | * @} |
mbed_official | 237:f3da66175598 | 316 | */ |
mbed_official | 237:f3da66175598 | 317 | |
mbed_official | 237:f3da66175598 | 318 | /** @defgroup RCC_PLL_Multiplication_Factor |
mbed_official | 237:f3da66175598 | 319 | * @{ |
mbed_official | 237:f3da66175598 | 320 | */ |
mbed_official | 237:f3da66175598 | 321 | #define RCC_PLL_MUL2 RCC_CFGR_PLLMUL2 |
mbed_official | 237:f3da66175598 | 322 | #define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3 |
mbed_official | 237:f3da66175598 | 323 | #define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4 |
mbed_official | 237:f3da66175598 | 324 | #define RCC_PLL_MUL5 RCC_CFGR_PLLMUL5 |
mbed_official | 237:f3da66175598 | 325 | #define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6 |
mbed_official | 237:f3da66175598 | 326 | #define RCC_PLL_MUL7 RCC_CFGR_PLLMUL7 |
mbed_official | 237:f3da66175598 | 327 | #define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8 |
mbed_official | 237:f3da66175598 | 328 | #define RCC_PLL_MUL9 RCC_CFGR_PLLMUL9 |
mbed_official | 237:f3da66175598 | 329 | #define RCC_PLL_MUL10 RCC_CFGR_PLLMUL10 |
mbed_official | 237:f3da66175598 | 330 | #define RCC_PLL_MUL11 RCC_CFGR_PLLMUL11 |
mbed_official | 237:f3da66175598 | 331 | #define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12 |
mbed_official | 237:f3da66175598 | 332 | #define RCC_PLL_MUL13 RCC_CFGR_PLLMUL13 |
mbed_official | 237:f3da66175598 | 333 | #define RCC_PLL_MUL14 RCC_CFGR_PLLMUL14 |
mbed_official | 237:f3da66175598 | 334 | #define RCC_PLL_MUL15 RCC_CFGR_PLLMUL15 |
mbed_official | 237:f3da66175598 | 335 | #define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16 |
mbed_official | 237:f3da66175598 | 336 | |
mbed_official | 237:f3da66175598 | 337 | #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLL_MUL2) || ((MUL) == RCC_PLL_MUL3) || \ |
mbed_official | 237:f3da66175598 | 338 | ((MUL) == RCC_PLL_MUL4) || ((MUL) == RCC_PLL_MUL5) || \ |
mbed_official | 237:f3da66175598 | 339 | ((MUL) == RCC_PLL_MUL6) || ((MUL) == RCC_PLL_MUL7) || \ |
mbed_official | 237:f3da66175598 | 340 | ((MUL) == RCC_PLL_MUL8) || ((MUL) == RCC_PLL_MUL9) || \ |
mbed_official | 237:f3da66175598 | 341 | ((MUL) == RCC_PLL_MUL10) || ((MUL) == RCC_PLL_MUL11) || \ |
mbed_official | 237:f3da66175598 | 342 | ((MUL) == RCC_PLL_MUL12) || ((MUL) == RCC_PLL_MUL13) || \ |
mbed_official | 237:f3da66175598 | 343 | ((MUL) == RCC_PLL_MUL14) || ((MUL) == RCC_PLL_MUL15) || \ |
mbed_official | 237:f3da66175598 | 344 | ((MUL) == RCC_PLL_MUL16)) |
mbed_official | 237:f3da66175598 | 345 | /** |
mbed_official | 237:f3da66175598 | 346 | * @} |
mbed_official | 237:f3da66175598 | 347 | */ |
mbed_official | 237:f3da66175598 | 348 | |
mbed_official | 237:f3da66175598 | 349 | /** @defgroup RCC_PLL_Clock_Source |
mbed_official | 237:f3da66175598 | 350 | * @{ |
mbed_official | 237:f3da66175598 | 351 | */ |
mbed_official | 237:f3da66175598 | 352 | #define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2 |
mbed_official | 237:f3da66175598 | 353 | #define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV |
mbed_official | 237:f3da66175598 | 354 | |
mbed_official | 237:f3da66175598 | 355 | #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \ |
mbed_official | 237:f3da66175598 | 356 | ((SOURCE) == RCC_PLLSOURCE_HSE)) |
mbed_official | 237:f3da66175598 | 357 | /** |
mbed_official | 237:f3da66175598 | 358 | * @} |
mbed_official | 237:f3da66175598 | 359 | */ |
mbed_official | 237:f3da66175598 | 360 | |
mbed_official | 237:f3da66175598 | 361 | /** @defgroup RCC_System_Clock_Type |
mbed_official | 237:f3da66175598 | 362 | * @{ |
mbed_official | 237:f3da66175598 | 363 | */ |
mbed_official | 237:f3da66175598 | 364 | #define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001) |
mbed_official | 237:f3da66175598 | 365 | #define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002) |
mbed_official | 237:f3da66175598 | 366 | #define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004) |
mbed_official | 237:f3da66175598 | 367 | #define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008) |
mbed_official | 237:f3da66175598 | 368 | |
mbed_official | 237:f3da66175598 | 369 | #define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \ |
mbed_official | 237:f3da66175598 | 370 | (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \ |
mbed_official | 237:f3da66175598 | 371 | (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || \ |
mbed_official | 237:f3da66175598 | 372 | (((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)) |
mbed_official | 237:f3da66175598 | 373 | /** |
mbed_official | 237:f3da66175598 | 374 | * @} |
mbed_official | 237:f3da66175598 | 375 | */ |
mbed_official | 237:f3da66175598 | 376 | |
mbed_official | 237:f3da66175598 | 377 | /** @defgroup RCC_System_Clock_Source |
mbed_official | 237:f3da66175598 | 378 | * @{ |
mbed_official | 237:f3da66175598 | 379 | */ |
mbed_official | 237:f3da66175598 | 380 | #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI |
mbed_official | 237:f3da66175598 | 381 | #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE |
mbed_official | 237:f3da66175598 | 382 | #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL |
mbed_official | 237:f3da66175598 | 383 | |
mbed_official | 237:f3da66175598 | 384 | #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \ |
mbed_official | 237:f3da66175598 | 385 | ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \ |
mbed_official | 237:f3da66175598 | 386 | ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK)) |
mbed_official | 237:f3da66175598 | 387 | /** |
mbed_official | 237:f3da66175598 | 388 | * @} |
mbed_official | 237:f3da66175598 | 389 | */ |
mbed_official | 237:f3da66175598 | 390 | |
mbed_official | 237:f3da66175598 | 391 | /** @defgroup RCC_System_Clock_Source_Status |
mbed_official | 237:f3da66175598 | 392 | * @{ |
mbed_official | 237:f3da66175598 | 393 | */ |
mbed_official | 237:f3da66175598 | 394 | #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI |
mbed_official | 237:f3da66175598 | 395 | #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE |
mbed_official | 237:f3da66175598 | 396 | #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL |
mbed_official | 237:f3da66175598 | 397 | |
mbed_official | 237:f3da66175598 | 398 | #define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) || \ |
mbed_official | 237:f3da66175598 | 399 | ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) || \ |
mbed_official | 237:f3da66175598 | 400 | ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))) |
mbed_official | 237:f3da66175598 | 401 | /** |
mbed_official | 237:f3da66175598 | 402 | * @} |
mbed_official | 237:f3da66175598 | 403 | */ |
mbed_official | 237:f3da66175598 | 404 | |
mbed_official | 237:f3da66175598 | 405 | /** @defgroup RCC_AHB_Clock_Source |
mbed_official | 237:f3da66175598 | 406 | * @{ |
mbed_official | 237:f3da66175598 | 407 | */ |
mbed_official | 237:f3da66175598 | 408 | #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 |
mbed_official | 237:f3da66175598 | 409 | #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 |
mbed_official | 237:f3da66175598 | 410 | #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 |
mbed_official | 237:f3da66175598 | 411 | #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 |
mbed_official | 237:f3da66175598 | 412 | #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 |
mbed_official | 237:f3da66175598 | 413 | #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 |
mbed_official | 237:f3da66175598 | 414 | #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 |
mbed_official | 237:f3da66175598 | 415 | #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 |
mbed_official | 237:f3da66175598 | 416 | #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 |
mbed_official | 237:f3da66175598 | 417 | |
mbed_official | 237:f3da66175598 | 418 | #define IS_RCC_SYSCLK_DIV(DIV) (((DIV) == RCC_SYSCLK_DIV1) || ((DIV) == RCC_SYSCLK_DIV2) || \ |
mbed_official | 237:f3da66175598 | 419 | ((DIV) == RCC_SYSCLK_DIV4) || ((DIV) == RCC_SYSCLK_DIV8) || \ |
mbed_official | 237:f3da66175598 | 420 | ((DIV) == RCC_SYSCLK_DIV16) || ((DIV) == RCC_SYSCLK_DIV64) || \ |
mbed_official | 237:f3da66175598 | 421 | ((DIV) == RCC_SYSCLK_DIV128) || ((DIV) == RCC_SYSCLK_DIV256) || \ |
mbed_official | 237:f3da66175598 | 422 | ((DIV) == RCC_SYSCLK_DIV512)) |
mbed_official | 237:f3da66175598 | 423 | /** |
mbed_official | 237:f3da66175598 | 424 | * @} |
mbed_official | 237:f3da66175598 | 425 | */ |
mbed_official | 237:f3da66175598 | 426 | |
mbed_official | 237:f3da66175598 | 427 | /** @defgroup RCC_APB1_APB2_Clock_Source |
mbed_official | 237:f3da66175598 | 428 | * @{ |
mbed_official | 237:f3da66175598 | 429 | */ |
mbed_official | 237:f3da66175598 | 430 | #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 |
mbed_official | 237:f3da66175598 | 431 | #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 |
mbed_official | 237:f3da66175598 | 432 | #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 |
mbed_official | 237:f3da66175598 | 433 | #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 |
mbed_official | 237:f3da66175598 | 434 | #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 |
mbed_official | 237:f3da66175598 | 435 | |
mbed_official | 237:f3da66175598 | 436 | #define IS_RCC_HCLK_DIV(DIV) (((DIV) == RCC_HCLK_DIV1) || ((DIV) == RCC_HCLK_DIV2) || \ |
mbed_official | 237:f3da66175598 | 437 | ((DIV) == RCC_HCLK_DIV4) || ((DIV) == RCC_HCLK_DIV8) || \ |
mbed_official | 237:f3da66175598 | 438 | ((DIV) == RCC_HCLK_DIV16)) |
mbed_official | 237:f3da66175598 | 439 | /** |
mbed_official | 237:f3da66175598 | 440 | * @} |
mbed_official | 237:f3da66175598 | 441 | */ |
mbed_official | 237:f3da66175598 | 442 | |
mbed_official | 237:f3da66175598 | 443 | /** @defgroup RCC_RTC_Clock_Source |
mbed_official | 237:f3da66175598 | 444 | * @{ |
mbed_official | 237:f3da66175598 | 445 | */ |
mbed_official | 237:f3da66175598 | 446 | #define RCC_RTCCLKSOURCE_NONE RCC_BDCR_RTCSEL_NOCLOCK |
mbed_official | 237:f3da66175598 | 447 | #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE |
mbed_official | 237:f3da66175598 | 448 | #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI |
mbed_official | 237:f3da66175598 | 449 | #define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL_HSE |
mbed_official | 237:f3da66175598 | 450 | |
mbed_official | 237:f3da66175598 | 451 | #define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_NONE) || \ |
mbed_official | 237:f3da66175598 | 452 | ((SOURCE) == RCC_RTCCLKSOURCE_LSE) || \ |
mbed_official | 237:f3da66175598 | 453 | ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \ |
mbed_official | 237:f3da66175598 | 454 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV32)) |
mbed_official | 237:f3da66175598 | 455 | /** |
mbed_official | 237:f3da66175598 | 456 | * @} |
mbed_official | 237:f3da66175598 | 457 | */ |
mbed_official | 237:f3da66175598 | 458 | |
mbed_official | 237:f3da66175598 | 459 | /** @defgroup RCC_USART2_Clock_Source |
mbed_official | 237:f3da66175598 | 460 | * @{ |
mbed_official | 237:f3da66175598 | 461 | */ |
mbed_official | 237:f3da66175598 | 462 | #define RCC_USART2CLKSOURCE_PCLK1 RCC_CFGR3_USART2SW_PCLK |
mbed_official | 237:f3da66175598 | 463 | #define RCC_USART2CLKSOURCE_SYSCLK RCC_CFGR3_USART2SW_SYSCLK |
mbed_official | 237:f3da66175598 | 464 | #define RCC_USART2CLKSOURCE_LSE RCC_CFGR3_USART2SW_LSE |
mbed_official | 237:f3da66175598 | 465 | #define RCC_USART2CLKSOURCE_HSI RCC_CFGR3_USART2SW_HSI |
mbed_official | 237:f3da66175598 | 466 | |
mbed_official | 237:f3da66175598 | 467 | #define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) || \ |
mbed_official | 237:f3da66175598 | 468 | ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \ |
mbed_official | 237:f3da66175598 | 469 | ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \ |
mbed_official | 237:f3da66175598 | 470 | ((SOURCE) == RCC_USART2CLKSOURCE_HSI)) |
mbed_official | 237:f3da66175598 | 471 | /** |
mbed_official | 237:f3da66175598 | 472 | * @} |
mbed_official | 237:f3da66175598 | 473 | */ |
mbed_official | 237:f3da66175598 | 474 | |
mbed_official | 237:f3da66175598 | 475 | /** @defgroup RCC_USART3_Clock_Source |
mbed_official | 237:f3da66175598 | 476 | * @{ |
mbed_official | 237:f3da66175598 | 477 | */ |
mbed_official | 237:f3da66175598 | 478 | #define RCC_USART3CLKSOURCE_PCLK1 RCC_CFGR3_USART3SW_PCLK |
mbed_official | 237:f3da66175598 | 479 | #define RCC_USART3CLKSOURCE_SYSCLK RCC_CFGR3_USART3SW_SYSCLK |
mbed_official | 237:f3da66175598 | 480 | #define RCC_USART3CLKSOURCE_LSE RCC_CFGR3_USART3SW_LSE |
mbed_official | 237:f3da66175598 | 481 | #define RCC_USART3CLKSOURCE_HSI RCC_CFGR3_USART3SW_HSI |
mbed_official | 237:f3da66175598 | 482 | |
mbed_official | 237:f3da66175598 | 483 | #define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) || \ |
mbed_official | 237:f3da66175598 | 484 | ((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) || \ |
mbed_official | 237:f3da66175598 | 485 | ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \ |
mbed_official | 237:f3da66175598 | 486 | ((SOURCE) == RCC_USART3CLKSOURCE_HSI)) |
mbed_official | 237:f3da66175598 | 487 | /** |
mbed_official | 237:f3da66175598 | 488 | * @} |
mbed_official | 237:f3da66175598 | 489 | */ |
mbed_official | 237:f3da66175598 | 490 | |
mbed_official | 237:f3da66175598 | 491 | /** @defgroup RCC_I2C1_Clock_Source |
mbed_official | 237:f3da66175598 | 492 | * @{ |
mbed_official | 237:f3da66175598 | 493 | */ |
mbed_official | 237:f3da66175598 | 494 | #define RCC_I2C1CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI |
mbed_official | 237:f3da66175598 | 495 | #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK |
mbed_official | 237:f3da66175598 | 496 | |
mbed_official | 237:f3da66175598 | 497 | #define IS_RCC_I2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C1CLKSOURCE_HSI) || \ |
mbed_official | 237:f3da66175598 | 498 | ((SOURCE) == RCC_I2C1CLKSOURCE_SYSCLK)) |
mbed_official | 237:f3da66175598 | 499 | /** |
mbed_official | 237:f3da66175598 | 500 | * @} |
mbed_official | 237:f3da66175598 | 501 | */ |
mbed_official | 237:f3da66175598 | 502 | |
mbed_official | 237:f3da66175598 | 503 | /** @defgroup RCC_MCOx_Index |
mbed_official | 237:f3da66175598 | 504 | * @{ |
mbed_official | 237:f3da66175598 | 505 | */ |
mbed_official | 237:f3da66175598 | 506 | #define RCC_MCO ((uint32_t)0x00000000) |
mbed_official | 237:f3da66175598 | 507 | |
mbed_official | 237:f3da66175598 | 508 | #define IS_RCC_MCO(MCOx) ((MCOx) == RCC_MCO) |
mbed_official | 237:f3da66175598 | 509 | /** |
mbed_official | 237:f3da66175598 | 510 | * @} |
mbed_official | 237:f3da66175598 | 511 | */ |
mbed_official | 237:f3da66175598 | 512 | |
mbed_official | 237:f3da66175598 | 513 | /** @defgroup RCC_MCO_Clock_Source |
mbed_official | 237:f3da66175598 | 514 | * @{ |
mbed_official | 237:f3da66175598 | 515 | */ |
mbed_official | 237:f3da66175598 | 516 | #define RCC_MCOSOURCE_NONE RCC_CFGR_MCO_NOCLOCK |
mbed_official | 237:f3da66175598 | 517 | #define RCC_MCOSOURCE_LSI RCC_CFGR_MCO_LSI |
mbed_official | 237:f3da66175598 | 518 | #define RCC_MCOSOURCE_LSE RCC_CFGR_MCO_LSE |
mbed_official | 237:f3da66175598 | 519 | #define RCC_MCOSOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK |
mbed_official | 237:f3da66175598 | 520 | #define RCC_MCOSOURCE_HSI RCC_CFGR_MCO_HSI |
mbed_official | 237:f3da66175598 | 521 | #define RCC_MCOSOURCE_HSE RCC_CFGR_MCO_HSE |
mbed_official | 237:f3da66175598 | 522 | #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL |
mbed_official | 237:f3da66175598 | 523 | |
mbed_official | 237:f3da66175598 | 524 | #define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) || \ |
mbed_official | 237:f3da66175598 | 525 | ((SOURCE) == RCC_MCOSOURCE_LSI) || \ |
mbed_official | 237:f3da66175598 | 526 | ((SOURCE) == RCC_MCOSOURCE_LSE) || \ |
mbed_official | 237:f3da66175598 | 527 | ((SOURCE) == RCC_MCOSOURCE_SYSCLK) || \ |
mbed_official | 237:f3da66175598 | 528 | ((SOURCE) == RCC_MCOSOURCE_HSI) || \ |
mbed_official | 237:f3da66175598 | 529 | ((SOURCE) == RCC_MCOSOURCE_HSE) || \ |
mbed_official | 237:f3da66175598 | 530 | ((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2)) |
mbed_official | 237:f3da66175598 | 531 | /** |
mbed_official | 237:f3da66175598 | 532 | * @} |
mbed_official | 237:f3da66175598 | 533 | */ |
mbed_official | 237:f3da66175598 | 534 | |
mbed_official | 237:f3da66175598 | 535 | /** @defgroup RCC_Interrupt |
mbed_official | 237:f3da66175598 | 536 | * @{ |
mbed_official | 237:f3da66175598 | 537 | */ |
mbed_official | 237:f3da66175598 | 538 | #define RCC_IT_LSIRDY ((uint32_t)0x00000001) |
mbed_official | 237:f3da66175598 | 539 | #define RCC_IT_LSERDY ((uint32_t)0x00000002) |
mbed_official | 237:f3da66175598 | 540 | #define RCC_IT_HSIRDY ((uint32_t)0x00000004) |
mbed_official | 237:f3da66175598 | 541 | #define RCC_IT_HSERDY ((uint32_t)0x00000008) |
mbed_official | 237:f3da66175598 | 542 | #define RCC_IT_PLLRDY ((uint32_t)0x00000010) |
mbed_official | 237:f3da66175598 | 543 | #define RCC_IT_CSS ((uint32_t)0x00000080) |
mbed_official | 237:f3da66175598 | 544 | /** |
mbed_official | 237:f3da66175598 | 545 | * @} |
mbed_official | 237:f3da66175598 | 546 | */ |
mbed_official | 237:f3da66175598 | 547 | |
mbed_official | 237:f3da66175598 | 548 | /** @defgroup RCC_Flag |
mbed_official | 237:f3da66175598 | 549 | * Elements values convention: 0XXYYYYYb |
mbed_official | 237:f3da66175598 | 550 | * - YYYYY : Flag position in the register |
mbed_official | 237:f3da66175598 | 551 | * - XX : Register index |
mbed_official | 237:f3da66175598 | 552 | * - 01: CR register |
mbed_official | 237:f3da66175598 | 553 | * - 10: BDCR register |
mbed_official | 237:f3da66175598 | 554 | * - 11: CSR register |
mbed_official | 237:f3da66175598 | 555 | * @{ |
mbed_official | 237:f3da66175598 | 556 | */ |
mbed_official | 237:f3da66175598 | 557 | #define CR_REG_INDEX 1U |
mbed_official | 237:f3da66175598 | 558 | #define BDCR_REG_INDEX 2U |
mbed_official | 237:f3da66175598 | 559 | #define CSR_REG_INDEX 3U |
mbed_official | 237:f3da66175598 | 560 | |
mbed_official | 237:f3da66175598 | 561 | /* Flags in the CR register */ |
mbed_official | 237:f3da66175598 | 562 | #define RCC_FLAG_HSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CR_HSIRDY)))) |
mbed_official | 237:f3da66175598 | 563 | #define RCC_FLAG_HSERDY ((uint32_t)((CR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CR_HSERDY)))) |
mbed_official | 237:f3da66175598 | 564 | #define RCC_FLAG_PLLRDY ((uint32_t)((CR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CR_PLLRDY)))) |
mbed_official | 237:f3da66175598 | 565 | |
mbed_official | 237:f3da66175598 | 566 | /* Flags in the BDCR register */ |
mbed_official | 237:f3da66175598 | 567 | #define RCC_FLAG_LSERDY ((uint32_t)((BDCR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_BDCR_LSERDY)))) |
mbed_official | 237:f3da66175598 | 568 | |
mbed_official | 237:f3da66175598 | 569 | /* Flags in the CSR register */ |
mbed_official | 237:f3da66175598 | 570 | #define RCC_FLAG_LSIRDY ((uint32_t)((CSR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CSR_LSIRDY)))) |
mbed_official | 237:f3da66175598 | 571 | #define RCC_FLAG_RMV ((uint32_t)((CSR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CSR_RMVF)))) |
mbed_official | 237:f3da66175598 | 572 | #define RCC_FLAG_OBLRST ((uint32_t)((CSR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CSR_OBLRSTF)))) |
mbed_official | 237:f3da66175598 | 573 | #define RCC_FLAG_PINRST ((uint32_t)((CSR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CSR_PINRSTF)))) |
mbed_official | 237:f3da66175598 | 574 | #define RCC_FLAG_PORRST ((uint32_t)((CSR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CSR_PORRSTF)))) |
mbed_official | 237:f3da66175598 | 575 | #define RCC_FLAG_SFTRST ((uint32_t)((CSR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CSR_SFTRSTF)))) |
mbed_official | 237:f3da66175598 | 576 | #define RCC_FLAG_IWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CSR_IWDGRSTF)))) |
mbed_official | 237:f3da66175598 | 577 | #define RCC_FLAG_WWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CSR_WWDGRSTF)))) |
mbed_official | 237:f3da66175598 | 578 | #define RCC_FLAG_LPWRRST ((uint32_t)((CSR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CSR_LPWRRSTF)))) |
mbed_official | 237:f3da66175598 | 579 | /** |
mbed_official | 237:f3da66175598 | 580 | * @} |
mbed_official | 237:f3da66175598 | 581 | */ |
mbed_official | 237:f3da66175598 | 582 | |
mbed_official | 237:f3da66175598 | 583 | #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) |
mbed_official | 237:f3da66175598 | 584 | /** |
mbed_official | 237:f3da66175598 | 585 | * @} |
mbed_official | 237:f3da66175598 | 586 | */ |
mbed_official | 237:f3da66175598 | 587 | /* Exported macro ------------------------------------------------------------*/ |
mbed_official | 237:f3da66175598 | 588 | |
mbed_official | 237:f3da66175598 | 589 | /** @brief Enable or disable the AHB peripheral clock. |
mbed_official | 237:f3da66175598 | 590 | * @note After reset, the peripheral clock (used for registers read/write access) |
mbed_official | 237:f3da66175598 | 591 | * is disabled and the application software has to enable this clock before |
mbed_official | 237:f3da66175598 | 592 | * using it. |
mbed_official | 237:f3da66175598 | 593 | */ |
mbed_official | 237:f3da66175598 | 594 | #define __GPIOA_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOAEN)) |
mbed_official | 237:f3da66175598 | 595 | #define __GPIOB_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOBEN)) |
mbed_official | 237:f3da66175598 | 596 | #define __GPIOC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOCEN)) |
mbed_official | 237:f3da66175598 | 597 | #define __GPIOD_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIODEN)) |
mbed_official | 237:f3da66175598 | 598 | #define __GPIOF_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOFEN)) |
mbed_official | 237:f3da66175598 | 599 | #define __CRC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_CRCEN)) |
mbed_official | 237:f3da66175598 | 600 | #define __DMA1_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_DMA1EN)) |
mbed_official | 237:f3da66175598 | 601 | #define __SRAM_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_SRAMEN)) |
mbed_official | 237:f3da66175598 | 602 | #define __FLITF_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_FLITFEN)) |
mbed_official | 237:f3da66175598 | 603 | #define __TSC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_TSCEN)) |
mbed_official | 237:f3da66175598 | 604 | |
mbed_official | 237:f3da66175598 | 605 | #define __GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN)) |
mbed_official | 237:f3da66175598 | 606 | #define __GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN)) |
mbed_official | 237:f3da66175598 | 607 | #define __GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN)) |
mbed_official | 237:f3da66175598 | 608 | #define __GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN)) |
mbed_official | 237:f3da66175598 | 609 | #define __GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN)) |
mbed_official | 237:f3da66175598 | 610 | #define __CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN)) |
mbed_official | 237:f3da66175598 | 611 | #define __DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN)) |
mbed_official | 237:f3da66175598 | 612 | #define __SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN)) |
mbed_official | 237:f3da66175598 | 613 | #define __FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN)) |
mbed_official | 237:f3da66175598 | 614 | #define __TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN)) |
mbed_official | 237:f3da66175598 | 615 | |
mbed_official | 237:f3da66175598 | 616 | /** @brief Enable or disable the Low Speed APB (APB1) peripheral clock. |
mbed_official | 237:f3da66175598 | 617 | * @note After reset, the peripheral clock (used for registers read/write access) |
mbed_official | 237:f3da66175598 | 618 | * is disabled and the application software has to enable this clock before |
mbed_official | 237:f3da66175598 | 619 | * using it. |
mbed_official | 237:f3da66175598 | 620 | */ |
mbed_official | 237:f3da66175598 | 621 | #define __TIM2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN)) |
mbed_official | 237:f3da66175598 | 622 | #define __TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN)) |
mbed_official | 237:f3da66175598 | 623 | #define __WWDG_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN)) |
mbed_official | 237:f3da66175598 | 624 | #define __USART2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART2EN)) |
mbed_official | 237:f3da66175598 | 625 | #define __USART3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART3EN)) |
mbed_official | 237:f3da66175598 | 626 | #define __I2C1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C1EN)) |
mbed_official | 237:f3da66175598 | 627 | #define __PWR_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_PWREN)) |
mbed_official | 237:f3da66175598 | 628 | #define __DAC1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DAC1EN)) |
mbed_official | 237:f3da66175598 | 629 | |
mbed_official | 237:f3da66175598 | 630 | #define __TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) |
mbed_official | 237:f3da66175598 | 631 | #define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) |
mbed_official | 237:f3da66175598 | 632 | #define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) |
mbed_official | 237:f3da66175598 | 633 | #define __USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) |
mbed_official | 237:f3da66175598 | 634 | #define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) |
mbed_official | 237:f3da66175598 | 635 | #define __I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) |
mbed_official | 237:f3da66175598 | 636 | #define __PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) |
mbed_official | 237:f3da66175598 | 637 | #define __DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC1EN)) |
mbed_official | 237:f3da66175598 | 638 | |
mbed_official | 237:f3da66175598 | 639 | /** @brief Enable or disable the High Speed APB (APB2) peripheral clock. |
mbed_official | 237:f3da66175598 | 640 | * @note After reset, the peripheral clock (used for registers read/write access) |
mbed_official | 237:f3da66175598 | 641 | * is disabled and the application software has to enable this clock before |
mbed_official | 237:f3da66175598 | 642 | * using it. |
mbed_official | 237:f3da66175598 | 643 | */ |
mbed_official | 237:f3da66175598 | 644 | #define __SYSCFG_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SYSCFGEN)) |
mbed_official | 237:f3da66175598 | 645 | #define __TIM15_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM15EN)) |
mbed_official | 237:f3da66175598 | 646 | #define __TIM16_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM16EN)) |
mbed_official | 237:f3da66175598 | 647 | #define __TIM17_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM17EN)) |
mbed_official | 237:f3da66175598 | 648 | #define __USART1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART1EN)) |
mbed_official | 237:f3da66175598 | 649 | |
mbed_official | 237:f3da66175598 | 650 | #define __SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN)) |
mbed_official | 237:f3da66175598 | 651 | #define __TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN)) |
mbed_official | 237:f3da66175598 | 652 | #define __TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN)) |
mbed_official | 237:f3da66175598 | 653 | #define __TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN)) |
mbed_official | 237:f3da66175598 | 654 | #define __USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) |
mbed_official | 237:f3da66175598 | 655 | |
mbed_official | 237:f3da66175598 | 656 | /** @brief Force or release AHB peripheral reset. |
mbed_official | 237:f3da66175598 | 657 | */ |
mbed_official | 237:f3da66175598 | 658 | #define __AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFF) |
mbed_official | 237:f3da66175598 | 659 | #define __GPIOA_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST)) |
mbed_official | 237:f3da66175598 | 660 | #define __GPIOB_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST)) |
mbed_official | 237:f3da66175598 | 661 | #define __GPIOC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST)) |
mbed_official | 237:f3da66175598 | 662 | #define __GPIOD_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST)) |
mbed_official | 237:f3da66175598 | 663 | #define __GPIOF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST)) |
mbed_official | 237:f3da66175598 | 664 | #define __TSC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_TSCRST)) |
mbed_official | 237:f3da66175598 | 665 | |
mbed_official | 237:f3da66175598 | 666 | #define __AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00) |
mbed_official | 237:f3da66175598 | 667 | #define __GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST)) |
mbed_official | 237:f3da66175598 | 668 | #define __GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST)) |
mbed_official | 237:f3da66175598 | 669 | #define __GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST)) |
mbed_official | 237:f3da66175598 | 670 | #define __GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST)) |
mbed_official | 237:f3da66175598 | 671 | #define __GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST)) |
mbed_official | 237:f3da66175598 | 672 | #define __TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST)) |
mbed_official | 237:f3da66175598 | 673 | |
mbed_official | 237:f3da66175598 | 674 | /** @brief Force or release APB1 peripheral reset. |
mbed_official | 237:f3da66175598 | 675 | */ |
mbed_official | 237:f3da66175598 | 676 | #define __APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF) |
mbed_official | 237:f3da66175598 | 677 | #define __TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) |
mbed_official | 237:f3da66175598 | 678 | #define __TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) |
mbed_official | 237:f3da66175598 | 679 | #define __WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) |
mbed_official | 237:f3da66175598 | 680 | #define __USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) |
mbed_official | 237:f3da66175598 | 681 | #define __USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) |
mbed_official | 237:f3da66175598 | 682 | #define __I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) |
mbed_official | 237:f3da66175598 | 683 | #define __PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) |
mbed_official | 237:f3da66175598 | 684 | #define __DAC1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DAC1RST)) |
mbed_official | 237:f3da66175598 | 685 | |
mbed_official | 237:f3da66175598 | 686 | #define __APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00) |
mbed_official | 237:f3da66175598 | 687 | #define __TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) |
mbed_official | 237:f3da66175598 | 688 | #define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) |
mbed_official | 237:f3da66175598 | 689 | #define __WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) |
mbed_official | 237:f3da66175598 | 690 | #define __USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) |
mbed_official | 237:f3da66175598 | 691 | #define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) |
mbed_official | 237:f3da66175598 | 692 | #define __I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)) |
mbed_official | 237:f3da66175598 | 693 | #define __PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) |
mbed_official | 237:f3da66175598 | 694 | #define __DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC1RST)) |
mbed_official | 237:f3da66175598 | 695 | |
mbed_official | 237:f3da66175598 | 696 | /** @brief Force or release APB2 peripheral reset. |
mbed_official | 237:f3da66175598 | 697 | */ |
mbed_official | 237:f3da66175598 | 698 | #define __APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF) |
mbed_official | 237:f3da66175598 | 699 | #define __SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST)) |
mbed_official | 237:f3da66175598 | 700 | #define __TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST)) |
mbed_official | 237:f3da66175598 | 701 | #define __TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST)) |
mbed_official | 237:f3da66175598 | 702 | #define __TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST)) |
mbed_official | 237:f3da66175598 | 703 | #define __USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) |
mbed_official | 237:f3da66175598 | 704 | |
mbed_official | 237:f3da66175598 | 705 | #define __APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00) |
mbed_official | 237:f3da66175598 | 706 | #define __SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST)) |
mbed_official | 237:f3da66175598 | 707 | #define __TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST)) |
mbed_official | 237:f3da66175598 | 708 | #define __TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST)) |
mbed_official | 237:f3da66175598 | 709 | #define __TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST)) |
mbed_official | 237:f3da66175598 | 710 | #define __USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST)) |
mbed_official | 237:f3da66175598 | 711 | |
mbed_official | 237:f3da66175598 | 712 | /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). |
mbed_official | 237:f3da66175598 | 713 | * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. |
mbed_official | 237:f3da66175598 | 714 | * It is used (enabled by hardware) as system clock source after startup |
mbed_official | 237:f3da66175598 | 715 | * from Reset, wakeup from STOP and STANDBY mode, or in case of failure |
mbed_official | 237:f3da66175598 | 716 | * of the HSE used directly or indirectly as system clock (if the Clock |
mbed_official | 237:f3da66175598 | 717 | * Security System CSS is enabled). |
mbed_official | 237:f3da66175598 | 718 | * @note HSI can not be stopped if it is used as system clock source. In this case, |
mbed_official | 237:f3da66175598 | 719 | * you have to select another source of the system clock then stop the HSI. |
mbed_official | 237:f3da66175598 | 720 | * @note After enabling the HSI, the application software should wait on HSIRDY |
mbed_official | 237:f3da66175598 | 721 | * flag to be set indicating that HSI clock is stable and can be used as |
mbed_official | 237:f3da66175598 | 722 | * system clock source. |
mbed_official | 237:f3da66175598 | 723 | * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator |
mbed_official | 237:f3da66175598 | 724 | * clock cycles. |
mbed_official | 237:f3da66175598 | 725 | */ |
mbed_official | 237:f3da66175598 | 726 | #define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *)CR_HSION_BB = ENABLE) |
mbed_official | 237:f3da66175598 | 727 | #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *)CR_HSION_BB = DISABLE) |
mbed_official | 237:f3da66175598 | 728 | |
mbed_official | 237:f3da66175598 | 729 | |
mbed_official | 237:f3da66175598 | 730 | /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. |
mbed_official | 237:f3da66175598 | 731 | * @note The calibration is used to compensate for the variations in voltage |
mbed_official | 237:f3da66175598 | 732 | * and temperature that influence the frequency of the internal HSI RC. |
mbed_official | 237:f3da66175598 | 733 | * @param __HSICalibrationValue__: specifies the calibration trimming value. |
mbed_official | 237:f3da66175598 | 734 | * This parameter must be a number between 0 and 0x1F. |
mbed_official | 237:f3da66175598 | 735 | */ |
mbed_official | 237:f3da66175598 | 736 | #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) \ |
mbed_official | 237:f3da66175598 | 737 | MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << POSITION_VAL(RCC_CR_HSITRIM)) |
mbed_official | 237:f3da66175598 | 738 | |
mbed_official | 237:f3da66175598 | 739 | |
mbed_official | 237:f3da66175598 | 740 | /** @brief Macro to enable or disable the Internal Low Speed oscillator (LSI). |
mbed_official | 237:f3da66175598 | 741 | * @note After enabling the LSI, the application software should wait on |
mbed_official | 237:f3da66175598 | 742 | * LSIRDY flag to be set indicating that LSI clock is stable and can |
mbed_official | 237:f3da66175598 | 743 | * be used to clock the IWDG and/or the RTC. |
mbed_official | 237:f3da66175598 | 744 | * @note LSI can not be disabled if the IWDG is running. |
mbed_official | 237:f3da66175598 | 745 | * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator |
mbed_official | 237:f3da66175598 | 746 | * clock cycles. |
mbed_official | 237:f3da66175598 | 747 | */ |
mbed_official | 237:f3da66175598 | 748 | #define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *)CSR_LSION_BB = ENABLE) |
mbed_official | 237:f3da66175598 | 749 | #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *)CSR_LSION_BB = DISABLE) |
mbed_official | 237:f3da66175598 | 750 | |
mbed_official | 237:f3da66175598 | 751 | /** |
mbed_official | 237:f3da66175598 | 752 | * @brief Macro to configure the External High Speed oscillator (HSE). |
mbed_official | 237:f3da66175598 | 753 | * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application |
mbed_official | 237:f3da66175598 | 754 | * software should wait on HSERDY flag to be set indicating that HSE clock |
mbed_official | 237:f3da66175598 | 755 | * is stable and can be used to clock the PLL and/or system clock. |
mbed_official | 237:f3da66175598 | 756 | * @note HSE state can not be changed if it is used directly or through the |
mbed_official | 237:f3da66175598 | 757 | * PLL as system clock. In this case, you have to select another source |
mbed_official | 237:f3da66175598 | 758 | * of the system clock then change the HSE state (ex. disable it). |
mbed_official | 237:f3da66175598 | 759 | * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. |
mbed_official | 237:f3da66175598 | 760 | * @note This function reset the CSSON bit, so if the Clock security system(CSS) |
mbed_official | 237:f3da66175598 | 761 | * was previously enabled you have to enable it again after calling this |
mbed_official | 237:f3da66175598 | 762 | * function. |
mbed_official | 237:f3da66175598 | 763 | * @param __STATE__: specifies the new state of the HSE. |
mbed_official | 237:f3da66175598 | 764 | * This parameter can be one of the following values: |
mbed_official | 237:f3da66175598 | 765 | * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after |
mbed_official | 237:f3da66175598 | 766 | * 6 HSE oscillator clock cycles. |
mbed_official | 237:f3da66175598 | 767 | * @arg RCC_HSE_ON: turn ON the HSE oscillator |
mbed_official | 237:f3da66175598 | 768 | * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock |
mbed_official | 237:f3da66175598 | 769 | */ |
mbed_official | 237:f3da66175598 | 770 | #define __HAL_RCC_HSE_CONFIG(__STATE__) (*(__IO uint8_t *)CR_BYTE2_ADDRESS = (__STATE__)) |
mbed_official | 237:f3da66175598 | 771 | |
mbed_official | 237:f3da66175598 | 772 | /** |
mbed_official | 237:f3da66175598 | 773 | * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL. |
mbed_official | 237:f3da66175598 | 774 | * @note Predivision factor can not be changed if PLL is used as system clock |
mbed_official | 237:f3da66175598 | 775 | * In this case, you have to select another source of the system clock, disable the PLL and |
mbed_official | 237:f3da66175598 | 776 | * then change the HSE predivision factor. |
mbed_official | 237:f3da66175598 | 777 | * @param __HSEPredivValue__: specifies the division value applied to HSE. |
mbed_official | 237:f3da66175598 | 778 | * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16. |
mbed_official | 237:f3da66175598 | 779 | */ |
mbed_official | 237:f3da66175598 | 780 | #define __HAL_RCC_HSE_PREDIV_CONFIG(__HSEPredivValue__) \ |
mbed_official | 237:f3da66175598 | 781 | MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (uint32_t)(__HSEPredivValue__)) |
mbed_official | 237:f3da66175598 | 782 | |
mbed_official | 237:f3da66175598 | 783 | /** |
mbed_official | 237:f3da66175598 | 784 | * @brief Macro to configure the External Low Speed oscillator (LSE). |
mbed_official | 237:f3da66175598 | 785 | * @note As the LSE is in the Backup domain and write access is denied to |
mbed_official | 237:f3da66175598 | 786 | * this domain after reset, you have to enable write access using |
mbed_official | 237:f3da66175598 | 787 | * HAL_PWR_EnableBkUpAccess() function before to configure the LSE |
mbed_official | 237:f3da66175598 | 788 | * (to be done once after reset). |
mbed_official | 237:f3da66175598 | 789 | * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application |
mbed_official | 237:f3da66175598 | 790 | * software should wait on LSERDY flag to be set indicating that LSE clock |
mbed_official | 237:f3da66175598 | 791 | * is stable and can be used to clock the RTC. |
mbed_official | 237:f3da66175598 | 792 | * @param __STATE__: specifies the new state of the LSE. |
mbed_official | 237:f3da66175598 | 793 | * This parameter can be one of the following values: |
mbed_official | 237:f3da66175598 | 794 | * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after |
mbed_official | 237:f3da66175598 | 795 | * 6 LSE oscillator clock cycles. |
mbed_official | 237:f3da66175598 | 796 | * @arg RCC_LSE_ON: turn ON the LSE oscillator |
mbed_official | 237:f3da66175598 | 797 | * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock |
mbed_official | 237:f3da66175598 | 798 | */ |
mbed_official | 237:f3da66175598 | 799 | #define __HAL_RCC_LSE_CONFIG(__STATE__) \ |
mbed_official | 237:f3da66175598 | 800 | MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEON|RCC_BDCR_LSEBYP, (uint32_t)(__STATE__)) |
mbed_official | 237:f3da66175598 | 801 | |
mbed_official | 237:f3da66175598 | 802 | /** @brief Macro to configure the I2C1 clock (I2C1CLK). |
mbed_official | 237:f3da66175598 | 803 | * @param __I2C1CLKSource__: specifies the I2C1 clock source. |
mbed_official | 237:f3da66175598 | 804 | * This parameter can be one of the following values: |
mbed_official | 237:f3da66175598 | 805 | * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock |
mbed_official | 237:f3da66175598 | 806 | * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock |
mbed_official | 237:f3da66175598 | 807 | */ |
mbed_official | 237:f3da66175598 | 808 | #define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSource__) \ |
mbed_official | 237:f3da66175598 | 809 | MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, (uint32_t)(__I2C1CLKSource__)) |
mbed_official | 237:f3da66175598 | 810 | |
mbed_official | 237:f3da66175598 | 811 | /** @brief Macro to get the I2C1 clock source. |
mbed_official | 237:f3da66175598 | 812 | * @retval The clock source can be one of the following values: |
mbed_official | 237:f3da66175598 | 813 | * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock |
mbed_official | 237:f3da66175598 | 814 | * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock |
mbed_official | 237:f3da66175598 | 815 | */ |
mbed_official | 237:f3da66175598 | 816 | #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C1SW))) |
mbed_official | 237:f3da66175598 | 817 | |
mbed_official | 237:f3da66175598 | 818 | /** @brief Macro to configure the USART1 clock (USART1CLK). |
mbed_official | 237:f3da66175598 | 819 | * @param __USART1CLKSource__: specifies the USART1 clock source. |
mbed_official | 237:f3da66175598 | 820 | * This parameter can be one of the following values: |
mbed_official | 237:f3da66175598 | 821 | * @arg RCC_USART1CLKSOURCE_PCLK2 or RCC_USART1CLKSOURCE_PCLK1: PCLK2 or PCLK1 selected as USART1 clock |
mbed_official | 237:f3da66175598 | 822 | * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock |
mbed_official | 237:f3da66175598 | 823 | * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock |
mbed_official | 237:f3da66175598 | 824 | * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock |
mbed_official | 237:f3da66175598 | 825 | */ |
mbed_official | 237:f3da66175598 | 826 | #define __HAL_RCC_USART1_CONFIG(__USART1CLKSource__) \ |
mbed_official | 237:f3da66175598 | 827 | MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART1SW, (uint32_t)(__USART1CLKSource__)) |
mbed_official | 237:f3da66175598 | 828 | |
mbed_official | 237:f3da66175598 | 829 | /** @brief Macro to get the USART1 clock source. |
mbed_official | 237:f3da66175598 | 830 | * @retval The clock source can be one of the following values: |
mbed_official | 237:f3da66175598 | 831 | * @arg RCC_USART1CLKSOURCE_PCLK2 or RCC_USART1CLKSOURCE_PCLK1: PCLK2 or PCLK1 selected as USART1 clock |
mbed_official | 237:f3da66175598 | 832 | * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock |
mbed_official | 237:f3da66175598 | 833 | * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock |
mbed_official | 237:f3da66175598 | 834 | * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock |
mbed_official | 237:f3da66175598 | 835 | */ |
mbed_official | 237:f3da66175598 | 836 | #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART1SW))) |
mbed_official | 237:f3da66175598 | 837 | |
mbed_official | 237:f3da66175598 | 838 | /** @brief Macro to configure the USART2 clock (USART2CLK). |
mbed_official | 237:f3da66175598 | 839 | * @param __USART2CLKSource__: specifies the USART2 clock source. |
mbed_official | 237:f3da66175598 | 840 | * This parameter can be one of the following values: |
mbed_official | 237:f3da66175598 | 841 | * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock |
mbed_official | 237:f3da66175598 | 842 | * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock |
mbed_official | 237:f3da66175598 | 843 | * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock |
mbed_official | 237:f3da66175598 | 844 | * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock |
mbed_official | 237:f3da66175598 | 845 | */ |
mbed_official | 237:f3da66175598 | 846 | #define __HAL_RCC_USART2_CONFIG(__USART2CLKSource__) \ |
mbed_official | 237:f3da66175598 | 847 | MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART2SW, (uint32_t)(__USART2CLKSource__)) |
mbed_official | 237:f3da66175598 | 848 | |
mbed_official | 237:f3da66175598 | 849 | /** @brief Macro to get the USART2 clock source. |
mbed_official | 237:f3da66175598 | 850 | * @retval The clock source can be one of the following values: |
mbed_official | 237:f3da66175598 | 851 | * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock |
mbed_official | 237:f3da66175598 | 852 | * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock |
mbed_official | 237:f3da66175598 | 853 | * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock |
mbed_official | 237:f3da66175598 | 854 | * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock |
mbed_official | 237:f3da66175598 | 855 | */ |
mbed_official | 237:f3da66175598 | 856 | #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART2SW))) |
mbed_official | 237:f3da66175598 | 857 | |
mbed_official | 237:f3da66175598 | 858 | /** @brief Macro to configure the USART3 clock (USART3CLK). |
mbed_official | 237:f3da66175598 | 859 | * @param __USART3CLKSource__: specifies the USART3 clock source. |
mbed_official | 237:f3da66175598 | 860 | * This parameter can be one of the following values: |
mbed_official | 237:f3da66175598 | 861 | * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock |
mbed_official | 237:f3da66175598 | 862 | * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock |
mbed_official | 237:f3da66175598 | 863 | * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock |
mbed_official | 237:f3da66175598 | 864 | * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock |
mbed_official | 237:f3da66175598 | 865 | */ |
mbed_official | 237:f3da66175598 | 866 | #define __HAL_RCC_USART3_CONFIG(__USART3CLKSource__) \ |
mbed_official | 237:f3da66175598 | 867 | MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART3SW, (uint32_t)(__USART3CLKSource__)) |
mbed_official | 237:f3da66175598 | 868 | |
mbed_official | 237:f3da66175598 | 869 | /** @brief Macro to get the USART3 clock source. |
mbed_official | 237:f3da66175598 | 870 | * @retval The clock source can be one of the following values: |
mbed_official | 237:f3da66175598 | 871 | * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock |
mbed_official | 237:f3da66175598 | 872 | * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock |
mbed_official | 237:f3da66175598 | 873 | * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock |
mbed_official | 237:f3da66175598 | 874 | * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock |
mbed_official | 237:f3da66175598 | 875 | */ |
mbed_official | 237:f3da66175598 | 876 | #define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART3SW))) |
mbed_official | 237:f3da66175598 | 877 | |
mbed_official | 237:f3da66175598 | 878 | /** @brief Macros to enable or disable the the RTC clock. |
mbed_official | 237:f3da66175598 | 879 | * @note These macros must be used only after the RTC clock source was selected. |
mbed_official | 237:f3da66175598 | 880 | */ |
mbed_official | 237:f3da66175598 | 881 | #define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *)BDCR_RTCEN_BB = ENABLE) |
mbed_official | 237:f3da66175598 | 882 | #define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *)BDCR_RTCEN_BB = DISABLE) |
mbed_official | 237:f3da66175598 | 883 | |
mbed_official | 237:f3da66175598 | 884 | /** @brief Macro to configure the RTC clock (RTCCLK). |
mbed_official | 237:f3da66175598 | 885 | * @note As the RTC clock configuration bits are in the Backup domain and write |
mbed_official | 237:f3da66175598 | 886 | * access is denied to this domain after reset, you have to enable write |
mbed_official | 237:f3da66175598 | 887 | * access using the Power Backup Access macro before to configure |
mbed_official | 237:f3da66175598 | 888 | * the RTC clock source (to be done once after reset). |
mbed_official | 237:f3da66175598 | 889 | * @note Once the RTC clock is configured it can't be changed unless the |
mbed_official | 237:f3da66175598 | 890 | * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by |
mbed_official | 237:f3da66175598 | 891 | * a Power On Reset (POR). |
mbed_official | 237:f3da66175598 | 892 | * @param __RTCCLKSource__: specifies the RTC clock source. |
mbed_official | 237:f3da66175598 | 893 | * This parameter can be one of the following values: |
mbed_official | 237:f3da66175598 | 894 | * @arg RCC_RTCCLKSOURCE_NONE: No clock selected as RTC clock |
mbed_official | 237:f3da66175598 | 895 | * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock |
mbed_official | 237:f3da66175598 | 896 | * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock |
mbed_official | 237:f3da66175598 | 897 | * @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32 |
mbed_official | 237:f3da66175598 | 898 | * |
mbed_official | 237:f3da66175598 | 899 | * @note If the LSE is used as RTC clock source, the RTC continues to |
mbed_official | 237:f3da66175598 | 900 | * work in STOP and STANDBY modes, and can be used as wakeup source. |
mbed_official | 237:f3da66175598 | 901 | * However, when the LSI clock and HSE clock divided by 32 is used as RTC clock source, |
mbed_official | 237:f3da66175598 | 902 | * the RTC cannot be used in STOP and STANDBY modes. |
mbed_official | 237:f3da66175598 | 903 | * @note The system must always be configured so as to get a PCLK frequency greater than or |
mbed_official | 237:f3da66175598 | 904 | * equal to the RTCCLK frequency for a proper operation of the RTC. |
mbed_official | 237:f3da66175598 | 905 | */ |
mbed_official | 237:f3da66175598 | 906 | #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) \ |
mbed_official | 237:f3da66175598 | 907 | MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (uint32_t)(__RTCCLKSource__)) |
mbed_official | 237:f3da66175598 | 908 | |
mbed_official | 237:f3da66175598 | 909 | /** @brief Macro to get the RTC clock source. |
mbed_official | 237:f3da66175598 | 910 | * @retval The clock source can be one of the following values: |
mbed_official | 237:f3da66175598 | 911 | * @arg RCC_RTCCLKSOURCE_NONE: No clock selected as RTC clock |
mbed_official | 237:f3da66175598 | 912 | * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock |
mbed_official | 237:f3da66175598 | 913 | * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock |
mbed_official | 237:f3da66175598 | 914 | * @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32 selected as RTC clock |
mbed_official | 237:f3da66175598 | 915 | */ |
mbed_official | 237:f3da66175598 | 916 | #define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))) |
mbed_official | 237:f3da66175598 | 917 | |
mbed_official | 237:f3da66175598 | 918 | /** @brief Macro to force or release the Backup domain reset. |
mbed_official | 237:f3da66175598 | 919 | * @note These macros reset the RTC peripheral (including the backup registers) |
mbed_official | 237:f3da66175598 | 920 | * and the RTC clock source selection in RCC_CSR register. |
mbed_official | 237:f3da66175598 | 921 | * @note The BKPSRAM is not affected by this reset. |
mbed_official | 237:f3da66175598 | 922 | */ |
mbed_official | 237:f3da66175598 | 923 | #define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *)BDCR_BDRST_BB = ENABLE) |
mbed_official | 237:f3da66175598 | 924 | #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *)BDCR_BDRST_BB = DISABLE) |
mbed_official | 237:f3da66175598 | 925 | |
mbed_official | 237:f3da66175598 | 926 | /** @brief Macro to enable or disable the PLL. |
mbed_official | 237:f3da66175598 | 927 | * @note After enabling the PLL, the application software should wait on |
mbed_official | 237:f3da66175598 | 928 | * PLLRDY flag to be set indicating that PLL clock is stable and can |
mbed_official | 237:f3da66175598 | 929 | * be used as system clock source. |
mbed_official | 237:f3da66175598 | 930 | * @note The PLL can not be disabled if it is used as system clock source |
mbed_official | 237:f3da66175598 | 931 | * @note The PLL is disabled by hardware when entering STOP and STANDBY modes. |
mbed_official | 237:f3da66175598 | 932 | */ |
mbed_official | 237:f3da66175598 | 933 | #define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *)CR_PLLON_BB = ENABLE) |
mbed_official | 237:f3da66175598 | 934 | #define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *)CR_PLLON_BB = DISABLE) |
mbed_official | 237:f3da66175598 | 935 | |
mbed_official | 237:f3da66175598 | 936 | /** @brief Macro to configure the PLL clock source and multiplication factor. |
mbed_official | 237:f3da66175598 | 937 | * @note This macro must be used only when the PLL is disabled. |
mbed_official | 237:f3da66175598 | 938 | * |
mbed_official | 237:f3da66175598 | 939 | * @param __RCC_PLLSource__: specifies the PLL entry clock source. |
mbed_official | 237:f3da66175598 | 940 | * This parameter can be one of the following values: |
mbed_official | 237:f3da66175598 | 941 | * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry |
mbed_official | 237:f3da66175598 | 942 | * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry |
mbed_official | 237:f3da66175598 | 943 | * @param __PLLMUL__: specifies the multiplication factor for PLL VCO input clock |
mbed_official | 237:f3da66175598 | 944 | * This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16. |
mbed_official | 237:f3da66175598 | 945 | * |
mbed_official | 237:f3da66175598 | 946 | */ |
mbed_official | 237:f3da66175598 | 947 | #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PLLMUL__) \ |
mbed_official | 237:f3da66175598 | 948 | MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSource__))) |
mbed_official | 237:f3da66175598 | 949 | |
mbed_official | 237:f3da66175598 | 950 | |
mbed_official | 237:f3da66175598 | 951 | /** @brief Macro to get the clock source used as system clock. |
mbed_official | 237:f3da66175598 | 952 | * @retval The clock source used as system clock. |
mbed_official | 237:f3da66175598 | 953 | * The returned value can be one of the following value: |
mbed_official | 237:f3da66175598 | 954 | * @arg RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock |
mbed_official | 237:f3da66175598 | 955 | * @arg RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock |
mbed_official | 237:f3da66175598 | 956 | * @arg RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock |
mbed_official | 237:f3da66175598 | 957 | */ |
mbed_official | 237:f3da66175598 | 958 | #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS))) |
mbed_official | 237:f3da66175598 | 959 | |
mbed_official | 237:f3da66175598 | 960 | /** @brief Macro to get the oscillator used as PLL clock source. |
mbed_official | 237:f3da66175598 | 961 | * @retval The oscillator used as PLL clock source. The returned value can be one |
mbed_official | 237:f3da66175598 | 962 | * of the following: |
mbed_official | 237:f3da66175598 | 963 | * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. |
mbed_official | 237:f3da66175598 | 964 | * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. |
mbed_official | 237:f3da66175598 | 965 | */ |
mbed_official | 237:f3da66175598 | 966 | #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC))) |
mbed_official | 237:f3da66175598 | 967 | |
mbed_official | 237:f3da66175598 | 968 | /** @defgroup RCC_Flags_Interrupts_Management |
mbed_official | 237:f3da66175598 | 969 | * @brief macros to manage the specified RCC Flags and interrupts. |
mbed_official | 237:f3da66175598 | 970 | * @{ |
mbed_official | 237:f3da66175598 | 971 | */ |
mbed_official | 237:f3da66175598 | 972 | |
mbed_official | 237:f3da66175598 | 973 | /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[12:8] bits to enable |
mbed_official | 237:f3da66175598 | 974 | * the selected interrupts.). |
mbed_official | 237:f3da66175598 | 975 | * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled. |
mbed_official | 237:f3da66175598 | 976 | * This parameter can be any combination of the following values: |
mbed_official | 237:f3da66175598 | 977 | * @arg RCC_IT_LSIRDY: LSI ready interrupt enable |
mbed_official | 237:f3da66175598 | 978 | * @arg RCC_IT_LSERDY: LSE ready interrupt enable |
mbed_official | 237:f3da66175598 | 979 | * @arg RCC_IT_HSIRDY: HSI ready interrupt enable |
mbed_official | 237:f3da66175598 | 980 | * @arg RCC_IT_HSERDY: HSE ready interrupt enable |
mbed_official | 237:f3da66175598 | 981 | * @arg RCC_IT_PLLRDY: PLL ready interrupt enable |
mbed_official | 237:f3da66175598 | 982 | */ |
mbed_official | 237:f3da66175598 | 983 | #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *)CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) |
mbed_official | 237:f3da66175598 | 984 | |
mbed_official | 237:f3da66175598 | 985 | /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[12:8] bits to disable |
mbed_official | 237:f3da66175598 | 986 | * the selected interrupts.). |
mbed_official | 237:f3da66175598 | 987 | * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled. |
mbed_official | 237:f3da66175598 | 988 | * This parameter can be any combination of the following values: |
mbed_official | 237:f3da66175598 | 989 | * @arg RCC_IT_LSIRDYIE: LSI ready interrupt enable |
mbed_official | 237:f3da66175598 | 990 | * @arg RCC_IT_LSERDYIE: LSE ready interrupt enable |
mbed_official | 237:f3da66175598 | 991 | * @arg RCC_IT_HSIRDYIE: HSI ready interrupt enable |
mbed_official | 237:f3da66175598 | 992 | * @arg RCC_IT_HSERDYIE: HSE ready interrupt enable |
mbed_official | 237:f3da66175598 | 993 | * @arg RCC_IT_PLLRDYIE: PLL ready interrupt enable |
mbed_official | 237:f3da66175598 | 994 | */ |
mbed_official | 237:f3da66175598 | 995 | #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *)CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__)) |
mbed_official | 237:f3da66175598 | 996 | |
mbed_official | 237:f3da66175598 | 997 | /** @brief Clear the RCC's interrupt pending bits ( Perform Byte access to RCC_CIR[23:16] |
mbed_official | 237:f3da66175598 | 998 | * bits to clear the selected interrupt pending bits. |
mbed_official | 237:f3da66175598 | 999 | * @param __IT__: specifies the interrupt pending bit to clear. |
mbed_official | 237:f3da66175598 | 1000 | * This parameter can be any combination of the following values: |
mbed_official | 237:f3da66175598 | 1001 | * @arg RCC_IT_LSIRDYC: LSI ready interrupt clear |
mbed_official | 237:f3da66175598 | 1002 | * @arg RCC_IT_LSERDYC: LSE ready interrupt clear |
mbed_official | 237:f3da66175598 | 1003 | * @arg RCC_IT_HSIRDYC: HSI ready interrupt clear |
mbed_official | 237:f3da66175598 | 1004 | * @arg RCC_IT_HSERDYC: HSE ready interrupt clear |
mbed_official | 237:f3da66175598 | 1005 | * @arg RCC_IT_PLLRDYC: PLL ready interrupt clear |
mbed_official | 237:f3da66175598 | 1006 | * @arg RCC_IT_CSSC: Clock Security System interrupt clear |
mbed_official | 237:f3da66175598 | 1007 | */ |
mbed_official | 237:f3da66175598 | 1008 | #define __HAL_RCC_CLEAR_IT(__IT__) (*(__IO uint8_t *)CIR_BYTE2_ADDRESS = (__IT__)) |
mbed_official | 237:f3da66175598 | 1009 | |
mbed_official | 237:f3da66175598 | 1010 | /** @brief Check the RCC's interrupt has occurred or not. |
mbed_official | 237:f3da66175598 | 1011 | * @param __IT__: specifies the RCC interrupt source to check. |
mbed_official | 237:f3da66175598 | 1012 | * This parameter can be one of the following values: |
mbed_official | 237:f3da66175598 | 1013 | * @arg RCC_IT_LSIRDYF: LSI ready interrupt flag |
mbed_official | 237:f3da66175598 | 1014 | * @arg RCC_IT_LSERDYF: LSE ready interrupt flag |
mbed_official | 237:f3da66175598 | 1015 | * @arg RCC_IT_HSIRDYF: HSI ready interrupt flag |
mbed_official | 237:f3da66175598 | 1016 | * @arg RCC_IT_HSERDYF: HSE ready interrupt flag |
mbed_official | 237:f3da66175598 | 1017 | * @arg RCC_IT_PLLRDYF: PLL ready interrupt flag |
mbed_official | 237:f3da66175598 | 1018 | * @arg RCC_IT_CSSF: Clock Security System interrupt flag |
mbed_official | 237:f3da66175598 | 1019 | * @retval The new state of __IT__ (TRUE or FALSE). |
mbed_official | 237:f3da66175598 | 1020 | */ |
mbed_official | 237:f3da66175598 | 1021 | #define __HAL_RCC_GET_IT(__IT__) ((RCC->CIR & (__IT__)) == (__IT__)) |
mbed_official | 237:f3da66175598 | 1022 | |
mbed_official | 237:f3da66175598 | 1023 | /** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, |
mbed_official | 237:f3da66175598 | 1024 | * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST |
mbed_official | 237:f3da66175598 | 1025 | */ |
mbed_official | 237:f3da66175598 | 1026 | #define __HAL_RCC_CLEAR_RESET_FLAGS() (*(__IO uint32_t *)CSR_RMVF_BB = ENABLE) |
mbed_official | 237:f3da66175598 | 1027 | |
mbed_official | 237:f3da66175598 | 1028 | /** @brief Check RCC flag is set or not. |
mbed_official | 237:f3da66175598 | 1029 | * @param __FLAG__: specifies the flag to check. |
mbed_official | 237:f3da66175598 | 1030 | * This parameter can be one of the following values: |
mbed_official | 237:f3da66175598 | 1031 | * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready |
mbed_official | 237:f3da66175598 | 1032 | * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready |
mbed_official | 237:f3da66175598 | 1033 | * @arg RCC_FLAG_PLLRDY: PLL clock ready |
mbed_official | 237:f3da66175598 | 1034 | * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready |
mbed_official | 237:f3da66175598 | 1035 | * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready |
mbed_official | 237:f3da66175598 | 1036 | * @arg RCC_FLAG_OBLRST: Option Byte Load reset |
mbed_official | 237:f3da66175598 | 1037 | * @arg RCC_FLAG_PINRST: Pin reset |
mbed_official | 237:f3da66175598 | 1038 | * @arg RCC_FLAG_PORRST: POR/PDR reset |
mbed_official | 237:f3da66175598 | 1039 | * @arg RCC_FLAG_SFTRST: Software reset |
mbed_official | 237:f3da66175598 | 1040 | * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset |
mbed_official | 237:f3da66175598 | 1041 | * @arg RCC_FLAG_WWDGRST: Window Watchdog reset |
mbed_official | 237:f3da66175598 | 1042 | * @arg RCC_FLAG_LPWRRST: Low Power reset |
mbed_official | 237:f3da66175598 | 1043 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
mbed_official | 237:f3da66175598 | 1044 | */ |
mbed_official | 237:f3da66175598 | 1045 | #define RCC_FLAG_MASK ((uint32_t)0x0000001F) |
mbed_official | 237:f3da66175598 | 1046 | #define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX)? RCC->CR : \ |
mbed_official | 237:f3da66175598 | 1047 | ((((__FLAG__) >> 5U) == BDCR_REG_INDEX) ? RCC->BDCR : \ |
mbed_official | 237:f3da66175598 | 1048 | RCC->CSR)) & (1U << ((__FLAG__) & RCC_FLAG_MASK))) |
mbed_official | 237:f3da66175598 | 1049 | |
mbed_official | 237:f3da66175598 | 1050 | |
mbed_official | 237:f3da66175598 | 1051 | /** |
mbed_official | 237:f3da66175598 | 1052 | * @} |
mbed_official | 237:f3da66175598 | 1053 | */ |
mbed_official | 237:f3da66175598 | 1054 | |
mbed_official | 237:f3da66175598 | 1055 | /* Include RCC HAL Extension module */ |
mbed_official | 237:f3da66175598 | 1056 | #include "stm32f3xx_hal_rcc_ex.h" |
mbed_official | 237:f3da66175598 | 1057 | |
mbed_official | 237:f3da66175598 | 1058 | /* Exported functions --------------------------------------------------------*/ |
mbed_official | 237:f3da66175598 | 1059 | |
mbed_official | 237:f3da66175598 | 1060 | /* Initialization and de-initialization functions ***************************/ |
mbed_official | 237:f3da66175598 | 1061 | void HAL_RCC_DeInit(void); |
mbed_official | 237:f3da66175598 | 1062 | HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); |
mbed_official | 237:f3da66175598 | 1063 | HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); |
mbed_official | 237:f3da66175598 | 1064 | |
mbed_official | 237:f3da66175598 | 1065 | /* Peripheral Control functions *********************************************/ |
mbed_official | 237:f3da66175598 | 1066 | void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); |
mbed_official | 237:f3da66175598 | 1067 | void HAL_RCC_EnableCSS(void); |
mbed_official | 237:f3da66175598 | 1068 | void HAL_RCC_DisableCSS(void); |
mbed_official | 237:f3da66175598 | 1069 | uint32_t HAL_RCC_GetSysClockFreq(void); |
mbed_official | 237:f3da66175598 | 1070 | uint32_t HAL_RCC_GetHCLKFreq(void); |
mbed_official | 237:f3da66175598 | 1071 | uint32_t HAL_RCC_GetPCLK1Freq(void); |
mbed_official | 237:f3da66175598 | 1072 | uint32_t HAL_RCC_GetPCLK2Freq(void); |
mbed_official | 237:f3da66175598 | 1073 | void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); |
mbed_official | 237:f3da66175598 | 1074 | void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); |
mbed_official | 237:f3da66175598 | 1075 | |
mbed_official | 237:f3da66175598 | 1076 | /* CSS NMI IRQ handler */ |
mbed_official | 237:f3da66175598 | 1077 | void HAL_RCC_NMI_IRQHandler(void); |
mbed_official | 237:f3da66175598 | 1078 | |
mbed_official | 237:f3da66175598 | 1079 | /* User Callbacks in non blocking mode (IT mode) */ |
mbed_official | 237:f3da66175598 | 1080 | void HAL_RCC_CCSCallback(void); |
mbed_official | 237:f3da66175598 | 1081 | |
mbed_official | 237:f3da66175598 | 1082 | /** |
mbed_official | 237:f3da66175598 | 1083 | * @} |
mbed_official | 237:f3da66175598 | 1084 | */ |
mbed_official | 237:f3da66175598 | 1085 | |
mbed_official | 237:f3da66175598 | 1086 | /** |
mbed_official | 237:f3da66175598 | 1087 | * @} |
mbed_official | 237:f3da66175598 | 1088 | */ |
mbed_official | 237:f3da66175598 | 1089 | |
mbed_official | 237:f3da66175598 | 1090 | #ifdef __cplusplus |
mbed_official | 237:f3da66175598 | 1091 | } |
mbed_official | 237:f3da66175598 | 1092 | #endif |
mbed_official | 237:f3da66175598 | 1093 | |
mbed_official | 237:f3da66175598 | 1094 | #endif /* __STM32F3xx_HAL_RCC_H */ |
mbed_official | 237:f3da66175598 | 1095 | |
mbed_official | 237:f3da66175598 | 1096 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |