mbed library sources modified for open wear
Dependents: openwear-lifelogger-example
Fork of mbed-src by
targets/cmsis/TARGET_STM/TARGET_NUCLEO_F072RB/stm32f0xx_hal_rcc.h@218:44081b78fdc2, 2014-05-30 (annotated)
- Committer:
- mbed_official
- Date:
- Fri May 30 15:30:09 2014 +0100
- Revision:
- 218:44081b78fdc2
- Parent:
- 205:c41fc65bcfb4
Synchronized with git revision d854859072d318241476ccc5f335965444d4c1d8
Full URL: https://github.com/mbedmicro/mbed/commit/d854859072d318241476ccc5f335965444d4c1d8/
[NUCLEO_F072RB] Update CubeF0 HAL driver
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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mbed_official | 205:c41fc65bcfb4 | 1 | /** |
mbed_official | 205:c41fc65bcfb4 | 2 | ****************************************************************************** |
mbed_official | 205:c41fc65bcfb4 | 3 | * @file stm32f0xx_hal_rcc.h |
mbed_official | 205:c41fc65bcfb4 | 4 | * @author MCD Application Team |
mbed_official | 205:c41fc65bcfb4 | 5 | * @version V1.0.0 |
mbed_official | 218:44081b78fdc2 | 6 | * @date 28-May-2014 |
mbed_official | 205:c41fc65bcfb4 | 7 | * @brief Header file of RCC HAL module. |
mbed_official | 205:c41fc65bcfb4 | 8 | ****************************************************************************** |
mbed_official | 205:c41fc65bcfb4 | 9 | * @attention |
mbed_official | 205:c41fc65bcfb4 | 10 | * |
mbed_official | 205:c41fc65bcfb4 | 11 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
mbed_official | 205:c41fc65bcfb4 | 12 | * |
mbed_official | 205:c41fc65bcfb4 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
mbed_official | 205:c41fc65bcfb4 | 14 | * are permitted provided that the following conditions are met: |
mbed_official | 205:c41fc65bcfb4 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
mbed_official | 205:c41fc65bcfb4 | 16 | * this list of conditions and the following disclaimer. |
mbed_official | 205:c41fc65bcfb4 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
mbed_official | 205:c41fc65bcfb4 | 18 | * this list of conditions and the following disclaimer in the documentation |
mbed_official | 205:c41fc65bcfb4 | 19 | * and/or other materials provided with the distribution. |
mbed_official | 205:c41fc65bcfb4 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
mbed_official | 205:c41fc65bcfb4 | 21 | * may be used to endorse or promote products derived from this software |
mbed_official | 205:c41fc65bcfb4 | 22 | * without specific prior written permission. |
mbed_official | 205:c41fc65bcfb4 | 23 | * |
mbed_official | 205:c41fc65bcfb4 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
mbed_official | 205:c41fc65bcfb4 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
mbed_official | 205:c41fc65bcfb4 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
mbed_official | 205:c41fc65bcfb4 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
mbed_official | 205:c41fc65bcfb4 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
mbed_official | 205:c41fc65bcfb4 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
mbed_official | 205:c41fc65bcfb4 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
mbed_official | 205:c41fc65bcfb4 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
mbed_official | 205:c41fc65bcfb4 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
mbed_official | 205:c41fc65bcfb4 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
mbed_official | 205:c41fc65bcfb4 | 34 | * |
mbed_official | 205:c41fc65bcfb4 | 35 | ****************************************************************************** |
mbed_official | 205:c41fc65bcfb4 | 36 | */ |
mbed_official | 205:c41fc65bcfb4 | 37 | |
mbed_official | 205:c41fc65bcfb4 | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
mbed_official | 205:c41fc65bcfb4 | 39 | #ifndef __STM32F0xx_HAL_RCC_H |
mbed_official | 205:c41fc65bcfb4 | 40 | #define __STM32F0xx_HAL_RCC_H |
mbed_official | 205:c41fc65bcfb4 | 41 | |
mbed_official | 205:c41fc65bcfb4 | 42 | #ifdef __cplusplus |
mbed_official | 205:c41fc65bcfb4 | 43 | extern "C" { |
mbed_official | 205:c41fc65bcfb4 | 44 | #endif |
mbed_official | 205:c41fc65bcfb4 | 45 | |
mbed_official | 205:c41fc65bcfb4 | 46 | /* Includes ------------------------------------------------------------------*/ |
mbed_official | 205:c41fc65bcfb4 | 47 | #include "stm32f0xx_hal_def.h" |
mbed_official | 205:c41fc65bcfb4 | 48 | |
mbed_official | 205:c41fc65bcfb4 | 49 | /** @addtogroup STM32F0xx_HAL_Driver |
mbed_official | 205:c41fc65bcfb4 | 50 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 51 | */ |
mbed_official | 205:c41fc65bcfb4 | 52 | |
mbed_official | 205:c41fc65bcfb4 | 53 | /** @addtogroup RCC |
mbed_official | 205:c41fc65bcfb4 | 54 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 55 | */ |
mbed_official | 205:c41fc65bcfb4 | 56 | |
mbed_official | 205:c41fc65bcfb4 | 57 | /* Exported types ------------------------------------------------------------*/ |
mbed_official | 205:c41fc65bcfb4 | 58 | |
mbed_official | 205:c41fc65bcfb4 | 59 | /** |
mbed_official | 205:c41fc65bcfb4 | 60 | * @brief RCC PLL configuration structure definition |
mbed_official | 205:c41fc65bcfb4 | 61 | */ |
mbed_official | 205:c41fc65bcfb4 | 62 | typedef struct |
mbed_official | 205:c41fc65bcfb4 | 63 | { |
mbed_official | 205:c41fc65bcfb4 | 64 | uint32_t PLLState; /*!< PLLState: The new state of the PLL. |
mbed_official | 205:c41fc65bcfb4 | 65 | This parameter can be a value of @ref RCC_PLL_Config */ |
mbed_official | 205:c41fc65bcfb4 | 66 | |
mbed_official | 205:c41fc65bcfb4 | 67 | uint32_t PLLSource; /*!< PLLSource: PLL entry clock source. |
mbed_official | 205:c41fc65bcfb4 | 68 | This parameter must be a value of @ref RCC_PLL_Clock_Source */ |
mbed_official | 205:c41fc65bcfb4 | 69 | |
mbed_official | 205:c41fc65bcfb4 | 70 | uint32_t PREDIV; /*!< PREDIV: Predivision factor for PLL VCO input clock |
mbed_official | 205:c41fc65bcfb4 | 71 | This parameter must be a value of @ref RCC_PLL_Prediv_Factor */ |
mbed_official | 205:c41fc65bcfb4 | 72 | |
mbed_official | 205:c41fc65bcfb4 | 73 | uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock |
mbed_official | 205:c41fc65bcfb4 | 74 | This parameter must be a value of @ref RCC_PLL_Multiplication_Factor */ |
mbed_official | 205:c41fc65bcfb4 | 75 | |
mbed_official | 205:c41fc65bcfb4 | 76 | }RCC_PLLInitTypeDef; |
mbed_official | 205:c41fc65bcfb4 | 77 | |
mbed_official | 205:c41fc65bcfb4 | 78 | /** |
mbed_official | 205:c41fc65bcfb4 | 79 | * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition |
mbed_official | 205:c41fc65bcfb4 | 80 | */ |
mbed_official | 205:c41fc65bcfb4 | 81 | typedef struct |
mbed_official | 205:c41fc65bcfb4 | 82 | { |
mbed_official | 205:c41fc65bcfb4 | 83 | uint32_t OscillatorType; /*!< The Oscillators to be configured. |
mbed_official | 205:c41fc65bcfb4 | 84 | This parameter can be a value of @ref RCC_Oscillator_Type */ |
mbed_official | 205:c41fc65bcfb4 | 85 | |
mbed_official | 205:c41fc65bcfb4 | 86 | uint32_t HSEState; /*!< The new state of the HSE. |
mbed_official | 205:c41fc65bcfb4 | 87 | This parameter can be a value of @ref RCC_HSE_Config */ |
mbed_official | 205:c41fc65bcfb4 | 88 | |
mbed_official | 205:c41fc65bcfb4 | 89 | uint32_t LSEState; /*!< The new state of the LSE. |
mbed_official | 205:c41fc65bcfb4 | 90 | This parameter can be a value of @ref RCC_LSE_Config */ |
mbed_official | 205:c41fc65bcfb4 | 91 | |
mbed_official | 205:c41fc65bcfb4 | 92 | uint32_t HSIState; /*!< The new state of the HSI. |
mbed_official | 205:c41fc65bcfb4 | 93 | This parameter can be a value of @ref RCC_HSI_Config */ |
mbed_official | 205:c41fc65bcfb4 | 94 | |
mbed_official | 205:c41fc65bcfb4 | 95 | uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). |
mbed_official | 205:c41fc65bcfb4 | 96 | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ |
mbed_official | 205:c41fc65bcfb4 | 97 | |
mbed_official | 205:c41fc65bcfb4 | 98 | uint32_t HSI14State; /*!< The new state of the HSI14. |
mbed_official | 205:c41fc65bcfb4 | 99 | This parameter can be a value of @ref RCC_HSI14_Config */ |
mbed_official | 205:c41fc65bcfb4 | 100 | |
mbed_official | 205:c41fc65bcfb4 | 101 | uint32_t HSI14CalibrationValue; /*!< The HSI14 calibration trimming value (default is RCC_HSI14CALIBRATION_DEFAULT). |
mbed_official | 205:c41fc65bcfb4 | 102 | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ |
mbed_official | 205:c41fc65bcfb4 | 103 | |
mbed_official | 205:c41fc65bcfb4 | 104 | uint32_t HSI48State; /*!< The new state of the HSI48 (only applicable to STM32F07x and STM32F0x2 devices). |
mbed_official | 205:c41fc65bcfb4 | 105 | This parameter can be a value of @ref RCCEx_HSI48_Config */ |
mbed_official | 205:c41fc65bcfb4 | 106 | |
mbed_official | 205:c41fc65bcfb4 | 107 | uint32_t LSIState; /*!< The new state of the LSI. |
mbed_official | 205:c41fc65bcfb4 | 108 | This parameter can be a value of @ref RCC_LSI_Config */ |
mbed_official | 205:c41fc65bcfb4 | 109 | |
mbed_official | 205:c41fc65bcfb4 | 110 | RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ |
mbed_official | 205:c41fc65bcfb4 | 111 | |
mbed_official | 205:c41fc65bcfb4 | 112 | }RCC_OscInitTypeDef; |
mbed_official | 205:c41fc65bcfb4 | 113 | |
mbed_official | 205:c41fc65bcfb4 | 114 | /** |
mbed_official | 205:c41fc65bcfb4 | 115 | * @brief RCC System, AHB and APB busses clock configuration structure definition |
mbed_official | 205:c41fc65bcfb4 | 116 | */ |
mbed_official | 205:c41fc65bcfb4 | 117 | typedef struct |
mbed_official | 205:c41fc65bcfb4 | 118 | { |
mbed_official | 205:c41fc65bcfb4 | 119 | uint32_t ClockType; /*!< The clock to be configured. |
mbed_official | 205:c41fc65bcfb4 | 120 | This parameter can be a value of @ref RCC_System_Clock_Type */ |
mbed_official | 205:c41fc65bcfb4 | 121 | |
mbed_official | 205:c41fc65bcfb4 | 122 | uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock. |
mbed_official | 205:c41fc65bcfb4 | 123 | This parameter can be a value of @ref RCC_System_Clock_Source */ |
mbed_official | 205:c41fc65bcfb4 | 124 | |
mbed_official | 205:c41fc65bcfb4 | 125 | uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). |
mbed_official | 205:c41fc65bcfb4 | 126 | This parameter can be a value of @ref RCC_AHB_Clock_Source */ |
mbed_official | 205:c41fc65bcfb4 | 127 | |
mbed_official | 205:c41fc65bcfb4 | 128 | uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). |
mbed_official | 205:c41fc65bcfb4 | 129 | This parameter can be a value of @ref RCC_APB1_Clock_Source */ |
mbed_official | 205:c41fc65bcfb4 | 130 | |
mbed_official | 205:c41fc65bcfb4 | 131 | }RCC_ClkInitTypeDef; |
mbed_official | 205:c41fc65bcfb4 | 132 | |
mbed_official | 205:c41fc65bcfb4 | 133 | /* Exported constants --------------------------------------------------------*/ |
mbed_official | 205:c41fc65bcfb4 | 134 | /** @defgroup RCC_Exported_Constants |
mbed_official | 205:c41fc65bcfb4 | 135 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 136 | */ |
mbed_official | 205:c41fc65bcfb4 | 137 | |
mbed_official | 205:c41fc65bcfb4 | 138 | #define RCC_OFFSET (RCC_BASE - PERIPH_BASE) |
mbed_official | 205:c41fc65bcfb4 | 139 | /* --- CR Register ---*/ |
mbed_official | 205:c41fc65bcfb4 | 140 | #define RCC_CR_OFFSET (RCC_OFFSET + 0x00) |
mbed_official | 205:c41fc65bcfb4 | 141 | /* --- CFGR Register ---*/ |
mbed_official | 205:c41fc65bcfb4 | 142 | #define RCC_CFGR_OFFSET (RCC_OFFSET + 0x04) |
mbed_official | 205:c41fc65bcfb4 | 143 | /* --- CIR Register ---*/ |
mbed_official | 205:c41fc65bcfb4 | 144 | #define RCC_CIR_OFFSET (RCC_OFFSET + 0x08) |
mbed_official | 205:c41fc65bcfb4 | 145 | /* --- BDCR Register ---*/ |
mbed_official | 205:c41fc65bcfb4 | 146 | #define RCC_BDCR_OFFSET (RCC_OFFSET + 0x20) |
mbed_official | 205:c41fc65bcfb4 | 147 | /* --- CSR Register ---*/ |
mbed_official | 205:c41fc65bcfb4 | 148 | #define RCC_CSR_OFFSET (RCC_OFFSET + 0x24) |
mbed_official | 205:c41fc65bcfb4 | 149 | /* --- CR2 Register ---*/ |
mbed_official | 205:c41fc65bcfb4 | 150 | #define RCC_CR2_OFFSET (RCC_OFFSET + 0x34) |
mbed_official | 205:c41fc65bcfb4 | 151 | |
mbed_official | 205:c41fc65bcfb4 | 152 | /* CR register byte 2 (Bits[23:16]) base address */ |
mbed_official | 205:c41fc65bcfb4 | 153 | #define RCC_CR_BYTE2_ADDRESS (PERIPH_BASE + RCC_CR_OFFSET + 0x02) |
mbed_official | 205:c41fc65bcfb4 | 154 | |
mbed_official | 205:c41fc65bcfb4 | 155 | /* CIR register byte 1 (Bits[15:8]) base address */ |
mbed_official | 205:c41fc65bcfb4 | 156 | #define RCC_CIR_BYTE1_ADDRESS (PERIPH_BASE + RCC_CIR_OFFSET + 0x01) |
mbed_official | 205:c41fc65bcfb4 | 157 | |
mbed_official | 205:c41fc65bcfb4 | 158 | /* CIR register byte 2 (Bits[23:16]) base address */ |
mbed_official | 205:c41fc65bcfb4 | 159 | #define RCC_CIR_BYTE2_ADDRESS (PERIPH_BASE + RCC_CIR_OFFSET + 0x02) |
mbed_official | 205:c41fc65bcfb4 | 160 | |
mbed_official | 205:c41fc65bcfb4 | 161 | /* CSR register byte 1 (Bits[15:8]) base address */ |
mbed_official | 205:c41fc65bcfb4 | 162 | #define RCC_CSR_BYTE1_ADDRESS (PERIPH_BASE + RCC_CSR_OFFSET + 0x01) |
mbed_official | 205:c41fc65bcfb4 | 163 | |
mbed_official | 205:c41fc65bcfb4 | 164 | /* BDCR register byte 0 (Bits[7:0] base address */ |
mbed_official | 205:c41fc65bcfb4 | 165 | #define RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET) |
mbed_official | 205:c41fc65bcfb4 | 166 | |
mbed_official | 205:c41fc65bcfb4 | 167 | /* LSE state change timeout */ |
mbed_official | 205:c41fc65bcfb4 | 168 | #define LSE_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */ |
mbed_official | 205:c41fc65bcfb4 | 169 | |
mbed_official | 205:c41fc65bcfb4 | 170 | /* Disable Backup domain write protection state change timeout */ |
mbed_official | 205:c41fc65bcfb4 | 171 | #define DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ |
mbed_official | 205:c41fc65bcfb4 | 172 | |
mbed_official | 205:c41fc65bcfb4 | 173 | #define RCC_CFGR_PLLMUL_BITNUMBER 18 |
mbed_official | 205:c41fc65bcfb4 | 174 | #define RCC_CFGR2_PREDIV_BITNUMBER 0 |
mbed_official | 205:c41fc65bcfb4 | 175 | |
mbed_official | 205:c41fc65bcfb4 | 176 | /** @defgroup RCC_Oscillator_Type |
mbed_official | 205:c41fc65bcfb4 | 177 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 178 | */ |
mbed_official | 205:c41fc65bcfb4 | 179 | #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000) |
mbed_official | 205:c41fc65bcfb4 | 180 | #define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001) |
mbed_official | 205:c41fc65bcfb4 | 181 | #define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002) |
mbed_official | 205:c41fc65bcfb4 | 182 | #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004) |
mbed_official | 205:c41fc65bcfb4 | 183 | #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008) |
mbed_official | 205:c41fc65bcfb4 | 184 | #define RCC_OSCILLATORTYPE_HSI14 ((uint32_t)0x00000010) |
mbed_official | 205:c41fc65bcfb4 | 185 | #define RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020) |
mbed_official | 205:c41fc65bcfb4 | 186 | |
mbed_official | 205:c41fc65bcfb4 | 187 | #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \ |
mbed_official | 205:c41fc65bcfb4 | 188 | (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ |
mbed_official | 205:c41fc65bcfb4 | 189 | (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ |
mbed_official | 205:c41fc65bcfb4 | 190 | (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ |
mbed_official | 205:c41fc65bcfb4 | 191 | (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \ |
mbed_official | 205:c41fc65bcfb4 | 192 | (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14) || \ |
mbed_official | 205:c41fc65bcfb4 | 193 | (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)) |
mbed_official | 205:c41fc65bcfb4 | 194 | /** |
mbed_official | 205:c41fc65bcfb4 | 195 | * @} |
mbed_official | 205:c41fc65bcfb4 | 196 | */ |
mbed_official | 205:c41fc65bcfb4 | 197 | |
mbed_official | 205:c41fc65bcfb4 | 198 | /** @defgroup RCC_HSE_Config |
mbed_official | 205:c41fc65bcfb4 | 199 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 200 | */ |
mbed_official | 205:c41fc65bcfb4 | 201 | #define RCC_HSE_OFF ((uint8_t)0x00) |
mbed_official | 205:c41fc65bcfb4 | 202 | #define RCC_HSE_ON ((uint8_t)0x01) |
mbed_official | 205:c41fc65bcfb4 | 203 | #define RCC_HSE_BYPASS ((uint8_t)0x05) |
mbed_official | 205:c41fc65bcfb4 | 204 | |
mbed_official | 205:c41fc65bcfb4 | 205 | #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ |
mbed_official | 205:c41fc65bcfb4 | 206 | ((HSE) == RCC_HSE_BYPASS)) |
mbed_official | 205:c41fc65bcfb4 | 207 | /** |
mbed_official | 205:c41fc65bcfb4 | 208 | * @} |
mbed_official | 205:c41fc65bcfb4 | 209 | */ |
mbed_official | 205:c41fc65bcfb4 | 210 | |
mbed_official | 205:c41fc65bcfb4 | 211 | /** @defgroup RCC_LSE_Config |
mbed_official | 205:c41fc65bcfb4 | 212 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 213 | */ |
mbed_official | 205:c41fc65bcfb4 | 214 | #define RCC_LSE_OFF ((uint8_t)0x00) |
mbed_official | 205:c41fc65bcfb4 | 215 | #define RCC_LSE_ON ((uint8_t)0x01) |
mbed_official | 205:c41fc65bcfb4 | 216 | #define RCC_LSE_BYPASS ((uint8_t)0x05) |
mbed_official | 205:c41fc65bcfb4 | 217 | |
mbed_official | 205:c41fc65bcfb4 | 218 | #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ |
mbed_official | 205:c41fc65bcfb4 | 219 | ((LSE) == RCC_LSE_BYPASS)) |
mbed_official | 205:c41fc65bcfb4 | 220 | /** |
mbed_official | 205:c41fc65bcfb4 | 221 | * @} |
mbed_official | 205:c41fc65bcfb4 | 222 | */ |
mbed_official | 205:c41fc65bcfb4 | 223 | |
mbed_official | 205:c41fc65bcfb4 | 224 | /** @defgroup RCC_HSI_Config |
mbed_official | 205:c41fc65bcfb4 | 225 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 226 | */ |
mbed_official | 205:c41fc65bcfb4 | 227 | #define RCC_HSI_OFF ((uint8_t)0x00) |
mbed_official | 205:c41fc65bcfb4 | 228 | #define RCC_HSI_ON ((uint8_t)0x01) |
mbed_official | 205:c41fc65bcfb4 | 229 | |
mbed_official | 205:c41fc65bcfb4 | 230 | #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON)) |
mbed_official | 205:c41fc65bcfb4 | 231 | |
mbed_official | 205:c41fc65bcfb4 | 232 | #define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */ |
mbed_official | 205:c41fc65bcfb4 | 233 | /** |
mbed_official | 205:c41fc65bcfb4 | 234 | * @} |
mbed_official | 205:c41fc65bcfb4 | 235 | */ |
mbed_official | 205:c41fc65bcfb4 | 236 | |
mbed_official | 205:c41fc65bcfb4 | 237 | /** @defgroup RCC_HSI14_Config |
mbed_official | 205:c41fc65bcfb4 | 238 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 239 | */ |
mbed_official | 205:c41fc65bcfb4 | 240 | #define RCC_HSI14_OFF ((uint32_t)0x00) |
mbed_official | 205:c41fc65bcfb4 | 241 | #define RCC_HSI14_ON RCC_CR2_HSI14ON |
mbed_official | 205:c41fc65bcfb4 | 242 | #define RCC_HSI14_ADC_CONTROL (~RCC_CR2_HSI14DIS) |
mbed_official | 205:c41fc65bcfb4 | 243 | |
mbed_official | 205:c41fc65bcfb4 | 244 | #define IS_RCC_HSI14(HSI14) (((HSI14) == RCC_HSI14_OFF) || ((HSI14) == RCC_HSI14_ON) || ((HSI14) == RCC_HSI14_ADC_CONTROL)) |
mbed_official | 205:c41fc65bcfb4 | 245 | |
mbed_official | 205:c41fc65bcfb4 | 246 | #define RCC_HSI14CALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI14 calibration trimming value */ |
mbed_official | 205:c41fc65bcfb4 | 247 | /** |
mbed_official | 205:c41fc65bcfb4 | 248 | * @} |
mbed_official | 205:c41fc65bcfb4 | 249 | */ |
mbed_official | 205:c41fc65bcfb4 | 250 | |
mbed_official | 205:c41fc65bcfb4 | 251 | /** @defgroup RCC_LSI_Config |
mbed_official | 205:c41fc65bcfb4 | 252 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 253 | */ |
mbed_official | 205:c41fc65bcfb4 | 254 | #define RCC_LSI_OFF ((uint8_t)0x00) |
mbed_official | 205:c41fc65bcfb4 | 255 | #define RCC_LSI_ON ((uint8_t)0x01) |
mbed_official | 205:c41fc65bcfb4 | 256 | |
mbed_official | 205:c41fc65bcfb4 | 257 | #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON)) |
mbed_official | 205:c41fc65bcfb4 | 258 | /** |
mbed_official | 205:c41fc65bcfb4 | 259 | * @} |
mbed_official | 205:c41fc65bcfb4 | 260 | */ |
mbed_official | 205:c41fc65bcfb4 | 261 | |
mbed_official | 205:c41fc65bcfb4 | 262 | /** @defgroup RCC_PLL_Config |
mbed_official | 205:c41fc65bcfb4 | 263 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 264 | */ |
mbed_official | 205:c41fc65bcfb4 | 265 | #define RCC_PLL_NONE ((uint8_t)0x00) |
mbed_official | 205:c41fc65bcfb4 | 266 | #define RCC_PLL_OFF ((uint8_t)0x01) |
mbed_official | 205:c41fc65bcfb4 | 267 | #define RCC_PLL_ON ((uint8_t)0x02) |
mbed_official | 205:c41fc65bcfb4 | 268 | |
mbed_official | 205:c41fc65bcfb4 | 269 | #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON)) |
mbed_official | 205:c41fc65bcfb4 | 270 | /** |
mbed_official | 205:c41fc65bcfb4 | 271 | * @} |
mbed_official | 205:c41fc65bcfb4 | 272 | */ |
mbed_official | 205:c41fc65bcfb4 | 273 | |
mbed_official | 205:c41fc65bcfb4 | 274 | /** @defgroup RCC_PLL_Prediv_Factor |
mbed_official | 205:c41fc65bcfb4 | 275 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 276 | */ |
mbed_official | 205:c41fc65bcfb4 | 277 | #define RCC_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1 |
mbed_official | 205:c41fc65bcfb4 | 278 | #define RCC_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2 |
mbed_official | 205:c41fc65bcfb4 | 279 | #define RCC_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3 |
mbed_official | 205:c41fc65bcfb4 | 280 | #define RCC_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4 |
mbed_official | 205:c41fc65bcfb4 | 281 | #define RCC_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5 |
mbed_official | 205:c41fc65bcfb4 | 282 | #define RCC_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6 |
mbed_official | 205:c41fc65bcfb4 | 283 | #define RCC_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7 |
mbed_official | 205:c41fc65bcfb4 | 284 | #define RCC_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8 |
mbed_official | 205:c41fc65bcfb4 | 285 | #define RCC_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9 |
mbed_official | 205:c41fc65bcfb4 | 286 | #define RCC_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10 |
mbed_official | 205:c41fc65bcfb4 | 287 | #define RCC_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11 |
mbed_official | 205:c41fc65bcfb4 | 288 | #define RCC_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12 |
mbed_official | 205:c41fc65bcfb4 | 289 | #define RCC_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13 |
mbed_official | 205:c41fc65bcfb4 | 290 | #define RCC_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14 |
mbed_official | 205:c41fc65bcfb4 | 291 | #define RCC_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15 |
mbed_official | 205:c41fc65bcfb4 | 292 | #define RCC_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16 |
mbed_official | 205:c41fc65bcfb4 | 293 | |
mbed_official | 205:c41fc65bcfb4 | 294 | #define IS_RCC_PREDIV(PREDIV) (((PREDIV) == RCC_PREDIV_DIV1) || ((PREDIV) == RCC_PREDIV_DIV2) || \ |
mbed_official | 205:c41fc65bcfb4 | 295 | ((PREDIV) == RCC_PREDIV_DIV3) || ((PREDIV) == RCC_PREDIV_DIV4) || \ |
mbed_official | 205:c41fc65bcfb4 | 296 | ((PREDIV) == RCC_PREDIV_DIV5) || ((PREDIV) == RCC_PREDIV_DIV6) || \ |
mbed_official | 205:c41fc65bcfb4 | 297 | ((PREDIV) == RCC_PREDIV_DIV7) || ((PREDIV) == RCC_PREDIV_DIV8) || \ |
mbed_official | 205:c41fc65bcfb4 | 298 | ((PREDIV) == RCC_PREDIV_DIV9) || ((PREDIV) == RCC_PREDIV_DIV10) || \ |
mbed_official | 205:c41fc65bcfb4 | 299 | ((PREDIV) == RCC_PREDIV_DIV11) || ((PREDIV) == RCC_PREDIV_DIV12) || \ |
mbed_official | 205:c41fc65bcfb4 | 300 | ((PREDIV) == RCC_PREDIV_DIV13) || ((PREDIV) == RCC_PREDIV_DIV14) || \ |
mbed_official | 205:c41fc65bcfb4 | 301 | ((PREDIV) == RCC_PREDIV_DIV15) || ((PREDIV) == RCC_PREDIV_DIV16)) |
mbed_official | 205:c41fc65bcfb4 | 302 | /** |
mbed_official | 205:c41fc65bcfb4 | 303 | * @} |
mbed_official | 205:c41fc65bcfb4 | 304 | */ |
mbed_official | 205:c41fc65bcfb4 | 305 | |
mbed_official | 205:c41fc65bcfb4 | 306 | /** @defgroup RCC_PLL_Multiplication_Factor |
mbed_official | 205:c41fc65bcfb4 | 307 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 308 | */ |
mbed_official | 205:c41fc65bcfb4 | 309 | #define RCC_PLL_MUL2 RCC_CFGR_PLLMUL2 |
mbed_official | 205:c41fc65bcfb4 | 310 | #define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3 |
mbed_official | 205:c41fc65bcfb4 | 311 | #define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4 |
mbed_official | 205:c41fc65bcfb4 | 312 | #define RCC_PLL_MUL5 RCC_CFGR_PLLMUL5 |
mbed_official | 205:c41fc65bcfb4 | 313 | #define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6 |
mbed_official | 205:c41fc65bcfb4 | 314 | #define RCC_PLL_MUL7 RCC_CFGR_PLLMUL7 |
mbed_official | 205:c41fc65bcfb4 | 315 | #define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8 |
mbed_official | 205:c41fc65bcfb4 | 316 | #define RCC_PLL_MUL9 RCC_CFGR_PLLMUL9 |
mbed_official | 205:c41fc65bcfb4 | 317 | #define RCC_PLL_MUL10 RCC_CFGR_PLLMUL10 |
mbed_official | 205:c41fc65bcfb4 | 318 | #define RCC_PLL_MUL11 RCC_CFGR_PLLMUL11 |
mbed_official | 205:c41fc65bcfb4 | 319 | #define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12 |
mbed_official | 205:c41fc65bcfb4 | 320 | #define RCC_PLL_MUL13 RCC_CFGR_PLLMUL13 |
mbed_official | 205:c41fc65bcfb4 | 321 | #define RCC_PLL_MUL14 RCC_CFGR_PLLMUL14 |
mbed_official | 205:c41fc65bcfb4 | 322 | #define RCC_PLL_MUL15 RCC_CFGR_PLLMUL15 |
mbed_official | 205:c41fc65bcfb4 | 323 | #define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16 |
mbed_official | 205:c41fc65bcfb4 | 324 | |
mbed_official | 205:c41fc65bcfb4 | 325 | #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLL_MUL2) || ((MUL) == RCC_PLL_MUL3) || \ |
mbed_official | 205:c41fc65bcfb4 | 326 | ((MUL) == RCC_PLL_MUL4) || ((MUL) == RCC_PLL_MUL5) || \ |
mbed_official | 205:c41fc65bcfb4 | 327 | ((MUL) == RCC_PLL_MUL6) || ((MUL) == RCC_PLL_MUL7) || \ |
mbed_official | 205:c41fc65bcfb4 | 328 | ((MUL) == RCC_PLL_MUL8) || ((MUL) == RCC_PLL_MUL9) || \ |
mbed_official | 205:c41fc65bcfb4 | 329 | ((MUL) == RCC_PLL_MUL10) || ((MUL) == RCC_PLL_MUL11) || \ |
mbed_official | 205:c41fc65bcfb4 | 330 | ((MUL) == RCC_PLL_MUL12) || ((MUL) == RCC_PLL_MUL13) || \ |
mbed_official | 205:c41fc65bcfb4 | 331 | ((MUL) == RCC_PLL_MUL14) || ((MUL) == RCC_PLL_MUL15) || \ |
mbed_official | 205:c41fc65bcfb4 | 332 | ((MUL) == RCC_PLL_MUL16)) |
mbed_official | 205:c41fc65bcfb4 | 333 | /** |
mbed_official | 205:c41fc65bcfb4 | 334 | * @} |
mbed_official | 205:c41fc65bcfb4 | 335 | */ |
mbed_official | 205:c41fc65bcfb4 | 336 | |
mbed_official | 205:c41fc65bcfb4 | 337 | /** @defgroup RCC_PLL_Clock_Source |
mbed_official | 205:c41fc65bcfb4 | 338 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 339 | */ |
mbed_official | 205:c41fc65bcfb4 | 340 | #define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV |
mbed_official | 205:c41fc65bcfb4 | 341 | /** |
mbed_official | 205:c41fc65bcfb4 | 342 | * @} |
mbed_official | 205:c41fc65bcfb4 | 343 | */ |
mbed_official | 205:c41fc65bcfb4 | 344 | |
mbed_official | 205:c41fc65bcfb4 | 345 | /** @defgroup RCC_System_Clock_Type |
mbed_official | 205:c41fc65bcfb4 | 346 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 347 | */ |
mbed_official | 205:c41fc65bcfb4 | 348 | #define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001) |
mbed_official | 205:c41fc65bcfb4 | 349 | #define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002) |
mbed_official | 205:c41fc65bcfb4 | 350 | #define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004) |
mbed_official | 205:c41fc65bcfb4 | 351 | |
mbed_official | 205:c41fc65bcfb4 | 352 | #define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \ |
mbed_official | 205:c41fc65bcfb4 | 353 | (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \ |
mbed_official | 205:c41fc65bcfb4 | 354 | (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)) |
mbed_official | 205:c41fc65bcfb4 | 355 | /** |
mbed_official | 205:c41fc65bcfb4 | 356 | * @} |
mbed_official | 205:c41fc65bcfb4 | 357 | */ |
mbed_official | 205:c41fc65bcfb4 | 358 | |
mbed_official | 205:c41fc65bcfb4 | 359 | /** @defgroup RCC_System_Clock_Source |
mbed_official | 205:c41fc65bcfb4 | 360 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 361 | */ |
mbed_official | 205:c41fc65bcfb4 | 362 | #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI |
mbed_official | 205:c41fc65bcfb4 | 363 | #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE |
mbed_official | 205:c41fc65bcfb4 | 364 | #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL |
mbed_official | 205:c41fc65bcfb4 | 365 | /** |
mbed_official | 205:c41fc65bcfb4 | 366 | * @} |
mbed_official | 205:c41fc65bcfb4 | 367 | */ |
mbed_official | 205:c41fc65bcfb4 | 368 | |
mbed_official | 205:c41fc65bcfb4 | 369 | /** @defgroup RCC_System_Clock_Source_Status |
mbed_official | 205:c41fc65bcfb4 | 370 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 371 | */ |
mbed_official | 205:c41fc65bcfb4 | 372 | #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI |
mbed_official | 205:c41fc65bcfb4 | 373 | #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE |
mbed_official | 205:c41fc65bcfb4 | 374 | #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL |
mbed_official | 205:c41fc65bcfb4 | 375 | /** |
mbed_official | 205:c41fc65bcfb4 | 376 | * @} |
mbed_official | 205:c41fc65bcfb4 | 377 | */ |
mbed_official | 205:c41fc65bcfb4 | 378 | |
mbed_official | 205:c41fc65bcfb4 | 379 | /** @defgroup RCC_AHB_Clock_Source |
mbed_official | 205:c41fc65bcfb4 | 380 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 381 | */ |
mbed_official | 205:c41fc65bcfb4 | 382 | #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 |
mbed_official | 205:c41fc65bcfb4 | 383 | #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 |
mbed_official | 205:c41fc65bcfb4 | 384 | #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 |
mbed_official | 205:c41fc65bcfb4 | 385 | #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 |
mbed_official | 205:c41fc65bcfb4 | 386 | #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 |
mbed_official | 205:c41fc65bcfb4 | 387 | #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 |
mbed_official | 205:c41fc65bcfb4 | 388 | #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 |
mbed_official | 205:c41fc65bcfb4 | 389 | #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 |
mbed_official | 205:c41fc65bcfb4 | 390 | #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 |
mbed_official | 205:c41fc65bcfb4 | 391 | |
mbed_official | 205:c41fc65bcfb4 | 392 | #define IS_RCC_SYSCLK_DIV(DIV) (((DIV) == RCC_SYSCLK_DIV1) || ((DIV) == RCC_SYSCLK_DIV2) || \ |
mbed_official | 205:c41fc65bcfb4 | 393 | ((DIV) == RCC_SYSCLK_DIV4) || ((DIV) == RCC_SYSCLK_DIV8) || \ |
mbed_official | 205:c41fc65bcfb4 | 394 | ((DIV) == RCC_SYSCLK_DIV16) || ((DIV) == RCC_SYSCLK_DIV64) || \ |
mbed_official | 205:c41fc65bcfb4 | 395 | ((DIV) == RCC_SYSCLK_DIV128) || ((DIV) == RCC_SYSCLK_DIV256) || \ |
mbed_official | 205:c41fc65bcfb4 | 396 | ((DIV) == RCC_SYSCLK_DIV512)) |
mbed_official | 205:c41fc65bcfb4 | 397 | /** |
mbed_official | 205:c41fc65bcfb4 | 398 | * @} |
mbed_official | 205:c41fc65bcfb4 | 399 | */ |
mbed_official | 205:c41fc65bcfb4 | 400 | |
mbed_official | 205:c41fc65bcfb4 | 401 | /** @defgroup RCC_APB1_Clock_Source |
mbed_official | 205:c41fc65bcfb4 | 402 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 403 | */ |
mbed_official | 205:c41fc65bcfb4 | 404 | #define RCC_HCLK_DIV1 RCC_CFGR_PPRE_DIV1 |
mbed_official | 205:c41fc65bcfb4 | 405 | #define RCC_HCLK_DIV2 RCC_CFGR_PPRE_DIV2 |
mbed_official | 205:c41fc65bcfb4 | 406 | #define RCC_HCLK_DIV4 RCC_CFGR_PPRE_DIV4 |
mbed_official | 205:c41fc65bcfb4 | 407 | #define RCC_HCLK_DIV8 RCC_CFGR_PPRE_DIV8 |
mbed_official | 205:c41fc65bcfb4 | 408 | #define RCC_HCLK_DIV16 RCC_CFGR_PPRE_DIV16 |
mbed_official | 205:c41fc65bcfb4 | 409 | |
mbed_official | 205:c41fc65bcfb4 | 410 | #define IS_RCC_HCLK_DIV(DIV) (((DIV) == RCC_HCLK_DIV1) || ((DIV) == RCC_HCLK_DIV2) || \ |
mbed_official | 205:c41fc65bcfb4 | 411 | ((DIV) == RCC_HCLK_DIV4) || ((DIV) == RCC_HCLK_DIV8) || \ |
mbed_official | 205:c41fc65bcfb4 | 412 | ((DIV) == RCC_HCLK_DIV16)) |
mbed_official | 205:c41fc65bcfb4 | 413 | /** |
mbed_official | 205:c41fc65bcfb4 | 414 | * @} |
mbed_official | 205:c41fc65bcfb4 | 415 | */ |
mbed_official | 205:c41fc65bcfb4 | 416 | |
mbed_official | 205:c41fc65bcfb4 | 417 | /** @defgroup RCC_RTC_Clock_Source |
mbed_official | 205:c41fc65bcfb4 | 418 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 419 | */ |
mbed_official | 205:c41fc65bcfb4 | 420 | #define RCC_RTCCLKSOURCE_NONE RCC_BDCR_RTCSEL_NOCLOCK |
mbed_official | 205:c41fc65bcfb4 | 421 | #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE |
mbed_official | 205:c41fc65bcfb4 | 422 | #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI |
mbed_official | 205:c41fc65bcfb4 | 423 | #define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL_HSE |
mbed_official | 205:c41fc65bcfb4 | 424 | |
mbed_official | 205:c41fc65bcfb4 | 425 | #define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_NONE) || \ |
mbed_official | 205:c41fc65bcfb4 | 426 | ((SOURCE) == RCC_RTCCLKSOURCE_LSE) || \ |
mbed_official | 205:c41fc65bcfb4 | 427 | ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \ |
mbed_official | 205:c41fc65bcfb4 | 428 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV32)) |
mbed_official | 205:c41fc65bcfb4 | 429 | /** |
mbed_official | 205:c41fc65bcfb4 | 430 | * @} |
mbed_official | 205:c41fc65bcfb4 | 431 | */ |
mbed_official | 205:c41fc65bcfb4 | 432 | |
mbed_official | 205:c41fc65bcfb4 | 433 | |
mbed_official | 205:c41fc65bcfb4 | 434 | /** @defgroup RCC_USART1_Clock_Source |
mbed_official | 205:c41fc65bcfb4 | 435 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 436 | */ |
mbed_official | 205:c41fc65bcfb4 | 437 | #define RCC_USART1CLKSOURCE_PCLK1 RCC_CFGR3_USART1SW_PCLK |
mbed_official | 205:c41fc65bcfb4 | 438 | #define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK |
mbed_official | 205:c41fc65bcfb4 | 439 | #define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE |
mbed_official | 205:c41fc65bcfb4 | 440 | #define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI |
mbed_official | 205:c41fc65bcfb4 | 441 | |
mbed_official | 205:c41fc65bcfb4 | 442 | #define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK1) || \ |
mbed_official | 205:c41fc65bcfb4 | 443 | ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \ |
mbed_official | 205:c41fc65bcfb4 | 444 | ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \ |
mbed_official | 205:c41fc65bcfb4 | 445 | ((SOURCE) == RCC_USART1CLKSOURCE_HSI)) |
mbed_official | 205:c41fc65bcfb4 | 446 | /** |
mbed_official | 205:c41fc65bcfb4 | 447 | * @} |
mbed_official | 205:c41fc65bcfb4 | 448 | */ |
mbed_official | 205:c41fc65bcfb4 | 449 | |
mbed_official | 205:c41fc65bcfb4 | 450 | /** @defgroup RCC_I2C1_Clock_Source |
mbed_official | 205:c41fc65bcfb4 | 451 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 452 | */ |
mbed_official | 205:c41fc65bcfb4 | 453 | #define RCC_I2C1CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI |
mbed_official | 205:c41fc65bcfb4 | 454 | #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK |
mbed_official | 205:c41fc65bcfb4 | 455 | |
mbed_official | 205:c41fc65bcfb4 | 456 | #define IS_RCC_I2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C1CLKSOURCE_HSI) || \ |
mbed_official | 205:c41fc65bcfb4 | 457 | ((SOURCE) == RCC_I2C1CLKSOURCE_SYSCLK)) |
mbed_official | 205:c41fc65bcfb4 | 458 | /** |
mbed_official | 205:c41fc65bcfb4 | 459 | * @} |
mbed_official | 205:c41fc65bcfb4 | 460 | */ |
mbed_official | 205:c41fc65bcfb4 | 461 | |
mbed_official | 205:c41fc65bcfb4 | 462 | /** @defgroup RCC_MCOx_Index |
mbed_official | 205:c41fc65bcfb4 | 463 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 464 | */ |
mbed_official | 205:c41fc65bcfb4 | 465 | #define RCC_MCO ((uint32_t)0x00000000) |
mbed_official | 205:c41fc65bcfb4 | 466 | |
mbed_official | 205:c41fc65bcfb4 | 467 | #define IS_RCC_MCO(MCOx) ((MCOx) == RCC_MCO) |
mbed_official | 205:c41fc65bcfb4 | 468 | /** |
mbed_official | 205:c41fc65bcfb4 | 469 | * @} |
mbed_official | 205:c41fc65bcfb4 | 470 | */ |
mbed_official | 205:c41fc65bcfb4 | 471 | |
mbed_official | 205:c41fc65bcfb4 | 472 | /** @defgroup RCC_MCO_Clock_Source |
mbed_official | 205:c41fc65bcfb4 | 473 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 474 | */ |
mbed_official | 205:c41fc65bcfb4 | 475 | #define RCC_MCOSOURCE_NONE RCC_CFGR_MCO_NOCLOCK |
mbed_official | 205:c41fc65bcfb4 | 476 | #define RCC_MCOSOURCE_LSI RCC_CFGR_MCO_LSI |
mbed_official | 205:c41fc65bcfb4 | 477 | #define RCC_MCOSOURCE_LSE RCC_CFGR_MCO_LSE |
mbed_official | 205:c41fc65bcfb4 | 478 | #define RCC_MCOSOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK |
mbed_official | 205:c41fc65bcfb4 | 479 | #define RCC_MCOSOURCE_HSI RCC_CFGR_MCO_HSI |
mbed_official | 205:c41fc65bcfb4 | 480 | #define RCC_MCOSOURCE_HSE RCC_CFGR_MCO_HSE |
mbed_official | 205:c41fc65bcfb4 | 481 | #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL |
mbed_official | 205:c41fc65bcfb4 | 482 | #define RCC_MCOSOURCE_HSI14 RCC_CFGR_MCO_HSI14 |
mbed_official | 205:c41fc65bcfb4 | 483 | /** |
mbed_official | 205:c41fc65bcfb4 | 484 | * @} |
mbed_official | 205:c41fc65bcfb4 | 485 | */ |
mbed_official | 205:c41fc65bcfb4 | 486 | |
mbed_official | 205:c41fc65bcfb4 | 487 | /** @defgroup RCC_Interrupt |
mbed_official | 205:c41fc65bcfb4 | 488 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 489 | */ |
mbed_official | 205:c41fc65bcfb4 | 490 | #define RCC_IT_LSIRDY ((uint8_t)0x01) |
mbed_official | 205:c41fc65bcfb4 | 491 | #define RCC_IT_LSERDY ((uint8_t)0x02) |
mbed_official | 205:c41fc65bcfb4 | 492 | #define RCC_IT_HSIRDY ((uint8_t)0x04) |
mbed_official | 205:c41fc65bcfb4 | 493 | #define RCC_IT_HSERDY ((uint8_t)0x08) |
mbed_official | 205:c41fc65bcfb4 | 494 | #define RCC_IT_PLLRDY ((uint8_t)0x10) |
mbed_official | 205:c41fc65bcfb4 | 495 | #define RCC_IT_HSI14 ((uint8_t)0x20) |
mbed_official | 205:c41fc65bcfb4 | 496 | #define RCC_IT_CSS ((uint8_t)0x80) |
mbed_official | 205:c41fc65bcfb4 | 497 | /** |
mbed_official | 205:c41fc65bcfb4 | 498 | * @} |
mbed_official | 205:c41fc65bcfb4 | 499 | */ |
mbed_official | 205:c41fc65bcfb4 | 500 | |
mbed_official | 205:c41fc65bcfb4 | 501 | /** @defgroup RCC_Flag |
mbed_official | 205:c41fc65bcfb4 | 502 | * Elements values convention: 0XXYYYYYb |
mbed_official | 205:c41fc65bcfb4 | 503 | * - YYYYY : Flag position in the register |
mbed_official | 205:c41fc65bcfb4 | 504 | * - XX : Register index |
mbed_official | 205:c41fc65bcfb4 | 505 | * - 00: CR register |
mbed_official | 205:c41fc65bcfb4 | 506 | * - 01: CR2 register |
mbed_official | 205:c41fc65bcfb4 | 507 | * - 10: BDCR register |
mbed_official | 205:c41fc65bcfb4 | 508 | * - 11: CSR register |
mbed_official | 205:c41fc65bcfb4 | 509 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 510 | */ |
mbed_official | 205:c41fc65bcfb4 | 511 | #define CR_REG_INDEX 0 |
mbed_official | 205:c41fc65bcfb4 | 512 | #define CR2_REG_INDEX 1 |
mbed_official | 205:c41fc65bcfb4 | 513 | #define BDCR_REG_INDEX 2 |
mbed_official | 205:c41fc65bcfb4 | 514 | #define CSR_REG_INDEX 3 |
mbed_official | 205:c41fc65bcfb4 | 515 | |
mbed_official | 205:c41fc65bcfb4 | 516 | /* Flags in the CR register */ |
mbed_official | 205:c41fc65bcfb4 | 517 | #define RCC_CR_HSIRDY_BitNumber 1 |
mbed_official | 205:c41fc65bcfb4 | 518 | #define RCC_CR_HSERDY_BitNumber 17 |
mbed_official | 205:c41fc65bcfb4 | 519 | #define RCC_CR_PLLRDY_BitNumber 25 |
mbed_official | 205:c41fc65bcfb4 | 520 | |
mbed_official | 205:c41fc65bcfb4 | 521 | #define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_HSIRDY_BitNumber)) |
mbed_official | 205:c41fc65bcfb4 | 522 | #define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_HSERDY_BitNumber)) |
mbed_official | 205:c41fc65bcfb4 | 523 | #define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_PLLRDY_BitNumber)) |
mbed_official | 205:c41fc65bcfb4 | 524 | |
mbed_official | 205:c41fc65bcfb4 | 525 | /* Flags in the CR2 register */ |
mbed_official | 205:c41fc65bcfb4 | 526 | #define RCC_CR2_HSI14RDY_BitNumber 1 |
mbed_official | 205:c41fc65bcfb4 | 527 | |
mbed_official | 205:c41fc65bcfb4 | 528 | #define RCC_FLAG_HSI14RDY ((uint8_t)((CR2_REG_INDEX << 5) | RCC_CR2_HSI14RDY_BitNumber)) |
mbed_official | 205:c41fc65bcfb4 | 529 | |
mbed_official | 205:c41fc65bcfb4 | 530 | /* Flags in the BDCR register */ |
mbed_official | 205:c41fc65bcfb4 | 531 | #define RCC_BDCR_LSERDY_BitNumber 1 |
mbed_official | 205:c41fc65bcfb4 | 532 | |
mbed_official | 205:c41fc65bcfb4 | 533 | #define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5) | RCC_BDCR_LSERDY_BitNumber)) |
mbed_official | 205:c41fc65bcfb4 | 534 | |
mbed_official | 205:c41fc65bcfb4 | 535 | /* Flags in the CSR register */ |
mbed_official | 205:c41fc65bcfb4 | 536 | #define RCC_CSR_LSIRDY_BitNumber 1 |
mbed_official | 205:c41fc65bcfb4 | 537 | #define RCC_CSR_V18PWRRSTF_BitNumber 23 |
mbed_official | 205:c41fc65bcfb4 | 538 | #define RCC_CSR_RMVF_BitNumber 24 |
mbed_official | 205:c41fc65bcfb4 | 539 | #define RCC_CSR_OBLRSTF_BitNumber 25 |
mbed_official | 205:c41fc65bcfb4 | 540 | #define RCC_CSR_PINRSTF_BitNumber 26 |
mbed_official | 205:c41fc65bcfb4 | 541 | #define RCC_CSR_PORRSTF_BitNumber 27 |
mbed_official | 205:c41fc65bcfb4 | 542 | #define RCC_CSR_SFTRSTF_BitNumber 28 |
mbed_official | 205:c41fc65bcfb4 | 543 | #define RCC_CSR_IWDGRSTF_BitNumber 29 |
mbed_official | 205:c41fc65bcfb4 | 544 | #define RCC_CSR_WWDGRSTF_BitNumber 30 |
mbed_official | 205:c41fc65bcfb4 | 545 | #define RCC_CSR_LPWRRSTF_BitNumber 31 |
mbed_official | 205:c41fc65bcfb4 | 546 | |
mbed_official | 205:c41fc65bcfb4 | 547 | #define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_LSIRDY_BitNumber)) |
mbed_official | 205:c41fc65bcfb4 | 548 | #define RCC_FLAG_V18PWRRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_LSIRDY_BitNumber)) |
mbed_official | 205:c41fc65bcfb4 | 549 | #define RCC_FLAG_RMV ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_RMVF_BitNumber)) |
mbed_official | 205:c41fc65bcfb4 | 550 | #define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_OBLRSTF_BitNumber)) |
mbed_official | 205:c41fc65bcfb4 | 551 | #define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_PINRSTF_BitNumber)) |
mbed_official | 205:c41fc65bcfb4 | 552 | #define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_PORRSTF_BitNumber)) |
mbed_official | 205:c41fc65bcfb4 | 553 | #define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_SFTRSTF_BitNumber)) |
mbed_official | 205:c41fc65bcfb4 | 554 | #define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_IWDGRSTF_BitNumber)) |
mbed_official | 205:c41fc65bcfb4 | 555 | #define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_WWDGRSTF_BitNumber)) |
mbed_official | 205:c41fc65bcfb4 | 556 | #define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_LPWRRSTF_BitNumber)) |
mbed_official | 205:c41fc65bcfb4 | 557 | /** |
mbed_official | 205:c41fc65bcfb4 | 558 | * @} |
mbed_official | 205:c41fc65bcfb4 | 559 | */ |
mbed_official | 205:c41fc65bcfb4 | 560 | |
mbed_official | 205:c41fc65bcfb4 | 561 | #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) |
mbed_official | 205:c41fc65bcfb4 | 562 | |
mbed_official | 205:c41fc65bcfb4 | 563 | #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT |
mbed_official | 205:c41fc65bcfb4 | 564 | #define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ |
mbed_official | 205:c41fc65bcfb4 | 565 | #define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ |
mbed_official | 205:c41fc65bcfb4 | 566 | #define LSE_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */ |
mbed_official | 205:c41fc65bcfb4 | 567 | #define HSI14_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ |
mbed_official | 205:c41fc65bcfb4 | 568 | #define HSI48_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ |
mbed_official | 205:c41fc65bcfb4 | 569 | #define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ |
mbed_official | 205:c41fc65bcfb4 | 570 | #define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */ |
mbed_official | 205:c41fc65bcfb4 | 571 | |
mbed_official | 205:c41fc65bcfb4 | 572 | /** |
mbed_official | 205:c41fc65bcfb4 | 573 | * @} |
mbed_official | 205:c41fc65bcfb4 | 574 | */ |
mbed_official | 205:c41fc65bcfb4 | 575 | /* Exported macro ------------------------------------------------------------*/ |
mbed_official | 205:c41fc65bcfb4 | 576 | /** @defgroup RCC_Exported_Macros |
mbed_official | 205:c41fc65bcfb4 | 577 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 578 | */ |
mbed_official | 205:c41fc65bcfb4 | 579 | |
mbed_official | 205:c41fc65bcfb4 | 580 | /** @brief Enable or disable the AHB peripheral clock. |
mbed_official | 205:c41fc65bcfb4 | 581 | * @note After reset, the peripheral clock (used for registers read/write access) |
mbed_official | 205:c41fc65bcfb4 | 582 | * is disabled and the application software has to enable this clock before |
mbed_official | 205:c41fc65bcfb4 | 583 | * using it. |
mbed_official | 205:c41fc65bcfb4 | 584 | */ |
mbed_official | 205:c41fc65bcfb4 | 585 | #define __GPIOA_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOAEN)) |
mbed_official | 205:c41fc65bcfb4 | 586 | #define __GPIOB_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOBEN)) |
mbed_official | 205:c41fc65bcfb4 | 587 | #define __GPIOC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOCEN)) |
mbed_official | 205:c41fc65bcfb4 | 588 | #define __GPIOF_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOFEN)) |
mbed_official | 205:c41fc65bcfb4 | 589 | #define __CRC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_CRCEN)) |
mbed_official | 205:c41fc65bcfb4 | 590 | #define __DMA1_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_DMA1EN)) |
mbed_official | 205:c41fc65bcfb4 | 591 | #define __SRAM_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_SRAMEN)) |
mbed_official | 205:c41fc65bcfb4 | 592 | #define __FLITF_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_FLITFEN)) |
mbed_official | 205:c41fc65bcfb4 | 593 | |
mbed_official | 205:c41fc65bcfb4 | 594 | #define __GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN)) |
mbed_official | 205:c41fc65bcfb4 | 595 | #define __GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN)) |
mbed_official | 205:c41fc65bcfb4 | 596 | #define __GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN)) |
mbed_official | 205:c41fc65bcfb4 | 597 | #define __GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN)) |
mbed_official | 205:c41fc65bcfb4 | 598 | #define __CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN)) |
mbed_official | 205:c41fc65bcfb4 | 599 | #define __DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN)) |
mbed_official | 205:c41fc65bcfb4 | 600 | #define __SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN)) |
mbed_official | 205:c41fc65bcfb4 | 601 | #define __FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN)) |
mbed_official | 205:c41fc65bcfb4 | 602 | |
mbed_official | 205:c41fc65bcfb4 | 603 | /** @brief Enable or disable the Low Speed APB (APB1) peripheral clock. |
mbed_official | 205:c41fc65bcfb4 | 604 | * @note After reset, the peripheral clock (used for registers read/write access) |
mbed_official | 205:c41fc65bcfb4 | 605 | * is disabled and the application software has to enable this clock before |
mbed_official | 205:c41fc65bcfb4 | 606 | * using it. |
mbed_official | 205:c41fc65bcfb4 | 607 | */ |
mbed_official | 205:c41fc65bcfb4 | 608 | #define __TIM3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM3EN)) |
mbed_official | 205:c41fc65bcfb4 | 609 | #define __TIM14_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM14EN)) |
mbed_official | 205:c41fc65bcfb4 | 610 | #define __WWDG_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN)) |
mbed_official | 205:c41fc65bcfb4 | 611 | #define __I2C1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C1EN)) |
mbed_official | 205:c41fc65bcfb4 | 612 | #define __PWR_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_PWREN)) |
mbed_official | 205:c41fc65bcfb4 | 613 | |
mbed_official | 205:c41fc65bcfb4 | 614 | #define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) |
mbed_official | 205:c41fc65bcfb4 | 615 | #define __TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) |
mbed_official | 205:c41fc65bcfb4 | 616 | #define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) |
mbed_official | 205:c41fc65bcfb4 | 617 | #define __I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) |
mbed_official | 205:c41fc65bcfb4 | 618 | #define __PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) |
mbed_official | 205:c41fc65bcfb4 | 619 | |
mbed_official | 205:c41fc65bcfb4 | 620 | /** @brief Enable or disable the High Speed APB (APB2) peripheral clock. |
mbed_official | 205:c41fc65bcfb4 | 621 | * @note After reset, the peripheral clock (used for registers read/write access) |
mbed_official | 205:c41fc65bcfb4 | 622 | * is disabled and the application software has to enable this clock before |
mbed_official | 205:c41fc65bcfb4 | 623 | * using it. |
mbed_official | 205:c41fc65bcfb4 | 624 | */ |
mbed_official | 205:c41fc65bcfb4 | 625 | #define __SYSCFG_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SYSCFGEN)) |
mbed_official | 205:c41fc65bcfb4 | 626 | #define __ADC1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC1EN)) |
mbed_official | 205:c41fc65bcfb4 | 627 | #define __TIM1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM1EN)) |
mbed_official | 205:c41fc65bcfb4 | 628 | #define __SPI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI1EN)) |
mbed_official | 205:c41fc65bcfb4 | 629 | #define __TIM16_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM16EN)) |
mbed_official | 205:c41fc65bcfb4 | 630 | #define __TIM17_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM17EN)) |
mbed_official | 205:c41fc65bcfb4 | 631 | #define __USART1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART1EN)) |
mbed_official | 205:c41fc65bcfb4 | 632 | #define __DBGMCU_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_DBGMCUEN)) |
mbed_official | 205:c41fc65bcfb4 | 633 | |
mbed_official | 205:c41fc65bcfb4 | 634 | #define __SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN)) |
mbed_official | 205:c41fc65bcfb4 | 635 | #define __ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) |
mbed_official | 205:c41fc65bcfb4 | 636 | #define __TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN)) |
mbed_official | 205:c41fc65bcfb4 | 637 | #define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) |
mbed_official | 205:c41fc65bcfb4 | 638 | #define __TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN)) |
mbed_official | 205:c41fc65bcfb4 | 639 | #define __TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN)) |
mbed_official | 205:c41fc65bcfb4 | 640 | #define __USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) |
mbed_official | 205:c41fc65bcfb4 | 641 | #define __DBGMCU_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DBGMCUEN)) |
mbed_official | 205:c41fc65bcfb4 | 642 | |
mbed_official | 205:c41fc65bcfb4 | 643 | /** @brief Force or release AHB peripheral reset. |
mbed_official | 205:c41fc65bcfb4 | 644 | */ |
mbed_official | 205:c41fc65bcfb4 | 645 | #define __AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFF) |
mbed_official | 205:c41fc65bcfb4 | 646 | #define __GPIOA_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST)) |
mbed_official | 205:c41fc65bcfb4 | 647 | #define __GPIOB_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST)) |
mbed_official | 205:c41fc65bcfb4 | 648 | #define __GPIOC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST)) |
mbed_official | 205:c41fc65bcfb4 | 649 | #define __GPIOF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST)) |
mbed_official | 205:c41fc65bcfb4 | 650 | |
mbed_official | 205:c41fc65bcfb4 | 651 | #define __AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00) |
mbed_official | 205:c41fc65bcfb4 | 652 | #define __GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST)) |
mbed_official | 205:c41fc65bcfb4 | 653 | #define __GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST)) |
mbed_official | 205:c41fc65bcfb4 | 654 | #define __GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST)) |
mbed_official | 205:c41fc65bcfb4 | 655 | #define __GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST)) |
mbed_official | 205:c41fc65bcfb4 | 656 | |
mbed_official | 205:c41fc65bcfb4 | 657 | /** @brief Force or release APB1 peripheral reset. |
mbed_official | 205:c41fc65bcfb4 | 658 | */ |
mbed_official | 205:c41fc65bcfb4 | 659 | #define __APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF) |
mbed_official | 205:c41fc65bcfb4 | 660 | #define __TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) |
mbed_official | 205:c41fc65bcfb4 | 661 | #define __TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) |
mbed_official | 205:c41fc65bcfb4 | 662 | #define __WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) |
mbed_official | 205:c41fc65bcfb4 | 663 | #define __I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) |
mbed_official | 205:c41fc65bcfb4 | 664 | #define __PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) |
mbed_official | 205:c41fc65bcfb4 | 665 | |
mbed_official | 205:c41fc65bcfb4 | 666 | #define __APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00) |
mbed_official | 205:c41fc65bcfb4 | 667 | #define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) |
mbed_official | 205:c41fc65bcfb4 | 668 | #define __TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) |
mbed_official | 205:c41fc65bcfb4 | 669 | #define __WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) |
mbed_official | 205:c41fc65bcfb4 | 670 | #define __I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)) |
mbed_official | 205:c41fc65bcfb4 | 671 | #define __PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) |
mbed_official | 205:c41fc65bcfb4 | 672 | |
mbed_official | 205:c41fc65bcfb4 | 673 | /** @brief Force or release APB2 peripheral reset. |
mbed_official | 205:c41fc65bcfb4 | 674 | */ |
mbed_official | 205:c41fc65bcfb4 | 675 | #define __APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF) |
mbed_official | 205:c41fc65bcfb4 | 676 | #define __SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST)) |
mbed_official | 205:c41fc65bcfb4 | 677 | #define __ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST)) |
mbed_official | 205:c41fc65bcfb4 | 678 | #define __TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST)) |
mbed_official | 205:c41fc65bcfb4 | 679 | #define __SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) |
mbed_official | 205:c41fc65bcfb4 | 680 | #define __USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) |
mbed_official | 205:c41fc65bcfb4 | 681 | #define __TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST)) |
mbed_official | 205:c41fc65bcfb4 | 682 | #define __TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST)) |
mbed_official | 205:c41fc65bcfb4 | 683 | #define __DBGMCU_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DBGMCURST)) |
mbed_official | 205:c41fc65bcfb4 | 684 | |
mbed_official | 205:c41fc65bcfb4 | 685 | #define __APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00) |
mbed_official | 205:c41fc65bcfb4 | 686 | #define __SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST)) |
mbed_official | 205:c41fc65bcfb4 | 687 | #define __ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST)) |
mbed_official | 205:c41fc65bcfb4 | 688 | #define __TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST)) |
mbed_official | 205:c41fc65bcfb4 | 689 | #define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) |
mbed_official | 205:c41fc65bcfb4 | 690 | #define __USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST)) |
mbed_official | 205:c41fc65bcfb4 | 691 | #define __TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST)) |
mbed_official | 205:c41fc65bcfb4 | 692 | #define __TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST)) |
mbed_official | 205:c41fc65bcfb4 | 693 | #define __DBGMCU_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DBGMCURST)) |
mbed_official | 205:c41fc65bcfb4 | 694 | |
mbed_official | 205:c41fc65bcfb4 | 695 | /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). |
mbed_official | 205:c41fc65bcfb4 | 696 | * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. |
mbed_official | 205:c41fc65bcfb4 | 697 | * It is used (enabled by hardware) as system clock source after startup |
mbed_official | 205:c41fc65bcfb4 | 698 | * from Reset, wakeup from STOP and STANDBY mode, or in case of failure |
mbed_official | 205:c41fc65bcfb4 | 699 | * of the HSE used directly or indirectly as system clock (if the Clock |
mbed_official | 205:c41fc65bcfb4 | 700 | * Security System CSS is enabled). |
mbed_official | 205:c41fc65bcfb4 | 701 | * @note HSI can not be stopped if it is used as system clock source. In this case, |
mbed_official | 205:c41fc65bcfb4 | 702 | * you have to select another source of the system clock then stop the HSI. |
mbed_official | 205:c41fc65bcfb4 | 703 | * @note After enabling the HSI, the application software should wait on HSIRDY |
mbed_official | 205:c41fc65bcfb4 | 704 | * flag to be set indicating that HSI clock is stable and can be used as |
mbed_official | 205:c41fc65bcfb4 | 705 | * system clock source. |
mbed_official | 205:c41fc65bcfb4 | 706 | * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator |
mbed_official | 205:c41fc65bcfb4 | 707 | * clock cycles. |
mbed_official | 205:c41fc65bcfb4 | 708 | */ |
mbed_official | 205:c41fc65bcfb4 | 709 | #define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION) |
mbed_official | 205:c41fc65bcfb4 | 710 | #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION) |
mbed_official | 205:c41fc65bcfb4 | 711 | |
mbed_official | 205:c41fc65bcfb4 | 712 | |
mbed_official | 205:c41fc65bcfb4 | 713 | /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. |
mbed_official | 205:c41fc65bcfb4 | 714 | * @note The calibration is used to compensate for the variations in voltage |
mbed_official | 205:c41fc65bcfb4 | 715 | * and temperature that influence the frequency of the internal HSI RC. |
mbed_official | 205:c41fc65bcfb4 | 716 | * @param __HSICalibrationValue__: specifies the calibration trimming value |
mbed_official | 205:c41fc65bcfb4 | 717 | * (default is RCC_HSICALIBRATION_DEFAULT). |
mbed_official | 205:c41fc65bcfb4 | 718 | * This parameter must be a number between 0 and 0x1F. |
mbed_official | 205:c41fc65bcfb4 | 719 | */ |
mbed_official | 205:c41fc65bcfb4 | 720 | #define RCC_CR_HSITRIM_BitNumber 3 |
mbed_official | 205:c41fc65bcfb4 | 721 | #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) \ |
mbed_official | 205:c41fc65bcfb4 | 722 | MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_CR_HSITRIM_BitNumber) |
mbed_official | 205:c41fc65bcfb4 | 723 | |
mbed_official | 205:c41fc65bcfb4 | 724 | /** @brief Macro to enable or disable the Internal Low Speed oscillator (LSI). |
mbed_official | 205:c41fc65bcfb4 | 725 | * @note After enabling the LSI, the application software should wait on |
mbed_official | 205:c41fc65bcfb4 | 726 | * LSIRDY flag to be set indicating that LSI clock is stable and can |
mbed_official | 205:c41fc65bcfb4 | 727 | * be used to clock the IWDG and/or the RTC. |
mbed_official | 205:c41fc65bcfb4 | 728 | * @note LSI can not be disabled if the IWDG is running. |
mbed_official | 205:c41fc65bcfb4 | 729 | * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator |
mbed_official | 205:c41fc65bcfb4 | 730 | * clock cycles. |
mbed_official | 205:c41fc65bcfb4 | 731 | */ |
mbed_official | 205:c41fc65bcfb4 | 732 | #define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION) |
mbed_official | 205:c41fc65bcfb4 | 733 | #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION) |
mbed_official | 205:c41fc65bcfb4 | 734 | |
mbed_official | 205:c41fc65bcfb4 | 735 | /** |
mbed_official | 205:c41fc65bcfb4 | 736 | * @brief Macro to configure the External High Speed oscillator (HSE). |
mbed_official | 205:c41fc65bcfb4 | 737 | * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application |
mbed_official | 205:c41fc65bcfb4 | 738 | * software should wait on HSERDY flag to be set indicating that HSE clock |
mbed_official | 205:c41fc65bcfb4 | 739 | * is stable and can be used to clock the PLL and/or system clock. |
mbed_official | 205:c41fc65bcfb4 | 740 | * @note HSE state can not be changed if it is used directly or through the |
mbed_official | 205:c41fc65bcfb4 | 741 | * PLL as system clock. In this case, you have to select another source |
mbed_official | 205:c41fc65bcfb4 | 742 | * of the system clock then change the HSE state (ex. disable it). |
mbed_official | 205:c41fc65bcfb4 | 743 | * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. |
mbed_official | 205:c41fc65bcfb4 | 744 | * @note This function reset the CSSON bit, so if the Clock security system(CSS) |
mbed_official | 205:c41fc65bcfb4 | 745 | * was previously enabled you have to enable it again after calling this |
mbed_official | 205:c41fc65bcfb4 | 746 | * function. |
mbed_official | 205:c41fc65bcfb4 | 747 | * @param __STATE__: specifies the new state of the HSE. |
mbed_official | 205:c41fc65bcfb4 | 748 | * This parameter can be one of the following values: |
mbed_official | 205:c41fc65bcfb4 | 749 | * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after |
mbed_official | 205:c41fc65bcfb4 | 750 | * 6 HSE oscillator clock cycles. |
mbed_official | 205:c41fc65bcfb4 | 751 | * @arg RCC_HSE_ON: turn ON the HSE oscillator |
mbed_official | 205:c41fc65bcfb4 | 752 | * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock |
mbed_official | 205:c41fc65bcfb4 | 753 | */ |
mbed_official | 205:c41fc65bcfb4 | 754 | #define __HAL_RCC_HSE_CONFIG(__STATE__) (*(__IO uint8_t *)RCC_CR_BYTE2_ADDRESS = (__STATE__)) |
mbed_official | 205:c41fc65bcfb4 | 755 | |
mbed_official | 205:c41fc65bcfb4 | 756 | /** |
mbed_official | 205:c41fc65bcfb4 | 757 | * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL. |
mbed_official | 205:c41fc65bcfb4 | 758 | * @note Predivision factor can not be changed if PLL is used as system clock |
mbed_official | 205:c41fc65bcfb4 | 759 | * In this case, you have to select another source of the system clock, disable the PLL and |
mbed_official | 205:c41fc65bcfb4 | 760 | * then change the HSE predivision factor. |
mbed_official | 205:c41fc65bcfb4 | 761 | * @param __HSEPredivValue__: specifies the division value applied to HSE. |
mbed_official | 205:c41fc65bcfb4 | 762 | * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16. |
mbed_official | 205:c41fc65bcfb4 | 763 | */ |
mbed_official | 205:c41fc65bcfb4 | 764 | #define __HAL_RCC_HSE_PREDIV_CONFIG(__HSEPredivValue__) \ |
mbed_official | 205:c41fc65bcfb4 | 765 | MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (uint32_t)(__HSEPredivValue__)) |
mbed_official | 205:c41fc65bcfb4 | 766 | |
mbed_official | 205:c41fc65bcfb4 | 767 | /** |
mbed_official | 205:c41fc65bcfb4 | 768 | * @brief Macro to configure the External Low Speed oscillator (LSE). |
mbed_official | 205:c41fc65bcfb4 | 769 | * @note As the LSE is in the Backup domain and write access is denied to |
mbed_official | 205:c41fc65bcfb4 | 770 | * this domain after reset, you have to enable write access using |
mbed_official | 205:c41fc65bcfb4 | 771 | * HAL_PWR_EnableBkUpAccess() function before to configure the LSE |
mbed_official | 205:c41fc65bcfb4 | 772 | * (to be done once after reset). |
mbed_official | 205:c41fc65bcfb4 | 773 | * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application |
mbed_official | 205:c41fc65bcfb4 | 774 | * software should wait on LSERDY flag to be set indicating that LSE clock |
mbed_official | 205:c41fc65bcfb4 | 775 | * is stable and can be used to clock the RTC. |
mbed_official | 205:c41fc65bcfb4 | 776 | * @param __STATE__: specifies the new state of the LSE. |
mbed_official | 205:c41fc65bcfb4 | 777 | * This parameter can be one of the following values: |
mbed_official | 205:c41fc65bcfb4 | 778 | * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after |
mbed_official | 205:c41fc65bcfb4 | 779 | * 6 LSE oscillator clock cycles. |
mbed_official | 205:c41fc65bcfb4 | 780 | * @arg RCC_LSE_ON: turn ON the LSE oscillator |
mbed_official | 205:c41fc65bcfb4 | 781 | * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock |
mbed_official | 205:c41fc65bcfb4 | 782 | */ |
mbed_official | 205:c41fc65bcfb4 | 783 | #define __HAL_RCC_LSE_CONFIG(__STATE__) \ |
mbed_official | 205:c41fc65bcfb4 | 784 | MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEON|RCC_BDCR_LSEBYP, (uint32_t)(__STATE__)) |
mbed_official | 205:c41fc65bcfb4 | 785 | |
mbed_official | 205:c41fc65bcfb4 | 786 | /** @brief Macros to enable or disable the Internal 14Mhz High Speed oscillator (HSI14). |
mbed_official | 205:c41fc65bcfb4 | 787 | * @note The HSI14 is stopped by hardware when entering STOP and STANDBY modes. |
mbed_official | 205:c41fc65bcfb4 | 788 | * @note HSI14 can not be stopped if it is used as system clock source. In this case, |
mbed_official | 205:c41fc65bcfb4 | 789 | * you have to select another source of the system clock then stop the HSI14. |
mbed_official | 205:c41fc65bcfb4 | 790 | * @note After enabling the HSI14 with __HAL_RCC_HSI14_ENABLE(), the application software |
mbed_official | 205:c41fc65bcfb4 | 791 | * should wait on HSI14RDY flag to be set indicating that HSI clock is stable and can be |
mbed_official | 205:c41fc65bcfb4 | 792 | * used as system clock source. This is not necessary if HAL_RCC_OscConfig() is used. |
mbed_official | 205:c41fc65bcfb4 | 793 | * @note When the HSI14 is stopped, HSI14RDY flag goes low after 6 HSI14 oscillator |
mbed_official | 205:c41fc65bcfb4 | 794 | * clock cycles. |
mbed_official | 205:c41fc65bcfb4 | 795 | */ |
mbed_official | 205:c41fc65bcfb4 | 796 | #define __HAL_RCC_HSI14_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI14ON) |
mbed_official | 205:c41fc65bcfb4 | 797 | #define __HAL_RCC_HSI14_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14ON) |
mbed_official | 205:c41fc65bcfb4 | 798 | |
mbed_official | 205:c41fc65bcfb4 | 799 | /** @brief macros to Enable or Disable the Internal 14Mhz High Speed oscillator (HSI14) usage by ADC. |
mbed_official | 205:c41fc65bcfb4 | 800 | */ |
mbed_official | 205:c41fc65bcfb4 | 801 | #define __HAL_RCC_HSI14ADC_ENABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14DIS) |
mbed_official | 205:c41fc65bcfb4 | 802 | #define __HAL_RCC_HSI14ADC_DISABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI14DIS) |
mbed_official | 205:c41fc65bcfb4 | 803 | |
mbed_official | 205:c41fc65bcfb4 | 804 | |
mbed_official | 205:c41fc65bcfb4 | 805 | /** @brief Macro to adjust the Internal 14Mhz High Speed oscillator (HSI) calibration value. |
mbed_official | 205:c41fc65bcfb4 | 806 | * @note The calibration is used to compensate for the variations in voltage |
mbed_official | 205:c41fc65bcfb4 | 807 | * and temperature that influence the frequency of the internal HSI14 RC. |
mbed_official | 205:c41fc65bcfb4 | 808 | * @param __HSI14CalibrationValue__: specifies the calibration trimming value |
mbed_official | 205:c41fc65bcfb4 | 809 | * (default is RCC_HSI14CALIBRATION_DEFAULT). |
mbed_official | 205:c41fc65bcfb4 | 810 | * This parameter must be a number between 0 and 0x1F. |
mbed_official | 205:c41fc65bcfb4 | 811 | */ |
mbed_official | 205:c41fc65bcfb4 | 812 | #define RCC_CR2_HSI14TRIM_BitNumber 3 |
mbed_official | 205:c41fc65bcfb4 | 813 | #define __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(__HSI14CalibrationValue__) \ |
mbed_official | 205:c41fc65bcfb4 | 814 | MODIFY_REG(RCC->CR2, RCC_CR2_HSI14TRIM, (uint32_t)(__HSI14CalibrationValue__) << RCC_CR2_HSI14TRIM_BitNumber) |
mbed_official | 205:c41fc65bcfb4 | 815 | |
mbed_official | 205:c41fc65bcfb4 | 816 | /** @brief Macro to configure the USART1 clock (USART1CLK). |
mbed_official | 205:c41fc65bcfb4 | 817 | * @param __USART1CLKSource__: specifies the USART1 clock source. |
mbed_official | 205:c41fc65bcfb4 | 818 | * This parameter can be one of the following values: |
mbed_official | 205:c41fc65bcfb4 | 819 | * @arg RCC_USART1CLKSOURCE_PCLK1: PCLK1 selected as USART1 clock |
mbed_official | 205:c41fc65bcfb4 | 820 | * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock |
mbed_official | 205:c41fc65bcfb4 | 821 | * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock |
mbed_official | 205:c41fc65bcfb4 | 822 | * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock |
mbed_official | 205:c41fc65bcfb4 | 823 | */ |
mbed_official | 205:c41fc65bcfb4 | 824 | #define __HAL_RCC_USART1_CONFIG(__USART1CLKSource__) \ |
mbed_official | 205:c41fc65bcfb4 | 825 | MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART1SW, (uint32_t)(__USART1CLKSource__)) |
mbed_official | 205:c41fc65bcfb4 | 826 | |
mbed_official | 205:c41fc65bcfb4 | 827 | /** @brief Macro to get the USART1 clock source. |
mbed_official | 205:c41fc65bcfb4 | 828 | * @retval The clock source can be one of the following values: |
mbed_official | 205:c41fc65bcfb4 | 829 | * @arg RCC_USART1CLKSOURCE_PCLK1: PCLK1 selected as USART1 clock |
mbed_official | 205:c41fc65bcfb4 | 830 | * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock |
mbed_official | 205:c41fc65bcfb4 | 831 | * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock |
mbed_official | 205:c41fc65bcfb4 | 832 | * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock |
mbed_official | 205:c41fc65bcfb4 | 833 | */ |
mbed_official | 205:c41fc65bcfb4 | 834 | #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART1SW))) |
mbed_official | 205:c41fc65bcfb4 | 835 | |
mbed_official | 205:c41fc65bcfb4 | 836 | /** @brief Macro to configure the I2C1 clock (I2C1CLK). |
mbed_official | 205:c41fc65bcfb4 | 837 | * @param __I2C1CLKSource__: specifies the I2C1 clock source. |
mbed_official | 205:c41fc65bcfb4 | 838 | * This parameter can be one of the following values: |
mbed_official | 205:c41fc65bcfb4 | 839 | * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock |
mbed_official | 205:c41fc65bcfb4 | 840 | * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock |
mbed_official | 205:c41fc65bcfb4 | 841 | */ |
mbed_official | 205:c41fc65bcfb4 | 842 | #define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSource__) \ |
mbed_official | 205:c41fc65bcfb4 | 843 | MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, (uint32_t)(__I2C1CLKSource__)) |
mbed_official | 205:c41fc65bcfb4 | 844 | |
mbed_official | 205:c41fc65bcfb4 | 845 | /** @brief Macro to get the I2C1 clock source. |
mbed_official | 205:c41fc65bcfb4 | 846 | * @retval The clock source can be one of the following values: |
mbed_official | 205:c41fc65bcfb4 | 847 | * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock |
mbed_official | 205:c41fc65bcfb4 | 848 | * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock |
mbed_official | 205:c41fc65bcfb4 | 849 | */ |
mbed_official | 205:c41fc65bcfb4 | 850 | #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C1SW))) |
mbed_official | 205:c41fc65bcfb4 | 851 | |
mbed_official | 205:c41fc65bcfb4 | 852 | /** @brief Macro to configure the USART2 clock (USART2CLK). |
mbed_official | 205:c41fc65bcfb4 | 853 | * @param __USART2CLKSource__: specifies the USART2 clock source. |
mbed_official | 205:c41fc65bcfb4 | 854 | * This parameter can be one of the following values: |
mbed_official | 205:c41fc65bcfb4 | 855 | * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock |
mbed_official | 205:c41fc65bcfb4 | 856 | * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock |
mbed_official | 205:c41fc65bcfb4 | 857 | * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock |
mbed_official | 205:c41fc65bcfb4 | 858 | * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock |
mbed_official | 205:c41fc65bcfb4 | 859 | */ |
mbed_official | 205:c41fc65bcfb4 | 860 | #define __HAL_RCC_USART2_CONFIG(__USART2CLKSource__) \ |
mbed_official | 205:c41fc65bcfb4 | 861 | MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART2SW, (uint32_t)(__USART2CLKSource__)) |
mbed_official | 205:c41fc65bcfb4 | 862 | |
mbed_official | 205:c41fc65bcfb4 | 863 | /** @brief Macro to get the USART2 clock source. |
mbed_official | 205:c41fc65bcfb4 | 864 | * @retval The clock source can be one of the following values: |
mbed_official | 205:c41fc65bcfb4 | 865 | * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock |
mbed_official | 205:c41fc65bcfb4 | 866 | * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock |
mbed_official | 205:c41fc65bcfb4 | 867 | * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock |
mbed_official | 205:c41fc65bcfb4 | 868 | * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock |
mbed_official | 205:c41fc65bcfb4 | 869 | */ |
mbed_official | 205:c41fc65bcfb4 | 870 | #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART2SW))) |
mbed_official | 205:c41fc65bcfb4 | 871 | |
mbed_official | 205:c41fc65bcfb4 | 872 | /** @brief Macros to enable or disable the the RTC clock. |
mbed_official | 205:c41fc65bcfb4 | 873 | * @note These macros must be used only after the RTC clock source was selected. |
mbed_official | 205:c41fc65bcfb4 | 874 | */ |
mbed_official | 205:c41fc65bcfb4 | 875 | #define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN) |
mbed_official | 205:c41fc65bcfb4 | 876 | #define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN) |
mbed_official | 205:c41fc65bcfb4 | 877 | |
mbed_official | 205:c41fc65bcfb4 | 878 | /** @brief Macro to configure the RTC clock (RTCCLK). |
mbed_official | 205:c41fc65bcfb4 | 879 | * @note As the RTC clock configuration bits are in the Backup domain and write |
mbed_official | 205:c41fc65bcfb4 | 880 | * access is denied to this domain after reset, you have to enable write |
mbed_official | 205:c41fc65bcfb4 | 881 | * access using the Power Backup Access macro before to configure |
mbed_official | 205:c41fc65bcfb4 | 882 | * the RTC clock source (to be done once after reset). |
mbed_official | 205:c41fc65bcfb4 | 883 | * @note Once the RTC clock is configured it can't be changed unless the |
mbed_official | 205:c41fc65bcfb4 | 884 | * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by |
mbed_official | 205:c41fc65bcfb4 | 885 | * a Power On Reset (POR). |
mbed_official | 205:c41fc65bcfb4 | 886 | * @param __RTCCLKSource__: specifies the RTC clock source. |
mbed_official | 205:c41fc65bcfb4 | 887 | * This parameter can be one of the following values: |
mbed_official | 205:c41fc65bcfb4 | 888 | * @arg RCC_RTCCLKSOURCE_NONE: No clock selected as RTC clock |
mbed_official | 205:c41fc65bcfb4 | 889 | * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock |
mbed_official | 205:c41fc65bcfb4 | 890 | * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock |
mbed_official | 205:c41fc65bcfb4 | 891 | * @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32 |
mbed_official | 205:c41fc65bcfb4 | 892 | * |
mbed_official | 205:c41fc65bcfb4 | 893 | * @note If the LSE is used as RTC clock source, the RTC continues to |
mbed_official | 205:c41fc65bcfb4 | 894 | * work in STOP and STANDBY modes, and can be used as wakeup source. |
mbed_official | 205:c41fc65bcfb4 | 895 | * However, when the LSI clock and HSE clock divided by 32 is used as RTC clock source, |
mbed_official | 205:c41fc65bcfb4 | 896 | * the RTC cannot be used in STOP and STANDBY modes. |
mbed_official | 205:c41fc65bcfb4 | 897 | * @note The system must always be configured so as to get a PCLK frequency greater than or |
mbed_official | 205:c41fc65bcfb4 | 898 | * equal to the RTCCLK frequency for a proper operation of the RTC. |
mbed_official | 205:c41fc65bcfb4 | 899 | */ |
mbed_official | 205:c41fc65bcfb4 | 900 | #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) \ |
mbed_official | 205:c41fc65bcfb4 | 901 | MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (uint32_t)(__RTCCLKSource__)) |
mbed_official | 205:c41fc65bcfb4 | 902 | |
mbed_official | 205:c41fc65bcfb4 | 903 | /** @brief Macro to get the RTC clock source. |
mbed_official | 205:c41fc65bcfb4 | 904 | * @retval The clock source can be one of the following values: |
mbed_official | 205:c41fc65bcfb4 | 905 | * @arg RCC_RTCCLKSOURCE_NONE: No clock selected as RTC clock |
mbed_official | 205:c41fc65bcfb4 | 906 | * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock |
mbed_official | 205:c41fc65bcfb4 | 907 | * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock |
mbed_official | 205:c41fc65bcfb4 | 908 | * @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32 selected as RTC clock |
mbed_official | 205:c41fc65bcfb4 | 909 | */ |
mbed_official | 205:c41fc65bcfb4 | 910 | #define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))) |
mbed_official | 205:c41fc65bcfb4 | 911 | |
mbed_official | 205:c41fc65bcfb4 | 912 | /** @brief Macro to force or release the Backup domain reset. |
mbed_official | 205:c41fc65bcfb4 | 913 | * @note These macros reset the RTC peripheral (including the backup registers) |
mbed_official | 205:c41fc65bcfb4 | 914 | * and the RTC clock source selection in RCC_CSR register. |
mbed_official | 205:c41fc65bcfb4 | 915 | * @note The BKPSRAM is not affected by this reset. |
mbed_official | 205:c41fc65bcfb4 | 916 | */ |
mbed_official | 205:c41fc65bcfb4 | 917 | #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST) |
mbed_official | 205:c41fc65bcfb4 | 918 | #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST) |
mbed_official | 205:c41fc65bcfb4 | 919 | |
mbed_official | 205:c41fc65bcfb4 | 920 | /** @brief Macro to enable or disable the PLL. |
mbed_official | 205:c41fc65bcfb4 | 921 | * @note After enabling the PLL, the application software should wait on |
mbed_official | 205:c41fc65bcfb4 | 922 | * PLLRDY flag to be set indicating that PLL clock is stable and can |
mbed_official | 205:c41fc65bcfb4 | 923 | * be used as system clock source. |
mbed_official | 205:c41fc65bcfb4 | 924 | * @note The PLL can not be disabled if it is used as system clock source |
mbed_official | 205:c41fc65bcfb4 | 925 | * @note The PLL is disabled by hardware when entering STOP and STANDBY modes. |
mbed_official | 205:c41fc65bcfb4 | 926 | */ |
mbed_official | 205:c41fc65bcfb4 | 927 | #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON) |
mbed_official | 205:c41fc65bcfb4 | 928 | #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON) |
mbed_official | 205:c41fc65bcfb4 | 929 | |
mbed_official | 205:c41fc65bcfb4 | 930 | /** @brief Macro to configure the PLL clock source, multiplication and division factors. |
mbed_official | 205:c41fc65bcfb4 | 931 | * @note This macro must be used only when the PLL is disabled. |
mbed_official | 205:c41fc65bcfb4 | 932 | * |
mbed_official | 205:c41fc65bcfb4 | 933 | * @param __RCC_PLLSource__: specifies the PLL entry clock source. |
mbed_official | 205:c41fc65bcfb4 | 934 | * This parameter can be one of the following values: |
mbed_official | 205:c41fc65bcfb4 | 935 | * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry |
mbed_official | 205:c41fc65bcfb4 | 936 | * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry |
mbed_official | 205:c41fc65bcfb4 | 937 | * @param __PREDIV__: specifies the predivider factor for PLL VCO input clock |
mbed_official | 205:c41fc65bcfb4 | 938 | * This parameter must be a number between RCC_PREDIV_DIV1 and RCC_PREDIV_DIV16. |
mbed_official | 205:c41fc65bcfb4 | 939 | * @param __PLLMUL__: specifies the multiplication factor for PLL VCO input clock |
mbed_official | 205:c41fc65bcfb4 | 940 | * This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16. |
mbed_official | 205:c41fc65bcfb4 | 941 | * |
mbed_official | 205:c41fc65bcfb4 | 942 | */ |
mbed_official | 205:c41fc65bcfb4 | 943 | #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PREDIV__, __PLLMUL__) \ |
mbed_official | 205:c41fc65bcfb4 | 944 | do { \ |
mbed_official | 205:c41fc65bcfb4 | 945 | MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (__PREDIV__)); \ |
mbed_official | 205:c41fc65bcfb4 | 946 | MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSource__))); \ |
mbed_official | 205:c41fc65bcfb4 | 947 | } while(0) |
mbed_official | 205:c41fc65bcfb4 | 948 | |
mbed_official | 205:c41fc65bcfb4 | 949 | |
mbed_official | 205:c41fc65bcfb4 | 950 | /** @brief Macro to get the clock source used as system clock. |
mbed_official | 205:c41fc65bcfb4 | 951 | * @retval The clock source used as system clock. |
mbed_official | 205:c41fc65bcfb4 | 952 | * The returned value can be one of the following value: |
mbed_official | 205:c41fc65bcfb4 | 953 | * @arg RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock |
mbed_official | 205:c41fc65bcfb4 | 954 | * @arg RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock |
mbed_official | 205:c41fc65bcfb4 | 955 | * @arg RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock |
mbed_official | 205:c41fc65bcfb4 | 956 | */ |
mbed_official | 205:c41fc65bcfb4 | 957 | #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS))) |
mbed_official | 205:c41fc65bcfb4 | 958 | |
mbed_official | 205:c41fc65bcfb4 | 959 | /** @brief Macro to get the oscillator used as PLL clock source. |
mbed_official | 205:c41fc65bcfb4 | 960 | * @retval The oscillator used as PLL clock source. The returned value can be one |
mbed_official | 205:c41fc65bcfb4 | 961 | * of the following: |
mbed_official | 205:c41fc65bcfb4 | 962 | * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. |
mbed_official | 205:c41fc65bcfb4 | 963 | * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. |
mbed_official | 205:c41fc65bcfb4 | 964 | */ |
mbed_official | 205:c41fc65bcfb4 | 965 | #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC))) |
mbed_official | 205:c41fc65bcfb4 | 966 | |
mbed_official | 205:c41fc65bcfb4 | 967 | /** |
mbed_official | 205:c41fc65bcfb4 | 968 | * @} |
mbed_official | 205:c41fc65bcfb4 | 969 | */ |
mbed_official | 205:c41fc65bcfb4 | 970 | |
mbed_official | 205:c41fc65bcfb4 | 971 | /** @defgroup RCC_Flags_Interrupts_Management |
mbed_official | 205:c41fc65bcfb4 | 972 | * @brief macros to manage the specified RCC Flags and interrupts. |
mbed_official | 205:c41fc65bcfb4 | 973 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 974 | */ |
mbed_official | 205:c41fc65bcfb4 | 975 | |
mbed_official | 205:c41fc65bcfb4 | 976 | /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[12:8] bits to enable |
mbed_official | 205:c41fc65bcfb4 | 977 | * the selected interrupts.). |
mbed_official | 205:c41fc65bcfb4 | 978 | * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled. |
mbed_official | 205:c41fc65bcfb4 | 979 | * This parameter can be any combination of the following values: |
mbed_official | 205:c41fc65bcfb4 | 980 | * @arg RCC_IT_LSIRDY: LSI ready interrupt enable |
mbed_official | 205:c41fc65bcfb4 | 981 | * @arg RCC_IT_LSERDY: LSE ready interrupt enable |
mbed_official | 205:c41fc65bcfb4 | 982 | * @arg RCC_IT_HSIRDY: HSI ready interrupt enable |
mbed_official | 205:c41fc65bcfb4 | 983 | * @arg RCC_IT_HSERDY: HSE ready interrupt enable |
mbed_official | 205:c41fc65bcfb4 | 984 | * @arg RCC_IT_PLLRDY: PLL ready interrupt enable |
mbed_official | 205:c41fc65bcfb4 | 985 | * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt enable |
mbed_official | 205:c41fc65bcfb4 | 986 | * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt enable (only applicable to STM32F0X2 USB devices) |
mbed_official | 205:c41fc65bcfb4 | 987 | */ |
mbed_official | 205:c41fc65bcfb4 | 988 | #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *)RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) |
mbed_official | 205:c41fc65bcfb4 | 989 | |
mbed_official | 205:c41fc65bcfb4 | 990 | /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[12:8] bits to disable |
mbed_official | 205:c41fc65bcfb4 | 991 | * the selected interrupts.). |
mbed_official | 205:c41fc65bcfb4 | 992 | * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled. |
mbed_official | 205:c41fc65bcfb4 | 993 | * This parameter can be any combination of the following values: |
mbed_official | 205:c41fc65bcfb4 | 994 | * @arg RCC_IT_LSIRDY: LSI ready interrupt enable |
mbed_official | 205:c41fc65bcfb4 | 995 | * @arg RCC_IT_LSERDY: LSE ready interrupt enable |
mbed_official | 205:c41fc65bcfb4 | 996 | * @arg RCC_IT_HSIRDY: HSI ready interrupt enable |
mbed_official | 205:c41fc65bcfb4 | 997 | * @arg RCC_IT_HSERDY: HSE ready interrupt enable |
mbed_official | 205:c41fc65bcfb4 | 998 | * @arg RCC_IT_PLLRDY: PLL ready interrupt enable |
mbed_official | 205:c41fc65bcfb4 | 999 | * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt enable |
mbed_official | 205:c41fc65bcfb4 | 1000 | * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt enable (only applicable to STM32F0X2 USB devices) |
mbed_official | 205:c41fc65bcfb4 | 1001 | */ |
mbed_official | 205:c41fc65bcfb4 | 1002 | #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *)RCC_CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__)) |
mbed_official | 205:c41fc65bcfb4 | 1003 | |
mbed_official | 205:c41fc65bcfb4 | 1004 | /** @brief Clear the RCC's interrupt pending bits ( Perform Byte access to RCC_CIR[23:16] |
mbed_official | 205:c41fc65bcfb4 | 1005 | * bits to clear the selected interrupt pending bits. |
mbed_official | 205:c41fc65bcfb4 | 1006 | * @param __IT__: specifies the interrupt pending bit to clear. |
mbed_official | 205:c41fc65bcfb4 | 1007 | * This parameter can be any combination of the following values: |
mbed_official | 205:c41fc65bcfb4 | 1008 | * @arg RCC_IT_LSIRDY: LSI ready interrupt clear |
mbed_official | 205:c41fc65bcfb4 | 1009 | * @arg RCC_IT_LSERDY: LSE ready interrupt clear |
mbed_official | 205:c41fc65bcfb4 | 1010 | * @arg RCC_IT_HSIRDY: HSI ready interrupt clear |
mbed_official | 205:c41fc65bcfb4 | 1011 | * @arg RCC_IT_HSERDY: HSE ready interrupt clear |
mbed_official | 205:c41fc65bcfb4 | 1012 | * @arg RCC_IT_PLLRDY: PLL ready interrupt clear |
mbed_official | 205:c41fc65bcfb4 | 1013 | * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt clear |
mbed_official | 205:c41fc65bcfb4 | 1014 | * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt clear (only applicable to STM32F0X2 USB devices) |
mbed_official | 205:c41fc65bcfb4 | 1015 | * @arg RCC_IT_CSS: Clock Security System interrupt clear |
mbed_official | 205:c41fc65bcfb4 | 1016 | */ |
mbed_official | 205:c41fc65bcfb4 | 1017 | #define __HAL_RCC_CLEAR_IT(__IT__) (*(__IO uint8_t *)RCC_CIR_BYTE2_ADDRESS = (__IT__)) |
mbed_official | 205:c41fc65bcfb4 | 1018 | |
mbed_official | 205:c41fc65bcfb4 | 1019 | /** @brief Check the RCC's interrupt has occurred or not. |
mbed_official | 205:c41fc65bcfb4 | 1020 | * @param __IT__: specifies the RCC interrupt source to check. |
mbed_official | 205:c41fc65bcfb4 | 1021 | * This parameter can be one of the following values: |
mbed_official | 205:c41fc65bcfb4 | 1022 | * @arg RCC_IT_LSIRDY: LSI ready interrupt flag |
mbed_official | 205:c41fc65bcfb4 | 1023 | * @arg RCC_IT_LSERDY: LSE ready interrupt flag |
mbed_official | 205:c41fc65bcfb4 | 1024 | * @arg RCC_IT_HSIRDY: HSI ready interrupt flag |
mbed_official | 205:c41fc65bcfb4 | 1025 | * @arg RCC_IT_HSERDY: HSE ready interrupt flag |
mbed_official | 205:c41fc65bcfb4 | 1026 | * @arg RCC_IT_PLLRDY: PLL ready interrupt flag |
mbed_official | 205:c41fc65bcfb4 | 1027 | * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt flag |
mbed_official | 205:c41fc65bcfb4 | 1028 | * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt flag (only applicable to STM32F0X2 USB devices) |
mbed_official | 205:c41fc65bcfb4 | 1029 | * @arg RCC_IT_CSS: Clock Security System interrupt flag |
mbed_official | 205:c41fc65bcfb4 | 1030 | * @retval The new state of __IT__ (TRUE or FALSE). |
mbed_official | 205:c41fc65bcfb4 | 1031 | */ |
mbed_official | 205:c41fc65bcfb4 | 1032 | #define __HAL_RCC_GET_IT(__IT__) ((RCC->CIR & (__IT__)) == (__IT__)) |
mbed_official | 205:c41fc65bcfb4 | 1033 | |
mbed_official | 205:c41fc65bcfb4 | 1034 | /** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, |
mbed_official | 205:c41fc65bcfb4 | 1035 | * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST |
mbed_official | 205:c41fc65bcfb4 | 1036 | */ |
mbed_official | 205:c41fc65bcfb4 | 1037 | #define __HAL_RCC_CLEAR_RESET_FLAGS() SET_BIT(RCC->CSR, RCC_CSR_RMVF) |
mbed_official | 205:c41fc65bcfb4 | 1038 | |
mbed_official | 205:c41fc65bcfb4 | 1039 | /** @brief Check RCC flag is set or not. |
mbed_official | 205:c41fc65bcfb4 | 1040 | * @param __FLAG__: specifies the flag to check. |
mbed_official | 205:c41fc65bcfb4 | 1041 | * This parameter can be one of the following values: |
mbed_official | 205:c41fc65bcfb4 | 1042 | * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready |
mbed_official | 205:c41fc65bcfb4 | 1043 | * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready |
mbed_official | 205:c41fc65bcfb4 | 1044 | * @arg RCC_FLAG_PLLRDY: PLL clock ready |
mbed_official | 205:c41fc65bcfb4 | 1045 | * @arg RCC_FLAG_HSI14RDY: HSI14 oscillator clock ready |
mbed_official | 205:c41fc65bcfb4 | 1046 | * @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready (only applicable to STM32F0X2 USB devices) |
mbed_official | 205:c41fc65bcfb4 | 1047 | * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready |
mbed_official | 205:c41fc65bcfb4 | 1048 | * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready |
mbed_official | 205:c41fc65bcfb4 | 1049 | * @arg RCC_FLAG_OBLRST: Option Byte Load reset |
mbed_official | 205:c41fc65bcfb4 | 1050 | * @arg RCC_FLAG_PINRST: Pin reset |
mbed_official | 205:c41fc65bcfb4 | 1051 | * @arg RCC_FLAG_PORRST: POR/PDR reset |
mbed_official | 205:c41fc65bcfb4 | 1052 | * @arg RCC_FLAG_SFTRST: Software reset |
mbed_official | 205:c41fc65bcfb4 | 1053 | * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset |
mbed_official | 205:c41fc65bcfb4 | 1054 | * @arg RCC_FLAG_WWDGRST: Window Watchdog reset |
mbed_official | 205:c41fc65bcfb4 | 1055 | * @arg RCC_FLAG_LPWRRST: Low Power reset |
mbed_official | 205:c41fc65bcfb4 | 1056 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
mbed_official | 205:c41fc65bcfb4 | 1057 | */ |
mbed_official | 205:c41fc65bcfb4 | 1058 | #define RCC_FLAG_MASK ((uint8_t)0x1F) |
mbed_official | 205:c41fc65bcfb4 | 1059 | #define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5) == CR_REG_INDEX)? RCC->CR : \ |
mbed_official | 205:c41fc65bcfb4 | 1060 | (((__FLAG__) >> 5) == CR2_REG_INDEX)? RCC->CR2 : \ |
mbed_official | 205:c41fc65bcfb4 | 1061 | (((__FLAG__) >> 5) == BDCR_REG_INDEX) ? RCC->BDCR : \ |
mbed_official | 205:c41fc65bcfb4 | 1062 | RCC->CSR) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) |
mbed_official | 205:c41fc65bcfb4 | 1063 | |
mbed_official | 205:c41fc65bcfb4 | 1064 | |
mbed_official | 205:c41fc65bcfb4 | 1065 | |
mbed_official | 205:c41fc65bcfb4 | 1066 | /** |
mbed_official | 205:c41fc65bcfb4 | 1067 | * @} |
mbed_official | 205:c41fc65bcfb4 | 1068 | */ |
mbed_official | 205:c41fc65bcfb4 | 1069 | |
mbed_official | 205:c41fc65bcfb4 | 1070 | /* Include RCC HAL Extension module */ |
mbed_official | 205:c41fc65bcfb4 | 1071 | #include "stm32f0xx_hal_rcc_ex.h" |
mbed_official | 205:c41fc65bcfb4 | 1072 | |
mbed_official | 205:c41fc65bcfb4 | 1073 | /* Exported functions --------------------------------------------------------*/ |
mbed_official | 205:c41fc65bcfb4 | 1074 | |
mbed_official | 205:c41fc65bcfb4 | 1075 | /* Initialization and de-initialization functions ***************************/ |
mbed_official | 205:c41fc65bcfb4 | 1076 | void HAL_RCC_DeInit(void); |
mbed_official | 205:c41fc65bcfb4 | 1077 | HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); |
mbed_official | 205:c41fc65bcfb4 | 1078 | HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); |
mbed_official | 205:c41fc65bcfb4 | 1079 | |
mbed_official | 205:c41fc65bcfb4 | 1080 | /* Peripheral Control functions *********************************************/ |
mbed_official | 205:c41fc65bcfb4 | 1081 | void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); |
mbed_official | 205:c41fc65bcfb4 | 1082 | void HAL_RCC_EnableCSS(void); |
mbed_official | 205:c41fc65bcfb4 | 1083 | void HAL_RCC_DisableCSS(void); |
mbed_official | 205:c41fc65bcfb4 | 1084 | uint32_t HAL_RCC_GetSysClockFreq(void); |
mbed_official | 205:c41fc65bcfb4 | 1085 | uint32_t HAL_RCC_GetHCLKFreq(void); |
mbed_official | 205:c41fc65bcfb4 | 1086 | uint32_t HAL_RCC_GetPCLK1Freq(void); |
mbed_official | 205:c41fc65bcfb4 | 1087 | void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); |
mbed_official | 205:c41fc65bcfb4 | 1088 | void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); |
mbed_official | 205:c41fc65bcfb4 | 1089 | |
mbed_official | 205:c41fc65bcfb4 | 1090 | /* CSS NMI IRQ handler */ |
mbed_official | 205:c41fc65bcfb4 | 1091 | void HAL_RCC_NMI_IRQHandler(void); |
mbed_official | 205:c41fc65bcfb4 | 1092 | |
mbed_official | 205:c41fc65bcfb4 | 1093 | /* User Callbacks in non blocking mode (IT mode) */ |
mbed_official | 205:c41fc65bcfb4 | 1094 | void HAL_RCC_CCSCallback(void); |
mbed_official | 205:c41fc65bcfb4 | 1095 | |
mbed_official | 205:c41fc65bcfb4 | 1096 | /** |
mbed_official | 205:c41fc65bcfb4 | 1097 | * @} |
mbed_official | 205:c41fc65bcfb4 | 1098 | */ |
mbed_official | 205:c41fc65bcfb4 | 1099 | |
mbed_official | 205:c41fc65bcfb4 | 1100 | /** |
mbed_official | 205:c41fc65bcfb4 | 1101 | * @} |
mbed_official | 205:c41fc65bcfb4 | 1102 | */ |
mbed_official | 205:c41fc65bcfb4 | 1103 | |
mbed_official | 205:c41fc65bcfb4 | 1104 | #ifdef __cplusplus |
mbed_official | 205:c41fc65bcfb4 | 1105 | } |
mbed_official | 205:c41fc65bcfb4 | 1106 | #endif |
mbed_official | 205:c41fc65bcfb4 | 1107 | |
mbed_official | 205:c41fc65bcfb4 | 1108 | #endif /* __STM32F0xx_HAL_RCC_H */ |
mbed_official | 205:c41fc65bcfb4 | 1109 | |
mbed_official | 205:c41fc65bcfb4 | 1110 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |