mbed library sources modified for open wear
Dependents: openwear-lifelogger-example
Fork of mbed-src by
targets/cmsis/TARGET_STM/TARGET_STM32F4XX/system_stm32f4xx.c@20:4263a77256ae, 2013-09-10 (annotated)
- Committer:
- bogdanm
- Date:
- Tue Sep 10 15:14:19 2013 +0300
- Revision:
- 20:4263a77256ae
Sync with git revision 171dda705c947bf910926a0b73d6a4797802554d
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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bogdanm | 20:4263a77256ae | 1 | /** |
bogdanm | 20:4263a77256ae | 2 | ****************************************************************************** |
bogdanm | 20:4263a77256ae | 3 | * @file system_stm32f4xx.c |
bogdanm | 20:4263a77256ae | 4 | * @author MCD Application Team |
bogdanm | 20:4263a77256ae | 5 | * @version V1.1.0 |
bogdanm | 20:4263a77256ae | 6 | * @date 11-January-2013 |
bogdanm | 20:4263a77256ae | 7 | * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. |
bogdanm | 20:4263a77256ae | 8 | * This file contains the system clock configuration for STM32F4xx devices, |
bogdanm | 20:4263a77256ae | 9 | * and is generated by the clock configuration tool |
bogdanm | 20:4263a77256ae | 10 | * stm32f4xx_Clock_Configuration_V1.1.0.xls |
bogdanm | 20:4263a77256ae | 11 | * |
bogdanm | 20:4263a77256ae | 12 | * 1. This file provides two functions and one global variable to be called from |
bogdanm | 20:4263a77256ae | 13 | * user application: |
bogdanm | 20:4263a77256ae | 14 | * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier |
bogdanm | 20:4263a77256ae | 15 | * and Divider factors, AHB/APBx prescalers and Flash settings), |
bogdanm | 20:4263a77256ae | 16 | * depending on the configuration made in the clock xls tool. |
bogdanm | 20:4263a77256ae | 17 | * This function is called at startup just after reset and |
bogdanm | 20:4263a77256ae | 18 | * before branch to main program. This call is made inside |
bogdanm | 20:4263a77256ae | 19 | * the "startup_stm32f4xx.s" file. |
bogdanm | 20:4263a77256ae | 20 | * |
bogdanm | 20:4263a77256ae | 21 | * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used |
bogdanm | 20:4263a77256ae | 22 | * by the user application to setup the SysTick |
bogdanm | 20:4263a77256ae | 23 | * timer or configure other parameters. |
bogdanm | 20:4263a77256ae | 24 | * |
bogdanm | 20:4263a77256ae | 25 | * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must |
bogdanm | 20:4263a77256ae | 26 | * be called whenever the core clock is changed |
bogdanm | 20:4263a77256ae | 27 | * during program execution. |
bogdanm | 20:4263a77256ae | 28 | * |
bogdanm | 20:4263a77256ae | 29 | * 2. After each device reset the HSI (16 MHz) is used as system clock source. |
bogdanm | 20:4263a77256ae | 30 | * Then SystemInit() function is called, in "startup_stm32f4xx.s" file, to |
bogdanm | 20:4263a77256ae | 31 | * configure the system clock before to branch to main program. |
bogdanm | 20:4263a77256ae | 32 | * |
bogdanm | 20:4263a77256ae | 33 | * 3. If the system clock source selected by user fails to startup, the SystemInit() |
bogdanm | 20:4263a77256ae | 34 | * function will do nothing and HSI still used as system clock source. User can |
bogdanm | 20:4263a77256ae | 35 | * add some code to deal with this issue inside the SetSysClock() function. |
bogdanm | 20:4263a77256ae | 36 | * |
bogdanm | 20:4263a77256ae | 37 | * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define |
bogdanm | 20:4263a77256ae | 38 | * in "stm32f4xx.h" file. When HSE is used as system clock source, directly or |
bogdanm | 20:4263a77256ae | 39 | * through PLL, and you are using different crystal you have to adapt the HSE |
bogdanm | 20:4263a77256ae | 40 | * value to your own configuration. |
bogdanm | 20:4263a77256ae | 41 | * |
bogdanm | 20:4263a77256ae | 42 | * 5. This file configures the system clock as follows: |
bogdanm | 20:4263a77256ae | 43 | *============================================================================= |
bogdanm | 20:4263a77256ae | 44 | *============================================================================= |
bogdanm | 20:4263a77256ae | 45 | * Supported STM32F40xx/41xx/427x/437x devices |
bogdanm | 20:4263a77256ae | 46 | *----------------------------------------------------------------------------- |
bogdanm | 20:4263a77256ae | 47 | * System Clock source | PLL (HSE) |
bogdanm | 20:4263a77256ae | 48 | *----------------------------------------------------------------------------- |
bogdanm | 20:4263a77256ae | 49 | * SYSCLK(Hz) | 168000000 |
bogdanm | 20:4263a77256ae | 50 | *----------------------------------------------------------------------------- |
bogdanm | 20:4263a77256ae | 51 | * HCLK(Hz) | 168000000 |
bogdanm | 20:4263a77256ae | 52 | *----------------------------------------------------------------------------- |
bogdanm | 20:4263a77256ae | 53 | * AHB Prescaler | 1 |
bogdanm | 20:4263a77256ae | 54 | *----------------------------------------------------------------------------- |
bogdanm | 20:4263a77256ae | 55 | * APB1 Prescaler | 4 |
bogdanm | 20:4263a77256ae | 56 | *----------------------------------------------------------------------------- |
bogdanm | 20:4263a77256ae | 57 | * APB2 Prescaler | 2 |
bogdanm | 20:4263a77256ae | 58 | *----------------------------------------------------------------------------- |
bogdanm | 20:4263a77256ae | 59 | * HSE Frequency(Hz) | 8000000 |
bogdanm | 20:4263a77256ae | 60 | *----------------------------------------------------------------------------- |
bogdanm | 20:4263a77256ae | 61 | * PLL_M | 8 |
bogdanm | 20:4263a77256ae | 62 | *----------------------------------------------------------------------------- |
bogdanm | 20:4263a77256ae | 63 | * PLL_N | 336 |
bogdanm | 20:4263a77256ae | 64 | *----------------------------------------------------------------------------- |
bogdanm | 20:4263a77256ae | 65 | * PLL_P | 2 |
bogdanm | 20:4263a77256ae | 66 | *----------------------------------------------------------------------------- |
bogdanm | 20:4263a77256ae | 67 | * PLL_Q | 7 |
bogdanm | 20:4263a77256ae | 68 | *----------------------------------------------------------------------------- |
bogdanm | 20:4263a77256ae | 69 | * PLLI2S_N | 271 |
bogdanm | 20:4263a77256ae | 70 | *----------------------------------------------------------------------------- |
bogdanm | 20:4263a77256ae | 71 | * PLLI2S_R | 2 |
bogdanm | 20:4263a77256ae | 72 | *----------------------------------------------------------------------------- |
bogdanm | 20:4263a77256ae | 73 | * I2S input clock | NA |
bogdanm | 20:4263a77256ae | 74 | *----------------------------------------------------------------------------- |
bogdanm | 20:4263a77256ae | 75 | * VDD(V) | 3.3 |
bogdanm | 20:4263a77256ae | 76 | *----------------------------------------------------------------------------- |
bogdanm | 20:4263a77256ae | 77 | * Main regulator output voltage | Scale1 mode |
bogdanm | 20:4263a77256ae | 78 | *----------------------------------------------------------------------------- |
bogdanm | 20:4263a77256ae | 79 | * Flash Latency(WS) | 5 |
bogdanm | 20:4263a77256ae | 80 | *----------------------------------------------------------------------------- |
bogdanm | 20:4263a77256ae | 81 | * Prefetch Buffer | ON |
bogdanm | 20:4263a77256ae | 82 | *----------------------------------------------------------------------------- |
bogdanm | 20:4263a77256ae | 83 | * Instruction cache | ON |
bogdanm | 20:4263a77256ae | 84 | *----------------------------------------------------------------------------- |
bogdanm | 20:4263a77256ae | 85 | * Data cache | ON |
bogdanm | 20:4263a77256ae | 86 | *----------------------------------------------------------------------------- |
bogdanm | 20:4263a77256ae | 87 | * Require 48MHz for USB OTG FS, | Disabled |
bogdanm | 20:4263a77256ae | 88 | * SDIO and RNG clock | |
bogdanm | 20:4263a77256ae | 89 | *----------------------------------------------------------------------------- |
bogdanm | 20:4263a77256ae | 90 | *============================================================================= |
bogdanm | 20:4263a77256ae | 91 | ****************************************************************************** |
bogdanm | 20:4263a77256ae | 92 | * @attention |
bogdanm | 20:4263a77256ae | 93 | * |
bogdanm | 20:4263a77256ae | 94 | * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2> |
bogdanm | 20:4263a77256ae | 95 | * |
bogdanm | 20:4263a77256ae | 96 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); |
bogdanm | 20:4263a77256ae | 97 | * You may not use this file except in compliance with the License. |
bogdanm | 20:4263a77256ae | 98 | * You may obtain a copy of the License at: |
bogdanm | 20:4263a77256ae | 99 | * |
bogdanm | 20:4263a77256ae | 100 | * http://www.st.com/software_license_agreement_liberty_v2 |
bogdanm | 20:4263a77256ae | 101 | * |
bogdanm | 20:4263a77256ae | 102 | * Unless required by applicable law or agreed to in writing, software |
bogdanm | 20:4263a77256ae | 103 | * distributed under the License is distributed on an "AS IS" BASIS, |
bogdanm | 20:4263a77256ae | 104 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
bogdanm | 20:4263a77256ae | 105 | * See the License for the specific language governing permissions and |
bogdanm | 20:4263a77256ae | 106 | * limitations under the License. |
bogdanm | 20:4263a77256ae | 107 | * |
bogdanm | 20:4263a77256ae | 108 | ****************************************************************************** |
bogdanm | 20:4263a77256ae | 109 | */ |
bogdanm | 20:4263a77256ae | 110 | |
bogdanm | 20:4263a77256ae | 111 | /** @addtogroup CMSIS |
bogdanm | 20:4263a77256ae | 112 | * @{ |
bogdanm | 20:4263a77256ae | 113 | */ |
bogdanm | 20:4263a77256ae | 114 | |
bogdanm | 20:4263a77256ae | 115 | /** @addtogroup stm32f4xx_system |
bogdanm | 20:4263a77256ae | 116 | * @{ |
bogdanm | 20:4263a77256ae | 117 | */ |
bogdanm | 20:4263a77256ae | 118 | |
bogdanm | 20:4263a77256ae | 119 | /** @addtogroup STM32F4xx_System_Private_Includes |
bogdanm | 20:4263a77256ae | 120 | * @{ |
bogdanm | 20:4263a77256ae | 121 | */ |
bogdanm | 20:4263a77256ae | 122 | |
bogdanm | 20:4263a77256ae | 123 | #include "stm32f4xx.h" |
bogdanm | 20:4263a77256ae | 124 | |
bogdanm | 20:4263a77256ae | 125 | /** |
bogdanm | 20:4263a77256ae | 126 | * @} |
bogdanm | 20:4263a77256ae | 127 | */ |
bogdanm | 20:4263a77256ae | 128 | |
bogdanm | 20:4263a77256ae | 129 | /** @addtogroup STM32F4xx_System_Private_TypesDefinitions |
bogdanm | 20:4263a77256ae | 130 | * @{ |
bogdanm | 20:4263a77256ae | 131 | */ |
bogdanm | 20:4263a77256ae | 132 | |
bogdanm | 20:4263a77256ae | 133 | /** |
bogdanm | 20:4263a77256ae | 134 | * @} |
bogdanm | 20:4263a77256ae | 135 | */ |
bogdanm | 20:4263a77256ae | 136 | |
bogdanm | 20:4263a77256ae | 137 | /** @addtogroup STM32F4xx_System_Private_Defines |
bogdanm | 20:4263a77256ae | 138 | * @{ |
bogdanm | 20:4263a77256ae | 139 | */ |
bogdanm | 20:4263a77256ae | 140 | |
bogdanm | 20:4263a77256ae | 141 | /************************* Miscellaneous Configuration ************************/ |
bogdanm | 20:4263a77256ae | 142 | /*!< Uncomment the following line if you need to use external SRAM mounted |
bogdanm | 20:4263a77256ae | 143 | on STM324xG_EVAL/STM324x7I_EVAL boards as data memory */ |
bogdanm | 20:4263a77256ae | 144 | /* #define DATA_IN_ExtSRAM */ |
bogdanm | 20:4263a77256ae | 145 | |
bogdanm | 20:4263a77256ae | 146 | /*!< Uncomment the following line if you need to relocate your vector Table in |
bogdanm | 20:4263a77256ae | 147 | Internal SRAM. */ |
bogdanm | 20:4263a77256ae | 148 | /* #define VECT_TAB_SRAM */ |
bogdanm | 20:4263a77256ae | 149 | #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. |
bogdanm | 20:4263a77256ae | 150 | This value must be a multiple of 0x200. */ |
bogdanm | 20:4263a77256ae | 151 | /******************************************************************************/ |
bogdanm | 20:4263a77256ae | 152 | |
bogdanm | 20:4263a77256ae | 153 | /************************* PLL Parameters *************************************/ |
bogdanm | 20:4263a77256ae | 154 | /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ |
bogdanm | 20:4263a77256ae | 155 | #define PLL_M 8 |
bogdanm | 20:4263a77256ae | 156 | #define PLL_N 336 |
bogdanm | 20:4263a77256ae | 157 | |
bogdanm | 20:4263a77256ae | 158 | /* SYSCLK = PLL_VCO / PLL_P */ |
bogdanm | 20:4263a77256ae | 159 | #define PLL_P 2 |
bogdanm | 20:4263a77256ae | 160 | |
bogdanm | 20:4263a77256ae | 161 | /* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ |
bogdanm | 20:4263a77256ae | 162 | #define PLL_Q 7 |
bogdanm | 20:4263a77256ae | 163 | |
bogdanm | 20:4263a77256ae | 164 | #define PLLI2S_N 271 |
bogdanm | 20:4263a77256ae | 165 | #define PLLI2S_R 2 |
bogdanm | 20:4263a77256ae | 166 | |
bogdanm | 20:4263a77256ae | 167 | /******************************************************************************/ |
bogdanm | 20:4263a77256ae | 168 | |
bogdanm | 20:4263a77256ae | 169 | /** |
bogdanm | 20:4263a77256ae | 170 | * @} |
bogdanm | 20:4263a77256ae | 171 | */ |
bogdanm | 20:4263a77256ae | 172 | |
bogdanm | 20:4263a77256ae | 173 | /** @addtogroup STM32F4xx_System_Private_Macros |
bogdanm | 20:4263a77256ae | 174 | * @{ |
bogdanm | 20:4263a77256ae | 175 | */ |
bogdanm | 20:4263a77256ae | 176 | |
bogdanm | 20:4263a77256ae | 177 | /** |
bogdanm | 20:4263a77256ae | 178 | * @} |
bogdanm | 20:4263a77256ae | 179 | */ |
bogdanm | 20:4263a77256ae | 180 | |
bogdanm | 20:4263a77256ae | 181 | /** @addtogroup STM32F4xx_System_Private_Variables |
bogdanm | 20:4263a77256ae | 182 | * @{ |
bogdanm | 20:4263a77256ae | 183 | */ |
bogdanm | 20:4263a77256ae | 184 | |
bogdanm | 20:4263a77256ae | 185 | uint32_t SystemCoreClock = 168000000; |
bogdanm | 20:4263a77256ae | 186 | |
bogdanm | 20:4263a77256ae | 187 | __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; |
bogdanm | 20:4263a77256ae | 188 | |
bogdanm | 20:4263a77256ae | 189 | /** |
bogdanm | 20:4263a77256ae | 190 | * @} |
bogdanm | 20:4263a77256ae | 191 | */ |
bogdanm | 20:4263a77256ae | 192 | |
bogdanm | 20:4263a77256ae | 193 | /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes |
bogdanm | 20:4263a77256ae | 194 | * @{ |
bogdanm | 20:4263a77256ae | 195 | */ |
bogdanm | 20:4263a77256ae | 196 | |
bogdanm | 20:4263a77256ae | 197 | static void SetSysClock(void); |
bogdanm | 20:4263a77256ae | 198 | #ifdef DATA_IN_ExtSRAM |
bogdanm | 20:4263a77256ae | 199 | static void SystemInit_ExtMemCtl(void); |
bogdanm | 20:4263a77256ae | 200 | #endif /* DATA_IN_ExtSRAM */ |
bogdanm | 20:4263a77256ae | 201 | |
bogdanm | 20:4263a77256ae | 202 | /** |
bogdanm | 20:4263a77256ae | 203 | * @} |
bogdanm | 20:4263a77256ae | 204 | */ |
bogdanm | 20:4263a77256ae | 205 | |
bogdanm | 20:4263a77256ae | 206 | /** @addtogroup STM32F4xx_System_Private_Functions |
bogdanm | 20:4263a77256ae | 207 | * @{ |
bogdanm | 20:4263a77256ae | 208 | */ |
bogdanm | 20:4263a77256ae | 209 | |
bogdanm | 20:4263a77256ae | 210 | /** |
bogdanm | 20:4263a77256ae | 211 | * @brief Setup the microcontroller system |
bogdanm | 20:4263a77256ae | 212 | * Initialize the Embedded Flash Interface, the PLL and update the |
bogdanm | 20:4263a77256ae | 213 | * SystemFrequency variable. |
bogdanm | 20:4263a77256ae | 214 | * @param None |
bogdanm | 20:4263a77256ae | 215 | * @retval None |
bogdanm | 20:4263a77256ae | 216 | */ |
bogdanm | 20:4263a77256ae | 217 | void SystemInit(void) |
bogdanm | 20:4263a77256ae | 218 | { |
bogdanm | 20:4263a77256ae | 219 | /* FPU settings ------------------------------------------------------------*/ |
bogdanm | 20:4263a77256ae | 220 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) |
bogdanm | 20:4263a77256ae | 221 | SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ |
bogdanm | 20:4263a77256ae | 222 | #endif |
bogdanm | 20:4263a77256ae | 223 | /* Reset the RCC clock configuration to the default reset state ------------*/ |
bogdanm | 20:4263a77256ae | 224 | /* Set HSION bit */ |
bogdanm | 20:4263a77256ae | 225 | RCC->CR |= (uint32_t)0x00000001; |
bogdanm | 20:4263a77256ae | 226 | |
bogdanm | 20:4263a77256ae | 227 | /* Reset CFGR register */ |
bogdanm | 20:4263a77256ae | 228 | RCC->CFGR = 0x00000000; |
bogdanm | 20:4263a77256ae | 229 | |
bogdanm | 20:4263a77256ae | 230 | /* Reset HSEON, CSSON and PLLON bits */ |
bogdanm | 20:4263a77256ae | 231 | RCC->CR &= (uint32_t)0xFEF6FFFF; |
bogdanm | 20:4263a77256ae | 232 | |
bogdanm | 20:4263a77256ae | 233 | /* Reset PLLCFGR register */ |
bogdanm | 20:4263a77256ae | 234 | RCC->PLLCFGR = 0x24003010; |
bogdanm | 20:4263a77256ae | 235 | |
bogdanm | 20:4263a77256ae | 236 | /* Reset HSEBYP bit */ |
bogdanm | 20:4263a77256ae | 237 | RCC->CR &= (uint32_t)0xFFFBFFFF; |
bogdanm | 20:4263a77256ae | 238 | |
bogdanm | 20:4263a77256ae | 239 | /* Disable all interrupts */ |
bogdanm | 20:4263a77256ae | 240 | RCC->CIR = 0x00000000; |
bogdanm | 20:4263a77256ae | 241 | |
bogdanm | 20:4263a77256ae | 242 | #ifdef DATA_IN_ExtSRAM |
bogdanm | 20:4263a77256ae | 243 | SystemInit_ExtMemCtl(); |
bogdanm | 20:4263a77256ae | 244 | #endif /* DATA_IN_ExtSRAM */ |
bogdanm | 20:4263a77256ae | 245 | |
bogdanm | 20:4263a77256ae | 246 | /* Configure the System clock source, PLL Multiplier and Divider factors, |
bogdanm | 20:4263a77256ae | 247 | AHB/APBx prescalers and Flash settings ----------------------------------*/ |
bogdanm | 20:4263a77256ae | 248 | SetSysClock(); |
bogdanm | 20:4263a77256ae | 249 | |
bogdanm | 20:4263a77256ae | 250 | /* Configure the Vector Table location add offset address ------------------*/ |
bogdanm | 20:4263a77256ae | 251 | #ifdef VECT_TAB_SRAM |
bogdanm | 20:4263a77256ae | 252 | SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ |
bogdanm | 20:4263a77256ae | 253 | #else |
bogdanm | 20:4263a77256ae | 254 | SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ |
bogdanm | 20:4263a77256ae | 255 | #endif |
bogdanm | 20:4263a77256ae | 256 | } |
bogdanm | 20:4263a77256ae | 257 | |
bogdanm | 20:4263a77256ae | 258 | /** |
bogdanm | 20:4263a77256ae | 259 | * @brief Update SystemCoreClock variable according to Clock Register Values. |
bogdanm | 20:4263a77256ae | 260 | * The SystemCoreClock variable contains the core clock (HCLK), it can |
bogdanm | 20:4263a77256ae | 261 | * be used by the user application to setup the SysTick timer or configure |
bogdanm | 20:4263a77256ae | 262 | * other parameters. |
bogdanm | 20:4263a77256ae | 263 | * |
bogdanm | 20:4263a77256ae | 264 | * @note Each time the core clock (HCLK) changes, this function must be called |
bogdanm | 20:4263a77256ae | 265 | * to update SystemCoreClock variable value. Otherwise, any configuration |
bogdanm | 20:4263a77256ae | 266 | * based on this variable will be incorrect. |
bogdanm | 20:4263a77256ae | 267 | * |
bogdanm | 20:4263a77256ae | 268 | * @note - The system frequency computed by this function is not the real |
bogdanm | 20:4263a77256ae | 269 | * frequency in the chip. It is calculated based on the predefined |
bogdanm | 20:4263a77256ae | 270 | * constant and the selected clock source: |
bogdanm | 20:4263a77256ae | 271 | * |
bogdanm | 20:4263a77256ae | 272 | * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) |
bogdanm | 20:4263a77256ae | 273 | * |
bogdanm | 20:4263a77256ae | 274 | * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) |
bogdanm | 20:4263a77256ae | 275 | * |
bogdanm | 20:4263a77256ae | 276 | * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) |
bogdanm | 20:4263a77256ae | 277 | * or HSI_VALUE(*) multiplied/divided by the PLL factors. |
bogdanm | 20:4263a77256ae | 278 | * |
bogdanm | 20:4263a77256ae | 279 | * (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value |
bogdanm | 20:4263a77256ae | 280 | * 16 MHz) but the real value may vary depending on the variations |
bogdanm | 20:4263a77256ae | 281 | * in voltage and temperature. |
bogdanm | 20:4263a77256ae | 282 | * |
bogdanm | 20:4263a77256ae | 283 | * (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value |
bogdanm | 20:4263a77256ae | 284 | * 25 MHz), user has to ensure that HSE_VALUE is same as the real |
bogdanm | 20:4263a77256ae | 285 | * frequency of the crystal used. Otherwise, this function may |
bogdanm | 20:4263a77256ae | 286 | * have wrong result. |
bogdanm | 20:4263a77256ae | 287 | * |
bogdanm | 20:4263a77256ae | 288 | * - The result of this function could be not correct when using fractional |
bogdanm | 20:4263a77256ae | 289 | * value for HSE crystal. |
bogdanm | 20:4263a77256ae | 290 | * |
bogdanm | 20:4263a77256ae | 291 | * @param None |
bogdanm | 20:4263a77256ae | 292 | * @retval None |
bogdanm | 20:4263a77256ae | 293 | */ |
bogdanm | 20:4263a77256ae | 294 | void SystemCoreClockUpdate(void) |
bogdanm | 20:4263a77256ae | 295 | { |
bogdanm | 20:4263a77256ae | 296 | uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; |
bogdanm | 20:4263a77256ae | 297 | |
bogdanm | 20:4263a77256ae | 298 | /* Get SYSCLK source -------------------------------------------------------*/ |
bogdanm | 20:4263a77256ae | 299 | tmp = RCC->CFGR & RCC_CFGR_SWS; |
bogdanm | 20:4263a77256ae | 300 | |
bogdanm | 20:4263a77256ae | 301 | switch (tmp) |
bogdanm | 20:4263a77256ae | 302 | { |
bogdanm | 20:4263a77256ae | 303 | case 0x00: /* HSI used as system clock source */ |
bogdanm | 20:4263a77256ae | 304 | SystemCoreClock = HSI_VALUE; |
bogdanm | 20:4263a77256ae | 305 | break; |
bogdanm | 20:4263a77256ae | 306 | case 0x04: /* HSE used as system clock source */ |
bogdanm | 20:4263a77256ae | 307 | SystemCoreClock = HSE_VALUE; |
bogdanm | 20:4263a77256ae | 308 | break; |
bogdanm | 20:4263a77256ae | 309 | case 0x08: /* PLL used as system clock source */ |
bogdanm | 20:4263a77256ae | 310 | |
bogdanm | 20:4263a77256ae | 311 | /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N |
bogdanm | 20:4263a77256ae | 312 | SYSCLK = PLL_VCO / PLL_P |
bogdanm | 20:4263a77256ae | 313 | */ |
bogdanm | 20:4263a77256ae | 314 | pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; |
bogdanm | 20:4263a77256ae | 315 | pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; |
bogdanm | 20:4263a77256ae | 316 | |
bogdanm | 20:4263a77256ae | 317 | if (pllsource != 0) |
bogdanm | 20:4263a77256ae | 318 | { |
bogdanm | 20:4263a77256ae | 319 | /* HSE used as PLL clock source */ |
bogdanm | 20:4263a77256ae | 320 | pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); |
bogdanm | 20:4263a77256ae | 321 | } |
bogdanm | 20:4263a77256ae | 322 | else |
bogdanm | 20:4263a77256ae | 323 | { |
bogdanm | 20:4263a77256ae | 324 | /* HSI used as PLL clock source */ |
bogdanm | 20:4263a77256ae | 325 | pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); |
bogdanm | 20:4263a77256ae | 326 | } |
bogdanm | 20:4263a77256ae | 327 | |
bogdanm | 20:4263a77256ae | 328 | pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; |
bogdanm | 20:4263a77256ae | 329 | SystemCoreClock = pllvco/pllp; |
bogdanm | 20:4263a77256ae | 330 | break; |
bogdanm | 20:4263a77256ae | 331 | default: |
bogdanm | 20:4263a77256ae | 332 | SystemCoreClock = HSI_VALUE; |
bogdanm | 20:4263a77256ae | 333 | break; |
bogdanm | 20:4263a77256ae | 334 | } |
bogdanm | 20:4263a77256ae | 335 | /* Compute HCLK frequency --------------------------------------------------*/ |
bogdanm | 20:4263a77256ae | 336 | /* Get HCLK prescaler */ |
bogdanm | 20:4263a77256ae | 337 | tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; |
bogdanm | 20:4263a77256ae | 338 | /* HCLK frequency */ |
bogdanm | 20:4263a77256ae | 339 | SystemCoreClock >>= tmp; |
bogdanm | 20:4263a77256ae | 340 | } |
bogdanm | 20:4263a77256ae | 341 | |
bogdanm | 20:4263a77256ae | 342 | /** |
bogdanm | 20:4263a77256ae | 343 | * @brief Configures the System clock source, PLL Multiplier and Divider factors, |
bogdanm | 20:4263a77256ae | 344 | * AHB/APBx prescalers and Flash settings |
bogdanm | 20:4263a77256ae | 345 | * @Note This function should be called only once the RCC clock configuration |
bogdanm | 20:4263a77256ae | 346 | * is reset to the default reset state (done in SystemInit() function). |
bogdanm | 20:4263a77256ae | 347 | * @param None |
bogdanm | 20:4263a77256ae | 348 | * @retval None |
bogdanm | 20:4263a77256ae | 349 | */ |
bogdanm | 20:4263a77256ae | 350 | static void SetSysClock(void) |
bogdanm | 20:4263a77256ae | 351 | { |
bogdanm | 20:4263a77256ae | 352 | /******************************************************************************/ |
bogdanm | 20:4263a77256ae | 353 | /* PLL (clocked by HSE) used as System clock source */ |
bogdanm | 20:4263a77256ae | 354 | /******************************************************************************/ |
bogdanm | 20:4263a77256ae | 355 | __IO uint32_t StartUpCounter = 0, HSEStatus = 0; |
bogdanm | 20:4263a77256ae | 356 | |
bogdanm | 20:4263a77256ae | 357 | /* Enable HSE */ |
bogdanm | 20:4263a77256ae | 358 | RCC->CR |= ((uint32_t)RCC_CR_HSEON); |
bogdanm | 20:4263a77256ae | 359 | |
bogdanm | 20:4263a77256ae | 360 | /* Wait till HSE is ready and if Time out is reached exit */ |
bogdanm | 20:4263a77256ae | 361 | do |
bogdanm | 20:4263a77256ae | 362 | { |
bogdanm | 20:4263a77256ae | 363 | HSEStatus = RCC->CR & RCC_CR_HSERDY; |
bogdanm | 20:4263a77256ae | 364 | StartUpCounter++; |
bogdanm | 20:4263a77256ae | 365 | } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); |
bogdanm | 20:4263a77256ae | 366 | |
bogdanm | 20:4263a77256ae | 367 | if ((RCC->CR & RCC_CR_HSERDY) != RESET) |
bogdanm | 20:4263a77256ae | 368 | { |
bogdanm | 20:4263a77256ae | 369 | HSEStatus = (uint32_t)0x01; |
bogdanm | 20:4263a77256ae | 370 | } |
bogdanm | 20:4263a77256ae | 371 | else |
bogdanm | 20:4263a77256ae | 372 | { |
bogdanm | 20:4263a77256ae | 373 | HSEStatus = (uint32_t)0x00; |
bogdanm | 20:4263a77256ae | 374 | } |
bogdanm | 20:4263a77256ae | 375 | |
bogdanm | 20:4263a77256ae | 376 | if (HSEStatus == (uint32_t)0x01) |
bogdanm | 20:4263a77256ae | 377 | { |
bogdanm | 20:4263a77256ae | 378 | /* Select regulator voltage output Scale 1 mode, System frequency up to 168 MHz */ |
bogdanm | 20:4263a77256ae | 379 | RCC->APB1ENR |= RCC_APB1ENR_PWREN; |
bogdanm | 20:4263a77256ae | 380 | PWR->CR |= PWR_CR_VOS; |
bogdanm | 20:4263a77256ae | 381 | |
bogdanm | 20:4263a77256ae | 382 | /* HCLK = SYSCLK / 1*/ |
bogdanm | 20:4263a77256ae | 383 | RCC->CFGR |= RCC_CFGR_HPRE_DIV1; |
bogdanm | 20:4263a77256ae | 384 | |
bogdanm | 20:4263a77256ae | 385 | /* PCLK2 = HCLK / 2*/ |
bogdanm | 20:4263a77256ae | 386 | RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; |
bogdanm | 20:4263a77256ae | 387 | |
bogdanm | 20:4263a77256ae | 388 | /* PCLK1 = HCLK / 4*/ |
bogdanm | 20:4263a77256ae | 389 | RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; |
bogdanm | 20:4263a77256ae | 390 | |
bogdanm | 20:4263a77256ae | 391 | /* Configure the main PLL */ |
bogdanm | 20:4263a77256ae | 392 | RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | |
bogdanm | 20:4263a77256ae | 393 | (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); |
bogdanm | 20:4263a77256ae | 394 | |
bogdanm | 20:4263a77256ae | 395 | /* Enable the main PLL */ |
bogdanm | 20:4263a77256ae | 396 | RCC->CR |= RCC_CR_PLLON; |
bogdanm | 20:4263a77256ae | 397 | |
bogdanm | 20:4263a77256ae | 398 | /* Wait till the main PLL is ready */ |
bogdanm | 20:4263a77256ae | 399 | while((RCC->CR & RCC_CR_PLLRDY) == 0) |
bogdanm | 20:4263a77256ae | 400 | { |
bogdanm | 20:4263a77256ae | 401 | } |
bogdanm | 20:4263a77256ae | 402 | |
bogdanm | 20:4263a77256ae | 403 | /* Configure the I2S PLL */ |
bogdanm | 20:4263a77256ae | 404 | RCC->PLLI2SCFGR = (PLLI2S_N << 6) | (PLLI2S_R << 28); |
bogdanm | 20:4263a77256ae | 405 | |
bogdanm | 20:4263a77256ae | 406 | /* Enable the I2S PLL */ |
bogdanm | 20:4263a77256ae | 407 | RCC->CR |= RCC_CR_PLLI2SON; |
bogdanm | 20:4263a77256ae | 408 | |
bogdanm | 20:4263a77256ae | 409 | /* Wait until the I2S PLL is ready */ |
bogdanm | 20:4263a77256ae | 410 | while (!(RCC->CR & RCC_CR_PLLI2SRDY)); |
bogdanm | 20:4263a77256ae | 411 | |
bogdanm | 20:4263a77256ae | 412 | /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ |
bogdanm | 20:4263a77256ae | 413 | FLASH->ACR = FLASH_ACR_PRFTEN |FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS; |
bogdanm | 20:4263a77256ae | 414 | |
bogdanm | 20:4263a77256ae | 415 | /* Select the main PLL as system clock source */ |
bogdanm | 20:4263a77256ae | 416 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); |
bogdanm | 20:4263a77256ae | 417 | RCC->CFGR |= RCC_CFGR_SW_PLL; |
bogdanm | 20:4263a77256ae | 418 | |
bogdanm | 20:4263a77256ae | 419 | /* Wait till the main PLL is used as system clock source */ |
bogdanm | 20:4263a77256ae | 420 | while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); |
bogdanm | 20:4263a77256ae | 421 | { |
bogdanm | 20:4263a77256ae | 422 | } |
bogdanm | 20:4263a77256ae | 423 | } |
bogdanm | 20:4263a77256ae | 424 | else |
bogdanm | 20:4263a77256ae | 425 | { /* If HSE fails to start-up, the application will have wrong clock |
bogdanm | 20:4263a77256ae | 426 | configuration. User can add here some code to deal with this error */ |
bogdanm | 20:4263a77256ae | 427 | } |
bogdanm | 20:4263a77256ae | 428 | |
bogdanm | 20:4263a77256ae | 429 | } |
bogdanm | 20:4263a77256ae | 430 | |
bogdanm | 20:4263a77256ae | 431 | /** |
bogdanm | 20:4263a77256ae | 432 | * @brief Setup the external memory controller. Called in startup_stm32f4xx.s |
bogdanm | 20:4263a77256ae | 433 | * before jump to __main |
bogdanm | 20:4263a77256ae | 434 | * @param None |
bogdanm | 20:4263a77256ae | 435 | * @retval None |
bogdanm | 20:4263a77256ae | 436 | */ |
bogdanm | 20:4263a77256ae | 437 | #ifdef DATA_IN_ExtSRAM |
bogdanm | 20:4263a77256ae | 438 | /** |
bogdanm | 20:4263a77256ae | 439 | * @brief Setup the external memory controller. |
bogdanm | 20:4263a77256ae | 440 | * Called in startup_stm32f4xx.s before jump to main. |
bogdanm | 20:4263a77256ae | 441 | * This function configures the external SRAM mounted on STM324xG_EVAL/STM324x7I boards |
bogdanm | 20:4263a77256ae | 442 | * This SRAM will be used as program data memory (including heap and stack). |
bogdanm | 20:4263a77256ae | 443 | * @param None |
bogdanm | 20:4263a77256ae | 444 | * @retval None |
bogdanm | 20:4263a77256ae | 445 | */ |
bogdanm | 20:4263a77256ae | 446 | void SystemInit_ExtMemCtl(void) |
bogdanm | 20:4263a77256ae | 447 | { |
bogdanm | 20:4263a77256ae | 448 | /*-- GPIOs Configuration -----------------------------------------------------*/ |
bogdanm | 20:4263a77256ae | 449 | /* |
bogdanm | 20:4263a77256ae | 450 | +-------------------+--------------------+------------------+------------------+ |
bogdanm | 20:4263a77256ae | 451 | + SRAM pins assignment + |
bogdanm | 20:4263a77256ae | 452 | +-------------------+--------------------+------------------+------------------+ |
bogdanm | 20:4263a77256ae | 453 | | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | |
bogdanm | 20:4263a77256ae | 454 | | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | |
bogdanm | 20:4263a77256ae | 455 | | PD4 <-> FSMC_NOE | PE2 <-> FSMC_A23 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | |
bogdanm | 20:4263a77256ae | 456 | | PD5 <-> FSMC_NWE | PE3 <-> FSMC_A19 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | |
bogdanm | 20:4263a77256ae | 457 | | PD8 <-> FSMC_D13 | PE4 <-> FSMC_A20 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | |
bogdanm | 20:4263a77256ae | 458 | | PD9 <-> FSMC_D14 | PE5 <-> FSMC_A21 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | |
bogdanm | 20:4263a77256ae | 459 | | PD10 <-> FSMC_D15 | PE6 <-> FSMC_A22 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | |
bogdanm | 20:4263a77256ae | 460 | | PD11 <-> FSMC_A16 | PE7 <-> FSMC_D4 | PF13 <-> FSMC_A7 |------------------+ |
bogdanm | 20:4263a77256ae | 461 | | PD12 <-> FSMC_A17 | PE8 <-> FSMC_D5 | PF14 <-> FSMC_A8 | |
bogdanm | 20:4263a77256ae | 462 | | PD13 <-> FSMC_A18 | PE9 <-> FSMC_D6 | PF15 <-> FSMC_A9 | |
bogdanm | 20:4263a77256ae | 463 | | PD14 <-> FSMC_D0 | PE10 <-> FSMC_D7 |------------------+ |
bogdanm | 20:4263a77256ae | 464 | | PD15 <-> FSMC_D1 | PE11 <-> FSMC_D8 | |
bogdanm | 20:4263a77256ae | 465 | +-------------------| PE12 <-> FSMC_D9 | |
bogdanm | 20:4263a77256ae | 466 | | PE13 <-> FSMC_D10 | |
bogdanm | 20:4263a77256ae | 467 | | PE14 <-> FSMC_D11 | |
bogdanm | 20:4263a77256ae | 468 | | PE15 <-> FSMC_D12 | |
bogdanm | 20:4263a77256ae | 469 | +--------------------+ |
bogdanm | 20:4263a77256ae | 470 | */ |
bogdanm | 20:4263a77256ae | 471 | /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ |
bogdanm | 20:4263a77256ae | 472 | RCC->AHB1ENR |= 0x00000078; |
bogdanm | 20:4263a77256ae | 473 | |
bogdanm | 20:4263a77256ae | 474 | /* Connect PDx pins to FSMC Alternate function */ |
bogdanm | 20:4263a77256ae | 475 | GPIOD->AFR[0] = 0x00cc00cc; |
bogdanm | 20:4263a77256ae | 476 | GPIOD->AFR[1] = 0xcccccccc; |
bogdanm | 20:4263a77256ae | 477 | /* Configure PDx pins in Alternate function mode */ |
bogdanm | 20:4263a77256ae | 478 | GPIOD->MODER = 0xaaaa0a0a; |
bogdanm | 20:4263a77256ae | 479 | /* Configure PDx pins speed to 100 MHz */ |
bogdanm | 20:4263a77256ae | 480 | GPIOD->OSPEEDR = 0xffff0f0f; |
bogdanm | 20:4263a77256ae | 481 | /* Configure PDx pins Output type to push-pull */ |
bogdanm | 20:4263a77256ae | 482 | GPIOD->OTYPER = 0x00000000; |
bogdanm | 20:4263a77256ae | 483 | /* No pull-up, pull-down for PDx pins */ |
bogdanm | 20:4263a77256ae | 484 | GPIOD->PUPDR = 0x00000000; |
bogdanm | 20:4263a77256ae | 485 | |
bogdanm | 20:4263a77256ae | 486 | /* Connect PEx pins to FSMC Alternate function */ |
bogdanm | 20:4263a77256ae | 487 | GPIOE->AFR[0] = 0xcccccccc; |
bogdanm | 20:4263a77256ae | 488 | GPIOE->AFR[1] = 0xcccccccc; |
bogdanm | 20:4263a77256ae | 489 | /* Configure PEx pins in Alternate function mode */ |
bogdanm | 20:4263a77256ae | 490 | GPIOE->MODER = 0xaaaaaaaa; |
bogdanm | 20:4263a77256ae | 491 | /* Configure PEx pins speed to 100 MHz */ |
bogdanm | 20:4263a77256ae | 492 | GPIOE->OSPEEDR = 0xffffffff; |
bogdanm | 20:4263a77256ae | 493 | /* Configure PEx pins Output type to push-pull */ |
bogdanm | 20:4263a77256ae | 494 | GPIOE->OTYPER = 0x00000000; |
bogdanm | 20:4263a77256ae | 495 | /* No pull-up, pull-down for PEx pins */ |
bogdanm | 20:4263a77256ae | 496 | GPIOE->PUPDR = 0x00000000; |
bogdanm | 20:4263a77256ae | 497 | |
bogdanm | 20:4263a77256ae | 498 | /* Connect PFx pins to FSMC Alternate function */ |
bogdanm | 20:4263a77256ae | 499 | GPIOF->AFR[0] = 0x00cccccc; |
bogdanm | 20:4263a77256ae | 500 | GPIOF->AFR[1] = 0xcccc0000; |
bogdanm | 20:4263a77256ae | 501 | /* Configure PFx pins in Alternate function mode */ |
bogdanm | 20:4263a77256ae | 502 | GPIOF->MODER = 0xaa000aaa; |
bogdanm | 20:4263a77256ae | 503 | /* Configure PFx pins speed to 100 MHz */ |
bogdanm | 20:4263a77256ae | 504 | GPIOF->OSPEEDR = 0xff000fff; |
bogdanm | 20:4263a77256ae | 505 | /* Configure PFx pins Output type to push-pull */ |
bogdanm | 20:4263a77256ae | 506 | GPIOF->OTYPER = 0x00000000; |
bogdanm | 20:4263a77256ae | 507 | /* No pull-up, pull-down for PFx pins */ |
bogdanm | 20:4263a77256ae | 508 | GPIOF->PUPDR = 0x00000000; |
bogdanm | 20:4263a77256ae | 509 | |
bogdanm | 20:4263a77256ae | 510 | /* Connect PGx pins to FSMC Alternate function */ |
bogdanm | 20:4263a77256ae | 511 | GPIOG->AFR[0] = 0x00cccccc; |
bogdanm | 20:4263a77256ae | 512 | GPIOG->AFR[1] = 0x000000c0; |
bogdanm | 20:4263a77256ae | 513 | /* Configure PGx pins in Alternate function mode */ |
bogdanm | 20:4263a77256ae | 514 | GPIOG->MODER = 0x00080aaa; |
bogdanm | 20:4263a77256ae | 515 | /* Configure PGx pins speed to 100 MHz */ |
bogdanm | 20:4263a77256ae | 516 | GPIOG->OSPEEDR = 0x000c0fff; |
bogdanm | 20:4263a77256ae | 517 | /* Configure PGx pins Output type to push-pull */ |
bogdanm | 20:4263a77256ae | 518 | GPIOG->OTYPER = 0x00000000; |
bogdanm | 20:4263a77256ae | 519 | /* No pull-up, pull-down for PGx pins */ |
bogdanm | 20:4263a77256ae | 520 | GPIOG->PUPDR = 0x00000000; |
bogdanm | 20:4263a77256ae | 521 | |
bogdanm | 20:4263a77256ae | 522 | /*-- FSMC Configuration ------------------------------------------------------*/ |
bogdanm | 20:4263a77256ae | 523 | /* Enable the FSMC interface clock */ |
bogdanm | 20:4263a77256ae | 524 | RCC->AHB3ENR |= 0x00000001; |
bogdanm | 20:4263a77256ae | 525 | |
bogdanm | 20:4263a77256ae | 526 | /* Configure and enable Bank1_SRAM2 */ |
bogdanm | 20:4263a77256ae | 527 | FSMC_Bank1->BTCR[2] = 0x00001011; |
bogdanm | 20:4263a77256ae | 528 | FSMC_Bank1->BTCR[3] = 0x00000201; |
bogdanm | 20:4263a77256ae | 529 | FSMC_Bank1E->BWTR[2] = 0x0fffffff; |
bogdanm | 20:4263a77256ae | 530 | /* |
bogdanm | 20:4263a77256ae | 531 | Bank1_SRAM2 is configured as follow: |
bogdanm | 20:4263a77256ae | 532 | |
bogdanm | 20:4263a77256ae | 533 | p.FSMC_AddressSetupTime = 1; |
bogdanm | 20:4263a77256ae | 534 | p.FSMC_AddressHoldTime = 0; |
bogdanm | 20:4263a77256ae | 535 | p.FSMC_DataSetupTime = 2; |
bogdanm | 20:4263a77256ae | 536 | p.FSMC_BusTurnAroundDuration = 0; |
bogdanm | 20:4263a77256ae | 537 | p.FSMC_CLKDivision = 0; |
bogdanm | 20:4263a77256ae | 538 | p.FSMC_DataLatency = 0; |
bogdanm | 20:4263a77256ae | 539 | p.FSMC_AccessMode = FSMC_AccessMode_A; |
bogdanm | 20:4263a77256ae | 540 | |
bogdanm | 20:4263a77256ae | 541 | FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; |
bogdanm | 20:4263a77256ae | 542 | FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; |
bogdanm | 20:4263a77256ae | 543 | FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM; |
bogdanm | 20:4263a77256ae | 544 | FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; |
bogdanm | 20:4263a77256ae | 545 | FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; |
bogdanm | 20:4263a77256ae | 546 | FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; |
bogdanm | 20:4263a77256ae | 547 | FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; |
bogdanm | 20:4263a77256ae | 548 | FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; |
bogdanm | 20:4263a77256ae | 549 | FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; |
bogdanm | 20:4263a77256ae | 550 | FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; |
bogdanm | 20:4263a77256ae | 551 | FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; |
bogdanm | 20:4263a77256ae | 552 | FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; |
bogdanm | 20:4263a77256ae | 553 | FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; |
bogdanm | 20:4263a77256ae | 554 | FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; |
bogdanm | 20:4263a77256ae | 555 | FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; |
bogdanm | 20:4263a77256ae | 556 | */ |
bogdanm | 20:4263a77256ae | 557 | } |
bogdanm | 20:4263a77256ae | 558 | #endif /* DATA_IN_ExtSRAM */ |
bogdanm | 20:4263a77256ae | 559 | |
bogdanm | 20:4263a77256ae | 560 | |
bogdanm | 20:4263a77256ae | 561 | /** |
bogdanm | 20:4263a77256ae | 562 | * @} |
bogdanm | 20:4263a77256ae | 563 | */ |
bogdanm | 20:4263a77256ae | 564 | |
bogdanm | 20:4263a77256ae | 565 | /** |
bogdanm | 20:4263a77256ae | 566 | * @} |
bogdanm | 20:4263a77256ae | 567 | */ |
bogdanm | 20:4263a77256ae | 568 | |
bogdanm | 20:4263a77256ae | 569 | /** |
bogdanm | 20:4263a77256ae | 570 | * @} |
bogdanm | 20:4263a77256ae | 571 | */ |
bogdanm | 20:4263a77256ae | 572 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
bogdanm | 20:4263a77256ae | 573 |