mbed library sources modified for open wear
Dependents: openwear-lifelogger-example
Fork of mbed-src by
targets/cmsis/TARGET_Freescale/TARGET_K20D5M/system_MK20D5.c@68:41613245dfd7, 2013-12-26 (annotated)
- Committer:
- mbed_official
- Date:
- Thu Dec 26 13:00:06 2013 +0000
- Revision:
- 68:41613245dfd7
Synchronized with git revision fba199a9c4445231b0f38e1e113c118182635546
Full URL: https://github.com/mbedmicro/mbed/commit/fba199a9c4445231b0f38e1e113c118182635546/
target K20D5M
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
mbed_official | 68:41613245dfd7 | 1 | /* |
mbed_official | 68:41613245dfd7 | 2 | ** ################################################################### |
mbed_official | 68:41613245dfd7 | 3 | ** Compilers: ARM Compiler |
mbed_official | 68:41613245dfd7 | 4 | ** Freescale C/C++ for Embedded ARM |
mbed_official | 68:41613245dfd7 | 5 | ** GNU C Compiler |
mbed_official | 68:41613245dfd7 | 6 | ** IAR ANSI C/C++ Compiler for ARM |
mbed_official | 68:41613245dfd7 | 7 | ** |
mbed_official | 68:41613245dfd7 | 8 | ** Reference manuals: K20P64M50SF0RM Rev. 1, Oct 2011 |
mbed_official | 68:41613245dfd7 | 9 | ** K20P32M50SF0RM Rev. 1, Oct 2011 |
mbed_official | 68:41613245dfd7 | 10 | ** K20P48M50SF0RM Rev. 1, Oct 2011 |
mbed_official | 68:41613245dfd7 | 11 | ** |
mbed_official | 68:41613245dfd7 | 12 | ** Version: rev. 1.0, 2011-12-15 |
mbed_official | 68:41613245dfd7 | 13 | ** |
mbed_official | 68:41613245dfd7 | 14 | ** Abstract: |
mbed_official | 68:41613245dfd7 | 15 | ** Provides a system configuration function and a global variable that |
mbed_official | 68:41613245dfd7 | 16 | ** contains the system frequency. It configures the device and initializes |
mbed_official | 68:41613245dfd7 | 17 | ** the oscillator (PLL) that is part of the microcontroller device. |
mbed_official | 68:41613245dfd7 | 18 | ** |
mbed_official | 68:41613245dfd7 | 19 | ** Copyright: 2011 Freescale Semiconductor, Inc. All Rights Reserved. |
mbed_official | 68:41613245dfd7 | 20 | ** |
mbed_official | 68:41613245dfd7 | 21 | ** http: www.freescale.com |
mbed_official | 68:41613245dfd7 | 22 | ** mail: support@freescale.com |
mbed_official | 68:41613245dfd7 | 23 | ** |
mbed_official | 68:41613245dfd7 | 24 | ** Revisions: |
mbed_official | 68:41613245dfd7 | 25 | ** - rev. 1.0 (2011-12-15) |
mbed_official | 68:41613245dfd7 | 26 | ** Initial version |
mbed_official | 68:41613245dfd7 | 27 | ** |
mbed_official | 68:41613245dfd7 | 28 | ** ################################################################### |
mbed_official | 68:41613245dfd7 | 29 | */ |
mbed_official | 68:41613245dfd7 | 30 | |
mbed_official | 68:41613245dfd7 | 31 | /** |
mbed_official | 68:41613245dfd7 | 32 | * @file MK20D5 |
mbed_official | 68:41613245dfd7 | 33 | * @version 1.0 |
mbed_official | 68:41613245dfd7 | 34 | * @date 2011-12-15 |
mbed_official | 68:41613245dfd7 | 35 | * @brief Device specific configuration file for MK20D5 (implementation file) |
mbed_official | 68:41613245dfd7 | 36 | * |
mbed_official | 68:41613245dfd7 | 37 | * Provides a system configuration function and a global variable that contains |
mbed_official | 68:41613245dfd7 | 38 | * the system frequency. It configures the device and initializes the oscillator |
mbed_official | 68:41613245dfd7 | 39 | * (PLL) that is part of the microcontroller device. |
mbed_official | 68:41613245dfd7 | 40 | */ |
mbed_official | 68:41613245dfd7 | 41 | |
mbed_official | 68:41613245dfd7 | 42 | #include <stdint.h> |
mbed_official | 68:41613245dfd7 | 43 | #include "MK20D5.h" |
mbed_official | 68:41613245dfd7 | 44 | |
mbed_official | 68:41613245dfd7 | 45 | #define DISABLE_WDOG 1 |
mbed_official | 68:41613245dfd7 | 46 | |
mbed_official | 68:41613245dfd7 | 47 | #define CLOCK_SETUP 1 |
mbed_official | 68:41613245dfd7 | 48 | /* Predefined clock setups |
mbed_official | 68:41613245dfd7 | 49 | 0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode |
mbed_official | 68:41613245dfd7 | 50 | Reference clock source for MCG module is the slow internal clock source 32.768kHz |
mbed_official | 68:41613245dfd7 | 51 | Core clock = 41.94MHz, BusClock = 41.94MHz |
mbed_official | 68:41613245dfd7 | 52 | 1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode |
mbed_official | 68:41613245dfd7 | 53 | Reference clock source for MCG module is an external crystal 8MHz |
mbed_official | 68:41613245dfd7 | 54 | Core clock = 48MHz, BusClock = 48MHz |
mbed_official | 68:41613245dfd7 | 55 | 2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode |
mbed_official | 68:41613245dfd7 | 56 | Core clock/Bus clock derived directly from an external crystal 8MHz with no multiplication |
mbed_official | 68:41613245dfd7 | 57 | Core clock = 8MHz, BusClock = 8MHz |
mbed_official | 68:41613245dfd7 | 58 | */ |
mbed_official | 68:41613245dfd7 | 59 | |
mbed_official | 68:41613245dfd7 | 60 | /*---------------------------------------------------------------------------- |
mbed_official | 68:41613245dfd7 | 61 | Define clock source values |
mbed_official | 68:41613245dfd7 | 62 | *----------------------------------------------------------------------------*/ |
mbed_official | 68:41613245dfd7 | 63 | #if (CLOCK_SETUP == 0) |
mbed_official | 68:41613245dfd7 | 64 | #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */ |
mbed_official | 68:41613245dfd7 | 65 | #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */ |
mbed_official | 68:41613245dfd7 | 66 | #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ |
mbed_official | 68:41613245dfd7 | 67 | #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ |
mbed_official | 68:41613245dfd7 | 68 | #define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value */ |
mbed_official | 68:41613245dfd7 | 69 | #elif (CLOCK_SETUP == 1) |
mbed_official | 68:41613245dfd7 | 70 | #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */ |
mbed_official | 68:41613245dfd7 | 71 | #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */ |
mbed_official | 68:41613245dfd7 | 72 | #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ |
mbed_official | 68:41613245dfd7 | 73 | #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ |
mbed_official | 68:41613245dfd7 | 74 | #define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */ |
mbed_official | 68:41613245dfd7 | 75 | #elif (CLOCK_SETUP == 2) |
mbed_official | 68:41613245dfd7 | 76 | #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */ |
mbed_official | 68:41613245dfd7 | 77 | #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */ |
mbed_official | 68:41613245dfd7 | 78 | #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ |
mbed_official | 68:41613245dfd7 | 79 | #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ |
mbed_official | 68:41613245dfd7 | 80 | #define DEFAULT_SYSTEM_CLOCK 8000000u /* Default System clock value */ |
mbed_official | 68:41613245dfd7 | 81 | #endif /* (CLOCK_SETUP == 2) */ |
mbed_official | 68:41613245dfd7 | 82 | |
mbed_official | 68:41613245dfd7 | 83 | |
mbed_official | 68:41613245dfd7 | 84 | /* ---------------------------------------------------------------------------- |
mbed_official | 68:41613245dfd7 | 85 | -- Core clock |
mbed_official | 68:41613245dfd7 | 86 | ---------------------------------------------------------------------------- */ |
mbed_official | 68:41613245dfd7 | 87 | |
mbed_official | 68:41613245dfd7 | 88 | uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; |
mbed_official | 68:41613245dfd7 | 89 | |
mbed_official | 68:41613245dfd7 | 90 | /* ---------------------------------------------------------------------------- |
mbed_official | 68:41613245dfd7 | 91 | -- SystemInit() |
mbed_official | 68:41613245dfd7 | 92 | ---------------------------------------------------------------------------- */ |
mbed_official | 68:41613245dfd7 | 93 | |
mbed_official | 68:41613245dfd7 | 94 | void SystemInit (void) { |
mbed_official | 68:41613245dfd7 | 95 | #if (DISABLE_WDOG) |
mbed_official | 68:41613245dfd7 | 96 | /* Disable the WDOG module */ |
mbed_official | 68:41613245dfd7 | 97 | /* WDOG_UNLOCK: WDOGUNLOCK=0xC520 */ |
mbed_official | 68:41613245dfd7 | 98 | WDOG->UNLOCK = (uint16_t)0xC520u; /* Key 1 */ |
mbed_official | 68:41613245dfd7 | 99 | /* WDOG_UNLOCK : WDOGUNLOCK=0xD928 */ |
mbed_official | 68:41613245dfd7 | 100 | WDOG->UNLOCK = (uint16_t)0xD928u; /* Key 2 */ |
mbed_official | 68:41613245dfd7 | 101 | /* WDOG_STCTRLH: ??=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,??=0,STNDBYEN=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */ |
mbed_official | 68:41613245dfd7 | 102 | WDOG->STCTRLH = (uint16_t)0x01D2u; |
mbed_official | 68:41613245dfd7 | 103 | #endif /* (DISABLE_WDOG) */ |
mbed_official | 68:41613245dfd7 | 104 | #if (CLOCK_SETUP == 0) |
mbed_official | 68:41613245dfd7 | 105 | /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ |
mbed_official | 68:41613245dfd7 | 106 | SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */ |
mbed_official | 68:41613245dfd7 | 107 | /* Switch to FEI Mode */ |
mbed_official | 68:41613245dfd7 | 108 | /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */ |
mbed_official | 68:41613245dfd7 | 109 | MCG->C1 = (uint8_t)0x06u; |
mbed_official | 68:41613245dfd7 | 110 | /* MCG->C2: ??=0,??=0,RANGE0=0,HGO=0,EREFS=0,LP=0,IRCS=0 */ |
mbed_official | 68:41613245dfd7 | 111 | MCG->C2 = (uint8_t)0x00u; |
mbed_official | 68:41613245dfd7 | 112 | /* MCG_C4: DMX32=0,DRST_DRS=1 */ |
mbed_official | 68:41613245dfd7 | 113 | MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0u) | (uint8_t)0x20u); |
mbed_official | 68:41613245dfd7 | 114 | /* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */ |
mbed_official | 68:41613245dfd7 | 115 | MCG->C5 = (uint8_t)0x00u; |
mbed_official | 68:41613245dfd7 | 116 | /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */ |
mbed_official | 68:41613245dfd7 | 117 | MCG->C6 = (uint8_t)0x00u; |
mbed_official | 68:41613245dfd7 | 118 | while((MCG->S & MCG_S_IREFST_MASK) == 0u) { /* Check that the source of the FLL reference clock is the internal reference clock. */ |
mbed_official | 68:41613245dfd7 | 119 | } |
mbed_official | 68:41613245dfd7 | 120 | while((MCG->S & 0x0Cu) != 0x00u) { /* Wait until output of the FLL is selected */ |
mbed_official | 68:41613245dfd7 | 121 | } |
mbed_official | 68:41613245dfd7 | 122 | #elif (CLOCK_SETUP == 1) |
mbed_official | 68:41613245dfd7 | 123 | /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ |
mbed_official | 68:41613245dfd7 | 124 | SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */ |
mbed_official | 68:41613245dfd7 | 125 | /* Switch to FBE Mode */ |
mbed_official | 68:41613245dfd7 | 126 | /* OSC0->CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ |
mbed_official | 68:41613245dfd7 | 127 | OSC0->CR = (uint8_t)0x00u; |
mbed_official | 68:41613245dfd7 | 128 | /* MCG->C7: OSCSEL=0 */ |
mbed_official | 68:41613245dfd7 | 129 | MCG->C7 = (uint8_t)0x00u; |
mbed_official | 68:41613245dfd7 | 130 | /* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */ |
mbed_official | 68:41613245dfd7 | 131 | MCG->C2 = (uint8_t)0x24u; |
mbed_official | 68:41613245dfd7 | 132 | /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ |
mbed_official | 68:41613245dfd7 | 133 | MCG->C1 = (uint8_t)0x9Au; |
mbed_official | 68:41613245dfd7 | 134 | /* MCG->C4: DMX32=0,DRST_DRS=0 */ |
mbed_official | 68:41613245dfd7 | 135 | MCG->C4 &= (uint8_t)~(uint8_t)0xE0u; |
mbed_official | 68:41613245dfd7 | 136 | /* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */ |
mbed_official | 68:41613245dfd7 | 137 | MCG->C5 = (uint8_t)0x03u; |
mbed_official | 68:41613245dfd7 | 138 | /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */ |
mbed_official | 68:41613245dfd7 | 139 | MCG->C6 = (uint8_t)0x00u; |
mbed_official | 68:41613245dfd7 | 140 | while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { /* Check that the oscillator is running */ |
mbed_official | 68:41613245dfd7 | 141 | } |
mbed_official | 68:41613245dfd7 | 142 | #if 0 /* ARM: THIS CHECK IS REMOVED DUE TO BUG WITH SLOW IRC IN REV. 1.0 */ |
mbed_official | 68:41613245dfd7 | 143 | while((MCG->S & MCG_S_IREFST_MASK) != 0u) { /* Check that the source of the FLL reference clock is the external reference clock. */ |
mbed_official | 68:41613245dfd7 | 144 | } |
mbed_official | 68:41613245dfd7 | 145 | #endif |
mbed_official | 68:41613245dfd7 | 146 | while((MCG->S & 0x0Cu) != 0x08u) { /* Wait until external reference clock is selected as MCG output */ |
mbed_official | 68:41613245dfd7 | 147 | } |
mbed_official | 68:41613245dfd7 | 148 | /* Switch to PBE Mode */ |
mbed_official | 68:41613245dfd7 | 149 | /* MCG_C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */ |
mbed_official | 68:41613245dfd7 | 150 | MCG->C5 = (uint8_t)0x03u; |
mbed_official | 68:41613245dfd7 | 151 | /* MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=0 */ |
mbed_official | 68:41613245dfd7 | 152 | MCG->C6 = (uint8_t)0x40u; |
mbed_official | 68:41613245dfd7 | 153 | while((MCG->S & MCG_S_PLLST_MASK) == 0u) { /* Wait until the source of the PLLS clock has switched to the PLL */ |
mbed_official | 68:41613245dfd7 | 154 | } |
mbed_official | 68:41613245dfd7 | 155 | while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { /* Wait until locked */ |
mbed_official | 68:41613245dfd7 | 156 | } |
mbed_official | 68:41613245dfd7 | 157 | /* Switch to PEE Mode */ |
mbed_official | 68:41613245dfd7 | 158 | /* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ |
mbed_official | 68:41613245dfd7 | 159 | MCG->C1 = (uint8_t)0x1Au; |
mbed_official | 68:41613245dfd7 | 160 | while((MCG->S & 0x0Cu) != 0x0Cu) { /* Wait until output of the PLL is selected */ |
mbed_official | 68:41613245dfd7 | 161 | } |
mbed_official | 68:41613245dfd7 | 162 | while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { /* Wait until locked */ |
mbed_official | 68:41613245dfd7 | 163 | } |
mbed_official | 68:41613245dfd7 | 164 | #elif (CLOCK_SETUP == 2) |
mbed_official | 68:41613245dfd7 | 165 | /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ |
mbed_official | 68:41613245dfd7 | 166 | SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */ |
mbed_official | 68:41613245dfd7 | 167 | /* Switch to FBE Mode */ |
mbed_official | 68:41613245dfd7 | 168 | /* OSC0->CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ |
mbed_official | 68:41613245dfd7 | 169 | OSC0->CR = (uint8_t)0x00u; |
mbed_official | 68:41613245dfd7 | 170 | /* MCG->C7: OSCSEL=0 */ |
mbed_official | 68:41613245dfd7 | 171 | MCG->C7 = (uint8_t)0x00u; |
mbed_official | 68:41613245dfd7 | 172 | /* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */ |
mbed_official | 68:41613245dfd7 | 173 | MCG->C2 = (uint8_t)0x24u; |
mbed_official | 68:41613245dfd7 | 174 | /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ |
mbed_official | 68:41613245dfd7 | 175 | MCG->C1 = (uint8_t)0x9Au; |
mbed_official | 68:41613245dfd7 | 176 | /* MCG->C4: DMX32=0,DRST_DRS=0 */ |
mbed_official | 68:41613245dfd7 | 177 | MCG->C4 &= (uint8_t)~(uint8_t)0xE0u; |
mbed_official | 68:41613245dfd7 | 178 | /* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */ |
mbed_official | 68:41613245dfd7 | 179 | MCG->C5 = (uint8_t)0x00u; |
mbed_official | 68:41613245dfd7 | 180 | /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */ |
mbed_official | 68:41613245dfd7 | 181 | MCG->C6 = (uint8_t)0x00u; |
mbed_official | 68:41613245dfd7 | 182 | while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { /* Check that the oscillator is running */ |
mbed_official | 68:41613245dfd7 | 183 | } |
mbed_official | 68:41613245dfd7 | 184 | #if 0 /* ARM: THIS CHECK IS REMOVED DUE TO BUG WITH SLOW IRC IN REV. 1.0 */ |
mbed_official | 68:41613245dfd7 | 185 | while((MCG->S & MCG_S_IREFST_MASK) != 0u) { /* Check that the source of the FLL reference clock is the external reference clock. */ |
mbed_official | 68:41613245dfd7 | 186 | } |
mbed_official | 68:41613245dfd7 | 187 | #endif |
mbed_official | 68:41613245dfd7 | 188 | while((MCG->S & 0x0CU) != 0x08u) { /* Wait until external reference clock is selected as MCG output */ |
mbed_official | 68:41613245dfd7 | 189 | } |
mbed_official | 68:41613245dfd7 | 190 | /* Switch to BLPE Mode */ |
mbed_official | 68:41613245dfd7 | 191 | /* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */ |
mbed_official | 68:41613245dfd7 | 192 | MCG->C2 = (uint8_t)0x24u; |
mbed_official | 68:41613245dfd7 | 193 | #endif /* (CLOCK_SETUP == 2) */ |
mbed_official | 68:41613245dfd7 | 194 | } |
mbed_official | 68:41613245dfd7 | 195 | |
mbed_official | 68:41613245dfd7 | 196 | /* ---------------------------------------------------------------------------- |
mbed_official | 68:41613245dfd7 | 197 | -- SystemCoreClockUpdate() |
mbed_official | 68:41613245dfd7 | 198 | ---------------------------------------------------------------------------- */ |
mbed_official | 68:41613245dfd7 | 199 | |
mbed_official | 68:41613245dfd7 | 200 | void SystemCoreClockUpdate (void) { |
mbed_official | 68:41613245dfd7 | 201 | uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */ |
mbed_official | 68:41613245dfd7 | 202 | uint8_t Divider; |
mbed_official | 68:41613245dfd7 | 203 | |
mbed_official | 68:41613245dfd7 | 204 | if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) { |
mbed_official | 68:41613245dfd7 | 205 | /* Output of FLL or PLL is selected */ |
mbed_official | 68:41613245dfd7 | 206 | if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { |
mbed_official | 68:41613245dfd7 | 207 | /* FLL is selected */ |
mbed_official | 68:41613245dfd7 | 208 | if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) { |
mbed_official | 68:41613245dfd7 | 209 | /* External reference clock is selected */ |
mbed_official | 68:41613245dfd7 | 210 | if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) { |
mbed_official | 68:41613245dfd7 | 211 | MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */ |
mbed_official | 68:41613245dfd7 | 212 | } else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */ |
mbed_official | 68:41613245dfd7 | 213 | MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */ |
mbed_official | 68:41613245dfd7 | 214 | } /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */ |
mbed_official | 68:41613245dfd7 | 215 | Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); |
mbed_official | 68:41613245dfd7 | 216 | MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ |
mbed_official | 68:41613245dfd7 | 217 | if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) { |
mbed_official | 68:41613245dfd7 | 218 | MCGOUTClock /= 32u; /* If high range is enabled, additional 32 divider is active */ |
mbed_official | 68:41613245dfd7 | 219 | } /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) */ |
mbed_official | 68:41613245dfd7 | 220 | } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */ |
mbed_official | 68:41613245dfd7 | 221 | MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */ |
mbed_official | 68:41613245dfd7 | 222 | } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */ |
mbed_official | 68:41613245dfd7 | 223 | /* Select correct multiplier to calculate the MCG output clock */ |
mbed_official | 68:41613245dfd7 | 224 | switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) { |
mbed_official | 68:41613245dfd7 | 225 | case 0x0u: |
mbed_official | 68:41613245dfd7 | 226 | MCGOUTClock *= 640u; |
mbed_official | 68:41613245dfd7 | 227 | break; |
mbed_official | 68:41613245dfd7 | 228 | case 0x20u: |
mbed_official | 68:41613245dfd7 | 229 | MCGOUTClock *= 1280u; |
mbed_official | 68:41613245dfd7 | 230 | break; |
mbed_official | 68:41613245dfd7 | 231 | case 0x40u: |
mbed_official | 68:41613245dfd7 | 232 | MCGOUTClock *= 1920u; |
mbed_official | 68:41613245dfd7 | 233 | break; |
mbed_official | 68:41613245dfd7 | 234 | case 0x60u: |
mbed_official | 68:41613245dfd7 | 235 | MCGOUTClock *= 2560u; |
mbed_official | 68:41613245dfd7 | 236 | break; |
mbed_official | 68:41613245dfd7 | 237 | case 0x80u: |
mbed_official | 68:41613245dfd7 | 238 | MCGOUTClock *= 732u; |
mbed_official | 68:41613245dfd7 | 239 | break; |
mbed_official | 68:41613245dfd7 | 240 | case 0xA0u: |
mbed_official | 68:41613245dfd7 | 241 | MCGOUTClock *= 1464u; |
mbed_official | 68:41613245dfd7 | 242 | break; |
mbed_official | 68:41613245dfd7 | 243 | case 0xC0u: |
mbed_official | 68:41613245dfd7 | 244 | MCGOUTClock *= 2197u; |
mbed_official | 68:41613245dfd7 | 245 | break; |
mbed_official | 68:41613245dfd7 | 246 | case 0xE0u: |
mbed_official | 68:41613245dfd7 | 247 | MCGOUTClock *= 2929u; |
mbed_official | 68:41613245dfd7 | 248 | break; |
mbed_official | 68:41613245dfd7 | 249 | default: |
mbed_official | 68:41613245dfd7 | 250 | break; |
mbed_official | 68:41613245dfd7 | 251 | } |
mbed_official | 68:41613245dfd7 | 252 | } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */ |
mbed_official | 68:41613245dfd7 | 253 | /* PLL is selected */ |
mbed_official | 68:41613245dfd7 | 254 | Divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK)); |
mbed_official | 68:41613245dfd7 | 255 | MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */ |
mbed_official | 68:41613245dfd7 | 256 | Divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u); |
mbed_official | 68:41613245dfd7 | 257 | MCGOUTClock *= Divider; /* Calculate the MCG output clock */ |
mbed_official | 68:41613245dfd7 | 258 | } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */ |
mbed_official | 68:41613245dfd7 | 259 | } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) { |
mbed_official | 68:41613245dfd7 | 260 | /* Internal reference clock is selected */ |
mbed_official | 68:41613245dfd7 | 261 | if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) { |
mbed_official | 68:41613245dfd7 | 262 | MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */ |
mbed_official | 68:41613245dfd7 | 263 | } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */ |
mbed_official | 68:41613245dfd7 | 264 | MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */ |
mbed_official | 68:41613245dfd7 | 265 | } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */ |
mbed_official | 68:41613245dfd7 | 266 | } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) { |
mbed_official | 68:41613245dfd7 | 267 | /* External reference clock is selected */ |
mbed_official | 68:41613245dfd7 | 268 | if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) { |
mbed_official | 68:41613245dfd7 | 269 | MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */ |
mbed_official | 68:41613245dfd7 | 270 | } else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */ |
mbed_official | 68:41613245dfd7 | 271 | MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */ |
mbed_official | 68:41613245dfd7 | 272 | } /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */ |
mbed_official | 68:41613245dfd7 | 273 | } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */ |
mbed_official | 68:41613245dfd7 | 274 | /* Reserved value */ |
mbed_official | 68:41613245dfd7 | 275 | return; |
mbed_official | 68:41613245dfd7 | 276 | } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */ |
mbed_official | 68:41613245dfd7 | 277 | SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT))); |
mbed_official | 68:41613245dfd7 | 278 | } |