mbed library sources modified for open wear
Dependents: openwear-lifelogger-example
Fork of mbed-src by
targets/hal/TARGET_NXP/TARGET_LPC13XX/spi_api.c@13:0645d8841f51, 2013-08-05 (annotated)
- Committer:
- bogdanm
- Date:
- Mon Aug 05 14:12:34 2013 +0300
- Revision:
- 13:0645d8841f51
- Parent:
- vendor/NXP/LPC11U24/hal/spi_api.c@10:3bc89ef62ce7
- Child:
- 81:a9456fdf72fa
Update mbed sources to revision 64
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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emilmont | 10:3bc89ef62ce7 | 1 | /* mbed Microcontroller Library |
emilmont | 10:3bc89ef62ce7 | 2 | * Copyright (c) 2006-2013 ARM Limited |
emilmont | 10:3bc89ef62ce7 | 3 | * |
emilmont | 10:3bc89ef62ce7 | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
emilmont | 10:3bc89ef62ce7 | 5 | * you may not use this file except in compliance with the License. |
emilmont | 10:3bc89ef62ce7 | 6 | * You may obtain a copy of the License at |
emilmont | 10:3bc89ef62ce7 | 7 | * |
emilmont | 10:3bc89ef62ce7 | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
emilmont | 10:3bc89ef62ce7 | 9 | * |
emilmont | 10:3bc89ef62ce7 | 10 | * Unless required by applicable law or agreed to in writing, software |
emilmont | 10:3bc89ef62ce7 | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
emilmont | 10:3bc89ef62ce7 | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
emilmont | 10:3bc89ef62ce7 | 13 | * See the License for the specific language governing permissions and |
emilmont | 10:3bc89ef62ce7 | 14 | * limitations under the License. |
emilmont | 10:3bc89ef62ce7 | 15 | */ |
emilmont | 10:3bc89ef62ce7 | 16 | #include <math.h> |
emilmont | 10:3bc89ef62ce7 | 17 | #include "spi_api.h" |
emilmont | 10:3bc89ef62ce7 | 18 | #include "cmsis.h" |
emilmont | 10:3bc89ef62ce7 | 19 | #include "pinmap.h" |
emilmont | 10:3bc89ef62ce7 | 20 | #include "error.h" |
emilmont | 10:3bc89ef62ce7 | 21 | |
emilmont | 10:3bc89ef62ce7 | 22 | static const PinMap PinMap_SPI_SCLK[] = { |
emilmont | 10:3bc89ef62ce7 | 23 | {P0_6 , SPI_0, 0x02}, |
emilmont | 10:3bc89ef62ce7 | 24 | {P0_10, SPI_0, 0x02}, |
emilmont | 10:3bc89ef62ce7 | 25 | {P1_29, SPI_0, 0x01}, |
emilmont | 10:3bc89ef62ce7 | 26 | {P1_15, SPI_1, 0x03}, |
emilmont | 10:3bc89ef62ce7 | 27 | {P1_20, SPI_1, 0x02}, |
emilmont | 10:3bc89ef62ce7 | 28 | {NC , NC , 0} |
emilmont | 10:3bc89ef62ce7 | 29 | }; |
emilmont | 10:3bc89ef62ce7 | 30 | |
emilmont | 10:3bc89ef62ce7 | 31 | static const PinMap PinMap_SPI_MOSI[] = { |
emilmont | 10:3bc89ef62ce7 | 32 | {P0_9 , SPI_0, 0x01}, |
emilmont | 10:3bc89ef62ce7 | 33 | {P0_21, SPI_1, 0x02}, |
emilmont | 10:3bc89ef62ce7 | 34 | {P1_22, SPI_1, 0x02}, |
emilmont | 10:3bc89ef62ce7 | 35 | {NC , NC , 0} |
emilmont | 10:3bc89ef62ce7 | 36 | }; |
emilmont | 10:3bc89ef62ce7 | 37 | |
emilmont | 10:3bc89ef62ce7 | 38 | static const PinMap PinMap_SPI_MISO[] = { |
emilmont | 10:3bc89ef62ce7 | 39 | {P0_8 , SPI_0, 0x01}, |
emilmont | 10:3bc89ef62ce7 | 40 | {P0_22, SPI_1, 0x03}, |
emilmont | 10:3bc89ef62ce7 | 41 | {P1_21, SPI_1, 0x02}, |
emilmont | 10:3bc89ef62ce7 | 42 | {NC , NC , 0} |
emilmont | 10:3bc89ef62ce7 | 43 | }; |
emilmont | 10:3bc89ef62ce7 | 44 | |
emilmont | 10:3bc89ef62ce7 | 45 | static const PinMap PinMap_SPI_SSEL[] = { |
emilmont | 10:3bc89ef62ce7 | 46 | {P0_2 , SPI_0, 0x01}, |
emilmont | 10:3bc89ef62ce7 | 47 | {P1_19, SPI_1, 0x02}, |
emilmont | 10:3bc89ef62ce7 | 48 | {P1_23, SPI_1, 0x02}, |
emilmont | 10:3bc89ef62ce7 | 49 | {NC , NC , 0} |
emilmont | 10:3bc89ef62ce7 | 50 | }; |
emilmont | 10:3bc89ef62ce7 | 51 | |
emilmont | 10:3bc89ef62ce7 | 52 | static inline int ssp_disable(spi_t *obj); |
emilmont | 10:3bc89ef62ce7 | 53 | static inline int ssp_enable(spi_t *obj); |
emilmont | 10:3bc89ef62ce7 | 54 | |
emilmont | 10:3bc89ef62ce7 | 55 | void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) { |
emilmont | 10:3bc89ef62ce7 | 56 | // determine the SPI to use |
emilmont | 10:3bc89ef62ce7 | 57 | SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); |
emilmont | 10:3bc89ef62ce7 | 58 | SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); |
emilmont | 10:3bc89ef62ce7 | 59 | SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); |
emilmont | 10:3bc89ef62ce7 | 60 | SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); |
emilmont | 10:3bc89ef62ce7 | 61 | SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); |
emilmont | 10:3bc89ef62ce7 | 62 | SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); |
emilmont | 10:3bc89ef62ce7 | 63 | |
emilmont | 10:3bc89ef62ce7 | 64 | obj->spi = (LPC_SSPx_Type*)pinmap_merge(spi_data, spi_cntl); |
emilmont | 10:3bc89ef62ce7 | 65 | |
emilmont | 10:3bc89ef62ce7 | 66 | if ((int)obj->spi == NC) { |
emilmont | 10:3bc89ef62ce7 | 67 | error("SPI pinout mapping failed"); |
emilmont | 10:3bc89ef62ce7 | 68 | } |
emilmont | 10:3bc89ef62ce7 | 69 | |
emilmont | 10:3bc89ef62ce7 | 70 | // enable power and clocking |
emilmont | 10:3bc89ef62ce7 | 71 | switch ((int)obj->spi) { |
emilmont | 10:3bc89ef62ce7 | 72 | case SPI_0: |
emilmont | 10:3bc89ef62ce7 | 73 | LPC_SYSCON->SYSAHBCLKCTRL |= 1 << 11; |
emilmont | 10:3bc89ef62ce7 | 74 | LPC_SYSCON->SSP0CLKDIV = 0x01; |
emilmont | 10:3bc89ef62ce7 | 75 | LPC_SYSCON->PRESETCTRL |= 1 << 0; |
emilmont | 10:3bc89ef62ce7 | 76 | break; |
emilmont | 10:3bc89ef62ce7 | 77 | case SPI_1: |
emilmont | 10:3bc89ef62ce7 | 78 | LPC_SYSCON->SYSAHBCLKCTRL |= 1 << 18; |
emilmont | 10:3bc89ef62ce7 | 79 | LPC_SYSCON->SSP1CLKDIV = 0x01; |
emilmont | 10:3bc89ef62ce7 | 80 | LPC_SYSCON->PRESETCTRL |= 1 << 2; |
emilmont | 10:3bc89ef62ce7 | 81 | break; |
emilmont | 10:3bc89ef62ce7 | 82 | } |
emilmont | 10:3bc89ef62ce7 | 83 | |
emilmont | 10:3bc89ef62ce7 | 84 | // set default format and frequency |
emilmont | 10:3bc89ef62ce7 | 85 | if (ssel == NC) { |
emilmont | 10:3bc89ef62ce7 | 86 | spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master |
emilmont | 10:3bc89ef62ce7 | 87 | } else { |
emilmont | 10:3bc89ef62ce7 | 88 | spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave |
emilmont | 10:3bc89ef62ce7 | 89 | } |
emilmont | 10:3bc89ef62ce7 | 90 | spi_frequency(obj, 1000000); |
emilmont | 10:3bc89ef62ce7 | 91 | |
emilmont | 10:3bc89ef62ce7 | 92 | // enable the ssp channel |
emilmont | 10:3bc89ef62ce7 | 93 | ssp_enable(obj); |
emilmont | 10:3bc89ef62ce7 | 94 | |
emilmont | 10:3bc89ef62ce7 | 95 | // pin out the spi pins |
emilmont | 10:3bc89ef62ce7 | 96 | pinmap_pinout(mosi, PinMap_SPI_MOSI); |
emilmont | 10:3bc89ef62ce7 | 97 | pinmap_pinout(miso, PinMap_SPI_MISO); |
emilmont | 10:3bc89ef62ce7 | 98 | pinmap_pinout(sclk, PinMap_SPI_SCLK); |
emilmont | 10:3bc89ef62ce7 | 99 | if (ssel != NC) { |
emilmont | 10:3bc89ef62ce7 | 100 | pinmap_pinout(ssel, PinMap_SPI_SSEL); |
emilmont | 10:3bc89ef62ce7 | 101 | } |
emilmont | 10:3bc89ef62ce7 | 102 | } |
emilmont | 10:3bc89ef62ce7 | 103 | |
emilmont | 10:3bc89ef62ce7 | 104 | void spi_free(spi_t *obj) {} |
emilmont | 10:3bc89ef62ce7 | 105 | |
emilmont | 10:3bc89ef62ce7 | 106 | void spi_format(spi_t *obj, int bits, int mode, int slave) { |
emilmont | 10:3bc89ef62ce7 | 107 | ssp_disable(obj); |
emilmont | 10:3bc89ef62ce7 | 108 | |
emilmont | 10:3bc89ef62ce7 | 109 | if (!(bits >= 4 && bits <= 16) || !(mode >= 0 && mode <= 3)) { |
emilmont | 10:3bc89ef62ce7 | 110 | error("SPI format error"); |
emilmont | 10:3bc89ef62ce7 | 111 | } |
emilmont | 10:3bc89ef62ce7 | 112 | |
emilmont | 10:3bc89ef62ce7 | 113 | int polarity = (mode & 0x2) ? 1 : 0; |
emilmont | 10:3bc89ef62ce7 | 114 | int phase = (mode & 0x1) ? 1 : 0; |
emilmont | 10:3bc89ef62ce7 | 115 | |
emilmont | 10:3bc89ef62ce7 | 116 | // set it up |
emilmont | 10:3bc89ef62ce7 | 117 | int DSS = bits - 1; // DSS (data select size) |
emilmont | 10:3bc89ef62ce7 | 118 | int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity |
emilmont | 10:3bc89ef62ce7 | 119 | int SPH = (phase) ? 1 : 0; // SPH - clock out phase |
emilmont | 10:3bc89ef62ce7 | 120 | |
emilmont | 10:3bc89ef62ce7 | 121 | int FRF = 0; // FRF (frame format) = SPI |
emilmont | 10:3bc89ef62ce7 | 122 | uint32_t tmp = obj->spi->CR0; |
emilmont | 10:3bc89ef62ce7 | 123 | tmp &= ~(0xFFFF); |
emilmont | 10:3bc89ef62ce7 | 124 | tmp |= DSS << 0 |
emilmont | 10:3bc89ef62ce7 | 125 | | FRF << 4 |
emilmont | 10:3bc89ef62ce7 | 126 | | SPO << 6 |
emilmont | 10:3bc89ef62ce7 | 127 | | SPH << 7; |
emilmont | 10:3bc89ef62ce7 | 128 | obj->spi->CR0 = tmp; |
emilmont | 10:3bc89ef62ce7 | 129 | |
emilmont | 10:3bc89ef62ce7 | 130 | tmp = obj->spi->CR1; |
emilmont | 10:3bc89ef62ce7 | 131 | tmp &= ~(0xD); |
emilmont | 10:3bc89ef62ce7 | 132 | tmp |= 0 << 0 // LBM - loop back mode - off |
emilmont | 10:3bc89ef62ce7 | 133 | | ((slave) ? 1 : 0) << 2 // MS - master slave mode, 1 = slave |
emilmont | 10:3bc89ef62ce7 | 134 | | 0 << 3; // SOD - slave output disable - na |
emilmont | 10:3bc89ef62ce7 | 135 | obj->spi->CR1 = tmp; |
emilmont | 10:3bc89ef62ce7 | 136 | |
emilmont | 10:3bc89ef62ce7 | 137 | ssp_enable(obj); |
emilmont | 10:3bc89ef62ce7 | 138 | } |
emilmont | 10:3bc89ef62ce7 | 139 | |
emilmont | 10:3bc89ef62ce7 | 140 | void spi_frequency(spi_t *obj, int hz) { |
emilmont | 10:3bc89ef62ce7 | 141 | ssp_disable(obj); |
emilmont | 10:3bc89ef62ce7 | 142 | |
emilmont | 10:3bc89ef62ce7 | 143 | uint32_t PCLK = SystemCoreClock; |
emilmont | 10:3bc89ef62ce7 | 144 | |
emilmont | 10:3bc89ef62ce7 | 145 | int prescaler; |
emilmont | 10:3bc89ef62ce7 | 146 | |
emilmont | 10:3bc89ef62ce7 | 147 | for (prescaler = 2; prescaler <= 254; prescaler += 2) { |
emilmont | 10:3bc89ef62ce7 | 148 | int prescale_hz = PCLK / prescaler; |
emilmont | 10:3bc89ef62ce7 | 149 | |
emilmont | 10:3bc89ef62ce7 | 150 | // calculate the divider |
emilmont | 10:3bc89ef62ce7 | 151 | int divider = floor(((float)prescale_hz / (float)hz) + 0.5f); |
emilmont | 10:3bc89ef62ce7 | 152 | |
emilmont | 10:3bc89ef62ce7 | 153 | // check we can support the divider |
emilmont | 10:3bc89ef62ce7 | 154 | if (divider < 256) { |
emilmont | 10:3bc89ef62ce7 | 155 | // prescaler |
emilmont | 10:3bc89ef62ce7 | 156 | obj->spi->CPSR = prescaler; |
emilmont | 10:3bc89ef62ce7 | 157 | |
emilmont | 10:3bc89ef62ce7 | 158 | // divider |
emilmont | 10:3bc89ef62ce7 | 159 | obj->spi->CR0 &= ~(0xFFFF << 8); |
emilmont | 10:3bc89ef62ce7 | 160 | obj->spi->CR0 |= (divider - 1) << 8; |
emilmont | 10:3bc89ef62ce7 | 161 | ssp_enable(obj); |
emilmont | 10:3bc89ef62ce7 | 162 | return; |
emilmont | 10:3bc89ef62ce7 | 163 | } |
emilmont | 10:3bc89ef62ce7 | 164 | } |
emilmont | 10:3bc89ef62ce7 | 165 | error("Couldn't setup requested SPI frequency"); |
emilmont | 10:3bc89ef62ce7 | 166 | } |
emilmont | 10:3bc89ef62ce7 | 167 | |
emilmont | 10:3bc89ef62ce7 | 168 | static inline int ssp_disable(spi_t *obj) { |
emilmont | 10:3bc89ef62ce7 | 169 | return obj->spi->CR1 &= ~(1 << 1); |
emilmont | 10:3bc89ef62ce7 | 170 | } |
emilmont | 10:3bc89ef62ce7 | 171 | |
emilmont | 10:3bc89ef62ce7 | 172 | static inline int ssp_enable(spi_t *obj) { |
emilmont | 10:3bc89ef62ce7 | 173 | return obj->spi->CR1 |= (1 << 1); |
emilmont | 10:3bc89ef62ce7 | 174 | } |
emilmont | 10:3bc89ef62ce7 | 175 | |
emilmont | 10:3bc89ef62ce7 | 176 | static inline int ssp_readable(spi_t *obj) { |
emilmont | 10:3bc89ef62ce7 | 177 | return obj->spi->SR & (1 << 2); |
emilmont | 10:3bc89ef62ce7 | 178 | } |
emilmont | 10:3bc89ef62ce7 | 179 | |
emilmont | 10:3bc89ef62ce7 | 180 | static inline int ssp_writeable(spi_t *obj) { |
emilmont | 10:3bc89ef62ce7 | 181 | return obj->spi->SR & (1 << 1); |
emilmont | 10:3bc89ef62ce7 | 182 | } |
emilmont | 10:3bc89ef62ce7 | 183 | |
emilmont | 10:3bc89ef62ce7 | 184 | static inline void ssp_write(spi_t *obj, int value) { |
emilmont | 10:3bc89ef62ce7 | 185 | while (!ssp_writeable(obj)); |
emilmont | 10:3bc89ef62ce7 | 186 | obj->spi->DR = value; |
emilmont | 10:3bc89ef62ce7 | 187 | } |
emilmont | 10:3bc89ef62ce7 | 188 | |
emilmont | 10:3bc89ef62ce7 | 189 | static inline int ssp_read(spi_t *obj) { |
emilmont | 10:3bc89ef62ce7 | 190 | while (!ssp_readable(obj)); |
emilmont | 10:3bc89ef62ce7 | 191 | return obj->spi->DR; |
emilmont | 10:3bc89ef62ce7 | 192 | } |
emilmont | 10:3bc89ef62ce7 | 193 | |
emilmont | 10:3bc89ef62ce7 | 194 | static inline int ssp_busy(spi_t *obj) { |
emilmont | 10:3bc89ef62ce7 | 195 | return (obj->spi->SR & (1 << 4)) ? (1) : (0); |
emilmont | 10:3bc89ef62ce7 | 196 | } |
emilmont | 10:3bc89ef62ce7 | 197 | |
emilmont | 10:3bc89ef62ce7 | 198 | int spi_master_write(spi_t *obj, int value) { |
emilmont | 10:3bc89ef62ce7 | 199 | ssp_write(obj, value); |
emilmont | 10:3bc89ef62ce7 | 200 | return ssp_read(obj); |
emilmont | 10:3bc89ef62ce7 | 201 | } |
emilmont | 10:3bc89ef62ce7 | 202 | |
emilmont | 10:3bc89ef62ce7 | 203 | int spi_slave_receive(spi_t *obj) { |
emilmont | 10:3bc89ef62ce7 | 204 | return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0); |
emilmont | 10:3bc89ef62ce7 | 205 | }; |
emilmont | 10:3bc89ef62ce7 | 206 | |
emilmont | 10:3bc89ef62ce7 | 207 | int spi_slave_read(spi_t *obj) { |
emilmont | 10:3bc89ef62ce7 | 208 | return obj->spi->DR; |
emilmont | 10:3bc89ef62ce7 | 209 | } |
emilmont | 10:3bc89ef62ce7 | 210 | |
emilmont | 10:3bc89ef62ce7 | 211 | void spi_slave_write(spi_t *obj, int value) { |
emilmont | 10:3bc89ef62ce7 | 212 | while (ssp_writeable(obj) == 0) ; |
emilmont | 10:3bc89ef62ce7 | 213 | obj->spi->DR = value; |
emilmont | 10:3bc89ef62ce7 | 214 | } |
emilmont | 10:3bc89ef62ce7 | 215 | |
emilmont | 10:3bc89ef62ce7 | 216 | int spi_busy(spi_t *obj) { |
emilmont | 10:3bc89ef62ce7 | 217 | return ssp_busy(obj); |
emilmont | 10:3bc89ef62ce7 | 218 | } |