mbed library sources modified for open wear
Dependents: openwear-lifelogger-example
Fork of mbed-src by
targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/system_stm32l1xx.c@129:0182c99221bc, 2014-03-20 (annotated)
- Committer:
- mbed_official
- Date:
- Thu Mar 20 11:45:07 2014 +0000
- Revision:
- 129:0182c99221bc
- Parent:
- 106:ced8cbb51063
- Child:
- 139:e3413eddde57
Synchronized with git revision 93e44fb5a5aa010177943aaaec0126ed8b8e014d
Full URL: https://github.com/mbedmicro/mbed/commit/93e44fb5a5aa010177943aaaec0126ed8b8e014d/
[NUCLEO_F302R8] and [NUCLEO_L152RE] updates
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
mbed_official | 76:aeb1df146756 | 1 | /** |
mbed_official | 76:aeb1df146756 | 2 | ****************************************************************************** |
mbed_official | 76:aeb1df146756 | 3 | * @file system_stm32l1xx.c |
mbed_official | 76:aeb1df146756 | 4 | * @author MCD Application Team |
mbed_official | 76:aeb1df146756 | 5 | * @version V1.2.0 |
mbed_official | 129:0182c99221bc | 6 | * @date 14-March-2014 |
mbed_official | 76:aeb1df146756 | 7 | * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. |
mbed_official | 76:aeb1df146756 | 8 | * This file contains the system clock configuration for STM32L1xx Ultra |
mbed_official | 76:aeb1df146756 | 9 | * Low power devices, and is generated by the clock configuration |
mbed_official | 76:aeb1df146756 | 10 | * tool STM32L1xx_Clock_Configuration_V1.2.0.xls |
mbed_official | 76:aeb1df146756 | 11 | * |
mbed_official | 76:aeb1df146756 | 12 | * 1. This file provides two functions and one global variable to be called from |
mbed_official | 76:aeb1df146756 | 13 | * user application: |
mbed_official | 76:aeb1df146756 | 14 | * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier |
mbed_official | 76:aeb1df146756 | 15 | * and Divider factors, AHB/APBx prescalers and Flash settings), |
mbed_official | 76:aeb1df146756 | 16 | * depending on the configuration made in the clock xls tool. |
mbed_official | 76:aeb1df146756 | 17 | * This function is called at startup just after reset and |
mbed_official | 76:aeb1df146756 | 18 | * before branch to main program. This call is made inside |
mbed_official | 76:aeb1df146756 | 19 | * the "startup_stm32l1xx_xx.s" file. |
mbed_official | 76:aeb1df146756 | 20 | * |
mbed_official | 76:aeb1df146756 | 21 | * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used |
mbed_official | 76:aeb1df146756 | 22 | * by the user application to setup the SysTick |
mbed_official | 76:aeb1df146756 | 23 | * timer or configure other parameters. |
mbed_official | 76:aeb1df146756 | 24 | * |
mbed_official | 76:aeb1df146756 | 25 | * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must |
mbed_official | 76:aeb1df146756 | 26 | * be called whenever the core clock is changed |
mbed_official | 76:aeb1df146756 | 27 | * during program execution. |
mbed_official | 76:aeb1df146756 | 28 | * |
mbed_official | 76:aeb1df146756 | 29 | * 2. After each device reset the MSI (2.1 MHz Range) is used as system clock source. |
mbed_official | 76:aeb1df146756 | 30 | * Then SystemInit() function is called, in "startup_stm32l1xx_xx.s" file, to |
mbed_official | 76:aeb1df146756 | 31 | * configure the system clock before to branch to main program. |
mbed_official | 76:aeb1df146756 | 32 | * |
mbed_official | 76:aeb1df146756 | 33 | * 3. If the system clock source selected by user fails to startup, the SystemInit() |
mbed_official | 76:aeb1df146756 | 34 | * function will do nothing and MSI still used as system clock source. User can |
mbed_official | 76:aeb1df146756 | 35 | * add some code to deal with this issue inside the SetSysClock() function. |
mbed_official | 76:aeb1df146756 | 36 | * |
mbed_official | 76:aeb1df146756 | 37 | * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define |
mbed_official | 76:aeb1df146756 | 38 | * in "stm32l1xx.h" file. When HSE is used as system clock source, directly or |
mbed_official | 76:aeb1df146756 | 39 | * through PLL, and you are using different crystal you have to adapt the HSE |
mbed_official | 76:aeb1df146756 | 40 | * value to your own configuration. |
mbed_official | 76:aeb1df146756 | 41 | * |
mbed_official | 76:aeb1df146756 | 42 | * 5. This file configures the system clock as follows: |
mbed_official | 76:aeb1df146756 | 43 | *============================================================================= |
mbed_official | 76:aeb1df146756 | 44 | * System Clock Configuration |
mbed_official | 76:aeb1df146756 | 45 | *============================================================================= |
mbed_official | 129:0182c99221bc | 46 | * System Clock source | PLL(HSI) |
mbed_official | 76:aeb1df146756 | 47 | *----------------------------------------------------------------------------- |
mbed_official | 129:0182c99221bc | 48 | * SYSCLK | 32000000 Hz |
mbed_official | 76:aeb1df146756 | 49 | *----------------------------------------------------------------------------- |
mbed_official | 129:0182c99221bc | 50 | * HCLK | 32000000 Hz |
mbed_official | 76:aeb1df146756 | 51 | *----------------------------------------------------------------------------- |
mbed_official | 76:aeb1df146756 | 52 | * AHB Prescaler | 1 |
mbed_official | 76:aeb1df146756 | 53 | *----------------------------------------------------------------------------- |
mbed_official | 76:aeb1df146756 | 54 | * APB1 Prescaler | 1 |
mbed_official | 76:aeb1df146756 | 55 | *----------------------------------------------------------------------------- |
mbed_official | 76:aeb1df146756 | 56 | * APB2 Prescaler | 1 |
mbed_official | 76:aeb1df146756 | 57 | *----------------------------------------------------------------------------- |
mbed_official | 129:0182c99221bc | 58 | * HSE Frequency | Not used |
mbed_official | 76:aeb1df146756 | 59 | *----------------------------------------------------------------------------- |
mbed_official | 129:0182c99221bc | 60 | * PLL DIV | 2 |
mbed_official | 76:aeb1df146756 | 61 | *----------------------------------------------------------------------------- |
mbed_official | 129:0182c99221bc | 62 | * PLL MUL | 4 |
mbed_official | 76:aeb1df146756 | 63 | *----------------------------------------------------------------------------- |
mbed_official | 76:aeb1df146756 | 64 | * VDD | 3.3 V |
mbed_official | 76:aeb1df146756 | 65 | *----------------------------------------------------------------------------- |
mbed_official | 76:aeb1df146756 | 66 | * Vcore | 1.8 V (Range 1) |
mbed_official | 76:aeb1df146756 | 67 | *----------------------------------------------------------------------------- |
mbed_official | 129:0182c99221bc | 68 | * Flash Latency | 1 WS |
mbed_official | 76:aeb1df146756 | 69 | *----------------------------------------------------------------------------- |
mbed_official | 76:aeb1df146756 | 70 | * Require 48MHz for USB clock | Disabled |
mbed_official | 76:aeb1df146756 | 71 | *----------------------------------------------------------------------------- |
mbed_official | 76:aeb1df146756 | 72 | *============================================================================= |
mbed_official | 76:aeb1df146756 | 73 | * @attention |
mbed_official | 76:aeb1df146756 | 74 | * |
mbed_official | 106:ced8cbb51063 | 75 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
mbed_official | 76:aeb1df146756 | 76 | * |
mbed_official | 106:ced8cbb51063 | 77 | * Redistribution and use in source and binary forms, with or without modification, |
mbed_official | 106:ced8cbb51063 | 78 | * are permitted provided that the following conditions are met: |
mbed_official | 106:ced8cbb51063 | 79 | * 1. Redistributions of source code must retain the above copyright notice, |
mbed_official | 106:ced8cbb51063 | 80 | * this list of conditions and the following disclaimer. |
mbed_official | 106:ced8cbb51063 | 81 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
mbed_official | 106:ced8cbb51063 | 82 | * this list of conditions and the following disclaimer in the documentation |
mbed_official | 106:ced8cbb51063 | 83 | * and/or other materials provided with the distribution. |
mbed_official | 106:ced8cbb51063 | 84 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
mbed_official | 106:ced8cbb51063 | 85 | * may be used to endorse or promote products derived from this software |
mbed_official | 106:ced8cbb51063 | 86 | * without specific prior written permission. |
mbed_official | 76:aeb1df146756 | 87 | * |
mbed_official | 106:ced8cbb51063 | 88 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
mbed_official | 106:ced8cbb51063 | 89 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
mbed_official | 106:ced8cbb51063 | 90 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
mbed_official | 106:ced8cbb51063 | 91 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
mbed_official | 106:ced8cbb51063 | 92 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
mbed_official | 106:ced8cbb51063 | 93 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
mbed_official | 106:ced8cbb51063 | 94 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
mbed_official | 106:ced8cbb51063 | 95 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
mbed_official | 106:ced8cbb51063 | 96 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
mbed_official | 106:ced8cbb51063 | 97 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
mbed_official | 76:aeb1df146756 | 98 | * |
mbed_official | 76:aeb1df146756 | 99 | ****************************************************************************** |
mbed_official | 76:aeb1df146756 | 100 | */ |
mbed_official | 76:aeb1df146756 | 101 | |
mbed_official | 76:aeb1df146756 | 102 | /** @addtogroup CMSIS |
mbed_official | 76:aeb1df146756 | 103 | * @{ |
mbed_official | 76:aeb1df146756 | 104 | */ |
mbed_official | 76:aeb1df146756 | 105 | |
mbed_official | 76:aeb1df146756 | 106 | /** @addtogroup stm32l1xx_system |
mbed_official | 76:aeb1df146756 | 107 | * @{ |
mbed_official | 76:aeb1df146756 | 108 | */ |
mbed_official | 76:aeb1df146756 | 109 | |
mbed_official | 76:aeb1df146756 | 110 | /** @addtogroup STM32L1xx_System_Private_Includes |
mbed_official | 76:aeb1df146756 | 111 | * @{ |
mbed_official | 76:aeb1df146756 | 112 | */ |
mbed_official | 76:aeb1df146756 | 113 | |
mbed_official | 76:aeb1df146756 | 114 | #include "stm32l1xx.h" |
mbed_official | 76:aeb1df146756 | 115 | |
mbed_official | 76:aeb1df146756 | 116 | /** |
mbed_official | 76:aeb1df146756 | 117 | * @} |
mbed_official | 76:aeb1df146756 | 118 | */ |
mbed_official | 76:aeb1df146756 | 119 | |
mbed_official | 76:aeb1df146756 | 120 | /** @addtogroup STM32L1xx_System_Private_TypesDefinitions |
mbed_official | 76:aeb1df146756 | 121 | * @{ |
mbed_official | 76:aeb1df146756 | 122 | */ |
mbed_official | 76:aeb1df146756 | 123 | |
mbed_official | 76:aeb1df146756 | 124 | /** |
mbed_official | 76:aeb1df146756 | 125 | * @} |
mbed_official | 76:aeb1df146756 | 126 | */ |
mbed_official | 76:aeb1df146756 | 127 | |
mbed_official | 76:aeb1df146756 | 128 | /** @addtogroup STM32L1xx_System_Private_Defines |
mbed_official | 76:aeb1df146756 | 129 | * @{ |
mbed_official | 76:aeb1df146756 | 130 | */ |
mbed_official | 76:aeb1df146756 | 131 | |
mbed_official | 76:aeb1df146756 | 132 | /*!< Uncomment the following line if you need to relocate your vector Table in |
mbed_official | 76:aeb1df146756 | 133 | Internal SRAM. */ |
mbed_official | 76:aeb1df146756 | 134 | /* #define VECT_TAB_SRAM */ |
mbed_official | 76:aeb1df146756 | 135 | #define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. |
mbed_official | 76:aeb1df146756 | 136 | This value must be a multiple of 0x200. */ |
mbed_official | 76:aeb1df146756 | 137 | /** |
mbed_official | 76:aeb1df146756 | 138 | * @} |
mbed_official | 76:aeb1df146756 | 139 | */ |
mbed_official | 76:aeb1df146756 | 140 | |
mbed_official | 76:aeb1df146756 | 141 | /** @addtogroup STM32L1xx_System_Private_Macros |
mbed_official | 76:aeb1df146756 | 142 | * @{ |
mbed_official | 76:aeb1df146756 | 143 | */ |
mbed_official | 76:aeb1df146756 | 144 | |
mbed_official | 76:aeb1df146756 | 145 | /** |
mbed_official | 76:aeb1df146756 | 146 | * @} |
mbed_official | 76:aeb1df146756 | 147 | */ |
mbed_official | 76:aeb1df146756 | 148 | |
mbed_official | 76:aeb1df146756 | 149 | /** @addtogroup STM32L1xx_System_Private_Variables |
mbed_official | 76:aeb1df146756 | 150 | * @{ |
mbed_official | 76:aeb1df146756 | 151 | */ |
mbed_official | 129:0182c99221bc | 152 | uint32_t SystemCoreClock = 32000000; |
mbed_official | 76:aeb1df146756 | 153 | __I uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48}; |
mbed_official | 76:aeb1df146756 | 154 | __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; |
mbed_official | 76:aeb1df146756 | 155 | |
mbed_official | 76:aeb1df146756 | 156 | /** |
mbed_official | 76:aeb1df146756 | 157 | * @} |
mbed_official | 76:aeb1df146756 | 158 | */ |
mbed_official | 76:aeb1df146756 | 159 | |
mbed_official | 76:aeb1df146756 | 160 | /** @addtogroup STM32L1xx_System_Private_FunctionPrototypes |
mbed_official | 76:aeb1df146756 | 161 | * @{ |
mbed_official | 76:aeb1df146756 | 162 | */ |
mbed_official | 76:aeb1df146756 | 163 | |
mbed_official | 129:0182c99221bc | 164 | void SetSysClock(void); |
mbed_official | 76:aeb1df146756 | 165 | |
mbed_official | 76:aeb1df146756 | 166 | /** |
mbed_official | 76:aeb1df146756 | 167 | * @} |
mbed_official | 76:aeb1df146756 | 168 | */ |
mbed_official | 76:aeb1df146756 | 169 | |
mbed_official | 76:aeb1df146756 | 170 | /** @addtogroup STM32L1xx_System_Private_Functions |
mbed_official | 76:aeb1df146756 | 171 | * @{ |
mbed_official | 76:aeb1df146756 | 172 | */ |
mbed_official | 76:aeb1df146756 | 173 | |
mbed_official | 76:aeb1df146756 | 174 | /** |
mbed_official | 76:aeb1df146756 | 175 | * @brief Setup the microcontroller system. |
mbed_official | 76:aeb1df146756 | 176 | * Initialize the Embedded Flash Interface, the PLL and update the |
mbed_official | 76:aeb1df146756 | 177 | * SystemCoreClock variable. |
mbed_official | 76:aeb1df146756 | 178 | * @param None |
mbed_official | 76:aeb1df146756 | 179 | * @retval None |
mbed_official | 76:aeb1df146756 | 180 | */ |
mbed_official | 76:aeb1df146756 | 181 | void SystemInit (void) |
mbed_official | 76:aeb1df146756 | 182 | { |
mbed_official | 76:aeb1df146756 | 183 | /*!< Set MSION bit */ |
mbed_official | 76:aeb1df146756 | 184 | RCC->CR |= (uint32_t)0x00000100; |
mbed_official | 76:aeb1df146756 | 185 | |
mbed_official | 76:aeb1df146756 | 186 | /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */ |
mbed_official | 76:aeb1df146756 | 187 | RCC->CFGR &= (uint32_t)0x88FFC00C; |
mbed_official | 76:aeb1df146756 | 188 | |
mbed_official | 76:aeb1df146756 | 189 | /*!< Reset HSION, HSEON, CSSON and PLLON bits */ |
mbed_official | 76:aeb1df146756 | 190 | RCC->CR &= (uint32_t)0xEEFEFFFE; |
mbed_official | 76:aeb1df146756 | 191 | |
mbed_official | 76:aeb1df146756 | 192 | /*!< Reset HSEBYP bit */ |
mbed_official | 76:aeb1df146756 | 193 | RCC->CR &= (uint32_t)0xFFFBFFFF; |
mbed_official | 76:aeb1df146756 | 194 | |
mbed_official | 76:aeb1df146756 | 195 | /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */ |
mbed_official | 76:aeb1df146756 | 196 | RCC->CFGR &= (uint32_t)0xFF02FFFF; |
mbed_official | 76:aeb1df146756 | 197 | |
mbed_official | 76:aeb1df146756 | 198 | /*!< Disable all interrupts */ |
mbed_official | 76:aeb1df146756 | 199 | RCC->CIR = 0x00000000; |
mbed_official | 76:aeb1df146756 | 200 | |
mbed_official | 76:aeb1df146756 | 201 | /* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */ |
mbed_official | 76:aeb1df146756 | 202 | SetSysClock(); |
mbed_official | 76:aeb1df146756 | 203 | |
mbed_official | 76:aeb1df146756 | 204 | #ifdef VECT_TAB_SRAM |
mbed_official | 76:aeb1df146756 | 205 | SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ |
mbed_official | 76:aeb1df146756 | 206 | #else |
mbed_official | 76:aeb1df146756 | 207 | SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ |
mbed_official | 76:aeb1df146756 | 208 | #endif |
mbed_official | 129:0182c99221bc | 209 | |
mbed_official | 129:0182c99221bc | 210 | /* ADDED FOR MBED DEBUG PURPOSE */ |
mbed_official | 129:0182c99221bc | 211 | /* |
mbed_official | 129:0182c99221bc | 212 | // Enable the GPIOA peripheral |
mbed_official | 129:0182c99221bc | 213 | RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE); |
mbed_official | 129:0182c99221bc | 214 | // Output the system clock on MCO pin (PA.08) |
mbed_official | 129:0182c99221bc | 215 | GPIO_InitTypeDef GPIO_InitStructure; |
mbed_official | 129:0182c99221bc | 216 | GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8; |
mbed_official | 129:0182c99221bc | 217 | GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz; |
mbed_official | 129:0182c99221bc | 218 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; |
mbed_official | 129:0182c99221bc | 219 | GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; |
mbed_official | 129:0182c99221bc | 220 | GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; |
mbed_official | 129:0182c99221bc | 221 | GPIO_Init(GPIOA, &GPIO_InitStructure); |
mbed_official | 129:0182c99221bc | 222 | // Select the clock to output on MCO pin (PA.08) |
mbed_official | 129:0182c99221bc | 223 | RCC_MCOConfig(RCC_MCOSource_SYSCLK, RCC_MCODiv_1); |
mbed_official | 129:0182c99221bc | 224 | //RCC_MCOConfig(RCC_MCOSource_HSI, RCC_MCODiv_1); |
mbed_official | 129:0182c99221bc | 225 | */ |
mbed_official | 76:aeb1df146756 | 226 | } |
mbed_official | 76:aeb1df146756 | 227 | |
mbed_official | 76:aeb1df146756 | 228 | /** |
mbed_official | 76:aeb1df146756 | 229 | * @brief Update SystemCoreClock according to Clock Register Values |
mbed_official | 76:aeb1df146756 | 230 | * The SystemCoreClock variable contains the core clock (HCLK), it can |
mbed_official | 76:aeb1df146756 | 231 | * be used by the user application to setup the SysTick timer or configure |
mbed_official | 76:aeb1df146756 | 232 | * other parameters. |
mbed_official | 76:aeb1df146756 | 233 | * |
mbed_official | 76:aeb1df146756 | 234 | * @note Each time the core clock (HCLK) changes, this function must be called |
mbed_official | 76:aeb1df146756 | 235 | * to update SystemCoreClock variable value. Otherwise, any configuration |
mbed_official | 76:aeb1df146756 | 236 | * based on this variable will be incorrect. |
mbed_official | 76:aeb1df146756 | 237 | * |
mbed_official | 76:aeb1df146756 | 238 | * @note - The system frequency computed by this function is not the real |
mbed_official | 76:aeb1df146756 | 239 | * frequency in the chip. It is calculated based on the predefined |
mbed_official | 76:aeb1df146756 | 240 | * constant and the selected clock source: |
mbed_official | 76:aeb1df146756 | 241 | * |
mbed_official | 76:aeb1df146756 | 242 | * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI |
mbed_official | 76:aeb1df146756 | 243 | * value as defined by the MSI range. |
mbed_official | 76:aeb1df146756 | 244 | * |
mbed_official | 76:aeb1df146756 | 245 | * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) |
mbed_official | 76:aeb1df146756 | 246 | * |
mbed_official | 76:aeb1df146756 | 247 | * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) |
mbed_official | 76:aeb1df146756 | 248 | * |
mbed_official | 76:aeb1df146756 | 249 | * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) |
mbed_official | 76:aeb1df146756 | 250 | * or HSI_VALUE(*) multiplied/divided by the PLL factors. |
mbed_official | 76:aeb1df146756 | 251 | * |
mbed_official | 76:aeb1df146756 | 252 | * (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value |
mbed_official | 76:aeb1df146756 | 253 | * 16 MHz) but the real value may vary depending on the variations |
mbed_official | 76:aeb1df146756 | 254 | * in voltage and temperature. |
mbed_official | 76:aeb1df146756 | 255 | * |
mbed_official | 76:aeb1df146756 | 256 | * (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value |
mbed_official | 76:aeb1df146756 | 257 | * 8 MHz), user has to ensure that HSE_VALUE is same as the real |
mbed_official | 76:aeb1df146756 | 258 | * frequency of the crystal used. Otherwise, this function may |
mbed_official | 76:aeb1df146756 | 259 | * have wrong result. |
mbed_official | 76:aeb1df146756 | 260 | * |
mbed_official | 76:aeb1df146756 | 261 | * - The result of this function could be not correct when using fractional |
mbed_official | 76:aeb1df146756 | 262 | * value for HSE crystal. |
mbed_official | 76:aeb1df146756 | 263 | * @param None |
mbed_official | 76:aeb1df146756 | 264 | * @retval None |
mbed_official | 76:aeb1df146756 | 265 | */ |
mbed_official | 76:aeb1df146756 | 266 | void SystemCoreClockUpdate (void) |
mbed_official | 76:aeb1df146756 | 267 | { |
mbed_official | 76:aeb1df146756 | 268 | uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0; |
mbed_official | 76:aeb1df146756 | 269 | |
mbed_official | 76:aeb1df146756 | 270 | /* Get SYSCLK source -------------------------------------------------------*/ |
mbed_official | 76:aeb1df146756 | 271 | tmp = RCC->CFGR & RCC_CFGR_SWS; |
mbed_official | 76:aeb1df146756 | 272 | |
mbed_official | 76:aeb1df146756 | 273 | switch (tmp) |
mbed_official | 76:aeb1df146756 | 274 | { |
mbed_official | 76:aeb1df146756 | 275 | case 0x00: /* MSI used as system clock */ |
mbed_official | 76:aeb1df146756 | 276 | msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13; |
mbed_official | 76:aeb1df146756 | 277 | SystemCoreClock = (32768 * (1 << (msirange + 1))); |
mbed_official | 76:aeb1df146756 | 278 | break; |
mbed_official | 76:aeb1df146756 | 279 | case 0x04: /* HSI used as system clock */ |
mbed_official | 76:aeb1df146756 | 280 | SystemCoreClock = HSI_VALUE; |
mbed_official | 76:aeb1df146756 | 281 | break; |
mbed_official | 76:aeb1df146756 | 282 | case 0x08: /* HSE used as system clock */ |
mbed_official | 76:aeb1df146756 | 283 | SystemCoreClock = HSE_VALUE; |
mbed_official | 76:aeb1df146756 | 284 | break; |
mbed_official | 76:aeb1df146756 | 285 | case 0x0C: /* PLL used as system clock */ |
mbed_official | 76:aeb1df146756 | 286 | /* Get PLL clock source and multiplication factor ----------------------*/ |
mbed_official | 76:aeb1df146756 | 287 | pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; |
mbed_official | 76:aeb1df146756 | 288 | plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; |
mbed_official | 76:aeb1df146756 | 289 | pllmul = PLLMulTable[(pllmul >> 18)]; |
mbed_official | 76:aeb1df146756 | 290 | plldiv = (plldiv >> 22) + 1; |
mbed_official | 76:aeb1df146756 | 291 | |
mbed_official | 76:aeb1df146756 | 292 | pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; |
mbed_official | 76:aeb1df146756 | 293 | |
mbed_official | 76:aeb1df146756 | 294 | if (pllsource == 0x00) |
mbed_official | 76:aeb1df146756 | 295 | { |
mbed_official | 76:aeb1df146756 | 296 | /* HSI oscillator clock selected as PLL clock entry */ |
mbed_official | 76:aeb1df146756 | 297 | SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv); |
mbed_official | 76:aeb1df146756 | 298 | } |
mbed_official | 76:aeb1df146756 | 299 | else |
mbed_official | 76:aeb1df146756 | 300 | { |
mbed_official | 76:aeb1df146756 | 301 | /* HSE selected as PLL clock entry */ |
mbed_official | 76:aeb1df146756 | 302 | SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv); |
mbed_official | 76:aeb1df146756 | 303 | } |
mbed_official | 76:aeb1df146756 | 304 | break; |
mbed_official | 76:aeb1df146756 | 305 | default: /* MSI used as system clock */ |
mbed_official | 76:aeb1df146756 | 306 | msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13; |
mbed_official | 76:aeb1df146756 | 307 | SystemCoreClock = (32768 * (1 << (msirange + 1))); |
mbed_official | 76:aeb1df146756 | 308 | break; |
mbed_official | 76:aeb1df146756 | 309 | } |
mbed_official | 76:aeb1df146756 | 310 | /* Compute HCLK clock frequency --------------------------------------------*/ |
mbed_official | 76:aeb1df146756 | 311 | /* Get HCLK prescaler */ |
mbed_official | 76:aeb1df146756 | 312 | tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; |
mbed_official | 76:aeb1df146756 | 313 | /* HCLK clock frequency */ |
mbed_official | 76:aeb1df146756 | 314 | SystemCoreClock >>= tmp; |
mbed_official | 76:aeb1df146756 | 315 | } |
mbed_official | 76:aeb1df146756 | 316 | |
mbed_official | 76:aeb1df146756 | 317 | /** |
mbed_official | 76:aeb1df146756 | 318 | * @brief Configures the System clock frequency, AHB/APBx prescalers and Flash |
mbed_official | 76:aeb1df146756 | 319 | * settings. |
mbed_official | 76:aeb1df146756 | 320 | * @note This function should be called only once the RCC clock configuration |
mbed_official | 76:aeb1df146756 | 321 | * is reset to the default reset state (done in SystemInit() function). |
mbed_official | 76:aeb1df146756 | 322 | * @param None |
mbed_official | 76:aeb1df146756 | 323 | * @retval None |
mbed_official | 76:aeb1df146756 | 324 | */ |
mbed_official | 129:0182c99221bc | 325 | void SetSysClock(void) |
mbed_official | 76:aeb1df146756 | 326 | { |
mbed_official | 76:aeb1df146756 | 327 | __IO uint32_t StartUpCounter = 0, HSIStatus = 0; |
mbed_official | 76:aeb1df146756 | 328 | |
mbed_official | 76:aeb1df146756 | 329 | /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ |
mbed_official | 76:aeb1df146756 | 330 | /* Enable HSI */ |
mbed_official | 76:aeb1df146756 | 331 | RCC->CR |= ((uint32_t)RCC_CR_HSION); |
mbed_official | 76:aeb1df146756 | 332 | |
mbed_official | 76:aeb1df146756 | 333 | /* Wait till HSI is ready and if Time out is reached exit */ |
mbed_official | 76:aeb1df146756 | 334 | do |
mbed_official | 76:aeb1df146756 | 335 | { |
mbed_official | 76:aeb1df146756 | 336 | HSIStatus = RCC->CR & RCC_CR_HSIRDY; |
mbed_official | 76:aeb1df146756 | 337 | } while((HSIStatus == 0) && (StartUpCounter != HSI_STARTUP_TIMEOUT)); |
mbed_official | 76:aeb1df146756 | 338 | |
mbed_official | 76:aeb1df146756 | 339 | if ((RCC->CR & RCC_CR_HSIRDY) != RESET) |
mbed_official | 76:aeb1df146756 | 340 | { |
mbed_official | 76:aeb1df146756 | 341 | HSIStatus = (uint32_t)0x01; |
mbed_official | 76:aeb1df146756 | 342 | } |
mbed_official | 76:aeb1df146756 | 343 | else |
mbed_official | 76:aeb1df146756 | 344 | { |
mbed_official | 76:aeb1df146756 | 345 | HSIStatus = (uint32_t)0x00; |
mbed_official | 76:aeb1df146756 | 346 | } |
mbed_official | 76:aeb1df146756 | 347 | |
mbed_official | 76:aeb1df146756 | 348 | if (HSIStatus == (uint32_t)0x01) |
mbed_official | 76:aeb1df146756 | 349 | { |
mbed_official | 129:0182c99221bc | 350 | /* Enable 64-bit access */ |
mbed_official | 129:0182c99221bc | 351 | FLASH->ACR |= FLASH_ACR_ACC64; |
mbed_official | 76:aeb1df146756 | 352 | |
mbed_official | 129:0182c99221bc | 353 | /* Enable Prefetch Buffer */ |
mbed_official | 129:0182c99221bc | 354 | FLASH->ACR |= FLASH_ACR_PRFTEN; |
mbed_official | 76:aeb1df146756 | 355 | |
mbed_official | 129:0182c99221bc | 356 | /* Flash 1 wait state (latency) */ |
mbed_official | 129:0182c99221bc | 357 | FLASH->ACR |= FLASH_ACR_LATENCY; |
mbed_official | 76:aeb1df146756 | 358 | |
mbed_official | 76:aeb1df146756 | 359 | /* Power enable */ |
mbed_official | 76:aeb1df146756 | 360 | RCC->APB1ENR |= RCC_APB1ENR_PWREN; |
mbed_official | 76:aeb1df146756 | 361 | |
mbed_official | 76:aeb1df146756 | 362 | /* Select the Voltage Range 1 (1.8 V) */ |
mbed_official | 76:aeb1df146756 | 363 | PWR->CR = PWR_CR_VOS_0; |
mbed_official | 129:0182c99221bc | 364 | |
mbed_official | 76:aeb1df146756 | 365 | /* Wait Until the Voltage Regulator is ready */ |
mbed_official | 76:aeb1df146756 | 366 | while((PWR->CSR & PWR_CSR_VOSF) != RESET) |
mbed_official | 76:aeb1df146756 | 367 | { |
mbed_official | 76:aeb1df146756 | 368 | } |
mbed_official | 129:0182c99221bc | 369 | |
mbed_official | 129:0182c99221bc | 370 | /* PLL configuration */ |
mbed_official | 129:0182c99221bc | 371 | /* SYSCLK = (HSI 16 MHz * 4) / 2 = 32 MHz */ |
mbed_official | 129:0182c99221bc | 372 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL | RCC_CFGR_PLLDIV)); |
mbed_official | 129:0182c99221bc | 373 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI | RCC_CFGR_PLLMUL4 | RCC_CFGR_PLLDIV2); |
mbed_official | 129:0182c99221bc | 374 | |
mbed_official | 129:0182c99221bc | 375 | /* HCLK = 32 MHz */ |
mbed_official | 76:aeb1df146756 | 376 | RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; |
mbed_official | 129:0182c99221bc | 377 | |
mbed_official | 129:0182c99221bc | 378 | /* PCLK2 = 32 MHz */ |
mbed_official | 76:aeb1df146756 | 379 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; |
mbed_official | 76:aeb1df146756 | 380 | |
mbed_official | 129:0182c99221bc | 381 | /* PCLK1 = 32 MHz */ |
mbed_official | 76:aeb1df146756 | 382 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; |
mbed_official | 129:0182c99221bc | 383 | |
mbed_official | 129:0182c99221bc | 384 | /* Enable PLL */ |
mbed_official | 129:0182c99221bc | 385 | RCC->CR |= RCC_CR_PLLON; |
mbed_official | 129:0182c99221bc | 386 | |
mbed_official | 129:0182c99221bc | 387 | /* Wait till PLL is ready */ |
mbed_official | 129:0182c99221bc | 388 | while((RCC->CR & RCC_CR_PLLRDY) == 0) |
mbed_official | 129:0182c99221bc | 389 | { |
mbed_official | 129:0182c99221bc | 390 | } |
mbed_official | 129:0182c99221bc | 391 | |
mbed_official | 129:0182c99221bc | 392 | /* Select PLL as system clock source */ |
mbed_official | 76:aeb1df146756 | 393 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); |
mbed_official | 129:0182c99221bc | 394 | RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; |
mbed_official | 76:aeb1df146756 | 395 | |
mbed_official | 129:0182c99221bc | 396 | /* Wait till PLL is used as system clock source */ |
mbed_official | 129:0182c99221bc | 397 | while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL) |
mbed_official | 76:aeb1df146756 | 398 | { |
mbed_official | 76:aeb1df146756 | 399 | } |
mbed_official | 76:aeb1df146756 | 400 | } |
mbed_official | 76:aeb1df146756 | 401 | else |
mbed_official | 76:aeb1df146756 | 402 | { |
mbed_official | 76:aeb1df146756 | 403 | /* If HSI fails to start-up, the application will have wrong clock |
mbed_official | 76:aeb1df146756 | 404 | configuration. User can add here some code to deal with this error */ |
mbed_official | 76:aeb1df146756 | 405 | } |
mbed_official | 76:aeb1df146756 | 406 | } |
mbed_official | 76:aeb1df146756 | 407 | |
mbed_official | 76:aeb1df146756 | 408 | /** |
mbed_official | 76:aeb1df146756 | 409 | * @} |
mbed_official | 76:aeb1df146756 | 410 | */ |
mbed_official | 76:aeb1df146756 | 411 | |
mbed_official | 76:aeb1df146756 | 412 | /** |
mbed_official | 76:aeb1df146756 | 413 | * @} |
mbed_official | 76:aeb1df146756 | 414 | */ |
mbed_official | 76:aeb1df146756 | 415 | |
mbed_official | 76:aeb1df146756 | 416 | /** |
mbed_official | 76:aeb1df146756 | 417 | * @} |
mbed_official | 76:aeb1df146756 | 418 | */ |
mbed_official | 76:aeb1df146756 | 419 | |
mbed_official | 76:aeb1df146756 | 420 | /******************* (C) COPYRIGHT 2013 STMicroelectronics *****END OF FILE****/ |