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TARGET_LPC11U24/system_LPC11Uxx.h@64:e3affc9e7238, 2013-08-05 (annotated)

Committer:
bogdanm
Date:
Mon Aug 05 12:28:09 2013 +0300
Revision:
64:e3affc9e7238
Parent:
LPC11U24/system_LPC11Uxx.h@40:976df7c37ad5
Child:
65:5798e58a58b1
New build system structure, new target (LPC1347), bug fixes (I2C read/write errors, LPC11U24 memory map and others)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 40:976df7c37ad5 1 /**************************************************************************//**
emilmont 40:976df7c37ad5 2 * @file system_LPC11Uxx.h
emilmont 40:976df7c37ad5 3 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File
emilmont 40:976df7c37ad5 4 * for the NXP LPC11Uxx Device Series
emilmont 40:976df7c37ad5 5 * @version V1.10
emilmont 40:976df7c37ad5 6 * @date 24. November 2010
emilmont 40:976df7c37ad5 7 *
emilmont 40:976df7c37ad5 8 * @note
emilmont 40:976df7c37ad5 9 * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
emilmont 40:976df7c37ad5 10 *
emilmont 40:976df7c37ad5 11 * @par
emilmont 40:976df7c37ad5 12 * ARM Limited (ARM) is supplying this software for use with Cortex-M
emilmont 40:976df7c37ad5 13 * processor based microcontrollers. This file can be freely distributed
emilmont 40:976df7c37ad5 14 * within development tools that are supporting such ARM based processors.
emilmont 40:976df7c37ad5 15 *
emilmont 40:976df7c37ad5 16 * @par
emilmont 40:976df7c37ad5 17 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
emilmont 40:976df7c37ad5 18 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
emilmont 40:976df7c37ad5 19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
emilmont 40:976df7c37ad5 20 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
emilmont 40:976df7c37ad5 21 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
emilmont 40:976df7c37ad5 22 *
emilmont 40:976df7c37ad5 23 ******************************************************************************/
emilmont 40:976df7c37ad5 24
emilmont 40:976df7c37ad5 25
emilmont 40:976df7c37ad5 26 #ifndef __SYSTEM_LPC11Uxx_H
emilmont 40:976df7c37ad5 27 #define __SYSTEM_LPC11Uxx_H
emilmont 40:976df7c37ad5 28
emilmont 40:976df7c37ad5 29 #ifdef __cplusplus
emilmont 40:976df7c37ad5 30 extern "C" {
emilmont 40:976df7c37ad5 31 #endif
emilmont 40:976df7c37ad5 32
emilmont 40:976df7c37ad5 33 #include <stdint.h>
emilmont 40:976df7c37ad5 34
emilmont 40:976df7c37ad5 35 extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
emilmont 40:976df7c37ad5 36
emilmont 40:976df7c37ad5 37
emilmont 40:976df7c37ad5 38 /**
emilmont 40:976df7c37ad5 39 * Initialize the system
emilmont 40:976df7c37ad5 40 *
emilmont 40:976df7c37ad5 41 * @param none
emilmont 40:976df7c37ad5 42 * @return none
emilmont 40:976df7c37ad5 43 *
emilmont 40:976df7c37ad5 44 * @brief Setup the microcontroller system.
emilmont 40:976df7c37ad5 45 * Initialize the System and update the SystemCoreClock variable.
emilmont 40:976df7c37ad5 46 */
emilmont 40:976df7c37ad5 47 extern void SystemInit (void);
emilmont 40:976df7c37ad5 48
emilmont 40:976df7c37ad5 49 /**
emilmont 40:976df7c37ad5 50 * Update SystemCoreClock variable
emilmont 40:976df7c37ad5 51 *
emilmont 40:976df7c37ad5 52 * @param none
emilmont 40:976df7c37ad5 53 * @return none
emilmont 40:976df7c37ad5 54 *
emilmont 40:976df7c37ad5 55 * @brief Updates the SystemCoreClock with current core Clock
emilmont 40:976df7c37ad5 56 * retrieved from cpu registers.
emilmont 40:976df7c37ad5 57 */
emilmont 40:976df7c37ad5 58 extern void SystemCoreClockUpdate (void);
emilmont 40:976df7c37ad5 59
emilmont 40:976df7c37ad5 60 #ifdef __cplusplus
emilmont 40:976df7c37ad5 61 }
emilmont 40:976df7c37ad5 62 #endif
emilmont 40:976df7c37ad5 63
emilmont 40:976df7c37ad5 64 #endif /* __SYSTEM_LPC11Uxx_H */