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targets/cmsis/TARGET_STM/TARGET_STM32F4XX/stm32f4xx.h@637:ed69428d4850, 2015-12-22 (annotated)

Committer:: jaerts
Date:: Tue Dec 22 13:22:16 2015 +0000
Revision:: 637:ed69428d4850
Parent:: 20:4263a77256ae

Add very shady LPC1768 CAN Filter implementation

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	20:4263a77256ae	1	/**
bogdanm	20:4263a77256ae	2	******************************************************************************
bogdanm	20:4263a77256ae	3	* @file stm32f4xx.h
bogdanm	20:4263a77256ae	4	* @author MCD Application Team
bogdanm	20:4263a77256ae	5	* @version V1.1.0
bogdanm	20:4263a77256ae	6	* @date 11-January-2013
bogdanm	20:4263a77256ae	7	* @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File.
bogdanm	20:4263a77256ae	8	* This file contains all the peripheral register's definitions, bits
bogdanm	20:4263a77256ae	9	* definitions and memory mapping for STM32F4xx devices.
bogdanm	20:4263a77256ae	10	*
bogdanm	20:4263a77256ae	11	* The file is the unique include file that the application programmer
bogdanm	20:4263a77256ae	12	* is using in the C source code, usually in main.c. This file contains:
bogdanm	20:4263a77256ae	13	* - Configuration section that allows to select:
bogdanm	20:4263a77256ae	14	* - The device used in the target application
bogdanm	20:4263a77256ae	15	* - To use or not the peripheral's drivers in application code(i.e.
bogdanm	20:4263a77256ae	16	* code will be based on direct access to peripheral's registers
bogdanm	20:4263a77256ae	17	* rather than drivers API), this option is controlled by
bogdanm	20:4263a77256ae	18	* "#define USE_STDPERIPH_DRIVER"
bogdanm	20:4263a77256ae	19	* - To change few application-specific parameters such as the HSE
bogdanm	20:4263a77256ae	20	* crystal frequency
bogdanm	20:4263a77256ae	21	* - Data structures and the address mapping for all peripherals
bogdanm	20:4263a77256ae	22	* - Peripheral's registers declarations and bits definition
bogdanm	20:4263a77256ae	23	* - Macros to access peripheral's registers hardware
bogdanm	20:4263a77256ae	24	*
bogdanm	20:4263a77256ae	25	******************************************************************************
bogdanm	20:4263a77256ae	26	* @attention
bogdanm	20:4263a77256ae	27	*
bogdanm	20:4263a77256ae	28	* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
bogdanm	20:4263a77256ae	29	*
bogdanm	20:4263a77256ae	30	* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
bogdanm	20:4263a77256ae	31	* You may not use this file except in compliance with the License.
bogdanm	20:4263a77256ae	32	* You may obtain a copy of the License at:
bogdanm	20:4263a77256ae	33	*
bogdanm	20:4263a77256ae	34	* http://www.st.com/software_license_agreement_liberty_v2
bogdanm	20:4263a77256ae	35	*
bogdanm	20:4263a77256ae	36	* Unless required by applicable law or agreed to in writing, software
bogdanm	20:4263a77256ae	37	* distributed under the License is distributed on an "AS IS" BASIS,
bogdanm	20:4263a77256ae	38	* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
bogdanm	20:4263a77256ae	39	* See the License for the specific language governing permissions and
bogdanm	20:4263a77256ae	40	* limitations under the License.
bogdanm	20:4263a77256ae	41	*
bogdanm	20:4263a77256ae	42	******************************************************************************
bogdanm	20:4263a77256ae	43	*/
bogdanm	20:4263a77256ae	44
bogdanm	20:4263a77256ae	45	/** @addtogroup CMSIS
bogdanm	20:4263a77256ae	46	* @{
bogdanm	20:4263a77256ae	47	*/
bogdanm	20:4263a77256ae	48
bogdanm	20:4263a77256ae	49	/** @addtogroup stm32f4xx
bogdanm	20:4263a77256ae	50	* @{
bogdanm	20:4263a77256ae	51	*/
bogdanm	20:4263a77256ae	52
bogdanm	20:4263a77256ae	53	#ifndef __STM32F4xx_H
bogdanm	20:4263a77256ae	54	#define __STM32F4xx_H
bogdanm	20:4263a77256ae	55
bogdanm	20:4263a77256ae	56	#ifdef __cplusplus
bogdanm	20:4263a77256ae	57	extern "C" {
bogdanm	20:4263a77256ae	58	#endif /* __cplusplus */
bogdanm	20:4263a77256ae	59
bogdanm	20:4263a77256ae	60	/** @addtogroup Library_configuration_section
bogdanm	20:4263a77256ae	61	* @{
bogdanm	20:4263a77256ae	62	*/
bogdanm	20:4263a77256ae	63
bogdanm	20:4263a77256ae	64	/* Uncomment the line below according to the target STM32 device used in your
bogdanm	20:4263a77256ae	65	application
bogdanm	20:4263a77256ae	66	*/
bogdanm	20:4263a77256ae	67
bogdanm	20:4263a77256ae	68	#if !defined (STM32F4XX) && !defined (STM32F40XX) && !defined (STM32F427X)
bogdanm	20:4263a77256ae	69	#define STM32F40XX /!< STM32F40xx/41xx Devices /
bogdanm	20:4263a77256ae	70	/* #define STM32F427X / /!< STM32F427x/437x Devices*/
bogdanm	20:4263a77256ae	71	#endif
bogdanm	20:4263a77256ae	72
bogdanm	20:4263a77256ae	73
bogdanm	20:4263a77256ae	74	/* Tip: To avoid modifying this file each time you need to switch between these
bogdanm	20:4263a77256ae	75	devices, you can define the device in your toolchain compiler preprocessor.
bogdanm	20:4263a77256ae	76	*/
bogdanm	20:4263a77256ae	77
bogdanm	20:4263a77256ae	78	#if !defined (STM32F4XX) && !defined (STM32F40XX) && !defined (STM32F427X)
bogdanm	20:4263a77256ae	79	#error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
bogdanm	20:4263a77256ae	80	#endif
bogdanm	20:4263a77256ae	81
bogdanm	20:4263a77256ae	82	#if !defined (USE_STDPERIPH_DRIVER)
bogdanm	20:4263a77256ae	83	/**
bogdanm	20:4263a77256ae	84	* @brief Comment the line below if you will not use the peripherals drivers.
bogdanm	20:4263a77256ae	85	In this case, these drivers will not be included and the application code will
bogdanm	20:4263a77256ae	86	be based on direct access to peripherals registers
bogdanm	20:4263a77256ae	87	*/
bogdanm	20:4263a77256ae	88	/#define USE_STDPERIPH_DRIVER /
bogdanm	20:4263a77256ae	89	#endif /* USE_STDPERIPH_DRIVER */
bogdanm	20:4263a77256ae	90
bogdanm	20:4263a77256ae	91	/**
bogdanm	20:4263a77256ae	92	* @brief In the following line adjust the value of External High Speed oscillator (HSE)
bogdanm	20:4263a77256ae	93	used in your application
bogdanm	20:4263a77256ae	94
bogdanm	20:4263a77256ae	95	Tip: To avoid modifying this file each time you need to use different HSE, you
bogdanm	20:4263a77256ae	96	can define the HSE value in your toolchain compiler preprocessor.
bogdanm	20:4263a77256ae	97	*/
bogdanm	20:4263a77256ae	98
bogdanm	20:4263a77256ae	99	#if !defined (HSE_VALUE)
bogdanm	20:4263a77256ae	100	#define HSE_VALUE ((uint32_t)8000000) /!< Value of the External oscillator in Hz /
bogdanm	20:4263a77256ae	101	#endif /* HSE_VALUE */
bogdanm	20:4263a77256ae	102
bogdanm	20:4263a77256ae	103	/**
bogdanm	20:4263a77256ae	104	* @brief In the following line adjust the External High Speed oscillator (HSE) Startup
bogdanm	20:4263a77256ae	105	Timeout value
bogdanm	20:4263a77256ae	106	*/
bogdanm	20:4263a77256ae	107	#if !defined (HSE_STARTUP_TIMEOUT)
bogdanm	20:4263a77256ae	108	#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /!< Time out for HSE start up /
bogdanm	20:4263a77256ae	109	#endif /* HSE_STARTUP_TIMEOUT */
bogdanm	20:4263a77256ae	110
bogdanm	20:4263a77256ae	111	#if !defined (HSI_VALUE)
bogdanm	20:4263a77256ae	112	#define HSI_VALUE ((uint32_t)16000000) /!< Value of the Internal oscillator in Hz/
bogdanm	20:4263a77256ae	113	#endif /* HSI_VALUE */
bogdanm	20:4263a77256ae	114
bogdanm	20:4263a77256ae	115	/**
bogdanm	20:4263a77256ae	116	* @brief STM32F4XX Standard Peripherals Library version number V1.1.0
bogdanm	20:4263a77256ae	117	*/
bogdanm	20:4263a77256ae	118	#define __STM32F4XX_STDPERIPH_VERSION_MAIN (0x01) /!< [31:24] main version /
bogdanm	20:4263a77256ae	119	#define __STM32F4XX_STDPERIPH_VERSION_SUB1 (0x01) /!< [23:16] sub1 version /
bogdanm	20:4263a77256ae	120	#define __STM32F4XX_STDPERIPH_VERSION_SUB2 (0x00) /!< [15:8] sub2 version /
bogdanm	20:4263a77256ae	121	#define __STM32F4XX_STDPERIPH_VERSION_RC (0x00) /!< [7:0] release candidate /
bogdanm	20:4263a77256ae	122	#define __STM32F4XX_STDPERIPH_VERSION ((__STM32F4XX_STDPERIPH_VERSION_MAIN << 24)\
bogdanm	20:4263a77256ae	123	\|(__STM32F4XX_STDPERIPH_VERSION_SUB1 << 16)\
bogdanm	20:4263a77256ae	124	\|(__STM32F4XX_STDPERIPH_VERSION_SUB2 << 8)\
bogdanm	20:4263a77256ae	125	\|(__STM32F4XX_STDPERIPH_VERSION_RC))
bogdanm	20:4263a77256ae	126
bogdanm	20:4263a77256ae	127	/**
bogdanm	20:4263a77256ae	128	* @}
bogdanm	20:4263a77256ae	129	*/
bogdanm	20:4263a77256ae	130
bogdanm	20:4263a77256ae	131	/** @addtogroup Configuration_section_for_CMSIS
bogdanm	20:4263a77256ae	132	* @{
bogdanm	20:4263a77256ae	133	*/
bogdanm	20:4263a77256ae	134
bogdanm	20:4263a77256ae	135	/**
bogdanm	20:4263a77256ae	136	* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
bogdanm	20:4263a77256ae	137	*/
bogdanm	20:4263a77256ae	138	#define __CM4_REV 0x0001 /!< Core revision r0p1 /
bogdanm	20:4263a77256ae	139	#define __MPU_PRESENT 1 /!< STM32F4XX provides an MPU /
bogdanm	20:4263a77256ae	140	#define __NVIC_PRIO_BITS 4 /!< STM32F4XX uses 4 Bits for the Priority Levels /
bogdanm	20:4263a77256ae	141	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
bogdanm	20:4263a77256ae	142	#define __FPU_PRESENT 1 /!< FPU present /
bogdanm	20:4263a77256ae	143
bogdanm	20:4263a77256ae	144	/**
bogdanm	20:4263a77256ae	145	* @brief STM32F4XX Interrupt Number Definition, according to the selected device
bogdanm	20:4263a77256ae	146	* in @ref Library_configuration_section
bogdanm	20:4263a77256ae	147	*/
bogdanm	20:4263a77256ae	148	typedef enum IRQn
bogdanm	20:4263a77256ae	149	{
bogdanm	20:4263a77256ae	150	/**** Cortex-M4 Processor Exceptions Numbers **************************************************************/
bogdanm	20:4263a77256ae	151	NonMaskableInt_IRQn = -14, /!< 2 Non Maskable Interrupt /
bogdanm	20:4263a77256ae	152	MemoryManagement_IRQn = -12, /!< 4 Cortex-M4 Memory Management Interrupt /
bogdanm	20:4263a77256ae	153	BusFault_IRQn = -11, /!< 5 Cortex-M4 Bus Fault Interrupt /
bogdanm	20:4263a77256ae	154	UsageFault_IRQn = -10, /!< 6 Cortex-M4 Usage Fault Interrupt /
bogdanm	20:4263a77256ae	155	SVCall_IRQn = -5, /!< 11 Cortex-M4 SV Call Interrupt /
bogdanm	20:4263a77256ae	156	DebugMonitor_IRQn = -4, /!< 12 Cortex-M4 Debug Monitor Interrupt /
bogdanm	20:4263a77256ae	157	PendSV_IRQn = -2, /!< 14 Cortex-M4 Pend SV Interrupt /
bogdanm	20:4263a77256ae	158	SysTick_IRQn = -1, /!< 15 Cortex-M4 System Tick Interrupt /
bogdanm	20:4263a77256ae	159	/**** STM32 specific Interrupt Numbers ********************************************************************/
bogdanm	20:4263a77256ae	160	WWDG_IRQn = 0, /!< Window WatchDog Interrupt /
bogdanm	20:4263a77256ae	161	PVD_IRQn = 1, /!< PVD through EXTI Line detection Interrupt /
bogdanm	20:4263a77256ae	162	TAMP_STAMP_IRQn = 2, /!< Tamper and TimeStamp interrupts through the EXTI line /
bogdanm	20:4263a77256ae	163	RTC_WKUP_IRQn = 3, /!< RTC Wakeup interrupt through the EXTI line /
bogdanm	20:4263a77256ae	164	FLASH_IRQn = 4, /!< FLASH global Interrupt /
bogdanm	20:4263a77256ae	165	RCC_IRQn = 5, /!< RCC global Interrupt /
bogdanm	20:4263a77256ae	166	EXTI0_IRQn = 6, /!< EXTI Line0 Interrupt /
bogdanm	20:4263a77256ae	167	EXTI1_IRQn = 7, /!< EXTI Line1 Interrupt /
bogdanm	20:4263a77256ae	168	EXTI2_IRQn = 8, /!< EXTI Line2 Interrupt /
bogdanm	20:4263a77256ae	169	EXTI3_IRQn = 9, /!< EXTI Line3 Interrupt /
bogdanm	20:4263a77256ae	170	EXTI4_IRQn = 10, /!< EXTI Line4 Interrupt /
bogdanm	20:4263a77256ae	171	DMA1_Stream0_IRQn = 11, /!< DMA1 Stream 0 global Interrupt /
bogdanm	20:4263a77256ae	172	DMA1_Stream1_IRQn = 12, /!< DMA1 Stream 1 global Interrupt /
bogdanm	20:4263a77256ae	173	DMA1_Stream2_IRQn = 13, /!< DMA1 Stream 2 global Interrupt /
bogdanm	20:4263a77256ae	174	DMA1_Stream3_IRQn = 14, /!< DMA1 Stream 3 global Interrupt /
bogdanm	20:4263a77256ae	175	DMA1_Stream4_IRQn = 15, /!< DMA1 Stream 4 global Interrupt /
bogdanm	20:4263a77256ae	176	DMA1_Stream5_IRQn = 16, /!< DMA1 Stream 5 global Interrupt /
bogdanm	20:4263a77256ae	177	DMA1_Stream6_IRQn = 17, /!< DMA1 Stream 6 global Interrupt /
bogdanm	20:4263a77256ae	178	ADC_IRQn = 18, /!< ADC1, ADC2 and ADC3 global Interrupts /
bogdanm	20:4263a77256ae	179	CAN1_TX_IRQn = 19, /!< CAN1 TX Interrupt /
bogdanm	20:4263a77256ae	180	CAN1_RX0_IRQn = 20, /!< CAN1 RX0 Interrupt /
bogdanm	20:4263a77256ae	181	CAN1_RX1_IRQn = 21, /!< CAN1 RX1 Interrupt /
bogdanm	20:4263a77256ae	182	CAN1_SCE_IRQn = 22, /!< CAN1 SCE Interrupt /
bogdanm	20:4263a77256ae	183	EXTI9_5_IRQn = 23, /!< External Line[9:5] Interrupts /
bogdanm	20:4263a77256ae	184	TIM1_BRK_TIM9_IRQn = 24, /!< TIM1 Break interrupt and TIM9 global interrupt /
bogdanm	20:4263a77256ae	185	TIM1_UP_TIM10_IRQn = 25, /!< TIM1 Update Interrupt and TIM10 global interrupt /
bogdanm	20:4263a77256ae	186	TIM1_TRG_COM_TIM11_IRQn = 26, /!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt /
bogdanm	20:4263a77256ae	187	TIM1_CC_IRQn = 27, /!< TIM1 Capture Compare Interrupt /
bogdanm	20:4263a77256ae	188	TIM2_IRQn = 28, /!< TIM2 global Interrupt /
bogdanm	20:4263a77256ae	189	TIM3_IRQn = 29, /!< TIM3 global Interrupt /
bogdanm	20:4263a77256ae	190	TIM4_IRQn = 30, /!< TIM4 global Interrupt /
bogdanm	20:4263a77256ae	191	I2C1_EV_IRQn = 31, /!< I2C1 Event Interrupt /
bogdanm	20:4263a77256ae	192	I2C1_ER_IRQn = 32, /!< I2C1 Error Interrupt /
bogdanm	20:4263a77256ae	193	I2C2_EV_IRQn = 33, /!< I2C2 Event Interrupt /
bogdanm	20:4263a77256ae	194	I2C2_ER_IRQn = 34, /!< I2C2 Error Interrupt /
bogdanm	20:4263a77256ae	195	SPI1_IRQn = 35, /!< SPI1 global Interrupt /
bogdanm	20:4263a77256ae	196	SPI2_IRQn = 36, /!< SPI2 global Interrupt /
bogdanm	20:4263a77256ae	197	USART1_IRQn = 37, /!< USART1 global Interrupt /
bogdanm	20:4263a77256ae	198	USART2_IRQn = 38, /!< USART2 global Interrupt /
bogdanm	20:4263a77256ae	199	USART3_IRQn = 39, /!< USART3 global Interrupt /
bogdanm	20:4263a77256ae	200	EXTI15_10_IRQn = 40, /!< External Line[15:10] Interrupts /
bogdanm	20:4263a77256ae	201	RTC_Alarm_IRQn = 41, /!< RTC Alarm (A and B) through EXTI Line Interrupt /
bogdanm	20:4263a77256ae	202	OTG_FS_WKUP_IRQn = 42, /!< USB OTG FS Wakeup through EXTI line interrupt /
bogdanm	20:4263a77256ae	203	TIM8_BRK_TIM12_IRQn = 43, /!< TIM8 Break Interrupt and TIM12 global interrupt /
bogdanm	20:4263a77256ae	204	TIM8_UP_TIM13_IRQn = 44, /!< TIM8 Update Interrupt and TIM13 global interrupt /
bogdanm	20:4263a77256ae	205	TIM8_TRG_COM_TIM14_IRQn = 45, /!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt /
bogdanm	20:4263a77256ae	206	TIM8_CC_IRQn = 46, /!< TIM8 Capture Compare Interrupt /
bogdanm	20:4263a77256ae	207	DMA1_Stream7_IRQn = 47, /!< DMA1 Stream7 Interrupt /
bogdanm	20:4263a77256ae	208	FSMC_IRQn = 48, /!< FSMC global Interrupt /
bogdanm	20:4263a77256ae	209	SDIO_IRQn = 49, /!< SDIO global Interrupt /
bogdanm	20:4263a77256ae	210	TIM5_IRQn = 50, /!< TIM5 global Interrupt /
bogdanm	20:4263a77256ae	211	SPI3_IRQn = 51, /!< SPI3 global Interrupt /
bogdanm	20:4263a77256ae	212	UART4_IRQn = 52, /!< UART4 global Interrupt /
bogdanm	20:4263a77256ae	213	UART5_IRQn = 53, /!< UART5 global Interrupt /
bogdanm	20:4263a77256ae	214	TIM6_DAC_IRQn = 54, /!< TIM6 global and DAC1&2 underrun error interrupts /
bogdanm	20:4263a77256ae	215	TIM7_IRQn = 55, /!< TIM7 global interrupt /
bogdanm	20:4263a77256ae	216	DMA2_Stream0_IRQn = 56, /!< DMA2 Stream 0 global Interrupt /
bogdanm	20:4263a77256ae	217	DMA2_Stream1_IRQn = 57, /!< DMA2 Stream 1 global Interrupt /
bogdanm	20:4263a77256ae	218	DMA2_Stream2_IRQn = 58, /!< DMA2 Stream 2 global Interrupt /
bogdanm	20:4263a77256ae	219	DMA2_Stream3_IRQn = 59, /!< DMA2 Stream 3 global Interrupt /
bogdanm	20:4263a77256ae	220	DMA2_Stream4_IRQn = 60, /!< DMA2 Stream 4 global Interrupt /
bogdanm	20:4263a77256ae	221	ETH_IRQn = 61, /!< Ethernet global Interrupt /
bogdanm	20:4263a77256ae	222	ETH_WKUP_IRQn = 62, /!< Ethernet Wakeup through EXTI line Interrupt /
bogdanm	20:4263a77256ae	223	CAN2_TX_IRQn = 63, /!< CAN2 TX Interrupt /
bogdanm	20:4263a77256ae	224	CAN2_RX0_IRQn = 64, /!< CAN2 RX0 Interrupt /
bogdanm	20:4263a77256ae	225	CAN2_RX1_IRQn = 65, /!< CAN2 RX1 Interrupt /
bogdanm	20:4263a77256ae	226	CAN2_SCE_IRQn = 66, /!< CAN2 SCE Interrupt /
bogdanm	20:4263a77256ae	227	OTG_FS_IRQn = 67, /!< USB OTG FS global Interrupt /
bogdanm	20:4263a77256ae	228	DMA2_Stream5_IRQn = 68, /!< DMA2 Stream 5 global interrupt /
bogdanm	20:4263a77256ae	229	DMA2_Stream6_IRQn = 69, /!< DMA2 Stream 6 global interrupt /
bogdanm	20:4263a77256ae	230	DMA2_Stream7_IRQn = 70, /!< DMA2 Stream 7 global interrupt /
bogdanm	20:4263a77256ae	231	USART6_IRQn = 71, /!< USART6 global interrupt /
bogdanm	20:4263a77256ae	232	I2C3_EV_IRQn = 72, /!< I2C3 event interrupt /
bogdanm	20:4263a77256ae	233	I2C3_ER_IRQn = 73, /!< I2C3 error interrupt /
bogdanm	20:4263a77256ae	234	OTG_HS_EP1_OUT_IRQn = 74, /!< USB OTG HS End Point 1 Out global interrupt /
bogdanm	20:4263a77256ae	235	OTG_HS_EP1_IN_IRQn = 75, /!< USB OTG HS End Point 1 In global interrupt /
bogdanm	20:4263a77256ae	236	OTG_HS_WKUP_IRQn = 76, /!< USB OTG HS Wakeup through EXTI interrupt /
bogdanm	20:4263a77256ae	237	OTG_HS_IRQn = 77, /!< USB OTG HS global interrupt /
bogdanm	20:4263a77256ae	238	DCMI_IRQn = 78, /!< DCMI global interrupt /
bogdanm	20:4263a77256ae	239	CRYP_IRQn = 79, /!< CRYP crypto global interrupt /
bogdanm	20:4263a77256ae	240	HASH_RNG_IRQn = 80, /!< Hash and Rng global interrupt /
bogdanm	20:4263a77256ae	241
bogdanm	20:4263a77256ae	242	#ifdef STM32F40XX
bogdanm	20:4263a77256ae	243	FPU_IRQn = 81 /!< FPU global interrupt /
bogdanm	20:4263a77256ae	244	#endif /* STM32F40XX */
bogdanm	20:4263a77256ae	245
bogdanm	20:4263a77256ae	246	#ifdef STM32F427X
bogdanm	20:4263a77256ae	247	FPU_IRQn = 81, /!< FPU global interrupt /
bogdanm	20:4263a77256ae	248	UART7_IRQn = 82, /!< UART7 global interrupt /
bogdanm	20:4263a77256ae	249	UART8_IRQn = 83, /!< UART8 global interrupt /
bogdanm	20:4263a77256ae	250	SPI4_IRQn = 84, /!< SPI4 global Interrupt /
bogdanm	20:4263a77256ae	251	SPI5_IRQn = 85, /!< SPI5 global Interrupt /
bogdanm	20:4263a77256ae	252	SPI6_IRQn = 86 /!< SPI6 global Interrupt /
bogdanm	20:4263a77256ae	253	#endif /* STM32F427X */
bogdanm	20:4263a77256ae	254
bogdanm	20:4263a77256ae	255	} IRQn_Type;
bogdanm	20:4263a77256ae	256
bogdanm	20:4263a77256ae	257	/**
bogdanm	20:4263a77256ae	258	* @}
bogdanm	20:4263a77256ae	259	*/
bogdanm	20:4263a77256ae	260
bogdanm	20:4263a77256ae	261	#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
bogdanm	20:4263a77256ae	262	#include "system_stm32f4xx.h"
bogdanm	20:4263a77256ae	263	#include <stdint.h>
bogdanm	20:4263a77256ae	264
bogdanm	20:4263a77256ae	265	/** @addtogroup Exported_types
bogdanm	20:4263a77256ae	266	* @{
bogdanm	20:4263a77256ae	267	*/
bogdanm	20:4263a77256ae	268	/!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) /
bogdanm	20:4263a77256ae	269	typedef int32_t s32;
bogdanm	20:4263a77256ae	270	typedef int16_t s16;
bogdanm	20:4263a77256ae	271	typedef int8_t s8;
bogdanm	20:4263a77256ae	272
bogdanm	20:4263a77256ae	273	typedef const int32_t sc32; /!< Read Only /
bogdanm	20:4263a77256ae	274	typedef const int16_t sc16; /!< Read Only /
bogdanm	20:4263a77256ae	275	typedef const int8_t sc8; /!< Read Only /
bogdanm	20:4263a77256ae	276
bogdanm	20:4263a77256ae	277	typedef __IO int32_t vs32;
bogdanm	20:4263a77256ae	278	typedef __IO int16_t vs16;
bogdanm	20:4263a77256ae	279	typedef __IO int8_t vs8;
bogdanm	20:4263a77256ae	280
bogdanm	20:4263a77256ae	281	typedef __I int32_t vsc32; /!< Read Only /
bogdanm	20:4263a77256ae	282	typedef __I int16_t vsc16; /!< Read Only /
bogdanm	20:4263a77256ae	283	typedef __I int8_t vsc8; /!< Read Only /
bogdanm	20:4263a77256ae	284
bogdanm	20:4263a77256ae	285	typedef uint32_t u32;
bogdanm	20:4263a77256ae	286	typedef uint16_t u16;
bogdanm	20:4263a77256ae	287	typedef uint8_t u8;
bogdanm	20:4263a77256ae	288
bogdanm	20:4263a77256ae	289	typedef const uint32_t uc32; /!< Read Only /
bogdanm	20:4263a77256ae	290	typedef const uint16_t uc16; /!< Read Only /
bogdanm	20:4263a77256ae	291	typedef const uint8_t uc8; /!< Read Only /
bogdanm	20:4263a77256ae	292
bogdanm	20:4263a77256ae	293	typedef __IO uint32_t vu32;
bogdanm	20:4263a77256ae	294	typedef __IO uint16_t vu16;
bogdanm	20:4263a77256ae	295	typedef __IO uint8_t vu8;
bogdanm	20:4263a77256ae	296
bogdanm	20:4263a77256ae	297	typedef __I uint32_t vuc32; /!< Read Only /
bogdanm	20:4263a77256ae	298	typedef __I uint16_t vuc16; /!< Read Only /
bogdanm	20:4263a77256ae	299	typedef __I uint8_t vuc8; /!< Read Only /
bogdanm	20:4263a77256ae	300
bogdanm	20:4263a77256ae	301	typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
bogdanm	20:4263a77256ae	302
bogdanm	20:4263a77256ae	303	typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
bogdanm	20:4263a77256ae	304	#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) \|\| ((STATE) == ENABLE))
bogdanm	20:4263a77256ae	305
bogdanm	20:4263a77256ae	306	typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
bogdanm	20:4263a77256ae	307
bogdanm	20:4263a77256ae	308	/**
bogdanm	20:4263a77256ae	309	* @}
bogdanm	20:4263a77256ae	310	*/
bogdanm	20:4263a77256ae	311
bogdanm	20:4263a77256ae	312	/** @addtogroup Peripheral_registers_structures
bogdanm	20:4263a77256ae	313	* @{
bogdanm	20:4263a77256ae	314	*/
bogdanm	20:4263a77256ae	315
bogdanm	20:4263a77256ae	316	/**
bogdanm	20:4263a77256ae	317	* @brief Analog to Digital Converter
bogdanm	20:4263a77256ae	318	*/
bogdanm	20:4263a77256ae	319
bogdanm	20:4263a77256ae	320	typedef struct
bogdanm	20:4263a77256ae	321	{
bogdanm	20:4263a77256ae	322	__IO uint32_t SR; /!< ADC status register, Address offset: 0x00 /
bogdanm	20:4263a77256ae	323	__IO uint32_t CR1; /!< ADC control register 1, Address offset: 0x04 /
bogdanm	20:4263a77256ae	324	__IO uint32_t CR2; /!< ADC control register 2, Address offset: 0x08 /
bogdanm	20:4263a77256ae	325	__IO uint32_t SMPR1; /!< ADC sample time register 1, Address offset: 0x0C /
bogdanm	20:4263a77256ae	326	__IO uint32_t SMPR2; /!< ADC sample time register 2, Address offset: 0x10 /
bogdanm	20:4263a77256ae	327	__IO uint32_t JOFR1; /!< ADC injected channel data offset register 1, Address offset: 0x14 /
bogdanm	20:4263a77256ae	328	__IO uint32_t JOFR2; /!< ADC injected channel data offset register 2, Address offset: 0x18 /
bogdanm	20:4263a77256ae	329	__IO uint32_t JOFR3; /!< ADC injected channel data offset register 3, Address offset: 0x1C /
bogdanm	20:4263a77256ae	330	__IO uint32_t JOFR4; /!< ADC injected channel data offset register 4, Address offset: 0x20 /
bogdanm	20:4263a77256ae	331	__IO uint32_t HTR; /!< ADC watchdog higher threshold register, Address offset: 0x24 /
bogdanm	20:4263a77256ae	332	__IO uint32_t LTR; /!< ADC watchdog lower threshold register, Address offset: 0x28 /
bogdanm	20:4263a77256ae	333	__IO uint32_t SQR1; /!< ADC regular sequence register 1, Address offset: 0x2C /
bogdanm	20:4263a77256ae	334	__IO uint32_t SQR2; /!< ADC regular sequence register 2, Address offset: 0x30 /
bogdanm	20:4263a77256ae	335	__IO uint32_t SQR3; /!< ADC regular sequence register 3, Address offset: 0x34 /
bogdanm	20:4263a77256ae	336	__IO uint32_t JSQR; /!< ADC injected sequence register, Address offset: 0x38/
bogdanm	20:4263a77256ae	337	__IO uint32_t JDR1; /!< ADC injected data register 1, Address offset: 0x3C /
bogdanm	20:4263a77256ae	338	__IO uint32_t JDR2; /!< ADC injected data register 2, Address offset: 0x40 /
bogdanm	20:4263a77256ae	339	__IO uint32_t JDR3; /!< ADC injected data register 3, Address offset: 0x44 /
bogdanm	20:4263a77256ae	340	__IO uint32_t JDR4; /!< ADC injected data register 4, Address offset: 0x48 /
bogdanm	20:4263a77256ae	341	__IO uint32_t DR; /!< ADC regular data register, Address offset: 0x4C /
bogdanm	20:4263a77256ae	342	} ADC_TypeDef;
bogdanm	20:4263a77256ae	343
bogdanm	20:4263a77256ae	344	typedef struct
bogdanm	20:4263a77256ae	345	{
bogdanm	20:4263a77256ae	346	__IO uint32_t CSR; /!< ADC Common status register, Address offset: ADC1 base address + 0x300 /
bogdanm	20:4263a77256ae	347	__IO uint32_t CCR; /!< ADC common control register, Address offset: ADC1 base address + 0x304 /
bogdanm	20:4263a77256ae	348	__IO uint32_t CDR; /*!< ADC common regular data register for dual
bogdanm	20:4263a77256ae	349	AND triple modes, Address offset: ADC1 base address + 0x308 */
bogdanm	20:4263a77256ae	350	} ADC_Common_TypeDef;
bogdanm	20:4263a77256ae	351
bogdanm	20:4263a77256ae	352
bogdanm	20:4263a77256ae	353	/**
bogdanm	20:4263a77256ae	354	* @brief Controller Area Network TxMailBox
bogdanm	20:4263a77256ae	355	*/
bogdanm	20:4263a77256ae	356
bogdanm	20:4263a77256ae	357	typedef struct
bogdanm	20:4263a77256ae	358	{
bogdanm	20:4263a77256ae	359	__IO uint32_t TIR; /!< CAN TX mailbox identifier register /
bogdanm	20:4263a77256ae	360	__IO uint32_t TDTR; /!< CAN mailbox data length control and time stamp register /
bogdanm	20:4263a77256ae	361	__IO uint32_t TDLR; /!< CAN mailbox data low register /
bogdanm	20:4263a77256ae	362	__IO uint32_t TDHR; /!< CAN mailbox data high register /
bogdanm	20:4263a77256ae	363	} CAN_TxMailBox_TypeDef;
bogdanm	20:4263a77256ae	364
bogdanm	20:4263a77256ae	365	/**
bogdanm	20:4263a77256ae	366	* @brief Controller Area Network FIFOMailBox
bogdanm	20:4263a77256ae	367	*/
bogdanm	20:4263a77256ae	368
bogdanm	20:4263a77256ae	369	typedef struct
bogdanm	20:4263a77256ae	370	{
bogdanm	20:4263a77256ae	371	__IO uint32_t RIR; /!< CAN receive FIFO mailbox identifier register /
bogdanm	20:4263a77256ae	372	__IO uint32_t RDTR; /!< CAN receive FIFO mailbox data length control and time stamp register /
bogdanm	20:4263a77256ae	373	__IO uint32_t RDLR; /!< CAN receive FIFO mailbox data low register /
bogdanm	20:4263a77256ae	374	__IO uint32_t RDHR; /!< CAN receive FIFO mailbox data high register /
bogdanm	20:4263a77256ae	375	} CAN_FIFOMailBox_TypeDef;
bogdanm	20:4263a77256ae	376
bogdanm	20:4263a77256ae	377	/**
bogdanm	20:4263a77256ae	378	* @brief Controller Area Network FilterRegister
bogdanm	20:4263a77256ae	379	*/
bogdanm	20:4263a77256ae	380
bogdanm	20:4263a77256ae	381	typedef struct
bogdanm	20:4263a77256ae	382	{
bogdanm	20:4263a77256ae	383	__IO uint32_t FR1; /!< CAN Filter bank register 1 /
bogdanm	20:4263a77256ae	384	__IO uint32_t FR2; /!< CAN Filter bank register 1 /
bogdanm	20:4263a77256ae	385	} CAN_FilterRegister_TypeDef;
bogdanm	20:4263a77256ae	386
bogdanm	20:4263a77256ae	387	/**
bogdanm	20:4263a77256ae	388	* @brief Controller Area Network
bogdanm	20:4263a77256ae	389	*/
bogdanm	20:4263a77256ae	390
bogdanm	20:4263a77256ae	391	typedef struct
bogdanm	20:4263a77256ae	392	{
bogdanm	20:4263a77256ae	393	__IO uint32_t MCR; /!< CAN master control register, Address offset: 0x00 /
bogdanm	20:4263a77256ae	394	__IO uint32_t MSR; /!< CAN master status register, Address offset: 0x04 /
bogdanm	20:4263a77256ae	395	__IO uint32_t TSR; /!< CAN transmit status register, Address offset: 0x08 /
bogdanm	20:4263a77256ae	396	__IO uint32_t RF0R; /!< CAN receive FIFO 0 register, Address offset: 0x0C /
bogdanm	20:4263a77256ae	397	__IO uint32_t RF1R; /!< CAN receive FIFO 1 register, Address offset: 0x10 /
bogdanm	20:4263a77256ae	398	__IO uint32_t IER; /!< CAN interrupt enable register, Address offset: 0x14 /
bogdanm	20:4263a77256ae	399	__IO uint32_t ESR; /!< CAN error status register, Address offset: 0x18 /
bogdanm	20:4263a77256ae	400	__IO uint32_t BTR; /!< CAN bit timing register, Address offset: 0x1C /
bogdanm	20:4263a77256ae	401	uint32_t RESERVED0[88]; /!< Reserved, 0x020 - 0x17F /
bogdanm	20:4263a77256ae	402	CAN_TxMailBox_TypeDef sTxMailBox[3]; /!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC /
bogdanm	20:4263a77256ae	403	CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC /
bogdanm	20:4263a77256ae	404	uint32_t RESERVED1[12]; /!< Reserved, 0x1D0 - 0x1FF /
bogdanm	20:4263a77256ae	405	__IO uint32_t FMR; /!< CAN filter master register, Address offset: 0x200 /
bogdanm	20:4263a77256ae	406	__IO uint32_t FM1R; /!< CAN filter mode register, Address offset: 0x204 /
bogdanm	20:4263a77256ae	407	uint32_t RESERVED2; /!< Reserved, 0x208 /
bogdanm	20:4263a77256ae	408	__IO uint32_t FS1R; /!< CAN filter scale register, Address offset: 0x20C /
bogdanm	20:4263a77256ae	409	uint32_t RESERVED3; /!< Reserved, 0x210 /
bogdanm	20:4263a77256ae	410	__IO uint32_t FFA1R; /!< CAN filter FIFO assignment register, Address offset: 0x214 /
bogdanm	20:4263a77256ae	411	uint32_t RESERVED4; /!< Reserved, 0x218 /
bogdanm	20:4263a77256ae	412	__IO uint32_t FA1R; /!< CAN filter activation register, Address offset: 0x21C /
bogdanm	20:4263a77256ae	413	uint32_t RESERVED5[8]; /!< Reserved, 0x220-0x23F /
bogdanm	20:4263a77256ae	414	CAN_FilterRegister_TypeDef sFilterRegister[28]; /!< CAN Filter Register, Address offset: 0x240-0x31C /
bogdanm	20:4263a77256ae	415	} CAN_TypeDef;
bogdanm	20:4263a77256ae	416
bogdanm	20:4263a77256ae	417	/**
bogdanm	20:4263a77256ae	418	* @brief CRC calculation unit
bogdanm	20:4263a77256ae	419	*/
bogdanm	20:4263a77256ae	420
bogdanm	20:4263a77256ae	421	typedef struct
bogdanm	20:4263a77256ae	422	{
bogdanm	20:4263a77256ae	423	__IO uint32_t DR; /!< CRC Data register, Address offset: 0x00 /
bogdanm	20:4263a77256ae	424	__IO uint8_t IDR; /!< CRC Independent data register, Address offset: 0x04 /
bogdanm	20:4263a77256ae	425	uint8_t RESERVED0; /!< Reserved, 0x05 /
bogdanm	20:4263a77256ae	426	uint16_t RESERVED1; /!< Reserved, 0x06 /
bogdanm	20:4263a77256ae	427	__IO uint32_t CR; /!< CRC Control register, Address offset: 0x08 /
bogdanm	20:4263a77256ae	428	} CRC_TypeDef;
bogdanm	20:4263a77256ae	429
bogdanm	20:4263a77256ae	430	/**
bogdanm	20:4263a77256ae	431	* @brief Digital to Analog Converter
bogdanm	20:4263a77256ae	432	*/
bogdanm	20:4263a77256ae	433
bogdanm	20:4263a77256ae	434	typedef struct
bogdanm	20:4263a77256ae	435	{
bogdanm	20:4263a77256ae	436	__IO uint32_t CR; /!< DAC control register, Address offset: 0x00 /
bogdanm	20:4263a77256ae	437	__IO uint32_t SWTRIGR; /!< DAC software trigger register, Address offset: 0x04 /
bogdanm	20:4263a77256ae	438	__IO uint32_t DHR12R1; /!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 /
bogdanm	20:4263a77256ae	439	__IO uint32_t DHR12L1; /!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C /
bogdanm	20:4263a77256ae	440	__IO uint32_t DHR8R1; /!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 /
bogdanm	20:4263a77256ae	441	__IO uint32_t DHR12R2; /!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 /
bogdanm	20:4263a77256ae	442	__IO uint32_t DHR12L2; /!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 /
bogdanm	20:4263a77256ae	443	__IO uint32_t DHR8R2; /!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C /
bogdanm	20:4263a77256ae	444	__IO uint32_t DHR12RD; /!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 /
bogdanm	20:4263a77256ae	445	__IO uint32_t DHR12LD; /!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 /
bogdanm	20:4263a77256ae	446	__IO uint32_t DHR8RD; /!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 /
bogdanm	20:4263a77256ae	447	__IO uint32_t DOR1; /!< DAC channel1 data output register, Address offset: 0x2C /
bogdanm	20:4263a77256ae	448	__IO uint32_t DOR2; /!< DAC channel2 data output register, Address offset: 0x30 /
bogdanm	20:4263a77256ae	449	__IO uint32_t SR; /!< DAC status register, Address offset: 0x34 /
bogdanm	20:4263a77256ae	450	} DAC_TypeDef;
bogdanm	20:4263a77256ae	451
bogdanm	20:4263a77256ae	452	/**
bogdanm	20:4263a77256ae	453	* @brief Debug MCU
bogdanm	20:4263a77256ae	454	*/
bogdanm	20:4263a77256ae	455
bogdanm	20:4263a77256ae	456	typedef struct
bogdanm	20:4263a77256ae	457	{
bogdanm	20:4263a77256ae	458	__IO uint32_t IDCODE; /!< MCU device ID code, Address offset: 0x00 /
bogdanm	20:4263a77256ae	459	__IO uint32_t CR; /!< Debug MCU configuration register, Address offset: 0x04 /
bogdanm	20:4263a77256ae	460	__IO uint32_t APB1FZ; /!< Debug MCU APB1 freeze register, Address offset: 0x08 /
bogdanm	20:4263a77256ae	461	__IO uint32_t APB2FZ; /!< Debug MCU APB2 freeze register, Address offset: 0x0C /
bogdanm	20:4263a77256ae	462	}DBGMCU_TypeDef;
bogdanm	20:4263a77256ae	463
bogdanm	20:4263a77256ae	464	/**
bogdanm	20:4263a77256ae	465	* @brief DCMI
bogdanm	20:4263a77256ae	466	*/
bogdanm	20:4263a77256ae	467
bogdanm	20:4263a77256ae	468	typedef struct
bogdanm	20:4263a77256ae	469	{
bogdanm	20:4263a77256ae	470	__IO uint32_t CR; /!< DCMI control register 1, Address offset: 0x00 /
bogdanm	20:4263a77256ae	471	__IO uint32_t SR; /!< DCMI status register, Address offset: 0x04 /
bogdanm	20:4263a77256ae	472	__IO uint32_t RISR; /!< DCMI raw interrupt status register, Address offset: 0x08 /
bogdanm	20:4263a77256ae	473	__IO uint32_t IER; /!< DCMI interrupt enable register, Address offset: 0x0C /
bogdanm	20:4263a77256ae	474	__IO uint32_t MISR; /!< DCMI masked interrupt status register, Address offset: 0x10 /
bogdanm	20:4263a77256ae	475	__IO uint32_t ICR; /!< DCMI interrupt clear register, Address offset: 0x14 /
bogdanm	20:4263a77256ae	476	__IO uint32_t ESCR; /!< DCMI embedded synchronization code register, Address offset: 0x18 /
bogdanm	20:4263a77256ae	477	__IO uint32_t ESUR; /!< DCMI embedded synchronization unmask register, Address offset: 0x1C /
bogdanm	20:4263a77256ae	478	__IO uint32_t CWSTRTR; /!< DCMI crop window start, Address offset: 0x20 /
bogdanm	20:4263a77256ae	479	__IO uint32_t CWSIZER; /!< DCMI crop window size, Address offset: 0x24 /
bogdanm	20:4263a77256ae	480	__IO uint32_t DR; /!< DCMI data register, Address offset: 0x28 /
bogdanm	20:4263a77256ae	481	} DCMI_TypeDef;
bogdanm	20:4263a77256ae	482
bogdanm	20:4263a77256ae	483	/**
bogdanm	20:4263a77256ae	484	* @brief DMA Controller
bogdanm	20:4263a77256ae	485	*/
bogdanm	20:4263a77256ae	486
bogdanm	20:4263a77256ae	487	typedef struct
bogdanm	20:4263a77256ae	488	{
bogdanm	20:4263a77256ae	489	__IO uint32_t CR; /!< DMA stream x configuration register /
bogdanm	20:4263a77256ae	490	__IO uint32_t NDTR; /!< DMA stream x number of data register /
bogdanm	20:4263a77256ae	491	__IO uint32_t PAR; /!< DMA stream x peripheral address register /
bogdanm	20:4263a77256ae	492	__IO uint32_t M0AR; /!< DMA stream x memory 0 address register /
bogdanm	20:4263a77256ae	493	__IO uint32_t M1AR; /!< DMA stream x memory 1 address register /
bogdanm	20:4263a77256ae	494	__IO uint32_t FCR; /!< DMA stream x FIFO control register /
bogdanm	20:4263a77256ae	495	} DMA_Stream_TypeDef;
bogdanm	20:4263a77256ae	496
bogdanm	20:4263a77256ae	497	typedef struct
bogdanm	20:4263a77256ae	498	{
bogdanm	20:4263a77256ae	499	__IO uint32_t LISR; /!< DMA low interrupt status register, Address offset: 0x00 /
bogdanm	20:4263a77256ae	500	__IO uint32_t HISR; /!< DMA high interrupt status register, Address offset: 0x04 /
bogdanm	20:4263a77256ae	501	__IO uint32_t LIFCR; /!< DMA low interrupt flag clear register, Address offset: 0x08 /
bogdanm	20:4263a77256ae	502	__IO uint32_t HIFCR; /!< DMA high interrupt flag clear register, Address offset: 0x0C /
bogdanm	20:4263a77256ae	503	} DMA_TypeDef;
bogdanm	20:4263a77256ae	504
bogdanm	20:4263a77256ae	505	/**
bogdanm	20:4263a77256ae	506	* @brief Ethernet MAC
bogdanm	20:4263a77256ae	507	*/
bogdanm	20:4263a77256ae	508
bogdanm	20:4263a77256ae	509	typedef struct
bogdanm	20:4263a77256ae	510	{
bogdanm	20:4263a77256ae	511	__IO uint32_t MACCR;
bogdanm	20:4263a77256ae	512	__IO uint32_t MACFFR;
bogdanm	20:4263a77256ae	513	__IO uint32_t MACHTHR;
bogdanm	20:4263a77256ae	514	__IO uint32_t MACHTLR;
bogdanm	20:4263a77256ae	515	__IO uint32_t MACMIIAR;
bogdanm	20:4263a77256ae	516	__IO uint32_t MACMIIDR;
bogdanm	20:4263a77256ae	517	__IO uint32_t MACFCR;
bogdanm	20:4263a77256ae	518	__IO uint32_t MACVLANTR; /* 8 */
bogdanm	20:4263a77256ae	519	uint32_t RESERVED0[2];
bogdanm	20:4263a77256ae	520	__IO uint32_t MACRWUFFR; /* 11 */
bogdanm	20:4263a77256ae	521	__IO uint32_t MACPMTCSR;
bogdanm	20:4263a77256ae	522	uint32_t RESERVED1[2];
bogdanm	20:4263a77256ae	523	__IO uint32_t MACSR; /* 15 */
bogdanm	20:4263a77256ae	524	__IO uint32_t MACIMR;
bogdanm	20:4263a77256ae	525	__IO uint32_t MACA0HR;
bogdanm	20:4263a77256ae	526	__IO uint32_t MACA0LR;
bogdanm	20:4263a77256ae	527	__IO uint32_t MACA1HR;
bogdanm	20:4263a77256ae	528	__IO uint32_t MACA1LR;
bogdanm	20:4263a77256ae	529	__IO uint32_t MACA2HR;
bogdanm	20:4263a77256ae	530	__IO uint32_t MACA2LR;
bogdanm	20:4263a77256ae	531	__IO uint32_t MACA3HR;
bogdanm	20:4263a77256ae	532	__IO uint32_t MACA3LR; /* 24 */
bogdanm	20:4263a77256ae	533	uint32_t RESERVED2[40];
bogdanm	20:4263a77256ae	534	__IO uint32_t MMCCR; /* 65 */
bogdanm	20:4263a77256ae	535	__IO uint32_t MMCRIR;
bogdanm	20:4263a77256ae	536	__IO uint32_t MMCTIR;
bogdanm	20:4263a77256ae	537	__IO uint32_t MMCRIMR;
bogdanm	20:4263a77256ae	538	__IO uint32_t MMCTIMR; /* 69 */
bogdanm	20:4263a77256ae	539	uint32_t RESERVED3[14];
bogdanm	20:4263a77256ae	540	__IO uint32_t MMCTGFSCCR; /* 84 */
bogdanm	20:4263a77256ae	541	__IO uint32_t MMCTGFMSCCR;
bogdanm	20:4263a77256ae	542	uint32_t RESERVED4[5];
bogdanm	20:4263a77256ae	543	__IO uint32_t MMCTGFCR;
bogdanm	20:4263a77256ae	544	uint32_t RESERVED5[10];
bogdanm	20:4263a77256ae	545	__IO uint32_t MMCRFCECR;
bogdanm	20:4263a77256ae	546	__IO uint32_t MMCRFAECR;
bogdanm	20:4263a77256ae	547	uint32_t RESERVED6[10];
bogdanm	20:4263a77256ae	548	__IO uint32_t MMCRGUFCR;
bogdanm	20:4263a77256ae	549	uint32_t RESERVED7[334];
bogdanm	20:4263a77256ae	550	__IO uint32_t PTPTSCR;
bogdanm	20:4263a77256ae	551	__IO uint32_t PTPSSIR;
bogdanm	20:4263a77256ae	552	__IO uint32_t PTPTSHR;
bogdanm	20:4263a77256ae	553	__IO uint32_t PTPTSLR;
bogdanm	20:4263a77256ae	554	__IO uint32_t PTPTSHUR;
bogdanm	20:4263a77256ae	555	__IO uint32_t PTPTSLUR;
bogdanm	20:4263a77256ae	556	__IO uint32_t PTPTSAR;
bogdanm	20:4263a77256ae	557	__IO uint32_t PTPTTHR;
bogdanm	20:4263a77256ae	558	__IO uint32_t PTPTTLR;
bogdanm	20:4263a77256ae	559	__IO uint32_t RESERVED8;
bogdanm	20:4263a77256ae	560	__IO uint32_t PTPTSSR;
bogdanm	20:4263a77256ae	561	uint32_t RESERVED9[565];
bogdanm	20:4263a77256ae	562	__IO uint32_t DMABMR;
bogdanm	20:4263a77256ae	563	__IO uint32_t DMATPDR;
bogdanm	20:4263a77256ae	564	__IO uint32_t DMARPDR;
bogdanm	20:4263a77256ae	565	__IO uint32_t DMARDLAR;
bogdanm	20:4263a77256ae	566	__IO uint32_t DMATDLAR;
bogdanm	20:4263a77256ae	567	__IO uint32_t DMASR;
bogdanm	20:4263a77256ae	568	__IO uint32_t DMAOMR;
bogdanm	20:4263a77256ae	569	__IO uint32_t DMAIER;
bogdanm	20:4263a77256ae	570	__IO uint32_t DMAMFBOCR;
bogdanm	20:4263a77256ae	571	__IO uint32_t DMARSWTR;
bogdanm	20:4263a77256ae	572	uint32_t RESERVED10[8];
bogdanm	20:4263a77256ae	573	__IO uint32_t DMACHTDR;
bogdanm	20:4263a77256ae	574	__IO uint32_t DMACHRDR;
bogdanm	20:4263a77256ae	575	__IO uint32_t DMACHTBAR;
bogdanm	20:4263a77256ae	576	__IO uint32_t DMACHRBAR;
bogdanm	20:4263a77256ae	577	} ETH_TypeDef;
bogdanm	20:4263a77256ae	578
bogdanm	20:4263a77256ae	579	/**
bogdanm	20:4263a77256ae	580	* @brief External Interrupt/Event Controller
bogdanm	20:4263a77256ae	581	*/
bogdanm	20:4263a77256ae	582
bogdanm	20:4263a77256ae	583	typedef struct
bogdanm	20:4263a77256ae	584	{
bogdanm	20:4263a77256ae	585	__IO uint32_t IMR; /!< EXTI Interrupt mask register, Address offset: 0x00 /
bogdanm	20:4263a77256ae	586	__IO uint32_t EMR; /!< EXTI Event mask register, Address offset: 0x04 /
bogdanm	20:4263a77256ae	587	__IO uint32_t RTSR; /!< EXTI Rising trigger selection register, Address offset: 0x08 /
bogdanm	20:4263a77256ae	588	__IO uint32_t FTSR; /!< EXTI Falling trigger selection register, Address offset: 0x0C /
bogdanm	20:4263a77256ae	589	__IO uint32_t SWIER; /!< EXTI Software interrupt event register, Address offset: 0x10 /
bogdanm	20:4263a77256ae	590	__IO uint32_t PR; /!< EXTI Pending register, Address offset: 0x14 /
bogdanm	20:4263a77256ae	591	} EXTI_TypeDef;
bogdanm	20:4263a77256ae	592
bogdanm	20:4263a77256ae	593	/**
bogdanm	20:4263a77256ae	594	* @brief FLASH Registers
bogdanm	20:4263a77256ae	595	*/
bogdanm	20:4263a77256ae	596
bogdanm	20:4263a77256ae	597	typedef struct
bogdanm	20:4263a77256ae	598	{
bogdanm	20:4263a77256ae	599	__IO uint32_t ACR; /!< FLASH access control register, Address offset: 0x00 /
bogdanm	20:4263a77256ae	600	__IO uint32_t KEYR; /!< FLASH key register, Address offset: 0x04 /
bogdanm	20:4263a77256ae	601	__IO uint32_t OPTKEYR; /!< FLASH option key register, Address offset: 0x08 /
bogdanm	20:4263a77256ae	602	__IO uint32_t SR; /!< FLASH status register, Address offset: 0x0C /
bogdanm	20:4263a77256ae	603	__IO uint32_t CR; /!< FLASH control register, Address offset: 0x10 /
bogdanm	20:4263a77256ae	604	__IO uint32_t OPTCR; /!< FLASH option control register , Address offset: 0x14 /
bogdanm	20:4263a77256ae	605	__IO uint32_t OPTCR1; /!< FLASH option control register 1, Address offset: 0x18 /
bogdanm	20:4263a77256ae	606	} FLASH_TypeDef;
bogdanm	20:4263a77256ae	607
bogdanm	20:4263a77256ae	608	/**
bogdanm	20:4263a77256ae	609	* @brief Flexible Static Memory Controller
bogdanm	20:4263a77256ae	610	*/
bogdanm	20:4263a77256ae	611
bogdanm	20:4263a77256ae	612	typedef struct
bogdanm	20:4263a77256ae	613	{
bogdanm	20:4263a77256ae	614	__IO uint32_t BTCR[8]; /!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C /
bogdanm	20:4263a77256ae	615	} FSMC_Bank1_TypeDef;
bogdanm	20:4263a77256ae	616
bogdanm	20:4263a77256ae	617	/**
bogdanm	20:4263a77256ae	618	* @brief Flexible Static Memory Controller Bank1E
bogdanm	20:4263a77256ae	619	*/
bogdanm	20:4263a77256ae	620
bogdanm	20:4263a77256ae	621	typedef struct
bogdanm	20:4263a77256ae	622	{
bogdanm	20:4263a77256ae	623	__IO uint32_t BWTR[7]; /!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C /
bogdanm	20:4263a77256ae	624	} FSMC_Bank1E_TypeDef;
bogdanm	20:4263a77256ae	625
bogdanm	20:4263a77256ae	626	/**
bogdanm	20:4263a77256ae	627	* @brief Flexible Static Memory Controller Bank2
bogdanm	20:4263a77256ae	628	*/
bogdanm	20:4263a77256ae	629
bogdanm	20:4263a77256ae	630	typedef struct
bogdanm	20:4263a77256ae	631	{
bogdanm	20:4263a77256ae	632	__IO uint32_t PCR2; /!< NAND Flash control register 2, Address offset: 0x60 /
bogdanm	20:4263a77256ae	633	__IO uint32_t SR2; /!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 /
bogdanm	20:4263a77256ae	634	__IO uint32_t PMEM2; /!< NAND Flash Common memory space timing register 2, Address offset: 0x68 /
bogdanm	20:4263a77256ae	635	__IO uint32_t PATT2; /!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C /
bogdanm	20:4263a77256ae	636	uint32_t RESERVED0; /!< Reserved, 0x70 /
bogdanm	20:4263a77256ae	637	__IO uint32_t ECCR2; /!< NAND Flash ECC result registers 2, Address offset: 0x74 /
bogdanm	20:4263a77256ae	638	} FSMC_Bank2_TypeDef;
bogdanm	20:4263a77256ae	639
bogdanm	20:4263a77256ae	640	/**
bogdanm	20:4263a77256ae	641	* @brief Flexible Static Memory Controller Bank3
bogdanm	20:4263a77256ae	642	*/
bogdanm	20:4263a77256ae	643
bogdanm	20:4263a77256ae	644	typedef struct
bogdanm	20:4263a77256ae	645	{
bogdanm	20:4263a77256ae	646	__IO uint32_t PCR3; /!< NAND Flash control register 3, Address offset: 0x80 /
bogdanm	20:4263a77256ae	647	__IO uint32_t SR3; /!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 /
bogdanm	20:4263a77256ae	648	__IO uint32_t PMEM3; /!< NAND Flash Common memory space timing register 3, Address offset: 0x88 /
bogdanm	20:4263a77256ae	649	__IO uint32_t PATT3; /!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C /
bogdanm	20:4263a77256ae	650	uint32_t RESERVED0; /!< Reserved, 0x90 /
bogdanm	20:4263a77256ae	651	__IO uint32_t ECCR3; /!< NAND Flash ECC result registers 3, Address offset: 0x94 /
bogdanm	20:4263a77256ae	652	} FSMC_Bank3_TypeDef;
bogdanm	20:4263a77256ae	653
bogdanm	20:4263a77256ae	654	/**
bogdanm	20:4263a77256ae	655	* @brief Flexible Static Memory Controller Bank4
bogdanm	20:4263a77256ae	656	*/
bogdanm	20:4263a77256ae	657
bogdanm	20:4263a77256ae	658	typedef struct
bogdanm	20:4263a77256ae	659	{
bogdanm	20:4263a77256ae	660	__IO uint32_t PCR4; /!< PC Card control register 4, Address offset: 0xA0 /
bogdanm	20:4263a77256ae	661	__IO uint32_t SR4; /!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 /
bogdanm	20:4263a77256ae	662	__IO uint32_t PMEM4; /!< PC Card Common memory space timing register 4, Address offset: 0xA8 /
bogdanm	20:4263a77256ae	663	__IO uint32_t PATT4; /!< PC Card Attribute memory space timing register 4, Address offset: 0xAC /
bogdanm	20:4263a77256ae	664	__IO uint32_t PIO4; /!< PC Card I/O space timing register 4, Address offset: 0xB0 /
bogdanm	20:4263a77256ae	665	} FSMC_Bank4_TypeDef;
bogdanm	20:4263a77256ae	666
bogdanm	20:4263a77256ae	667	/**
bogdanm	20:4263a77256ae	668	* @brief General Purpose I/O
bogdanm	20:4263a77256ae	669	*/
bogdanm	20:4263a77256ae	670
bogdanm	20:4263a77256ae	671	typedef struct
bogdanm	20:4263a77256ae	672	{
bogdanm	20:4263a77256ae	673	__IO uint32_t MODER; /!< GPIO port mode register, Address offset: 0x00 /
bogdanm	20:4263a77256ae	674	__IO uint32_t OTYPER; /!< GPIO port output type register, Address offset: 0x04 /
bogdanm	20:4263a77256ae	675	__IO uint32_t OSPEEDR; /!< GPIO port output speed register, Address offset: 0x08 /
bogdanm	20:4263a77256ae	676	__IO uint32_t PUPDR; /!< GPIO port pull-up/pull-down register, Address offset: 0x0C /
bogdanm	20:4263a77256ae	677	__IO uint32_t IDR; /!< GPIO port input data register, Address offset: 0x10 /
bogdanm	20:4263a77256ae	678	__IO uint32_t ODR; /!< GPIO port output data register, Address offset: 0x14 /
bogdanm	20:4263a77256ae	679	__IO uint16_t BSRRL; /!< GPIO port bit set/reset low register, Address offset: 0x18 /
bogdanm	20:4263a77256ae	680	__IO uint16_t BSRRH; /!< GPIO port bit set/reset high register, Address offset: 0x1A /
bogdanm	20:4263a77256ae	681	__IO uint32_t LCKR; /!< GPIO port configuration lock register, Address offset: 0x1C /
bogdanm	20:4263a77256ae	682	__IO uint32_t AFR[2]; /!< GPIO alternate function registers, Address offset: 0x20-0x24 /
bogdanm	20:4263a77256ae	683	} GPIO_TypeDef;
bogdanm	20:4263a77256ae	684
bogdanm	20:4263a77256ae	685	/**
bogdanm	20:4263a77256ae	686	* @brief System configuration controller
bogdanm	20:4263a77256ae	687	*/
bogdanm	20:4263a77256ae	688
bogdanm	20:4263a77256ae	689	typedef struct
bogdanm	20:4263a77256ae	690	{
bogdanm	20:4263a77256ae	691	__IO uint32_t MEMRMP; /!< SYSCFG memory remap register, Address offset: 0x00 /
bogdanm	20:4263a77256ae	692	__IO uint32_t PMC; /!< SYSCFG peripheral mode configuration register, Address offset: 0x04 /
bogdanm	20:4263a77256ae	693	__IO uint32_t EXTICR[4]; /!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 /
bogdanm	20:4263a77256ae	694	uint32_t RESERVED[2]; /!< Reserved, 0x18-0x1C /
bogdanm	20:4263a77256ae	695	__IO uint32_t CMPCR; /!< SYSCFG Compensation cell control register, Address offset: 0x20 /
bogdanm	20:4263a77256ae	696	} SYSCFG_TypeDef;
bogdanm	20:4263a77256ae	697
bogdanm	20:4263a77256ae	698	/**
bogdanm	20:4263a77256ae	699	* @brief Inter-integrated Circuit Interface
bogdanm	20:4263a77256ae	700	*/
bogdanm	20:4263a77256ae	701
bogdanm	20:4263a77256ae	702	typedef struct
bogdanm	20:4263a77256ae	703	{
bogdanm	20:4263a77256ae	704	__IO uint16_t CR1; /!< I2C Control register 1, Address offset: 0x00 /
bogdanm	20:4263a77256ae	705	uint16_t RESERVED0; /!< Reserved, 0x02 /
bogdanm	20:4263a77256ae	706	__IO uint16_t CR2; /!< I2C Control register 2, Address offset: 0x04 /
bogdanm	20:4263a77256ae	707	uint16_t RESERVED1; /!< Reserved, 0x06 /
bogdanm	20:4263a77256ae	708	__IO uint16_t OAR1; /!< I2C Own address register 1, Address offset: 0x08 /
bogdanm	20:4263a77256ae	709	uint16_t RESERVED2; /!< Reserved, 0x0A /
bogdanm	20:4263a77256ae	710	__IO uint16_t OAR2; /!< I2C Own address register 2, Address offset: 0x0C /
bogdanm	20:4263a77256ae	711	uint16_t RESERVED3; /!< Reserved, 0x0E /
bogdanm	20:4263a77256ae	712	__IO uint16_t DR; /!< I2C Data register, Address offset: 0x10 /
bogdanm	20:4263a77256ae	713	uint16_t RESERVED4; /!< Reserved, 0x12 /
bogdanm	20:4263a77256ae	714	__IO uint16_t SR1; /!< I2C Status register 1, Address offset: 0x14 /
bogdanm	20:4263a77256ae	715	uint16_t RESERVED5; /!< Reserved, 0x16 /
bogdanm	20:4263a77256ae	716	__IO uint16_t SR2; /!< I2C Status register 2, Address offset: 0x18 /
bogdanm	20:4263a77256ae	717	uint16_t RESERVED6; /!< Reserved, 0x1A /
bogdanm	20:4263a77256ae	718	__IO uint16_t CCR; /!< I2C Clock control register, Address offset: 0x1C /
bogdanm	20:4263a77256ae	719	uint16_t RESERVED7; /!< Reserved, 0x1E /
bogdanm	20:4263a77256ae	720	__IO uint16_t TRISE; /!< I2C TRISE register, Address offset: 0x20 /
bogdanm	20:4263a77256ae	721	uint16_t RESERVED8; /!< Reserved, 0x22 /
bogdanm	20:4263a77256ae	722	__IO uint16_t FLTR; /!< I2C FLTR register, Address offset: 0x24 /
bogdanm	20:4263a77256ae	723	uint16_t RESERVED9; /!< Reserved, 0x26 /
bogdanm	20:4263a77256ae	724	} I2C_TypeDef;
bogdanm	20:4263a77256ae	725
bogdanm	20:4263a77256ae	726	/**
bogdanm	20:4263a77256ae	727	* @brief Independent WATCHDOG
bogdanm	20:4263a77256ae	728	*/
bogdanm	20:4263a77256ae	729
bogdanm	20:4263a77256ae	730	typedef struct
bogdanm	20:4263a77256ae	731	{
bogdanm	20:4263a77256ae	732	__IO uint32_t KR; /!< IWDG Key register, Address offset: 0x00 /
bogdanm	20:4263a77256ae	733	__IO uint32_t PR; /!< IWDG Prescaler register, Address offset: 0x04 /
bogdanm	20:4263a77256ae	734	__IO uint32_t RLR; /!< IWDG Reload register, Address offset: 0x08 /
bogdanm	20:4263a77256ae	735	__IO uint32_t SR; /!< IWDG Status register, Address offset: 0x0C /
bogdanm	20:4263a77256ae	736	} IWDG_TypeDef;
bogdanm	20:4263a77256ae	737
bogdanm	20:4263a77256ae	738	/**
bogdanm	20:4263a77256ae	739	* @brief Power Control
bogdanm	20:4263a77256ae	740	*/
bogdanm	20:4263a77256ae	741
bogdanm	20:4263a77256ae	742	typedef struct
bogdanm	20:4263a77256ae	743	{
bogdanm	20:4263a77256ae	744	__IO uint32_t CR; /!< PWR power control register, Address offset: 0x00 /
bogdanm	20:4263a77256ae	745	__IO uint32_t CSR; /!< PWR power control/status register, Address offset: 0x04 /
bogdanm	20:4263a77256ae	746	} PWR_TypeDef;
bogdanm	20:4263a77256ae	747
bogdanm	20:4263a77256ae	748	/**
bogdanm	20:4263a77256ae	749	* @brief Reset and Clock Control
bogdanm	20:4263a77256ae	750	*/
bogdanm	20:4263a77256ae	751
bogdanm	20:4263a77256ae	752	typedef struct
bogdanm	20:4263a77256ae	753	{
bogdanm	20:4263a77256ae	754	__IO uint32_t CR; /!< RCC clock control register, Address offset: 0x00 /
bogdanm	20:4263a77256ae	755	__IO uint32_t PLLCFGR; /!< RCC PLL configuration register, Address offset: 0x04 /
bogdanm	20:4263a77256ae	756	__IO uint32_t CFGR; /!< RCC clock configuration register, Address offset: 0x08 /
bogdanm	20:4263a77256ae	757	__IO uint32_t CIR; /!< RCC clock interrupt register, Address offset: 0x0C /
bogdanm	20:4263a77256ae	758	__IO uint32_t AHB1RSTR; /!< RCC AHB1 peripheral reset register, Address offset: 0x10 /
bogdanm	20:4263a77256ae	759	__IO uint32_t AHB2RSTR; /!< RCC AHB2 peripheral reset register, Address offset: 0x14 /
bogdanm	20:4263a77256ae	760	__IO uint32_t AHB3RSTR; /!< RCC AHB3 peripheral reset register, Address offset: 0x18 /
bogdanm	20:4263a77256ae	761	uint32_t RESERVED0; /!< Reserved, 0x1C /
bogdanm	20:4263a77256ae	762	__IO uint32_t APB1RSTR; /!< RCC APB1 peripheral reset register, Address offset: 0x20 /
bogdanm	20:4263a77256ae	763	__IO uint32_t APB2RSTR; /!< RCC APB2 peripheral reset register, Address offset: 0x24 /
bogdanm	20:4263a77256ae	764	uint32_t RESERVED1[2]; /!< Reserved, 0x28-0x2C /
bogdanm	20:4263a77256ae	765	__IO uint32_t AHB1ENR; /!< RCC AHB1 peripheral clock register, Address offset: 0x30 /
bogdanm	20:4263a77256ae	766	__IO uint32_t AHB2ENR; /!< RCC AHB2 peripheral clock register, Address offset: 0x34 /
bogdanm	20:4263a77256ae	767	__IO uint32_t AHB3ENR; /!< RCC AHB3 peripheral clock register, Address offset: 0x38 /
bogdanm	20:4263a77256ae	768	uint32_t RESERVED2; /!< Reserved, 0x3C /
bogdanm	20:4263a77256ae	769	__IO uint32_t APB1ENR; /!< RCC APB1 peripheral clock enable register, Address offset: 0x40 /
bogdanm	20:4263a77256ae	770	__IO uint32_t APB2ENR; /!< RCC APB2 peripheral clock enable register, Address offset: 0x44 /
bogdanm	20:4263a77256ae	771	uint32_t RESERVED3[2]; /!< Reserved, 0x48-0x4C /
bogdanm	20:4263a77256ae	772	__IO uint32_t AHB1LPENR; /!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 /
bogdanm	20:4263a77256ae	773	__IO uint32_t AHB2LPENR; /!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 /
bogdanm	20:4263a77256ae	774	__IO uint32_t AHB3LPENR; /!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 /
bogdanm	20:4263a77256ae	775	uint32_t RESERVED4; /!< Reserved, 0x5C /
bogdanm	20:4263a77256ae	776	__IO uint32_t APB1LPENR; /!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 /
bogdanm	20:4263a77256ae	777	__IO uint32_t APB2LPENR; /!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 /
bogdanm	20:4263a77256ae	778	uint32_t RESERVED5[2]; /!< Reserved, 0x68-0x6C /
bogdanm	20:4263a77256ae	779	__IO uint32_t BDCR; /!< RCC Backup domain control register, Address offset: 0x70 /
bogdanm	20:4263a77256ae	780	__IO uint32_t CSR; /!< RCC clock control & status register, Address offset: 0x74 /
bogdanm	20:4263a77256ae	781	uint32_t RESERVED6[2]; /!< Reserved, 0x78-0x7C /
bogdanm	20:4263a77256ae	782	__IO uint32_t SSCGR; /!< RCC spread spectrum clock generation register, Address offset: 0x80 /
bogdanm	20:4263a77256ae	783	__IO uint32_t PLLI2SCFGR; /!< RCC PLLI2S configuration register, Address offset: 0x84 /
bogdanm	20:4263a77256ae	784
bogdanm	20:4263a77256ae	785	#ifdef STM32F427X
bogdanm	20:4263a77256ae	786	uint32_t RESERVED7; /!< Reserved, 0x88 /
bogdanm	20:4263a77256ae	787	__IO uint32_t DCKCFGR; /!< RCC Dedicated Clocks configuration register, Address offset: 0x8C /
bogdanm	20:4263a77256ae	788	#endif /* STM32F427X */
bogdanm	20:4263a77256ae	789
bogdanm	20:4263a77256ae	790	} RCC_TypeDef;
bogdanm	20:4263a77256ae	791
bogdanm	20:4263a77256ae	792	/**
bogdanm	20:4263a77256ae	793	* @brief Real-Time Clock
bogdanm	20:4263a77256ae	794	*/
bogdanm	20:4263a77256ae	795
bogdanm	20:4263a77256ae	796	typedef struct
bogdanm	20:4263a77256ae	797	{
bogdanm	20:4263a77256ae	798	__IO uint32_t TR; /!< RTC time register, Address offset: 0x00 /
bogdanm	20:4263a77256ae	799	__IO uint32_t DR; /!< RTC date register, Address offset: 0x04 /
bogdanm	20:4263a77256ae	800	__IO uint32_t CR; /!< RTC control register, Address offset: 0x08 /
bogdanm	20:4263a77256ae	801	__IO uint32_t ISR; /!< RTC initialization and status register, Address offset: 0x0C /
bogdanm	20:4263a77256ae	802	__IO uint32_t PRER; /!< RTC prescaler register, Address offset: 0x10 /
bogdanm	20:4263a77256ae	803	__IO uint32_t WUTR; /!< RTC wakeup timer register, Address offset: 0x14 /
bogdanm	20:4263a77256ae	804	__IO uint32_t CALIBR; /!< RTC calibration register, Address offset: 0x18 /
bogdanm	20:4263a77256ae	805	__IO uint32_t ALRMAR; /!< RTC alarm A register, Address offset: 0x1C /
bogdanm	20:4263a77256ae	806	__IO uint32_t ALRMBR; /!< RTC alarm B register, Address offset: 0x20 /
bogdanm	20:4263a77256ae	807	__IO uint32_t WPR; /!< RTC write protection register, Address offset: 0x24 /
bogdanm	20:4263a77256ae	808	__IO uint32_t SSR; /!< RTC sub second register, Address offset: 0x28 /
bogdanm	20:4263a77256ae	809	__IO uint32_t SHIFTR; /!< RTC shift control register, Address offset: 0x2C /
bogdanm	20:4263a77256ae	810	__IO uint32_t TSTR; /!< RTC time stamp time register, Address offset: 0x30 /
bogdanm	20:4263a77256ae	811	__IO uint32_t TSDR; /!< RTC time stamp date register, Address offset: 0x34 /
bogdanm	20:4263a77256ae	812	__IO uint32_t TSSSR; /!< RTC time-stamp sub second register, Address offset: 0x38 /
bogdanm	20:4263a77256ae	813	__IO uint32_t CALR; /!< RTC calibration register, Address offset: 0x3C /
bogdanm	20:4263a77256ae	814	__IO uint32_t TAFCR; /!< RTC tamper and alternate function configuration register, Address offset: 0x40 /
bogdanm	20:4263a77256ae	815	__IO uint32_t ALRMASSR;/!< RTC alarm A sub second register, Address offset: 0x44 /
bogdanm	20:4263a77256ae	816	__IO uint32_t ALRMBSSR;/!< RTC alarm B sub second register, Address offset: 0x48 /
bogdanm	20:4263a77256ae	817	uint32_t RESERVED7; /!< Reserved, 0x4C /
bogdanm	20:4263a77256ae	818	__IO uint32_t BKP0R; /!< RTC backup register 1, Address offset: 0x50 /
bogdanm	20:4263a77256ae	819	__IO uint32_t BKP1R; /!< RTC backup register 1, Address offset: 0x54 /
bogdanm	20:4263a77256ae	820	__IO uint32_t BKP2R; /!< RTC backup register 2, Address offset: 0x58 /
bogdanm	20:4263a77256ae	821	__IO uint32_t BKP3R; /!< RTC backup register 3, Address offset: 0x5C /
bogdanm	20:4263a77256ae	822	__IO uint32_t BKP4R; /!< RTC backup register 4, Address offset: 0x60 /
bogdanm	20:4263a77256ae	823	__IO uint32_t BKP5R; /!< RTC backup register 5, Address offset: 0x64 /
bogdanm	20:4263a77256ae	824	__IO uint32_t BKP6R; /!< RTC backup register 6, Address offset: 0x68 /
bogdanm	20:4263a77256ae	825	__IO uint32_t BKP7R; /!< RTC backup register 7, Address offset: 0x6C /
bogdanm	20:4263a77256ae	826	__IO uint32_t BKP8R; /!< RTC backup register 8, Address offset: 0x70 /
bogdanm	20:4263a77256ae	827	__IO uint32_t BKP9R; /!< RTC backup register 9, Address offset: 0x74 /
bogdanm	20:4263a77256ae	828	__IO uint32_t BKP10R; /!< RTC backup register 10, Address offset: 0x78 /
bogdanm	20:4263a77256ae	829	__IO uint32_t BKP11R; /!< RTC backup register 11, Address offset: 0x7C /
bogdanm	20:4263a77256ae	830	__IO uint32_t BKP12R; /!< RTC backup register 12, Address offset: 0x80 /
bogdanm	20:4263a77256ae	831	__IO uint32_t BKP13R; /!< RTC backup register 13, Address offset: 0x84 /
bogdanm	20:4263a77256ae	832	__IO uint32_t BKP14R; /!< RTC backup register 14, Address offset: 0x88 /
bogdanm	20:4263a77256ae	833	__IO uint32_t BKP15R; /!< RTC backup register 15, Address offset: 0x8C /
bogdanm	20:4263a77256ae	834	__IO uint32_t BKP16R; /!< RTC backup register 16, Address offset: 0x90 /
bogdanm	20:4263a77256ae	835	__IO uint32_t BKP17R; /!< RTC backup register 17, Address offset: 0x94 /
bogdanm	20:4263a77256ae	836	__IO uint32_t BKP18R; /!< RTC backup register 18, Address offset: 0x98 /
bogdanm	20:4263a77256ae	837	__IO uint32_t BKP19R; /!< RTC backup register 19, Address offset: 0x9C /
bogdanm	20:4263a77256ae	838	} RTC_TypeDef;
bogdanm	20:4263a77256ae	839
bogdanm	20:4263a77256ae	840	/**
bogdanm	20:4263a77256ae	841	* @brief SD host Interface
bogdanm	20:4263a77256ae	842	*/
bogdanm	20:4263a77256ae	843
bogdanm	20:4263a77256ae	844	typedef struct
bogdanm	20:4263a77256ae	845	{
bogdanm	20:4263a77256ae	846	__IO uint32_t POWER; /!< SDIO power control register, Address offset: 0x00 /
bogdanm	20:4263a77256ae	847	__IO uint32_t CLKCR; /!< SDI clock control register, Address offset: 0x04 /
bogdanm	20:4263a77256ae	848	__IO uint32_t ARG; /!< SDIO argument register, Address offset: 0x08 /
bogdanm	20:4263a77256ae	849	__IO uint32_t CMD; /!< SDIO command register, Address offset: 0x0C /
bogdanm	20:4263a77256ae	850	__I uint32_t RESPCMD; /!< SDIO command response register, Address offset: 0x10 /
bogdanm	20:4263a77256ae	851	__I uint32_t RESP1; /!< SDIO response 1 register, Address offset: 0x14 /
bogdanm	20:4263a77256ae	852	__I uint32_t RESP2; /!< SDIO response 2 register, Address offset: 0x18 /
bogdanm	20:4263a77256ae	853	__I uint32_t RESP3; /!< SDIO response 3 register, Address offset: 0x1C /
bogdanm	20:4263a77256ae	854	__I uint32_t RESP4; /!< SDIO response 4 register, Address offset: 0x20 /
bogdanm	20:4263a77256ae	855	__IO uint32_t DTIMER; /!< SDIO data timer register, Address offset: 0x24 /
bogdanm	20:4263a77256ae	856	__IO uint32_t DLEN; /!< SDIO data length register, Address offset: 0x28 /
bogdanm	20:4263a77256ae	857	__IO uint32_t DCTRL; /!< SDIO data control register, Address offset: 0x2C /
bogdanm	20:4263a77256ae	858	__I uint32_t DCOUNT; /!< SDIO data counter register, Address offset: 0x30 /
bogdanm	20:4263a77256ae	859	__I uint32_t STA; /!< SDIO status register, Address offset: 0x34 /
bogdanm	20:4263a77256ae	860	__IO uint32_t ICR; /!< SDIO interrupt clear register, Address offset: 0x38 /
bogdanm	20:4263a77256ae	861	__IO uint32_t MASK; /!< SDIO mask register, Address offset: 0x3C /
bogdanm	20:4263a77256ae	862	uint32_t RESERVED0[2]; /!< Reserved, 0x40-0x44 /
bogdanm	20:4263a77256ae	863	__I uint32_t FIFOCNT; /!< SDIO FIFO counter register, Address offset: 0x48 /
bogdanm	20:4263a77256ae	864	uint32_t RESERVED1[13]; /!< Reserved, 0x4C-0x7C /
bogdanm	20:4263a77256ae	865	__IO uint32_t FIFO; /!< SDIO data FIFO register, Address offset: 0x80 /
bogdanm	20:4263a77256ae	866	} SDIO_TypeDef;
bogdanm	20:4263a77256ae	867
bogdanm	20:4263a77256ae	868	/**
bogdanm	20:4263a77256ae	869	* @brief Serial Peripheral Interface
bogdanm	20:4263a77256ae	870	*/
bogdanm	20:4263a77256ae	871
bogdanm	20:4263a77256ae	872	typedef struct
bogdanm	20:4263a77256ae	873	{
bogdanm	20:4263a77256ae	874	__IO uint16_t CR1; /!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 /
bogdanm	20:4263a77256ae	875	uint16_t RESERVED0; /!< Reserved, 0x02 /
bogdanm	20:4263a77256ae	876	__IO uint16_t CR2; /!< SPI control register 2, Address offset: 0x04 /
bogdanm	20:4263a77256ae	877	uint16_t RESERVED1; /!< Reserved, 0x06 /
bogdanm	20:4263a77256ae	878	__IO uint16_t SR; /!< SPI status register, Address offset: 0x08 /
bogdanm	20:4263a77256ae	879	uint16_t RESERVED2; /!< Reserved, 0x0A /
bogdanm	20:4263a77256ae	880	__IO uint16_t DR; /!< SPI data register, Address offset: 0x0C /
bogdanm	20:4263a77256ae	881	uint16_t RESERVED3; /!< Reserved, 0x0E /
bogdanm	20:4263a77256ae	882	__IO uint16_t CRCPR; /!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 /
bogdanm	20:4263a77256ae	883	uint16_t RESERVED4; /!< Reserved, 0x12 /
bogdanm	20:4263a77256ae	884	__IO uint16_t RXCRCR; /!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 /
bogdanm	20:4263a77256ae	885	uint16_t RESERVED5; /!< Reserved, 0x16 /
bogdanm	20:4263a77256ae	886	__IO uint16_t TXCRCR; /!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 /
bogdanm	20:4263a77256ae	887	uint16_t RESERVED6; /!< Reserved, 0x1A /
bogdanm	20:4263a77256ae	888	__IO uint16_t I2SCFGR; /!< SPI_I2S configuration register, Address offset: 0x1C /
bogdanm	20:4263a77256ae	889	uint16_t RESERVED7; /!< Reserved, 0x1E /
bogdanm	20:4263a77256ae	890	__IO uint16_t I2SPR; /!< SPI_I2S prescaler register, Address offset: 0x20 /
bogdanm	20:4263a77256ae	891	uint16_t RESERVED8; /!< Reserved, 0x22 /
bogdanm	20:4263a77256ae	892	} SPI_TypeDef;
bogdanm	20:4263a77256ae	893
bogdanm	20:4263a77256ae	894	/**
bogdanm	20:4263a77256ae	895	* @brief TIM
bogdanm	20:4263a77256ae	896	*/
bogdanm	20:4263a77256ae	897
bogdanm	20:4263a77256ae	898	typedef struct
bogdanm	20:4263a77256ae	899	{
bogdanm	20:4263a77256ae	900	__IO uint16_t CR1; /!< TIM control register 1, Address offset: 0x00 /
bogdanm	20:4263a77256ae	901	uint16_t RESERVED0; /!< Reserved, 0x02 /
bogdanm	20:4263a77256ae	902	__IO uint16_t CR2; /!< TIM control register 2, Address offset: 0x04 /
bogdanm	20:4263a77256ae	903	uint16_t RESERVED1; /!< Reserved, 0x06 /
bogdanm	20:4263a77256ae	904	__IO uint16_t SMCR; /!< TIM slave mode control register, Address offset: 0x08 /
bogdanm	20:4263a77256ae	905	uint16_t RESERVED2; /!< Reserved, 0x0A /
bogdanm	20:4263a77256ae	906	__IO uint16_t DIER; /!< TIM DMA/interrupt enable register, Address offset: 0x0C /
bogdanm	20:4263a77256ae	907	uint16_t RESERVED3; /!< Reserved, 0x0E /
bogdanm	20:4263a77256ae	908	__IO uint16_t SR; /!< TIM status register, Address offset: 0x10 /
bogdanm	20:4263a77256ae	909	uint16_t RESERVED4; /!< Reserved, 0x12 /
bogdanm	20:4263a77256ae	910	__IO uint16_t EGR; /!< TIM event generation register, Address offset: 0x14 /
bogdanm	20:4263a77256ae	911	uint16_t RESERVED5; /!< Reserved, 0x16 /
bogdanm	20:4263a77256ae	912	__IO uint16_t CCMR1; /!< TIM capture/compare mode register 1, Address offset: 0x18 /
bogdanm	20:4263a77256ae	913	uint16_t RESERVED6; /!< Reserved, 0x1A /
bogdanm	20:4263a77256ae	914	__IO uint16_t CCMR2; /!< TIM capture/compare mode register 2, Address offset: 0x1C /
bogdanm	20:4263a77256ae	915	uint16_t RESERVED7; /!< Reserved, 0x1E /
bogdanm	20:4263a77256ae	916	__IO uint16_t CCER; /!< TIM capture/compare enable register, Address offset: 0x20 /
bogdanm	20:4263a77256ae	917	uint16_t RESERVED8; /!< Reserved, 0x22 /
bogdanm	20:4263a77256ae	918	__IO uint32_t CNT; /!< TIM counter register, Address offset: 0x24 /
bogdanm	20:4263a77256ae	919	__IO uint16_t PSC; /!< TIM prescaler, Address offset: 0x28 /
bogdanm	20:4263a77256ae	920	uint16_t RESERVED9; /!< Reserved, 0x2A /
bogdanm	20:4263a77256ae	921	__IO uint32_t ARR; /!< TIM auto-reload register, Address offset: 0x2C /
bogdanm	20:4263a77256ae	922	__IO uint16_t RCR; /!< TIM repetition counter register, Address offset: 0x30 /
bogdanm	20:4263a77256ae	923	uint16_t RESERVED10; /!< Reserved, 0x32 /
bogdanm	20:4263a77256ae	924	__IO uint32_t CCR1; /!< TIM capture/compare register 1, Address offset: 0x34 /
bogdanm	20:4263a77256ae	925	__IO uint32_t CCR2; /!< TIM capture/compare register 2, Address offset: 0x38 /
bogdanm	20:4263a77256ae	926	__IO uint32_t CCR3; /!< TIM capture/compare register 3, Address offset: 0x3C /
bogdanm	20:4263a77256ae	927	__IO uint32_t CCR4; /!< TIM capture/compare register 4, Address offset: 0x40 /
bogdanm	20:4263a77256ae	928	__IO uint16_t BDTR; /!< TIM break and dead-time register, Address offset: 0x44 /
bogdanm	20:4263a77256ae	929	uint16_t RESERVED11; /!< Reserved, 0x46 /
bogdanm	20:4263a77256ae	930	__IO uint16_t DCR; /!< TIM DMA control register, Address offset: 0x48 /
bogdanm	20:4263a77256ae	931	uint16_t RESERVED12; /!< Reserved, 0x4A /
bogdanm	20:4263a77256ae	932	__IO uint16_t DMAR; /!< TIM DMA address for full transfer, Address offset: 0x4C /
bogdanm	20:4263a77256ae	933	uint16_t RESERVED13; /!< Reserved, 0x4E /
bogdanm	20:4263a77256ae	934	__IO uint16_t OR; /!< TIM option register, Address offset: 0x50 /
bogdanm	20:4263a77256ae	935	uint16_t RESERVED14; /!< Reserved, 0x52 /
bogdanm	20:4263a77256ae	936	} TIM_TypeDef;
bogdanm	20:4263a77256ae	937
bogdanm	20:4263a77256ae	938	/**
bogdanm	20:4263a77256ae	939	* @brief Universal Synchronous Asynchronous Receiver Transmitter
bogdanm	20:4263a77256ae	940	*/
bogdanm	20:4263a77256ae	941
bogdanm	20:4263a77256ae	942	typedef struct
bogdanm	20:4263a77256ae	943	{
bogdanm	20:4263a77256ae	944	__IO uint16_t SR; /!< USART Status register, Address offset: 0x00 /
bogdanm	20:4263a77256ae	945	uint16_t RESERVED0; /!< Reserved, 0x02 /
bogdanm	20:4263a77256ae	946	__IO uint16_t DR; /!< USART Data register, Address offset: 0x04 /
bogdanm	20:4263a77256ae	947	uint16_t RESERVED1; /!< Reserved, 0x06 /
bogdanm	20:4263a77256ae	948	__IO uint16_t BRR; /!< USART Baud rate register, Address offset: 0x08 /
bogdanm	20:4263a77256ae	949	uint16_t RESERVED2; /!< Reserved, 0x0A /
bogdanm	20:4263a77256ae	950	__IO uint16_t CR1; /!< USART Control register 1, Address offset: 0x0C /
bogdanm	20:4263a77256ae	951	uint16_t RESERVED3; /!< Reserved, 0x0E /
bogdanm	20:4263a77256ae	952	__IO uint16_t CR2; /!< USART Control register 2, Address offset: 0x10 /
bogdanm	20:4263a77256ae	953	uint16_t RESERVED4; /!< Reserved, 0x12 /
bogdanm	20:4263a77256ae	954	__IO uint16_t CR3; /!< USART Control register 3, Address offset: 0x14 /
bogdanm	20:4263a77256ae	955	uint16_t RESERVED5; /!< Reserved, 0x16 /
bogdanm	20:4263a77256ae	956	__IO uint16_t GTPR; /!< USART Guard time and prescaler register, Address offset: 0x18 /
bogdanm	20:4263a77256ae	957	uint16_t RESERVED6; /!< Reserved, 0x1A /
bogdanm	20:4263a77256ae	958	} USART_TypeDef;
bogdanm	20:4263a77256ae	959
bogdanm	20:4263a77256ae	960	/**
bogdanm	20:4263a77256ae	961	* @brief Window WATCHDOG
bogdanm	20:4263a77256ae	962	*/
bogdanm	20:4263a77256ae	963
bogdanm	20:4263a77256ae	964	typedef struct
bogdanm	20:4263a77256ae	965	{
bogdanm	20:4263a77256ae	966	__IO uint32_t CR; /!< WWDG Control register, Address offset: 0x00 /
bogdanm	20:4263a77256ae	967	__IO uint32_t CFR; /!< WWDG Configuration register, Address offset: 0x04 /
bogdanm	20:4263a77256ae	968	__IO uint32_t SR; /!< WWDG Status register, Address offset: 0x08 /
bogdanm	20:4263a77256ae	969	} WWDG_TypeDef;
bogdanm	20:4263a77256ae	970
bogdanm	20:4263a77256ae	971	/**
bogdanm	20:4263a77256ae	972	* @brief Crypto Processor
bogdanm	20:4263a77256ae	973	*/
bogdanm	20:4263a77256ae	974
bogdanm	20:4263a77256ae	975	typedef struct
bogdanm	20:4263a77256ae	976	{
bogdanm	20:4263a77256ae	977	__IO uint32_t CR; /!< CRYP control register, Address offset: 0x00 /
bogdanm	20:4263a77256ae	978	__IO uint32_t SR; /!< CRYP status register, Address offset: 0x04 /
bogdanm	20:4263a77256ae	979	__IO uint32_t DR; /!< CRYP data input register, Address offset: 0x08 /
bogdanm	20:4263a77256ae	980	__IO uint32_t DOUT; /!< CRYP data output register, Address offset: 0x0C /
bogdanm	20:4263a77256ae	981	__IO uint32_t DMACR; /!< CRYP DMA control register, Address offset: 0x10 /
bogdanm	20:4263a77256ae	982	__IO uint32_t IMSCR; /!< CRYP interrupt mask set/clear register, Address offset: 0x14 /
bogdanm	20:4263a77256ae	983	__IO uint32_t RISR; /!< CRYP raw interrupt status register, Address offset: 0x18 /
bogdanm	20:4263a77256ae	984	__IO uint32_t MISR; /!< CRYP masked interrupt status register, Address offset: 0x1C /
bogdanm	20:4263a77256ae	985	__IO uint32_t K0LR; /!< CRYP key left register 0, Address offset: 0x20 /
bogdanm	20:4263a77256ae	986	__IO uint32_t K0RR; /!< CRYP key right register 0, Address offset: 0x24 /
bogdanm	20:4263a77256ae	987	__IO uint32_t K1LR; /!< CRYP key left register 1, Address offset: 0x28 /
bogdanm	20:4263a77256ae	988	__IO uint32_t K1RR; /!< CRYP key right register 1, Address offset: 0x2C /
bogdanm	20:4263a77256ae	989	__IO uint32_t K2LR; /!< CRYP key left register 2, Address offset: 0x30 /
bogdanm	20:4263a77256ae	990	__IO uint32_t K2RR; /!< CRYP key right register 2, Address offset: 0x34 /
bogdanm	20:4263a77256ae	991	__IO uint32_t K3LR; /!< CRYP key left register 3, Address offset: 0x38 /
bogdanm	20:4263a77256ae	992	__IO uint32_t K3RR; /!< CRYP key right register 3, Address offset: 0x3C /
bogdanm	20:4263a77256ae	993	__IO uint32_t IV0LR; /!< CRYP initialization vector left-word register 0, Address offset: 0x40 /
bogdanm	20:4263a77256ae	994	__IO uint32_t IV0RR; /!< CRYP initialization vector right-word register 0, Address offset: 0x44 /
bogdanm	20:4263a77256ae	995	__IO uint32_t IV1LR; /!< CRYP initialization vector left-word register 1, Address offset: 0x48 /
bogdanm	20:4263a77256ae	996	__IO uint32_t IV1RR; /!< CRYP initialization vector right-word register 1, Address offset: 0x4C /
bogdanm	20:4263a77256ae	997	__IO uint32_t CSGCMCCM0R; /!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 /
bogdanm	20:4263a77256ae	998	__IO uint32_t CSGCMCCM1R; /!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 /
bogdanm	20:4263a77256ae	999	__IO uint32_t CSGCMCCM2R; /!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 /
bogdanm	20:4263a77256ae	1000	__IO uint32_t CSGCMCCM3R; /!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C /
bogdanm	20:4263a77256ae	1001	__IO uint32_t CSGCMCCM4R; /!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 /
bogdanm	20:4263a77256ae	1002	__IO uint32_t CSGCMCCM5R; /!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 /
bogdanm	20:4263a77256ae	1003	__IO uint32_t CSGCMCCM6R; /!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 /
bogdanm	20:4263a77256ae	1004	__IO uint32_t CSGCMCCM7R; /!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C /
bogdanm	20:4263a77256ae	1005	__IO uint32_t CSGCM0R; /!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 /
bogdanm	20:4263a77256ae	1006	__IO uint32_t CSGCM1R; /!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 /
bogdanm	20:4263a77256ae	1007	__IO uint32_t CSGCM2R; /!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 /
bogdanm	20:4263a77256ae	1008	__IO uint32_t CSGCM3R; /!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C /
bogdanm	20:4263a77256ae	1009	__IO uint32_t CSGCM4R; /!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 /
bogdanm	20:4263a77256ae	1010	__IO uint32_t CSGCM5R; /!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 /
bogdanm	20:4263a77256ae	1011	__IO uint32_t CSGCM6R; /!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 /
bogdanm	20:4263a77256ae	1012	__IO uint32_t CSGCM7R; /!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C /
bogdanm	20:4263a77256ae	1013	} CRYP_TypeDef;
bogdanm	20:4263a77256ae	1014
bogdanm	20:4263a77256ae	1015	/**
bogdanm	20:4263a77256ae	1016	* @brief HASH
bogdanm	20:4263a77256ae	1017	*/
bogdanm	20:4263a77256ae	1018
bogdanm	20:4263a77256ae	1019	typedef struct
bogdanm	20:4263a77256ae	1020	{
bogdanm	20:4263a77256ae	1021	__IO uint32_t CR; /!< HASH control register, Address offset: 0x00 /
bogdanm	20:4263a77256ae	1022	__IO uint32_t DIN; /!< HASH data input register, Address offset: 0x04 /
bogdanm	20:4263a77256ae	1023	__IO uint32_t STR; /!< HASH start register, Address offset: 0x08 /
bogdanm	20:4263a77256ae	1024	__IO uint32_t HR[5]; /!< HASH digest registers, Address offset: 0x0C-0x1C /
bogdanm	20:4263a77256ae	1025	__IO uint32_t IMR; /!< HASH interrupt enable register, Address offset: 0x20 /
bogdanm	20:4263a77256ae	1026	__IO uint32_t SR; /!< HASH status register, Address offset: 0x24 /
bogdanm	20:4263a77256ae	1027	uint32_t RESERVED[52]; /!< Reserved, 0x28-0xF4 /
bogdanm	20:4263a77256ae	1028	__IO uint32_t CSR[54]; /!< HASH context swap registers, Address offset: 0x0F8-0x1CC /
bogdanm	20:4263a77256ae	1029	} HASH_TypeDef;
bogdanm	20:4263a77256ae	1030
bogdanm	20:4263a77256ae	1031	/**
bogdanm	20:4263a77256ae	1032	* @brief HASH_DIGEST
bogdanm	20:4263a77256ae	1033	*/
bogdanm	20:4263a77256ae	1034
bogdanm	20:4263a77256ae	1035	typedef struct
bogdanm	20:4263a77256ae	1036	{
bogdanm	20:4263a77256ae	1037	__IO uint32_t HR[8]; /!< HASH digest registers, Address offset: 0x310-0x32C /
bogdanm	20:4263a77256ae	1038	} HASH_DIGEST_TypeDef;
bogdanm	20:4263a77256ae	1039
bogdanm	20:4263a77256ae	1040	/**
bogdanm	20:4263a77256ae	1041	* @brief RNG
bogdanm	20:4263a77256ae	1042	*/
bogdanm	20:4263a77256ae	1043
bogdanm	20:4263a77256ae	1044	typedef struct
bogdanm	20:4263a77256ae	1045	{
bogdanm	20:4263a77256ae	1046	__IO uint32_t CR; /!< RNG control register, Address offset: 0x00 /
bogdanm	20:4263a77256ae	1047	__IO uint32_t SR; /!< RNG status register, Address offset: 0x04 /
bogdanm	20:4263a77256ae	1048	__IO uint32_t DR; /!< RNG data register, Address offset: 0x08 /
bogdanm	20:4263a77256ae	1049	} RNG_TypeDef;
bogdanm	20:4263a77256ae	1050
bogdanm	20:4263a77256ae	1051	/**
bogdanm	20:4263a77256ae	1052	* @}
bogdanm	20:4263a77256ae	1053	*/
bogdanm	20:4263a77256ae	1054
bogdanm	20:4263a77256ae	1055	/** @addtogroup Peripheral_memory_map
bogdanm	20:4263a77256ae	1056	* @{
bogdanm	20:4263a77256ae	1057	*/
bogdanm	20:4263a77256ae	1058	#define FLASH_BASE ((uint32_t)0x08000000) /!< FLASH(up to 1 MB) base address in the alias region /
bogdanm	20:4263a77256ae	1059	#define CCMDATARAM_BASE ((uint32_t)0x10000000) /!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region /
bogdanm	20:4263a77256ae	1060	#define SRAM1_BASE ((uint32_t)0x20000000) /!< SRAM1(112 KB) base address in the alias region /
bogdanm	20:4263a77256ae	1061	#define SRAM2_BASE ((uint32_t)0x2001C000) /!< SRAM2(16 KB) base address in the alias region /
bogdanm	20:4263a77256ae	1062	#define SRAM3_BASE ((uint32_t)0x20020000) /!< SRAM3(64 KB) base address in the alias region /
bogdanm	20:4263a77256ae	1063	#define PERIPH_BASE ((uint32_t)0x40000000) /!< Peripheral base address in the alias region /
bogdanm	20:4263a77256ae	1064	#define BKPSRAM_BASE ((uint32_t)0x40024000) /!< Backup SRAM(4 KB) base address in the alias region /
bogdanm	20:4263a77256ae	1065	#define FSMC_R_BASE ((uint32_t)0xA0000000) /!< FSMC registers base address /
bogdanm	20:4263a77256ae	1066
bogdanm	20:4263a77256ae	1067	#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region /
bogdanm	20:4263a77256ae	1068	#define SRAM1_BB_BASE ((uint32_t)0x22000000) /!< SRAM1(112 KB) base address in the bit-band region /
bogdanm	20:4263a77256ae	1069	#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /!< SRAM2(16 KB) base address in the bit-band region /
bogdanm	20:4263a77256ae	1070	#define SRAM3_BB_BASE ((uint32_t)0x22020000) /!< SRAM3(64 KB) base address in the bit-band region /
bogdanm	20:4263a77256ae	1071	#define PERIPH_BB_BASE ((uint32_t)0x42000000) /!< Peripheral base address in the bit-band region /
bogdanm	20:4263a77256ae	1072	#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /!< Backup SRAM(4 KB) base address in the bit-band region /
bogdanm	20:4263a77256ae	1073
bogdanm	20:4263a77256ae	1074	/* Legacy defines */
bogdanm	20:4263a77256ae	1075	#define SRAM_BASE SRAM1_BASE
bogdanm	20:4263a77256ae	1076	#define SRAM_BB_BASE SRAM1_BB_BASE
bogdanm	20:4263a77256ae	1077
bogdanm	20:4263a77256ae	1078	/!< Peripheral memory map /
bogdanm	20:4263a77256ae	1079	#define APB1PERIPH_BASE PERIPH_BASE
bogdanm	20:4263a77256ae	1080	#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
bogdanm	20:4263a77256ae	1081	#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
bogdanm	20:4263a77256ae	1082	#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
bogdanm	20:4263a77256ae	1083
bogdanm	20:4263a77256ae	1084	/!< APB1 peripherals /
bogdanm	20:4263a77256ae	1085	#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
bogdanm	20:4263a77256ae	1086	#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
bogdanm	20:4263a77256ae	1087	#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
bogdanm	20:4263a77256ae	1088	#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
bogdanm	20:4263a77256ae	1089	#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
bogdanm	20:4263a77256ae	1090	#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
bogdanm	20:4263a77256ae	1091	#define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
bogdanm	20:4263a77256ae	1092	#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
bogdanm	20:4263a77256ae	1093	#define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
bogdanm	20:4263a77256ae	1094	#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
bogdanm	20:4263a77256ae	1095	#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
bogdanm	20:4263a77256ae	1096	#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
bogdanm	20:4263a77256ae	1097	#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400)
bogdanm	20:4263a77256ae	1098	#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
bogdanm	20:4263a77256ae	1099	#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
bogdanm	20:4263a77256ae	1100	#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000)
bogdanm	20:4263a77256ae	1101	#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
bogdanm	20:4263a77256ae	1102	#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
bogdanm	20:4263a77256ae	1103	#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
bogdanm	20:4263a77256ae	1104	#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
bogdanm	20:4263a77256ae	1105	#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
bogdanm	20:4263a77256ae	1106	#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
bogdanm	20:4263a77256ae	1107	#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
bogdanm	20:4263a77256ae	1108	#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
bogdanm	20:4263a77256ae	1109	#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
bogdanm	20:4263a77256ae	1110	#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
bogdanm	20:4263a77256ae	1111	#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
bogdanm	20:4263a77256ae	1112	#define UART7_BASE (APB1PERIPH_BASE + 0x7800)
bogdanm	20:4263a77256ae	1113	#define UART8_BASE (APB1PERIPH_BASE + 0x7C00)
bogdanm	20:4263a77256ae	1114
bogdanm	20:4263a77256ae	1115	/!< APB2 peripherals /
bogdanm	20:4263a77256ae	1116	#define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
bogdanm	20:4263a77256ae	1117	#define TIM8_BASE (APB2PERIPH_BASE + 0x0400)
bogdanm	20:4263a77256ae	1118	#define USART1_BASE (APB2PERIPH_BASE + 0x1000)
bogdanm	20:4263a77256ae	1119	#define USART6_BASE (APB2PERIPH_BASE + 0x1400)
bogdanm	20:4263a77256ae	1120	#define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
bogdanm	20:4263a77256ae	1121	#define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
bogdanm	20:4263a77256ae	1122	#define ADC3_BASE (APB2PERIPH_BASE + 0x2200)
bogdanm	20:4263a77256ae	1123	#define ADC_BASE (APB2PERIPH_BASE + 0x2300)
bogdanm	20:4263a77256ae	1124	#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
bogdanm	20:4263a77256ae	1125	#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
bogdanm	20:4263a77256ae	1126	#define SPI4_BASE (APB2PERIPH_BASE + 0x3400)
bogdanm	20:4263a77256ae	1127	#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
bogdanm	20:4263a77256ae	1128	#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
bogdanm	20:4263a77256ae	1129	#define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
bogdanm	20:4263a77256ae	1130	#define TIM10_BASE (APB2PERIPH_BASE + 0x4400)
bogdanm	20:4263a77256ae	1131	#define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
bogdanm	20:4263a77256ae	1132	#define SPI5_BASE (APB2PERIPH_BASE + 0x5000)
bogdanm	20:4263a77256ae	1133	#define SPI6_BASE (APB2PERIPH_BASE + 0x5400)
bogdanm	20:4263a77256ae	1134
bogdanm	20:4263a77256ae	1135	/!< AHB1 peripherals /
bogdanm	20:4263a77256ae	1136	#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
bogdanm	20:4263a77256ae	1137	#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
bogdanm	20:4263a77256ae	1138	#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
bogdanm	20:4263a77256ae	1139	#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
bogdanm	20:4263a77256ae	1140	#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
bogdanm	20:4263a77256ae	1141	#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400)
bogdanm	20:4263a77256ae	1142	#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800)
bogdanm	20:4263a77256ae	1143	#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
bogdanm	20:4263a77256ae	1144	#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000)
bogdanm	20:4263a77256ae	1145
bogdanm	20:4263a77256ae	1146	#define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
bogdanm	20:4263a77256ae	1147	#define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
bogdanm	20:4263a77256ae	1148	#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
bogdanm	20:4263a77256ae	1149	#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
bogdanm	20:4263a77256ae	1150	#define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
bogdanm	20:4263a77256ae	1151	#define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
bogdanm	20:4263a77256ae	1152	#define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
bogdanm	20:4263a77256ae	1153	#define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
bogdanm	20:4263a77256ae	1154	#define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
bogdanm	20:4263a77256ae	1155	#define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
bogdanm	20:4263a77256ae	1156	#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
bogdanm	20:4263a77256ae	1157	#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
bogdanm	20:4263a77256ae	1158	#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
bogdanm	20:4263a77256ae	1159	#define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
bogdanm	20:4263a77256ae	1160	#define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
bogdanm	20:4263a77256ae	1161	#define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
bogdanm	20:4263a77256ae	1162	#define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
bogdanm	20:4263a77256ae	1163	#define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
bogdanm	20:4263a77256ae	1164	#define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
bogdanm	20:4263a77256ae	1165	#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
bogdanm	20:4263a77256ae	1166	#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
bogdanm	20:4263a77256ae	1167	#define ETH_BASE (AHB1PERIPH_BASE + 0x8000)
bogdanm	20:4263a77256ae	1168	#define ETH_MAC_BASE (ETH_BASE)
bogdanm	20:4263a77256ae	1169	#define ETH_MMC_BASE (ETH_BASE + 0x0100)
bogdanm	20:4263a77256ae	1170	#define ETH_PTP_BASE (ETH_BASE + 0x0700)
bogdanm	20:4263a77256ae	1171	#define ETH_DMA_BASE (ETH_BASE + 0x1000)
bogdanm	20:4263a77256ae	1172
bogdanm	20:4263a77256ae	1173	/!< AHB2 peripherals /
bogdanm	20:4263a77256ae	1174	#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000)
bogdanm	20:4263a77256ae	1175	#define CRYP_BASE (AHB2PERIPH_BASE + 0x60000)
bogdanm	20:4263a77256ae	1176	#define HASH_BASE (AHB2PERIPH_BASE + 0x60400)
bogdanm	20:4263a77256ae	1177	#define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710)
bogdanm	20:4263a77256ae	1178	#define RNG_BASE (AHB2PERIPH_BASE + 0x60800)
bogdanm	20:4263a77256ae	1179
bogdanm	20:4263a77256ae	1180	/!< FSMC Bankx registers base address /
bogdanm	20:4263a77256ae	1181	#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000)
bogdanm	20:4263a77256ae	1182	#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104)
bogdanm	20:4263a77256ae	1183	#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060)
bogdanm	20:4263a77256ae	1184	#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080)
bogdanm	20:4263a77256ae	1185	#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0)
bogdanm	20:4263a77256ae	1186
bogdanm	20:4263a77256ae	1187	/* Debug MCU registers base address */
bogdanm	20:4263a77256ae	1188	#define DBGMCU_BASE ((uint32_t )0xE0042000)
bogdanm	20:4263a77256ae	1189
bogdanm	20:4263a77256ae	1190	/**
bogdanm	20:4263a77256ae	1191	* @}
bogdanm	20:4263a77256ae	1192	*/
bogdanm	20:4263a77256ae	1193
bogdanm	20:4263a77256ae	1194	/** @addtogroup Peripheral_declaration
bogdanm	20:4263a77256ae	1195	* @{
bogdanm	20:4263a77256ae	1196	*/
bogdanm	20:4263a77256ae	1197	#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
bogdanm	20:4263a77256ae	1198	#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
bogdanm	20:4263a77256ae	1199	#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
bogdanm	20:4263a77256ae	1200	#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
bogdanm	20:4263a77256ae	1201	#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
bogdanm	20:4263a77256ae	1202	#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
bogdanm	20:4263a77256ae	1203	#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
bogdanm	20:4263a77256ae	1204	#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
bogdanm	20:4263a77256ae	1205	#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
bogdanm	20:4263a77256ae	1206	#define RTC ((RTC_TypeDef *) RTC_BASE)
bogdanm	20:4263a77256ae	1207	#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
bogdanm	20:4263a77256ae	1208	#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
bogdanm	20:4263a77256ae	1209	#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
bogdanm	20:4263a77256ae	1210	#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
bogdanm	20:4263a77256ae	1211	#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
bogdanm	20:4263a77256ae	1212	#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
bogdanm	20:4263a77256ae	1213	#define USART2 ((USART_TypeDef *) USART2_BASE)
bogdanm	20:4263a77256ae	1214	#define USART3 ((USART_TypeDef *) USART3_BASE)
bogdanm	20:4263a77256ae	1215	#define UART4 ((USART_TypeDef *) UART4_BASE)
bogdanm	20:4263a77256ae	1216	#define UART5 ((USART_TypeDef *) UART5_BASE)
bogdanm	20:4263a77256ae	1217	#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
bogdanm	20:4263a77256ae	1218	#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
bogdanm	20:4263a77256ae	1219	#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
bogdanm	20:4263a77256ae	1220	#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
bogdanm	20:4263a77256ae	1221	#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
bogdanm	20:4263a77256ae	1222	#define PWR ((PWR_TypeDef *) PWR_BASE)
bogdanm	20:4263a77256ae	1223	#define DAC ((DAC_TypeDef *) DAC_BASE)
bogdanm	20:4263a77256ae	1224	#define UART7 ((USART_TypeDef *) UART7_BASE)
bogdanm	20:4263a77256ae	1225	#define UART8 ((USART_TypeDef *) UART8_BASE)
bogdanm	20:4263a77256ae	1226	#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
bogdanm	20:4263a77256ae	1227	#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
bogdanm	20:4263a77256ae	1228	#define USART1 ((USART_TypeDef *) USART1_BASE)
bogdanm	20:4263a77256ae	1229	#define USART6 ((USART_TypeDef *) USART6_BASE)
bogdanm	20:4263a77256ae	1230	#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
bogdanm	20:4263a77256ae	1231	#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
bogdanm	20:4263a77256ae	1232	#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
bogdanm	20:4263a77256ae	1233	#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
bogdanm	20:4263a77256ae	1234	#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
bogdanm	20:4263a77256ae	1235	#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
bogdanm	20:4263a77256ae	1236	#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
bogdanm	20:4263a77256ae	1237	#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
bogdanm	20:4263a77256ae	1238	#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
bogdanm	20:4263a77256ae	1239	#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
bogdanm	20:4263a77256ae	1240	#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
bogdanm	20:4263a77256ae	1241	#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
bogdanm	20:4263a77256ae	1242	#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
bogdanm	20:4263a77256ae	1243	#define SPI6 ((SPI_TypeDef *) SPI6_BASE)
bogdanm	20:4263a77256ae	1244
bogdanm	20:4263a77256ae	1245	#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
bogdanm	20:4263a77256ae	1246	#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
bogdanm	20:4263a77256ae	1247	#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
bogdanm	20:4263a77256ae	1248	#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
bogdanm	20:4263a77256ae	1249	#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
bogdanm	20:4263a77256ae	1250	#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
bogdanm	20:4263a77256ae	1251	#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
bogdanm	20:4263a77256ae	1252	#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
bogdanm	20:4263a77256ae	1253	#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
bogdanm	20:4263a77256ae	1254
bogdanm	20:4263a77256ae	1255	#define CRC ((CRC_TypeDef *) CRC_BASE)
bogdanm	20:4263a77256ae	1256	#define RCC ((RCC_TypeDef *) RCC_BASE)
bogdanm	20:4263a77256ae	1257	#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
bogdanm	20:4263a77256ae	1258	#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
bogdanm	20:4263a77256ae	1259	#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
bogdanm	20:4263a77256ae	1260	#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
bogdanm	20:4263a77256ae	1261	#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
bogdanm	20:4263a77256ae	1262	#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
bogdanm	20:4263a77256ae	1263	#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
bogdanm	20:4263a77256ae	1264	#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
bogdanm	20:4263a77256ae	1265	#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
bogdanm	20:4263a77256ae	1266	#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
bogdanm	20:4263a77256ae	1267	#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
bogdanm	20:4263a77256ae	1268	#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
bogdanm	20:4263a77256ae	1269	#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
bogdanm	20:4263a77256ae	1270	#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
bogdanm	20:4263a77256ae	1271	#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
bogdanm	20:4263a77256ae	1272	#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
bogdanm	20:4263a77256ae	1273	#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
bogdanm	20:4263a77256ae	1274	#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
bogdanm	20:4263a77256ae	1275	#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
bogdanm	20:4263a77256ae	1276	#define ETH ((ETH_TypeDef *) ETH_BASE)
bogdanm	20:4263a77256ae	1277	#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
bogdanm	20:4263a77256ae	1278	#define CRYP ((CRYP_TypeDef *) CRYP_BASE)
bogdanm	20:4263a77256ae	1279	#define HASH ((HASH_TypeDef *) HASH_BASE)
bogdanm	20:4263a77256ae	1280	#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
bogdanm	20:4263a77256ae	1281	#define RNG ((RNG_TypeDef *) RNG_BASE)
bogdanm	20:4263a77256ae	1282	#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
bogdanm	20:4263a77256ae	1283	#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
bogdanm	20:4263a77256ae	1284	#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
bogdanm	20:4263a77256ae	1285	#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
bogdanm	20:4263a77256ae	1286	#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
bogdanm	20:4263a77256ae	1287	#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
bogdanm	20:4263a77256ae	1288
bogdanm	20:4263a77256ae	1289	/**
bogdanm	20:4263a77256ae	1290	* @}
bogdanm	20:4263a77256ae	1291	*/
bogdanm	20:4263a77256ae	1292
bogdanm	20:4263a77256ae	1293	/** @addtogroup Exported_constants
bogdanm	20:4263a77256ae	1294	* @{
bogdanm	20:4263a77256ae	1295	*/
bogdanm	20:4263a77256ae	1296
bogdanm	20:4263a77256ae	1297	/** @addtogroup Peripheral_Registers_Bits_Definition
bogdanm	20:4263a77256ae	1298	* @{
bogdanm	20:4263a77256ae	1299	*/
bogdanm	20:4263a77256ae	1300
bogdanm	20:4263a77256ae	1301	/******************************************************************************/
bogdanm	20:4263a77256ae	1302	/* Peripheral Registers_Bits_Definition */
bogdanm	20:4263a77256ae	1303	/******************************************************************************/
bogdanm	20:4263a77256ae	1304
bogdanm	20:4263a77256ae	1305	/******************************************************************************/
bogdanm	20:4263a77256ae	1306	/* */
bogdanm	20:4263a77256ae	1307	/* Analog to Digital Converter */
bogdanm	20:4263a77256ae	1308	/* */
bogdanm	20:4263a77256ae	1309	/******************************************************************************/
bogdanm	20:4263a77256ae	1310	/****************** Bit definition for ADC_SR register ******************/
bogdanm	20:4263a77256ae	1311	#define ADC_SR_AWD ((uint8_t)0x01) /!<Analog watchdog flag /
bogdanm	20:4263a77256ae	1312	#define ADC_SR_EOC ((uint8_t)0x02) /!<End of conversion /
bogdanm	20:4263a77256ae	1313	#define ADC_SR_JEOC ((uint8_t)0x04) /!<Injected channel end of conversion /
bogdanm	20:4263a77256ae	1314	#define ADC_SR_JSTRT ((uint8_t)0x08) /!<Injected channel Start flag /
bogdanm	20:4263a77256ae	1315	#define ADC_SR_STRT ((uint8_t)0x10) /!<Regular channel Start flag /
bogdanm	20:4263a77256ae	1316	#define ADC_SR_OVR ((uint8_t)0x20) /!<Overrun flag /
bogdanm	20:4263a77256ae	1317
bogdanm	20:4263a77256ae	1318	/***************** Bit definition for ADC_CR1 register ******************/
bogdanm	20:4263a77256ae	1319	#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /!<AWDCH[4:0] bits (Analog watchdog channel select bits) /
bogdanm	20:4263a77256ae	1320	#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	20:4263a77256ae	1321	#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	20:4263a77256ae	1322	#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /!<Bit 2 /
bogdanm	20:4263a77256ae	1323	#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /!<Bit 3 /
bogdanm	20:4263a77256ae	1324	#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /!<Bit 4 /
bogdanm	20:4263a77256ae	1325	#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /!<Interrupt enable for EOC /
bogdanm	20:4263a77256ae	1326	#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /!<AAnalog Watchdog interrupt enable /
bogdanm	20:4263a77256ae	1327	#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /!<Interrupt enable for injected channels /
bogdanm	20:4263a77256ae	1328	#define ADC_CR1_SCAN ((uint32_t)0x00000100) /!<Scan mode /
bogdanm	20:4263a77256ae	1329	#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /!<Enable the watchdog on a single channel in scan mode /
bogdanm	20:4263a77256ae	1330	#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /!<Automatic injected group conversion /
bogdanm	20:4263a77256ae	1331	#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /!<Discontinuous mode on regular channels /
bogdanm	20:4263a77256ae	1332	#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /!<Discontinuous mode on injected channels /
bogdanm	20:4263a77256ae	1333	#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /!<DISCNUM[2:0] bits (Discontinuous mode channel count) /
bogdanm	20:4263a77256ae	1334	#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /!<Bit 0 /
bogdanm	20:4263a77256ae	1335	#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /!<Bit 1 /
bogdanm	20:4263a77256ae	1336	#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /!<Bit 2 /
bogdanm	20:4263a77256ae	1337	#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /!<Analog watchdog enable on injected channels /
bogdanm	20:4263a77256ae	1338	#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /!<Analog watchdog enable on regular channels /
bogdanm	20:4263a77256ae	1339	#define ADC_CR1_RES ((uint32_t)0x03000000) /!<RES[2:0] bits (Resolution) /
bogdanm	20:4263a77256ae	1340	#define ADC_CR1_RES_0 ((uint32_t)0x01000000) /!<Bit 0 /
bogdanm	20:4263a77256ae	1341	#define ADC_CR1_RES_1 ((uint32_t)0x02000000) /!<Bit 1 /
bogdanm	20:4263a77256ae	1342	#define ADC_CR1_OVRIE ((uint32_t)0x04000000) /!<overrun interrupt enable /
bogdanm	20:4263a77256ae	1343
bogdanm	20:4263a77256ae	1344	/***************** Bit definition for ADC_CR2 register ******************/
bogdanm	20:4263a77256ae	1345	#define ADC_CR2_ADON ((uint32_t)0x00000001) /!<A/D Converter ON / OFF /
bogdanm	20:4263a77256ae	1346	#define ADC_CR2_CONT ((uint32_t)0x00000002) /!<Continuous Conversion /
bogdanm	20:4263a77256ae	1347	#define ADC_CR2_DMA ((uint32_t)0x00000100) /!<Direct Memory access mode /
bogdanm	20:4263a77256ae	1348	#define ADC_CR2_DDS ((uint32_t)0x00000200) /!<DMA disable selection (Single ADC) /
bogdanm	20:4263a77256ae	1349	#define ADC_CR2_EOCS ((uint32_t)0x00000400) /!<End of conversion selection /
bogdanm	20:4263a77256ae	1350	#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /!<Data Alignment /
bogdanm	20:4263a77256ae	1351	#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /!<JEXTSEL[3:0] bits (External event select for injected group) /
bogdanm	20:4263a77256ae	1352	#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /!<Bit 0 /
bogdanm	20:4263a77256ae	1353	#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /!<Bit 1 /
bogdanm	20:4263a77256ae	1354	#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /!<Bit 2 /
bogdanm	20:4263a77256ae	1355	#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /!<Bit 3 /
bogdanm	20:4263a77256ae	1356	#define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) /
bogdanm	20:4263a77256ae	1357	#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /!<Bit 0 /
bogdanm	20:4263a77256ae	1358	#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /!<Bit 1 /
bogdanm	20:4263a77256ae	1359	#define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /!<Start Conversion of injected channels /
bogdanm	20:4263a77256ae	1360	#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /!<EXTSEL[3:0] bits (External Event Select for regular group) /
bogdanm	20:4263a77256ae	1361	#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /!<Bit 0 /
bogdanm	20:4263a77256ae	1362	#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /!<Bit 1 /
bogdanm	20:4263a77256ae	1363	#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /!<Bit 2 /
bogdanm	20:4263a77256ae	1364	#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /!<Bit 3 /
bogdanm	20:4263a77256ae	1365	#define ADC_CR2_EXTEN ((uint32_t)0x30000000) /!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) /
bogdanm	20:4263a77256ae	1366	#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /!<Bit 0 /
bogdanm	20:4263a77256ae	1367	#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /!<Bit 1 /
bogdanm	20:4263a77256ae	1368	#define ADC_CR2_SWSTART ((uint32_t)0x40000000) /!<Start Conversion of regular channels /
bogdanm	20:4263a77256ae	1369
bogdanm	20:4263a77256ae	1370	/**************** Bit definition for ADC_SMPR1 register *****************/
bogdanm	20:4263a77256ae	1371	#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /!<SMP10[2:0] bits (Channel 10 Sample time selection) /
bogdanm	20:4263a77256ae	1372	#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	20:4263a77256ae	1373	#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	20:4263a77256ae	1374	#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /!<Bit 2 /
bogdanm	20:4263a77256ae	1375	#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /!<SMP11[2:0] bits (Channel 11 Sample time selection) /
bogdanm	20:4263a77256ae	1376	#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /!<Bit 0 /
bogdanm	20:4263a77256ae	1377	#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /!<Bit 1 /
bogdanm	20:4263a77256ae	1378	#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /!<Bit 2 /
bogdanm	20:4263a77256ae	1379	#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /!<SMP12[2:0] bits (Channel 12 Sample time selection) /
bogdanm	20:4263a77256ae	1380	#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /!<Bit 0 /
bogdanm	20:4263a77256ae	1381	#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /!<Bit 1 /
bogdanm	20:4263a77256ae	1382	#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /!<Bit 2 /
bogdanm	20:4263a77256ae	1383	#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /!<SMP13[2:0] bits (Channel 13 Sample time selection) /
bogdanm	20:4263a77256ae	1384	#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /!<Bit 0 /
bogdanm	20:4263a77256ae	1385	#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /!<Bit 1 /
bogdanm	20:4263a77256ae	1386	#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /!<Bit 2 /
bogdanm	20:4263a77256ae	1387	#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /!<SMP14[2:0] bits (Channel 14 Sample time selection) /
bogdanm	20:4263a77256ae	1388	#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /!<Bit 0 /
bogdanm	20:4263a77256ae	1389	#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /!<Bit 1 /
bogdanm	20:4263a77256ae	1390	#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /!<Bit 2 /
bogdanm	20:4263a77256ae	1391	#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /!<SMP15[2:0] bits (Channel 15 Sample time selection) /
bogdanm	20:4263a77256ae	1392	#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /!<Bit 0 /
bogdanm	20:4263a77256ae	1393	#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /!<Bit 1 /
bogdanm	20:4263a77256ae	1394	#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /!<Bit 2 /
bogdanm	20:4263a77256ae	1395	#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /!<SMP16[2:0] bits (Channel 16 Sample time selection) /
bogdanm	20:4263a77256ae	1396	#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /!<Bit 0 /
bogdanm	20:4263a77256ae	1397	#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /!<Bit 1 /
bogdanm	20:4263a77256ae	1398	#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /!<Bit 2 /
bogdanm	20:4263a77256ae	1399	#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /!<SMP17[2:0] bits (Channel 17 Sample time selection) /
bogdanm	20:4263a77256ae	1400	#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /!<Bit 0 /
bogdanm	20:4263a77256ae	1401	#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /!<Bit 1 /
bogdanm	20:4263a77256ae	1402	#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /!<Bit 2 /
bogdanm	20:4263a77256ae	1403	#define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /!<SMP18[2:0] bits (Channel 18 Sample time selection) /
bogdanm	20:4263a77256ae	1404	#define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /!<Bit 0 /
bogdanm	20:4263a77256ae	1405	#define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /!<Bit 1 /
bogdanm	20:4263a77256ae	1406	#define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /!<Bit 2 /
bogdanm	20:4263a77256ae	1407
bogdanm	20:4263a77256ae	1408	/**************** Bit definition for ADC_SMPR2 register *****************/
bogdanm	20:4263a77256ae	1409	#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /!<SMP0[2:0] bits (Channel 0 Sample time selection) /
bogdanm	20:4263a77256ae	1410	#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	20:4263a77256ae	1411	#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	20:4263a77256ae	1412	#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /!<Bit 2 /
bogdanm	20:4263a77256ae	1413	#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /!<SMP1[2:0] bits (Channel 1 Sample time selection) /
bogdanm	20:4263a77256ae	1414	#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /!<Bit 0 /
bogdanm	20:4263a77256ae	1415	#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /!<Bit 1 /
bogdanm	20:4263a77256ae	1416	#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /!<Bit 2 /
bogdanm	20:4263a77256ae	1417	#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /!<SMP2[2:0] bits (Channel 2 Sample time selection) /
bogdanm	20:4263a77256ae	1418	#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /!<Bit 0 /
bogdanm	20:4263a77256ae	1419	#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /!<Bit 1 /
bogdanm	20:4263a77256ae	1420	#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /!<Bit 2 /
bogdanm	20:4263a77256ae	1421	#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /!<SMP3[2:0] bits (Channel 3 Sample time selection) /
bogdanm	20:4263a77256ae	1422	#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /!<Bit 0 /
bogdanm	20:4263a77256ae	1423	#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /!<Bit 1 /
bogdanm	20:4263a77256ae	1424	#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /!<Bit 2 /
bogdanm	20:4263a77256ae	1425	#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /!<SMP4[2:0] bits (Channel 4 Sample time selection) /
bogdanm	20:4263a77256ae	1426	#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /!<Bit 0 /
bogdanm	20:4263a77256ae	1427	#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /!<Bit 1 /
bogdanm	20:4263a77256ae	1428	#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /!<Bit 2 /
bogdanm	20:4263a77256ae	1429	#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /!<SMP5[2:0] bits (Channel 5 Sample time selection) /
bogdanm	20:4263a77256ae	1430	#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /!<Bit 0 /
bogdanm	20:4263a77256ae	1431	#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /!<Bit 1 /
bogdanm	20:4263a77256ae	1432	#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /!<Bit 2 /
bogdanm	20:4263a77256ae	1433	#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /!<SMP6[2:0] bits (Channel 6 Sample time selection) /
bogdanm	20:4263a77256ae	1434	#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /!<Bit 0 /
bogdanm	20:4263a77256ae	1435	#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /!<Bit 1 /
bogdanm	20:4263a77256ae	1436	#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /!<Bit 2 /
bogdanm	20:4263a77256ae	1437	#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /!<SMP7[2:0] bits (Channel 7 Sample time selection) /
bogdanm	20:4263a77256ae	1438	#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /!<Bit 0 /
bogdanm	20:4263a77256ae	1439	#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /!<Bit 1 /
bogdanm	20:4263a77256ae	1440	#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /!<Bit 2 /
bogdanm	20:4263a77256ae	1441	#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /!<SMP8[2:0] bits (Channel 8 Sample time selection) /
bogdanm	20:4263a77256ae	1442	#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /!<Bit 0 /
bogdanm	20:4263a77256ae	1443	#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /!<Bit 1 /
bogdanm	20:4263a77256ae	1444	#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /!<Bit 2 /
bogdanm	20:4263a77256ae	1445	#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /!<SMP9[2:0] bits (Channel 9 Sample time selection) /
bogdanm	20:4263a77256ae	1446	#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /!<Bit 0 /
bogdanm	20:4263a77256ae	1447	#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /!<Bit 1 /
bogdanm	20:4263a77256ae	1448	#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /!<Bit 2 /
bogdanm	20:4263a77256ae	1449
bogdanm	20:4263a77256ae	1450	/**************** Bit definition for ADC_JOFR1 register *****************/
bogdanm	20:4263a77256ae	1451	#define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) /!<Data offset for injected channel 1 /
bogdanm	20:4263a77256ae	1452
bogdanm	20:4263a77256ae	1453	/**************** Bit definition for ADC_JOFR2 register *****************/
bogdanm	20:4263a77256ae	1454	#define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) /!<Data offset for injected channel 2 /
bogdanm	20:4263a77256ae	1455
bogdanm	20:4263a77256ae	1456	/**************** Bit definition for ADC_JOFR3 register *****************/
bogdanm	20:4263a77256ae	1457	#define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) /!<Data offset for injected channel 3 /
bogdanm	20:4263a77256ae	1458
bogdanm	20:4263a77256ae	1459	/**************** Bit definition for ADC_JOFR4 register *****************/
bogdanm	20:4263a77256ae	1460	#define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) /!<Data offset for injected channel 4 /
bogdanm	20:4263a77256ae	1461
bogdanm	20:4263a77256ae	1462	/***************** Bit definition for ADC_HTR register ******************/
bogdanm	20:4263a77256ae	1463	#define ADC_HTR_HT ((uint16_t)0x0FFF) /!<Analog watchdog high threshold /
bogdanm	20:4263a77256ae	1464
bogdanm	20:4263a77256ae	1465	/***************** Bit definition for ADC_LTR register ******************/
bogdanm	20:4263a77256ae	1466	#define ADC_LTR_LT ((uint16_t)0x0FFF) /!<Analog watchdog low threshold /
bogdanm	20:4263a77256ae	1467
bogdanm	20:4263a77256ae	1468	/***************** Bit definition for ADC_SQR1 register *****************/
bogdanm	20:4263a77256ae	1469	#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /!<SQ13[4:0] bits (13th conversion in regular sequence) /
bogdanm	20:4263a77256ae	1470	#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	20:4263a77256ae	1471	#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	20:4263a77256ae	1472	#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /!<Bit 2 /
bogdanm	20:4263a77256ae	1473	#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /!<Bit 3 /
bogdanm	20:4263a77256ae	1474	#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /!<Bit 4 /
bogdanm	20:4263a77256ae	1475	#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /!<SQ14[4:0] bits (14th conversion in regular sequence) /
bogdanm	20:4263a77256ae	1476	#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /!<Bit 0 /
bogdanm	20:4263a77256ae	1477	#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /!<Bit 1 /
bogdanm	20:4263a77256ae	1478	#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /!<Bit 2 /
bogdanm	20:4263a77256ae	1479	#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /!<Bit 3 /
bogdanm	20:4263a77256ae	1480	#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /!<Bit 4 /
bogdanm	20:4263a77256ae	1481	#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /!<SQ15[4:0] bits (15th conversion in regular sequence) /
bogdanm	20:4263a77256ae	1482	#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /!<Bit 0 /
bogdanm	20:4263a77256ae	1483	#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /!<Bit 1 /
bogdanm	20:4263a77256ae	1484	#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /!<Bit 2 /
bogdanm	20:4263a77256ae	1485	#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /!<Bit 3 /
bogdanm	20:4263a77256ae	1486	#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /!<Bit 4 /
bogdanm	20:4263a77256ae	1487	#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /!<SQ16[4:0] bits (16th conversion in regular sequence) /
bogdanm	20:4263a77256ae	1488	#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /!<Bit 0 /
bogdanm	20:4263a77256ae	1489	#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /!<Bit 1 /
bogdanm	20:4263a77256ae	1490	#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /!<Bit 2 /
bogdanm	20:4263a77256ae	1491	#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /!<Bit 3 /
bogdanm	20:4263a77256ae	1492	#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /!<Bit 4 /
bogdanm	20:4263a77256ae	1493	#define ADC_SQR1_L ((uint32_t)0x00F00000) /!<L[3:0] bits (Regular channel sequence length) /
bogdanm	20:4263a77256ae	1494	#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /!<Bit 0 /
bogdanm	20:4263a77256ae	1495	#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /!<Bit 1 /
bogdanm	20:4263a77256ae	1496	#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /!<Bit 2 /
bogdanm	20:4263a77256ae	1497	#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /!<Bit 3 /
bogdanm	20:4263a77256ae	1498
bogdanm	20:4263a77256ae	1499	/***************** Bit definition for ADC_SQR2 register *****************/
bogdanm	20:4263a77256ae	1500	#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /!<SQ7[4:0] bits (7th conversion in regular sequence) /
bogdanm	20:4263a77256ae	1501	#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	20:4263a77256ae	1502	#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	20:4263a77256ae	1503	#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /!<Bit 2 /
bogdanm	20:4263a77256ae	1504	#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /!<Bit 3 /
bogdanm	20:4263a77256ae	1505	#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /!<Bit 4 /
bogdanm	20:4263a77256ae	1506	#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /!<SQ8[4:0] bits (8th conversion in regular sequence) /
bogdanm	20:4263a77256ae	1507	#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /!<Bit 0 /
bogdanm	20:4263a77256ae	1508	#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /!<Bit 1 /
bogdanm	20:4263a77256ae	1509	#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /!<Bit 2 /
bogdanm	20:4263a77256ae	1510	#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /!<Bit 3 /
bogdanm	20:4263a77256ae	1511	#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /!<Bit 4 /
bogdanm	20:4263a77256ae	1512	#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /!<SQ9[4:0] bits (9th conversion in regular sequence) /
bogdanm	20:4263a77256ae	1513	#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /!<Bit 0 /
bogdanm	20:4263a77256ae	1514	#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /!<Bit 1 /
bogdanm	20:4263a77256ae	1515	#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /!<Bit 2 /
bogdanm	20:4263a77256ae	1516	#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /!<Bit 3 /
bogdanm	20:4263a77256ae	1517	#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /!<Bit 4 /
bogdanm	20:4263a77256ae	1518	#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /!<SQ10[4:0] bits (10th conversion in regular sequence) /
bogdanm	20:4263a77256ae	1519	#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /!<Bit 0 /
bogdanm	20:4263a77256ae	1520	#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /!<Bit 1 /
bogdanm	20:4263a77256ae	1521	#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /!<Bit 2 /
bogdanm	20:4263a77256ae	1522	#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /!<Bit 3 /
bogdanm	20:4263a77256ae	1523	#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /!<Bit 4 /
bogdanm	20:4263a77256ae	1524	#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /!<SQ11[4:0] bits (11th conversion in regular sequence) /
bogdanm	20:4263a77256ae	1525	#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /!<Bit 0 /
bogdanm	20:4263a77256ae	1526	#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /!<Bit 1 /
bogdanm	20:4263a77256ae	1527	#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /!<Bit 2 /
bogdanm	20:4263a77256ae	1528	#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /!<Bit 3 /
bogdanm	20:4263a77256ae	1529	#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /!<Bit 4 /
bogdanm	20:4263a77256ae	1530	#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /!<SQ12[4:0] bits (12th conversion in regular sequence) /
bogdanm	20:4263a77256ae	1531	#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /!<Bit 0 /
bogdanm	20:4263a77256ae	1532	#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /!<Bit 1 /
bogdanm	20:4263a77256ae	1533	#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /!<Bit 2 /
bogdanm	20:4263a77256ae	1534	#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /!<Bit 3 /
bogdanm	20:4263a77256ae	1535	#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /!<Bit 4 /
bogdanm	20:4263a77256ae	1536
bogdanm	20:4263a77256ae	1537	/***************** Bit definition for ADC_SQR3 register *****************/
bogdanm	20:4263a77256ae	1538	#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /!<SQ1[4:0] bits (1st conversion in regular sequence) /
bogdanm	20:4263a77256ae	1539	#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	20:4263a77256ae	1540	#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	20:4263a77256ae	1541	#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /!<Bit 2 /
bogdanm	20:4263a77256ae	1542	#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /!<Bit 3 /
bogdanm	20:4263a77256ae	1543	#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /!<Bit 4 /
bogdanm	20:4263a77256ae	1544	#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /!<SQ2[4:0] bits (2nd conversion in regular sequence) /
bogdanm	20:4263a77256ae	1545	#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /!<Bit 0 /
bogdanm	20:4263a77256ae	1546	#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /!<Bit 1 /
bogdanm	20:4263a77256ae	1547	#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /!<Bit 2 /
bogdanm	20:4263a77256ae	1548	#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /!<Bit 3 /
bogdanm	20:4263a77256ae	1549	#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /!<Bit 4 /
bogdanm	20:4263a77256ae	1550	#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /!<SQ3[4:0] bits (3rd conversion in regular sequence) /
bogdanm	20:4263a77256ae	1551	#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /!<Bit 0 /
bogdanm	20:4263a77256ae	1552	#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /!<Bit 1 /
bogdanm	20:4263a77256ae	1553	#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /!<Bit 2 /
bogdanm	20:4263a77256ae	1554	#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /!<Bit 3 /
bogdanm	20:4263a77256ae	1555	#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /!<Bit 4 /
bogdanm	20:4263a77256ae	1556	#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /!<SQ4[4:0] bits (4th conversion in regular sequence) /
bogdanm	20:4263a77256ae	1557	#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /!<Bit 0 /
bogdanm	20:4263a77256ae	1558	#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /!<Bit 1 /
bogdanm	20:4263a77256ae	1559	#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /!<Bit 2 /
bogdanm	20:4263a77256ae	1560	#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /!<Bit 3 /
bogdanm	20:4263a77256ae	1561	#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /!<Bit 4 /
bogdanm	20:4263a77256ae	1562	#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /!<SQ5[4:0] bits (5th conversion in regular sequence) /
bogdanm	20:4263a77256ae	1563	#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /!<Bit 0 /
bogdanm	20:4263a77256ae	1564	#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /!<Bit 1 /
bogdanm	20:4263a77256ae	1565	#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /!<Bit 2 /
bogdanm	20:4263a77256ae	1566	#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /!<Bit 3 /
bogdanm	20:4263a77256ae	1567	#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /!<Bit 4 /
bogdanm	20:4263a77256ae	1568	#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /!<SQ6[4:0] bits (6th conversion in regular sequence) /
bogdanm	20:4263a77256ae	1569	#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /!<Bit 0 /
bogdanm	20:4263a77256ae	1570	#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /!<Bit 1 /
bogdanm	20:4263a77256ae	1571	#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /!<Bit 2 /
bogdanm	20:4263a77256ae	1572	#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /!<Bit 3 /
bogdanm	20:4263a77256ae	1573	#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /!<Bit 4 /
bogdanm	20:4263a77256ae	1574
bogdanm	20:4263a77256ae	1575	/***************** Bit definition for ADC_JSQR register *****************/
bogdanm	20:4263a77256ae	1576	#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /!<JSQ1[4:0] bits (1st conversion in injected sequence) /
bogdanm	20:4263a77256ae	1577	#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	20:4263a77256ae	1578	#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	20:4263a77256ae	1579	#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /!<Bit 2 /
bogdanm	20:4263a77256ae	1580	#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /!<Bit 3 /
bogdanm	20:4263a77256ae	1581	#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /!<Bit 4 /
bogdanm	20:4263a77256ae	1582	#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /!<JSQ2[4:0] bits (2nd conversion in injected sequence) /
bogdanm	20:4263a77256ae	1583	#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /!<Bit 0 /
bogdanm	20:4263a77256ae	1584	#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /!<Bit 1 /
bogdanm	20:4263a77256ae	1585	#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /!<Bit 2 /
bogdanm	20:4263a77256ae	1586	#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /!<Bit 3 /
bogdanm	20:4263a77256ae	1587	#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /!<Bit 4 /
bogdanm	20:4263a77256ae	1588	#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /!<JSQ3[4:0] bits (3rd conversion in injected sequence) /
bogdanm	20:4263a77256ae	1589	#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /!<Bit 0 /
bogdanm	20:4263a77256ae	1590	#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /!<Bit 1 /
bogdanm	20:4263a77256ae	1591	#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /!<Bit 2 /
bogdanm	20:4263a77256ae	1592	#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /!<Bit 3 /
bogdanm	20:4263a77256ae	1593	#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /!<Bit 4 /
bogdanm	20:4263a77256ae	1594	#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /!<JSQ4[4:0] bits (4th conversion in injected sequence) /
bogdanm	20:4263a77256ae	1595	#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /!<Bit 0 /
bogdanm	20:4263a77256ae	1596	#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /!<Bit 1 /
bogdanm	20:4263a77256ae	1597	#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /!<Bit 2 /
bogdanm	20:4263a77256ae	1598	#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /!<Bit 3 /
bogdanm	20:4263a77256ae	1599	#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /!<Bit 4 /
bogdanm	20:4263a77256ae	1600	#define ADC_JSQR_JL ((uint32_t)0x00300000) /!<JL[1:0] bits (Injected Sequence length) /
bogdanm	20:4263a77256ae	1601	#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /!<Bit 0 /
bogdanm	20:4263a77256ae	1602	#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /!<Bit 1 /
bogdanm	20:4263a77256ae	1603
bogdanm	20:4263a77256ae	1604	/***************** Bit definition for ADC_JDR1 register *****************/
bogdanm	20:4263a77256ae	1605	#define ADC_JDR1_JDATA ((uint16_t)0xFFFF) /!<Injected data /
bogdanm	20:4263a77256ae	1606
bogdanm	20:4263a77256ae	1607	/***************** Bit definition for ADC_JDR2 register *****************/
bogdanm	20:4263a77256ae	1608	#define ADC_JDR2_JDATA ((uint16_t)0xFFFF) /!<Injected data /
bogdanm	20:4263a77256ae	1609
bogdanm	20:4263a77256ae	1610	/***************** Bit definition for ADC_JDR3 register *****************/
bogdanm	20:4263a77256ae	1611	#define ADC_JDR3_JDATA ((uint16_t)0xFFFF) /!<Injected data /
bogdanm	20:4263a77256ae	1612
bogdanm	20:4263a77256ae	1613	/***************** Bit definition for ADC_JDR4 register *****************/
bogdanm	20:4263a77256ae	1614	#define ADC_JDR4_JDATA ((uint16_t)0xFFFF) /!<Injected data /
bogdanm	20:4263a77256ae	1615
bogdanm	20:4263a77256ae	1616	/****************** Bit definition for ADC_DR register ******************/
bogdanm	20:4263a77256ae	1617	#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /!<Regular data /
bogdanm	20:4263a77256ae	1618	#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /!<ADC2 data /
bogdanm	20:4263a77256ae	1619
bogdanm	20:4263a77256ae	1620	/***************** Bit definition for ADC_CSR register ******************/
bogdanm	20:4263a77256ae	1621	#define ADC_CSR_AWD1 ((uint32_t)0x00000001) /!<ADC1 Analog watchdog flag /
bogdanm	20:4263a77256ae	1622	#define ADC_CSR_EOC1 ((uint32_t)0x00000002) /!<ADC1 End of conversion /
bogdanm	20:4263a77256ae	1623	#define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /!<ADC1 Injected channel end of conversion /
bogdanm	20:4263a77256ae	1624	#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /!<ADC1 Injected channel Start flag /
bogdanm	20:4263a77256ae	1625	#define ADC_CSR_STRT1 ((uint32_t)0x00000010) /!<ADC1 Regular channel Start flag /
bogdanm	20:4263a77256ae	1626	#define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /!<ADC1 DMA overrun flag /
bogdanm	20:4263a77256ae	1627	#define ADC_CSR_AWD2 ((uint32_t)0x00000100) /!<ADC2 Analog watchdog flag /
bogdanm	20:4263a77256ae	1628	#define ADC_CSR_EOC2 ((uint32_t)0x00000200) /!<ADC2 End of conversion /
bogdanm	20:4263a77256ae	1629	#define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /!<ADC2 Injected channel end of conversion /
bogdanm	20:4263a77256ae	1630	#define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /!<ADC2 Injected channel Start flag /
bogdanm	20:4263a77256ae	1631	#define ADC_CSR_STRT2 ((uint32_t)0x00001000) /!<ADC2 Regular channel Start flag /
bogdanm	20:4263a77256ae	1632	#define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /!<ADC2 DMA overrun flag /
bogdanm	20:4263a77256ae	1633	#define ADC_CSR_AWD3 ((uint32_t)0x00010000) /!<ADC3 Analog watchdog flag /
bogdanm	20:4263a77256ae	1634	#define ADC_CSR_EOC3 ((uint32_t)0x00020000) /!<ADC3 End of conversion /
bogdanm	20:4263a77256ae	1635	#define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /!<ADC3 Injected channel end of conversion /
bogdanm	20:4263a77256ae	1636	#define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /!<ADC3 Injected channel Start flag /
bogdanm	20:4263a77256ae	1637	#define ADC_CSR_STRT3 ((uint32_t)0x00100000) /!<ADC3 Regular channel Start flag /
bogdanm	20:4263a77256ae	1638	#define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /!<ADC3 DMA overrun flag /
bogdanm	20:4263a77256ae	1639
bogdanm	20:4263a77256ae	1640	/***************** Bit definition for ADC_CCR register ******************/
bogdanm	20:4263a77256ae	1641	#define ADC_CCR_MULTI ((uint32_t)0x0000001F) /!<MULTI[4:0] bits (Multi-ADC mode selection) /
bogdanm	20:4263a77256ae	1642	#define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	20:4263a77256ae	1643	#define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	20:4263a77256ae	1644	#define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /!<Bit 2 /
bogdanm	20:4263a77256ae	1645	#define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /!<Bit 3 /
bogdanm	20:4263a77256ae	1646	#define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /!<Bit 4 /
bogdanm	20:4263a77256ae	1647	#define ADC_CCR_DELAY ((uint32_t)0x00000F00) /!<DELAY[3:0] bits (Delay between 2 sampling phases) /
bogdanm	20:4263a77256ae	1648	#define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /!<Bit 0 /
bogdanm	20:4263a77256ae	1649	#define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /!<Bit 1 /
bogdanm	20:4263a77256ae	1650	#define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /!<Bit 2 /
bogdanm	20:4263a77256ae	1651	#define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /!<Bit 3 /
bogdanm	20:4263a77256ae	1652	#define ADC_CCR_DDS ((uint32_t)0x00002000) /!<DMA disable selection (Multi-ADC mode) /
bogdanm	20:4263a77256ae	1653	#define ADC_CCR_DMA ((uint32_t)0x0000C000) /!<DMA[1:0] bits (Direct Memory Access mode for multimode) /
bogdanm	20:4263a77256ae	1654	#define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /!<Bit 0 /
bogdanm	20:4263a77256ae	1655	#define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /!<Bit 1 /
bogdanm	20:4263a77256ae	1656	#define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /!<ADCPRE[1:0] bits (ADC prescaler) /
bogdanm	20:4263a77256ae	1657	#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /!<Bit 0 /
bogdanm	20:4263a77256ae	1658	#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /!<Bit 1 /
bogdanm	20:4263a77256ae	1659	#define ADC_CCR_VBATE ((uint32_t)0x00400000) /!<VBAT Enable /
bogdanm	20:4263a77256ae	1660	#define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /!<Temperature Sensor and VREFINT Enable /
bogdanm	20:4263a77256ae	1661
bogdanm	20:4263a77256ae	1662	/***************** Bit definition for ADC_CDR register ******************/
bogdanm	20:4263a77256ae	1663	#define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /!<1st data of a pair of regular conversions /
bogdanm	20:4263a77256ae	1664	#define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /!<2nd data of a pair of regular conversions /
bogdanm	20:4263a77256ae	1665
bogdanm	20:4263a77256ae	1666	/******************************************************************************/
bogdanm	20:4263a77256ae	1667	/* */
bogdanm	20:4263a77256ae	1668	/* Controller Area Network */
bogdanm	20:4263a77256ae	1669	/* */
bogdanm	20:4263a77256ae	1670	/******************************************************************************/
bogdanm	20:4263a77256ae	1671	/!<CAN control and status registers /
bogdanm	20:4263a77256ae	1672	/***************** Bit definition for CAN_MCR register ******************/
bogdanm	20:4263a77256ae	1673	#define CAN_MCR_INRQ ((uint16_t)0x0001) /!<Initialization Request /
bogdanm	20:4263a77256ae	1674	#define CAN_MCR_SLEEP ((uint16_t)0x0002) /!<Sleep Mode Request /
bogdanm	20:4263a77256ae	1675	#define CAN_MCR_TXFP ((uint16_t)0x0004) /!<Transmit FIFO Priority /
bogdanm	20:4263a77256ae	1676	#define CAN_MCR_RFLM ((uint16_t)0x0008) /!<Receive FIFO Locked Mode /
bogdanm	20:4263a77256ae	1677	#define CAN_MCR_NART ((uint16_t)0x0010) /!<No Automatic Retransmission /
bogdanm	20:4263a77256ae	1678	#define CAN_MCR_AWUM ((uint16_t)0x0020) /!<Automatic Wakeup Mode /
bogdanm	20:4263a77256ae	1679	#define CAN_MCR_ABOM ((uint16_t)0x0040) /!<Automatic Bus-Off Management /
bogdanm	20:4263a77256ae	1680	#define CAN_MCR_TTCM ((uint16_t)0x0080) /!<Time Triggered Communication Mode /
bogdanm	20:4263a77256ae	1681	#define CAN_MCR_RESET ((uint16_t)0x8000) /!<bxCAN software master reset /
bogdanm	20:4263a77256ae	1682
bogdanm	20:4263a77256ae	1683	/***************** Bit definition for CAN_MSR register ******************/
bogdanm	20:4263a77256ae	1684	#define CAN_MSR_INAK ((uint16_t)0x0001) /!<Initialization Acknowledge /
bogdanm	20:4263a77256ae	1685	#define CAN_MSR_SLAK ((uint16_t)0x0002) /!<Sleep Acknowledge /
bogdanm	20:4263a77256ae	1686	#define CAN_MSR_ERRI ((uint16_t)0x0004) /!<Error Interrupt /
bogdanm	20:4263a77256ae	1687	#define CAN_MSR_WKUI ((uint16_t)0x0008) /!<Wakeup Interrupt /
bogdanm	20:4263a77256ae	1688	#define CAN_MSR_SLAKI ((uint16_t)0x0010) /!<Sleep Acknowledge Interrupt /
bogdanm	20:4263a77256ae	1689	#define CAN_MSR_TXM ((uint16_t)0x0100) /!<Transmit Mode /
bogdanm	20:4263a77256ae	1690	#define CAN_MSR_RXM ((uint16_t)0x0200) /!<Receive Mode /
bogdanm	20:4263a77256ae	1691	#define CAN_MSR_SAMP ((uint16_t)0x0400) /!<Last Sample Point /
bogdanm	20:4263a77256ae	1692	#define CAN_MSR_RX ((uint16_t)0x0800) /!<CAN Rx Signal /
bogdanm	20:4263a77256ae	1693
bogdanm	20:4263a77256ae	1694	/***************** Bit definition for CAN_TSR register ******************/
bogdanm	20:4263a77256ae	1695	#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /!<Request Completed Mailbox0 /
bogdanm	20:4263a77256ae	1696	#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /!<Transmission OK of Mailbox0 /
bogdanm	20:4263a77256ae	1697	#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /!<Arbitration Lost for Mailbox0 /
bogdanm	20:4263a77256ae	1698	#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /!<Transmission Error of Mailbox0 /
bogdanm	20:4263a77256ae	1699	#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /!<Abort Request for Mailbox0 /
bogdanm	20:4263a77256ae	1700	#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /!<Request Completed Mailbox1 /
bogdanm	20:4263a77256ae	1701	#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /!<Transmission OK of Mailbox1 /
bogdanm	20:4263a77256ae	1702	#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /!<Arbitration Lost for Mailbox1 /
bogdanm	20:4263a77256ae	1703	#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /!<Transmission Error of Mailbox1 /
bogdanm	20:4263a77256ae	1704	#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /!<Abort Request for Mailbox 1 /
bogdanm	20:4263a77256ae	1705	#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /!<Request Completed Mailbox2 /
bogdanm	20:4263a77256ae	1706	#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /!<Transmission OK of Mailbox 2 /
bogdanm	20:4263a77256ae	1707	#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /!<Arbitration Lost for mailbox 2 /
bogdanm	20:4263a77256ae	1708	#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /!<Transmission Error of Mailbox 2 /
bogdanm	20:4263a77256ae	1709	#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /!<Abort Request for Mailbox 2 /
bogdanm	20:4263a77256ae	1710	#define CAN_TSR_CODE ((uint32_t)0x03000000) /!<Mailbox Code /
bogdanm	20:4263a77256ae	1711
bogdanm	20:4263a77256ae	1712	#define CAN_TSR_TME ((uint32_t)0x1C000000) /!<TME[2:0] bits /
bogdanm	20:4263a77256ae	1713	#define CAN_TSR_TME0 ((uint32_t)0x04000000) /!<Transmit Mailbox 0 Empty /
bogdanm	20:4263a77256ae	1714	#define CAN_TSR_TME1 ((uint32_t)0x08000000) /!<Transmit Mailbox 1 Empty /
bogdanm	20:4263a77256ae	1715	#define CAN_TSR_TME2 ((uint32_t)0x10000000) /!<Transmit Mailbox 2 Empty /
bogdanm	20:4263a77256ae	1716
bogdanm	20:4263a77256ae	1717	#define CAN_TSR_LOW ((uint32_t)0xE0000000) /!<LOW[2:0] bits /
bogdanm	20:4263a77256ae	1718	#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /!<Lowest Priority Flag for Mailbox 0 /
bogdanm	20:4263a77256ae	1719	#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /!<Lowest Priority Flag for Mailbox 1 /
bogdanm	20:4263a77256ae	1720	#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /!<Lowest Priority Flag for Mailbox 2 /
bogdanm	20:4263a77256ae	1721
bogdanm	20:4263a77256ae	1722	/***************** Bit definition for CAN_RF0R register *****************/
bogdanm	20:4263a77256ae	1723	#define CAN_RF0R_FMP0 ((uint8_t)0x03) /!<FIFO 0 Message Pending /
bogdanm	20:4263a77256ae	1724	#define CAN_RF0R_FULL0 ((uint8_t)0x08) /!<FIFO 0 Full /
bogdanm	20:4263a77256ae	1725	#define CAN_RF0R_FOVR0 ((uint8_t)0x10) /!<FIFO 0 Overrun /
bogdanm	20:4263a77256ae	1726	#define CAN_RF0R_RFOM0 ((uint8_t)0x20) /!<Release FIFO 0 Output Mailbox /
bogdanm	20:4263a77256ae	1727
bogdanm	20:4263a77256ae	1728	/***************** Bit definition for CAN_RF1R register *****************/
bogdanm	20:4263a77256ae	1729	#define CAN_RF1R_FMP1 ((uint8_t)0x03) /!<FIFO 1 Message Pending /
bogdanm	20:4263a77256ae	1730	#define CAN_RF1R_FULL1 ((uint8_t)0x08) /!<FIFO 1 Full /
bogdanm	20:4263a77256ae	1731	#define CAN_RF1R_FOVR1 ((uint8_t)0x10) /!<FIFO 1 Overrun /
bogdanm	20:4263a77256ae	1732	#define CAN_RF1R_RFOM1 ((uint8_t)0x20) /!<Release FIFO 1 Output Mailbox /
bogdanm	20:4263a77256ae	1733
bogdanm	20:4263a77256ae	1734	/****************** Bit definition for CAN_IER register *****************/
bogdanm	20:4263a77256ae	1735	#define CAN_IER_TMEIE ((uint32_t)0x00000001) /!<Transmit Mailbox Empty Interrupt Enable /
bogdanm	20:4263a77256ae	1736	#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /!<FIFO Message Pending Interrupt Enable /
bogdanm	20:4263a77256ae	1737	#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /!<FIFO Full Interrupt Enable /
bogdanm	20:4263a77256ae	1738	#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /!<FIFO Overrun Interrupt Enable /
bogdanm	20:4263a77256ae	1739	#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /!<FIFO Message Pending Interrupt Enable /
bogdanm	20:4263a77256ae	1740	#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /!<FIFO Full Interrupt Enable /
bogdanm	20:4263a77256ae	1741	#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /!<FIFO Overrun Interrupt Enable /
bogdanm	20:4263a77256ae	1742	#define CAN_IER_EWGIE ((uint32_t)0x00000100) /!<Error Warning Interrupt Enable /
bogdanm	20:4263a77256ae	1743	#define CAN_IER_EPVIE ((uint32_t)0x00000200) /!<Error Passive Interrupt Enable /
bogdanm	20:4263a77256ae	1744	#define CAN_IER_BOFIE ((uint32_t)0x00000400) /!<Bus-Off Interrupt Enable /
bogdanm	20:4263a77256ae	1745	#define CAN_IER_LECIE ((uint32_t)0x00000800) /!<Last Error Code Interrupt Enable /
bogdanm	20:4263a77256ae	1746	#define CAN_IER_ERRIE ((uint32_t)0x00008000) /!<Error Interrupt Enable /
bogdanm	20:4263a77256ae	1747	#define CAN_IER_WKUIE ((uint32_t)0x00010000) /!<Wakeup Interrupt Enable /
bogdanm	20:4263a77256ae	1748	#define CAN_IER_SLKIE ((uint32_t)0x00020000) /!<Sleep Interrupt Enable /
bogdanm	20:4263a77256ae	1749
bogdanm	20:4263a77256ae	1750	/****************** Bit definition for CAN_ESR register *****************/
bogdanm	20:4263a77256ae	1751	#define CAN_ESR_EWGF ((uint32_t)0x00000001) /!<Error Warning Flag /
bogdanm	20:4263a77256ae	1752	#define CAN_ESR_EPVF ((uint32_t)0x00000002) /!<Error Passive Flag /
bogdanm	20:4263a77256ae	1753	#define CAN_ESR_BOFF ((uint32_t)0x00000004) /!<Bus-Off Flag /
bogdanm	20:4263a77256ae	1754
bogdanm	20:4263a77256ae	1755	#define CAN_ESR_LEC ((uint32_t)0x00000070) /!<LEC[2:0] bits (Last Error Code) /
bogdanm	20:4263a77256ae	1756	#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	20:4263a77256ae	1757	#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	20:4263a77256ae	1758	#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /!<Bit 2 /
bogdanm	20:4263a77256ae	1759
bogdanm	20:4263a77256ae	1760	#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /!<Least significant byte of the 9-bit Transmit Error Counter /
bogdanm	20:4263a77256ae	1761	#define CAN_ESR_REC ((uint32_t)0xFF000000) /!<Receive Error Counter /
bogdanm	20:4263a77256ae	1762
bogdanm	20:4263a77256ae	1763	/***************** Bit definition for CAN_BTR register ******************/
bogdanm	20:4263a77256ae	1764	#define CAN_BTR_BRP ((uint32_t)0x000003FF) /!<Baud Rate Prescaler /
bogdanm	20:4263a77256ae	1765	#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /!<Time Segment 1 /
bogdanm	20:4263a77256ae	1766	#define CAN_BTR_TS2 ((uint32_t)0x00700000) /!<Time Segment 2 /
bogdanm	20:4263a77256ae	1767	#define CAN_BTR_SJW ((uint32_t)0x03000000) /!<Resynchronization Jump Width /
bogdanm	20:4263a77256ae	1768	#define CAN_BTR_LBKM ((uint32_t)0x40000000) /!<Loop Back Mode (Debug) /
bogdanm	20:4263a77256ae	1769	#define CAN_BTR_SILM ((uint32_t)0x80000000) /!<Silent Mode /
bogdanm	20:4263a77256ae	1770
bogdanm	20:4263a77256ae	1771	/!<Mailbox registers /
bogdanm	20:4263a77256ae	1772	/**************** Bit definition for CAN_TI0R register ******************/
bogdanm	20:4263a77256ae	1773	#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /!<Transmit Mailbox Request /
bogdanm	20:4263a77256ae	1774	#define CAN_TI0R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
bogdanm	20:4263a77256ae	1775	#define CAN_TI0R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
bogdanm	20:4263a77256ae	1776	#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /!<Extended Identifier /
bogdanm	20:4263a77256ae	1777	#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
bogdanm	20:4263a77256ae	1778
bogdanm	20:4263a77256ae	1779	/**************** Bit definition for CAN_TDT0R register *****************/
bogdanm	20:4263a77256ae	1780	#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
bogdanm	20:4263a77256ae	1781	#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /!<Transmit Global Time /
bogdanm	20:4263a77256ae	1782	#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
bogdanm	20:4263a77256ae	1783
bogdanm	20:4263a77256ae	1784	/**************** Bit definition for CAN_TDL0R register *****************/
bogdanm	20:4263a77256ae	1785	#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
bogdanm	20:4263a77256ae	1786	#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
bogdanm	20:4263a77256ae	1787	#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
bogdanm	20:4263a77256ae	1788	#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
bogdanm	20:4263a77256ae	1789
bogdanm	20:4263a77256ae	1790	/**************** Bit definition for CAN_TDH0R register *****************/
bogdanm	20:4263a77256ae	1791	#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
bogdanm	20:4263a77256ae	1792	#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
bogdanm	20:4263a77256ae	1793	#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
bogdanm	20:4263a77256ae	1794	#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
bogdanm	20:4263a77256ae	1795
bogdanm	20:4263a77256ae	1796	/***************** Bit definition for CAN_TI1R register *****************/
bogdanm	20:4263a77256ae	1797	#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /!<Transmit Mailbox Request /
bogdanm	20:4263a77256ae	1798	#define CAN_TI1R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
bogdanm	20:4263a77256ae	1799	#define CAN_TI1R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
bogdanm	20:4263a77256ae	1800	#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /!<Extended Identifier /
bogdanm	20:4263a77256ae	1801	#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
bogdanm	20:4263a77256ae	1802
bogdanm	20:4263a77256ae	1803	/***************** Bit definition for CAN_TDT1R register ****************/
bogdanm	20:4263a77256ae	1804	#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
bogdanm	20:4263a77256ae	1805	#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /!<Transmit Global Time /
bogdanm	20:4263a77256ae	1806	#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
bogdanm	20:4263a77256ae	1807
bogdanm	20:4263a77256ae	1808	/***************** Bit definition for CAN_TDL1R register ****************/
bogdanm	20:4263a77256ae	1809	#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
bogdanm	20:4263a77256ae	1810	#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
bogdanm	20:4263a77256ae	1811	#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
bogdanm	20:4263a77256ae	1812	#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
bogdanm	20:4263a77256ae	1813
bogdanm	20:4263a77256ae	1814	/***************** Bit definition for CAN_TDH1R register ****************/
bogdanm	20:4263a77256ae	1815	#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
bogdanm	20:4263a77256ae	1816	#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
bogdanm	20:4263a77256ae	1817	#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
bogdanm	20:4263a77256ae	1818	#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
bogdanm	20:4263a77256ae	1819
bogdanm	20:4263a77256ae	1820	/***************** Bit definition for CAN_TI2R register *****************/
bogdanm	20:4263a77256ae	1821	#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /!<Transmit Mailbox Request /
bogdanm	20:4263a77256ae	1822	#define CAN_TI2R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
bogdanm	20:4263a77256ae	1823	#define CAN_TI2R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
bogdanm	20:4263a77256ae	1824	#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /!<Extended identifier /
bogdanm	20:4263a77256ae	1825	#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
bogdanm	20:4263a77256ae	1826
bogdanm	20:4263a77256ae	1827	/***************** Bit definition for CAN_TDT2R register ****************/
bogdanm	20:4263a77256ae	1828	#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
bogdanm	20:4263a77256ae	1829	#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /!<Transmit Global Time /
bogdanm	20:4263a77256ae	1830	#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
bogdanm	20:4263a77256ae	1831
bogdanm	20:4263a77256ae	1832	/***************** Bit definition for CAN_TDL2R register ****************/
bogdanm	20:4263a77256ae	1833	#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
bogdanm	20:4263a77256ae	1834	#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
bogdanm	20:4263a77256ae	1835	#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
bogdanm	20:4263a77256ae	1836	#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
bogdanm	20:4263a77256ae	1837
bogdanm	20:4263a77256ae	1838	/***************** Bit definition for CAN_TDH2R register ****************/
bogdanm	20:4263a77256ae	1839	#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
bogdanm	20:4263a77256ae	1840	#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
bogdanm	20:4263a77256ae	1841	#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
bogdanm	20:4263a77256ae	1842	#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
bogdanm	20:4263a77256ae	1843
bogdanm	20:4263a77256ae	1844	/***************** Bit definition for CAN_RI0R register *****************/
bogdanm	20:4263a77256ae	1845	#define CAN_RI0R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
bogdanm	20:4263a77256ae	1846	#define CAN_RI0R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
bogdanm	20:4263a77256ae	1847	#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /!<Extended Identifier /
bogdanm	20:4263a77256ae	1848	#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
bogdanm	20:4263a77256ae	1849
bogdanm	20:4263a77256ae	1850	/***************** Bit definition for CAN_RDT0R register ****************/
bogdanm	20:4263a77256ae	1851	#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
bogdanm	20:4263a77256ae	1852	#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /!<Filter Match Index /
bogdanm	20:4263a77256ae	1853	#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
bogdanm	20:4263a77256ae	1854
bogdanm	20:4263a77256ae	1855	/***************** Bit definition for CAN_RDL0R register ****************/
bogdanm	20:4263a77256ae	1856	#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
bogdanm	20:4263a77256ae	1857	#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
bogdanm	20:4263a77256ae	1858	#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
bogdanm	20:4263a77256ae	1859	#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
bogdanm	20:4263a77256ae	1860
bogdanm	20:4263a77256ae	1861	/***************** Bit definition for CAN_RDH0R register ****************/
bogdanm	20:4263a77256ae	1862	#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
bogdanm	20:4263a77256ae	1863	#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
bogdanm	20:4263a77256ae	1864	#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
bogdanm	20:4263a77256ae	1865	#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
bogdanm	20:4263a77256ae	1866
bogdanm	20:4263a77256ae	1867	/***************** Bit definition for CAN_RI1R register *****************/
bogdanm	20:4263a77256ae	1868	#define CAN_RI1R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
bogdanm	20:4263a77256ae	1869	#define CAN_RI1R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
bogdanm	20:4263a77256ae	1870	#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /!<Extended identifier /
bogdanm	20:4263a77256ae	1871	#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
bogdanm	20:4263a77256ae	1872
bogdanm	20:4263a77256ae	1873	/***************** Bit definition for CAN_RDT1R register ****************/
bogdanm	20:4263a77256ae	1874	#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
bogdanm	20:4263a77256ae	1875	#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /!<Filter Match Index /
bogdanm	20:4263a77256ae	1876	#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
bogdanm	20:4263a77256ae	1877
bogdanm	20:4263a77256ae	1878	/***************** Bit definition for CAN_RDL1R register ****************/
bogdanm	20:4263a77256ae	1879	#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
bogdanm	20:4263a77256ae	1880	#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
bogdanm	20:4263a77256ae	1881	#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
bogdanm	20:4263a77256ae	1882	#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
bogdanm	20:4263a77256ae	1883
bogdanm	20:4263a77256ae	1884	/***************** Bit definition for CAN_RDH1R register ****************/
bogdanm	20:4263a77256ae	1885	#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
bogdanm	20:4263a77256ae	1886	#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
bogdanm	20:4263a77256ae	1887	#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
bogdanm	20:4263a77256ae	1888	#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
bogdanm	20:4263a77256ae	1889
bogdanm	20:4263a77256ae	1890	/!<CAN filter registers /
bogdanm	20:4263a77256ae	1891	/***************** Bit definition for CAN_FMR register ******************/
bogdanm	20:4263a77256ae	1892	#define CAN_FMR_FINIT ((uint8_t)0x01) /!<Filter Init Mode /
bogdanm	20:4263a77256ae	1893
bogdanm	20:4263a77256ae	1894	/***************** Bit definition for CAN_FM1R register *****************/
bogdanm	20:4263a77256ae	1895	#define CAN_FM1R_FBM ((uint16_t)0x3FFF) /!<Filter Mode /
bogdanm	20:4263a77256ae	1896	#define CAN_FM1R_FBM0 ((uint16_t)0x0001) /!<Filter Init Mode bit 0 /
bogdanm	20:4263a77256ae	1897	#define CAN_FM1R_FBM1 ((uint16_t)0x0002) /!<Filter Init Mode bit 1 /
bogdanm	20:4263a77256ae	1898	#define CAN_FM1R_FBM2 ((uint16_t)0x0004) /!<Filter Init Mode bit 2 /
bogdanm	20:4263a77256ae	1899	#define CAN_FM1R_FBM3 ((uint16_t)0x0008) /!<Filter Init Mode bit 3 /
bogdanm	20:4263a77256ae	1900	#define CAN_FM1R_FBM4 ((uint16_t)0x0010) /!<Filter Init Mode bit 4 /
bogdanm	20:4263a77256ae	1901	#define CAN_FM1R_FBM5 ((uint16_t)0x0020) /!<Filter Init Mode bit 5 /
bogdanm	20:4263a77256ae	1902	#define CAN_FM1R_FBM6 ((uint16_t)0x0040) /!<Filter Init Mode bit 6 /
bogdanm	20:4263a77256ae	1903	#define CAN_FM1R_FBM7 ((uint16_t)0x0080) /!<Filter Init Mode bit 7 /
bogdanm	20:4263a77256ae	1904	#define CAN_FM1R_FBM8 ((uint16_t)0x0100) /!<Filter Init Mode bit 8 /
bogdanm	20:4263a77256ae	1905	#define CAN_FM1R_FBM9 ((uint16_t)0x0200) /!<Filter Init Mode bit 9 /
bogdanm	20:4263a77256ae	1906	#define CAN_FM1R_FBM10 ((uint16_t)0x0400) /!<Filter Init Mode bit 10 /
bogdanm	20:4263a77256ae	1907	#define CAN_FM1R_FBM11 ((uint16_t)0x0800) /!<Filter Init Mode bit 11 /
bogdanm	20:4263a77256ae	1908	#define CAN_FM1R_FBM12 ((uint16_t)0x1000) /!<Filter Init Mode bit 12 /
bogdanm	20:4263a77256ae	1909	#define CAN_FM1R_FBM13 ((uint16_t)0x2000) /!<Filter Init Mode bit 13 /
bogdanm	20:4263a77256ae	1910
bogdanm	20:4263a77256ae	1911	/***************** Bit definition for CAN_FS1R register *****************/
bogdanm	20:4263a77256ae	1912	#define CAN_FS1R_FSC ((uint16_t)0x3FFF) /!<Filter Scale Configuration /
bogdanm	20:4263a77256ae	1913	#define CAN_FS1R_FSC0 ((uint16_t)0x0001) /!<Filter Scale Configuration bit 0 /
bogdanm	20:4263a77256ae	1914	#define CAN_FS1R_FSC1 ((uint16_t)0x0002) /!<Filter Scale Configuration bit 1 /
bogdanm	20:4263a77256ae	1915	#define CAN_FS1R_FSC2 ((uint16_t)0x0004) /!<Filter Scale Configuration bit 2 /
bogdanm	20:4263a77256ae	1916	#define CAN_FS1R_FSC3 ((uint16_t)0x0008) /!<Filter Scale Configuration bit 3 /
bogdanm	20:4263a77256ae	1917	#define CAN_FS1R_FSC4 ((uint16_t)0x0010) /!<Filter Scale Configuration bit 4 /
bogdanm	20:4263a77256ae	1918	#define CAN_FS1R_FSC5 ((uint16_t)0x0020) /!<Filter Scale Configuration bit 5 /
bogdanm	20:4263a77256ae	1919	#define CAN_FS1R_FSC6 ((uint16_t)0x0040) /!<Filter Scale Configuration bit 6 /
bogdanm	20:4263a77256ae	1920	#define CAN_FS1R_FSC7 ((uint16_t)0x0080) /!<Filter Scale Configuration bit 7 /
bogdanm	20:4263a77256ae	1921	#define CAN_FS1R_FSC8 ((uint16_t)0x0100) /!<Filter Scale Configuration bit 8 /
bogdanm	20:4263a77256ae	1922	#define CAN_FS1R_FSC9 ((uint16_t)0x0200) /!<Filter Scale Configuration bit 9 /
bogdanm	20:4263a77256ae	1923	#define CAN_FS1R_FSC10 ((uint16_t)0x0400) /!<Filter Scale Configuration bit 10 /
bogdanm	20:4263a77256ae	1924	#define CAN_FS1R_FSC11 ((uint16_t)0x0800) /!<Filter Scale Configuration bit 11 /
bogdanm	20:4263a77256ae	1925	#define CAN_FS1R_FSC12 ((uint16_t)0x1000) /!<Filter Scale Configuration bit 12 /
bogdanm	20:4263a77256ae	1926	#define CAN_FS1R_FSC13 ((uint16_t)0x2000) /!<Filter Scale Configuration bit 13 /
bogdanm	20:4263a77256ae	1927
bogdanm	20:4263a77256ae	1928	/**************** Bit definition for CAN_FFA1R register *****************/
bogdanm	20:4263a77256ae	1929	#define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /!<Filter FIFO Assignment /
bogdanm	20:4263a77256ae	1930	#define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /!<Filter FIFO Assignment for Filter 0 /
bogdanm	20:4263a77256ae	1931	#define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /!<Filter FIFO Assignment for Filter 1 /
bogdanm	20:4263a77256ae	1932	#define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /!<Filter FIFO Assignment for Filter 2 /
bogdanm	20:4263a77256ae	1933	#define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /!<Filter FIFO Assignment for Filter 3 /
bogdanm	20:4263a77256ae	1934	#define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /!<Filter FIFO Assignment for Filter 4 /
bogdanm	20:4263a77256ae	1935	#define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /!<Filter FIFO Assignment for Filter 5 /
bogdanm	20:4263a77256ae	1936	#define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /!<Filter FIFO Assignment for Filter 6 /
bogdanm	20:4263a77256ae	1937	#define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /!<Filter FIFO Assignment for Filter 7 /
bogdanm	20:4263a77256ae	1938	#define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /!<Filter FIFO Assignment for Filter 8 /
bogdanm	20:4263a77256ae	1939	#define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /!<Filter FIFO Assignment for Filter 9 /
bogdanm	20:4263a77256ae	1940	#define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /!<Filter FIFO Assignment for Filter 10 /
bogdanm	20:4263a77256ae	1941	#define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /!<Filter FIFO Assignment for Filter 11 /
bogdanm	20:4263a77256ae	1942	#define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /!<Filter FIFO Assignment for Filter 12 /
bogdanm	20:4263a77256ae	1943	#define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /!<Filter FIFO Assignment for Filter 13 /
bogdanm	20:4263a77256ae	1944
bogdanm	20:4263a77256ae	1945	/***************** Bit definition for CAN_FA1R register *****************/
bogdanm	20:4263a77256ae	1946	#define CAN_FA1R_FACT ((uint16_t)0x3FFF) /!<Filter Active /
bogdanm	20:4263a77256ae	1947	#define CAN_FA1R_FACT0 ((uint16_t)0x0001) /!<Filter 0 Active /
bogdanm	20:4263a77256ae	1948	#define CAN_FA1R_FACT1 ((uint16_t)0x0002) /!<Filter 1 Active /
bogdanm	20:4263a77256ae	1949	#define CAN_FA1R_FACT2 ((uint16_t)0x0004) /!<Filter 2 Active /
bogdanm	20:4263a77256ae	1950	#define CAN_FA1R_FACT3 ((uint16_t)0x0008) /!<Filter 3 Active /
bogdanm	20:4263a77256ae	1951	#define CAN_FA1R_FACT4 ((uint16_t)0x0010) /!<Filter 4 Active /
bogdanm	20:4263a77256ae	1952	#define CAN_FA1R_FACT5 ((uint16_t)0x0020) /!<Filter 5 Active /
bogdanm	20:4263a77256ae	1953	#define CAN_FA1R_FACT6 ((uint16_t)0x0040) /!<Filter 6 Active /
bogdanm	20:4263a77256ae	1954	#define CAN_FA1R_FACT7 ((uint16_t)0x0080) /!<Filter 7 Active /
bogdanm	20:4263a77256ae	1955	#define CAN_FA1R_FACT8 ((uint16_t)0x0100) /!<Filter 8 Active /
bogdanm	20:4263a77256ae	1956	#define CAN_FA1R_FACT9 ((uint16_t)0x0200) /!<Filter 9 Active /
bogdanm	20:4263a77256ae	1957	#define CAN_FA1R_FACT10 ((uint16_t)0x0400) /!<Filter 10 Active /
bogdanm	20:4263a77256ae	1958	#define CAN_FA1R_FACT11 ((uint16_t)0x0800) /!<Filter 11 Active /
bogdanm	20:4263a77256ae	1959	#define CAN_FA1R_FACT12 ((uint16_t)0x1000) /!<Filter 12 Active /
bogdanm	20:4263a77256ae	1960	#define CAN_FA1R_FACT13 ((uint16_t)0x2000) /!<Filter 13 Active /
bogdanm	20:4263a77256ae	1961
bogdanm	20:4263a77256ae	1962	/***************** Bit definition for CAN_F0R1 register *****************/
bogdanm	20:4263a77256ae	1963	#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	20:4263a77256ae	1964	#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	20:4263a77256ae	1965	#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	20:4263a77256ae	1966	#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	20:4263a77256ae	1967	#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	20:4263a77256ae	1968	#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	20:4263a77256ae	1969	#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	20:4263a77256ae	1970	#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	20:4263a77256ae	1971	#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	20:4263a77256ae	1972	#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	20:4263a77256ae	1973	#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	20:4263a77256ae	1974	#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	20:4263a77256ae	1975	#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	20:4263a77256ae	1976	#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	20:4263a77256ae	1977	#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	20:4263a77256ae	1978	#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	20:4263a77256ae	1979	#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	20:4263a77256ae	1980	#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	20:4263a77256ae	1981	#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	20:4263a77256ae	1982	#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	20:4263a77256ae	1983	#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	20:4263a77256ae	1984	#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	20:4263a77256ae	1985	#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	20:4263a77256ae	1986	#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	20:4263a77256ae	1987	#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	20:4263a77256ae	1988	#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	20:4263a77256ae	1989	#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	20:4263a77256ae	1990	#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	20:4263a77256ae	1991	#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	20:4263a77256ae	1992	#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	20:4263a77256ae	1993	#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	20:4263a77256ae	1994	#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	20:4263a77256ae	1995
bogdanm	20:4263a77256ae	1996	/***************** Bit definition for CAN_F1R1 register *****************/
bogdanm	20:4263a77256ae	1997	#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	20:4263a77256ae	1998	#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	20:4263a77256ae	1999	#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	20:4263a77256ae	2000	#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	20:4263a77256ae	2001	#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	20:4263a77256ae	2002	#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	20:4263a77256ae	2003	#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	20:4263a77256ae	2004	#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	20:4263a77256ae	2005	#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	20:4263a77256ae	2006	#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	20:4263a77256ae	2007	#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	20:4263a77256ae	2008	#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	20:4263a77256ae	2009	#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	20:4263a77256ae	2010	#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	20:4263a77256ae	2011	#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	20:4263a77256ae	2012	#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	20:4263a77256ae	2013	#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	20:4263a77256ae	2014	#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	20:4263a77256ae	2015	#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	20:4263a77256ae	2016	#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	20:4263a77256ae	2017	#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	20:4263a77256ae	2018	#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	20:4263a77256ae	2019	#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	20:4263a77256ae	2020	#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	20:4263a77256ae	2021	#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	20:4263a77256ae	2022	#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	20:4263a77256ae	2023	#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	20:4263a77256ae	2024	#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	20:4263a77256ae	2025	#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	20:4263a77256ae	2026	#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	20:4263a77256ae	2027	#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	20:4263a77256ae	2028	#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	20:4263a77256ae	2029
bogdanm	20:4263a77256ae	2030	/***************** Bit definition for CAN_F2R1 register *****************/
bogdanm	20:4263a77256ae	2031	#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	20:4263a77256ae	2032	#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	20:4263a77256ae	2033	#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	20:4263a77256ae	2034	#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	20:4263a77256ae	2035	#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	20:4263a77256ae	2036	#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	20:4263a77256ae	2037	#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	20:4263a77256ae	2038	#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	20:4263a77256ae	2039	#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	20:4263a77256ae	2040	#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	20:4263a77256ae	2041	#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	20:4263a77256ae	2042	#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	20:4263a77256ae	2043	#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	20:4263a77256ae	2044	#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	20:4263a77256ae	2045	#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	20:4263a77256ae	2046	#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	20:4263a77256ae	2047	#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	20:4263a77256ae	2048	#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	20:4263a77256ae	2049	#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	20:4263a77256ae	2050	#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	20:4263a77256ae	2051	#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	20:4263a77256ae	2052	#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	20:4263a77256ae	2053	#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	20:4263a77256ae	2054	#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	20:4263a77256ae	2055	#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	20:4263a77256ae	2056	#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	20:4263a77256ae	2057	#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	20:4263a77256ae	2058	#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	20:4263a77256ae	2059	#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	20:4263a77256ae	2060	#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	20:4263a77256ae	2061	#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	20:4263a77256ae	2062	#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	20:4263a77256ae	2063
bogdanm	20:4263a77256ae	2064	/***************** Bit definition for CAN_F3R1 register *****************/
bogdanm	20:4263a77256ae	2065	#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	20:4263a77256ae	2066	#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	20:4263a77256ae	2067	#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	20:4263a77256ae	2068	#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	20:4263a77256ae	2069	#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	20:4263a77256ae	2070	#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	20:4263a77256ae	2071	#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	20:4263a77256ae	2072	#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	20:4263a77256ae	2073	#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	20:4263a77256ae	2074	#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	20:4263a77256ae	2075	#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	20:4263a77256ae	2076	#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	20:4263a77256ae	2077	#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	20:4263a77256ae	2078	#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	20:4263a77256ae	2079	#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	20:4263a77256ae	2080	#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	20:4263a77256ae	2081	#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	20:4263a77256ae	2082	#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	20:4263a77256ae	2083	#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	20:4263a77256ae	2084	#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	20:4263a77256ae	2085	#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	20:4263a77256ae	2086	#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	20:4263a77256ae	2087	#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	20:4263a77256ae	2088	#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	20:4263a77256ae	2089	#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	20:4263a77256ae	2090	#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	20:4263a77256ae	2091	#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	20:4263a77256ae	2092	#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	20:4263a77256ae	2093	#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	20:4263a77256ae	2094	#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	20:4263a77256ae	2095	#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	20:4263a77256ae	2096	#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	20:4263a77256ae	2097
bogdanm	20:4263a77256ae	2098	/***************** Bit definition for CAN_F4R1 register *****************/
bogdanm	20:4263a77256ae	2099	#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	20:4263a77256ae	2100	#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	20:4263a77256ae	2101	#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	20:4263a77256ae	2102	#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	20:4263a77256ae	2103	#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	20:4263a77256ae	2104	#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	20:4263a77256ae	2105	#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	20:4263a77256ae	2106	#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	20:4263a77256ae	2107	#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	20:4263a77256ae	2108	#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	20:4263a77256ae	2109	#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	20:4263a77256ae	2110	#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	20:4263a77256ae	2111	#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	20:4263a77256ae	2112	#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	20:4263a77256ae	2113	#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	20:4263a77256ae	2114	#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	20:4263a77256ae	2115	#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	20:4263a77256ae	2116	#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	20:4263a77256ae	2117	#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	20:4263a77256ae	2118	#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	20:4263a77256ae	2119	#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	20:4263a77256ae	2120	#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	20:4263a77256ae	2121	#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	20:4263a77256ae	2122	#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	20:4263a77256ae	2123	#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	20:4263a77256ae	2124	#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	20:4263a77256ae	2125	#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	20:4263a77256ae	2126	#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	20:4263a77256ae	2127	#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	20:4263a77256ae	2128	#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	20:4263a77256ae	2129	#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	20:4263a77256ae	2130	#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	20:4263a77256ae	2131
bogdanm	20:4263a77256ae	2132	/***************** Bit definition for CAN_F5R1 register *****************/
bogdanm	20:4263a77256ae	2133	#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	20:4263a77256ae	2134	#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	20:4263a77256ae	2135	#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	20:4263a77256ae	2136	#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	20:4263a77256ae	2137	#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	20:4263a77256ae	2138	#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	20:4263a77256ae	2139	#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	20:4263a77256ae	2140	#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	20:4263a77256ae	2141	#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	20:4263a77256ae	2142	#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	20:4263a77256ae	2143	#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	20:4263a77256ae	2144	#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	20:4263a77256ae	2145	#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	20:4263a77256ae	2146	#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	20:4263a77256ae	2147	#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	20:4263a77256ae	2148	#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	20:4263a77256ae	2149	#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	20:4263a77256ae	2150	#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	20:4263a77256ae	2151	#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	20:4263a77256ae	2152	#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	20:4263a77256ae	2153	#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	20:4263a77256ae	2154	#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	20:4263a77256ae	2155	#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	20:4263a77256ae	2156	#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	20:4263a77256ae	2157	#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	20:4263a77256ae	2158	#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	20:4263a77256ae	2159	#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	20:4263a77256ae	2160	#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	20:4263a77256ae	2161	#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	20:4263a77256ae	2162	#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	20:4263a77256ae	2163	#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	20:4263a77256ae	2164	#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	20:4263a77256ae	2165
bogdanm	20:4263a77256ae	2166	/***************** Bit definition for CAN_F6R1 register *****************/
bogdanm	20:4263a77256ae	2167	#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	20:4263a77256ae	2168	#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	20:4263a77256ae	2169	#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	20:4263a77256ae	2170	#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	20:4263a77256ae	2171	#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	20:4263a77256ae	2172	#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	20:4263a77256ae	2173	#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	20:4263a77256ae	2174	#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	20:4263a77256ae	2175	#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	20:4263a77256ae	2176	#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	20:4263a77256ae	2177	#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	20:4263a77256ae	2178	#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	20:4263a77256ae	2179	#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	20:4263a77256ae	2180	#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	20:4263a77256ae	2181	#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	20:4263a77256ae	2182	#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	20:4263a77256ae	2183	#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	20:4263a77256ae	2184	#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	20:4263a77256ae	2185	#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	20:4263a77256ae	2186	#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	20:4263a77256ae	2187	#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	20:4263a77256ae	2188	#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	20:4263a77256ae	2189	#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	20:4263a77256ae	2190	#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	20:4263a77256ae	2191	#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	20:4263a77256ae	2192	#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	20:4263a77256ae	2193	#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	20:4263a77256ae	2194	#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	20:4263a77256ae	2195	#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	20:4263a77256ae	2196	#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	20:4263a77256ae	2197	#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	20:4263a77256ae	2198	#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	20:4263a77256ae	2199
bogdanm	20:4263a77256ae	2200	/***************** Bit definition for CAN_F7R1 register *****************/
bogdanm	20:4263a77256ae	2201	#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	20:4263a77256ae	2202	#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	20:4263a77256ae	2203	#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	20:4263a77256ae	2204	#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	20:4263a77256ae	2205	#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	20:4263a77256ae	2206	#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	20:4263a77256ae	2207	#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	20:4263a77256ae	2208	#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	20:4263a77256ae	2209	#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	20:4263a77256ae	2210	#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	20:4263a77256ae	2211	#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	20:4263a77256ae	2212	#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	20:4263a77256ae	2213	#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	20:4263a77256ae	2214	#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	20:4263a77256ae	2215	#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	20:4263a77256ae	2216	#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	20:4263a77256ae	2217	#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	20:4263a77256ae	2218	#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	20:4263a77256ae	2219	#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	20:4263a77256ae	2220	#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	20:4263a77256ae	2221	#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	20:4263a77256ae	2222	#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	20:4263a77256ae	2223	#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	20:4263a77256ae	2224	#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	20:4263a77256ae	2225	#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	20:4263a77256ae	2226	#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	20:4263a77256ae	2227	#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	20:4263a77256ae	2228	#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	20:4263a77256ae	2229	#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	20:4263a77256ae	2230	#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	20:4263a77256ae	2231	#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	20:4263a77256ae	2232	#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	20:4263a77256ae	2233
bogdanm	20:4263a77256ae	2234	/***************** Bit definition for CAN_F8R1 register *****************/
bogdanm	20:4263a77256ae	2235	#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	20:4263a77256ae	2236	#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	20:4263a77256ae	2237	#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	20:4263a77256ae	2238	#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	20:4263a77256ae	2239	#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	20:4263a77256ae	2240	#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	20:4263a77256ae	2241	#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	20:4263a77256ae	2242	#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	20:4263a77256ae	2243	#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	20:4263a77256ae	2244	#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	20:4263a77256ae	2245	#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	20:4263a77256ae	2246	#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	20:4263a77256ae	2247	#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	20:4263a77256ae	2248	#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	20:4263a77256ae	2249	#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	20:4263a77256ae	2250	#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	20:4263a77256ae	2251	#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	20:4263a77256ae	2252	#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	20:4263a77256ae	2253	#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	20:4263a77256ae	2254	#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	20:4263a77256ae	2255	#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	20:4263a77256ae	2256	#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	20:4263a77256ae	2257	#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	20:4263a77256ae	2258	#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	20:4263a77256ae	2259	#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	20:4263a77256ae	2260	#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	20:4263a77256ae	2261	#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	20:4263a77256ae	2262	#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	20:4263a77256ae	2263	#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	20:4263a77256ae	2264	#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	20:4263a77256ae	2265	#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	20:4263a77256ae	2266	#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	20:4263a77256ae	2267
bogdanm	20:4263a77256ae	2268	/***************** Bit definition for CAN_F9R1 register *****************/
bogdanm	20:4263a77256ae	2269	#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	20:4263a77256ae	2270	#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	20:4263a77256ae	2271	#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	20:4263a77256ae	2272	#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	20:4263a77256ae	2273	#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	20:4263a77256ae	2274	#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	20:4263a77256ae	2275	#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	20:4263a77256ae	2276	#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	20:4263a77256ae	2277	#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	20:4263a77256ae	2278	#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	20:4263a77256ae	2279	#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	20:4263a77256ae	2280	#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	20:4263a77256ae	2281	#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	20:4263a77256ae	2282	#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	20:4263a77256ae	2283	#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	20:4263a77256ae	2284	#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	20:4263a77256ae	2285	#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	20:4263a77256ae	2286	#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	20:4263a77256ae	2287	#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	20:4263a77256ae	2288	#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	20:4263a77256ae	2289	#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	20:4263a77256ae	2290	#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	20:4263a77256ae	2291	#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	20:4263a77256ae	2292	#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	20:4263a77256ae	2293	#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	20:4263a77256ae	2294	#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	20:4263a77256ae	2295	#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	20:4263a77256ae	2296	#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	20:4263a77256ae	2297	#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	20:4263a77256ae	2298	#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	20:4263a77256ae	2299	#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	20:4263a77256ae	2300	#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	20:4263a77256ae	2301
bogdanm	20:4263a77256ae	2302	/***************** Bit definition for CAN_F10R1 register ****************/
bogdanm	20:4263a77256ae	2303	#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	20:4263a77256ae	2304	#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	20:4263a77256ae	2305	#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	20:4263a77256ae	2306	#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	20:4263a77256ae	2307	#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	20:4263a77256ae	2308	#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	20:4263a77256ae	2309	#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	20:4263a77256ae	2310	#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	20:4263a77256ae	2311	#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	20:4263a77256ae	2312	#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	20:4263a77256ae	2313	#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	20:4263a77256ae	2314	#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	20:4263a77256ae	2315	#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	20:4263a77256ae	2316	#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	20:4263a77256ae	2317	#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	20:4263a77256ae	2318	#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	20:4263a77256ae	2319	#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	20:4263a77256ae	2320	#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	20:4263a77256ae	2321	#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	20:4263a77256ae	2322	#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	20:4263a77256ae	2323	#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	20:4263a77256ae	2324	#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	20:4263a77256ae	2325	#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	20:4263a77256ae	2326	#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	20:4263a77256ae	2327	#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	20:4263a77256ae	2328	#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	20:4263a77256ae	2329	#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	20:4263a77256ae	2330	#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	20:4263a77256ae	2331	#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	20:4263a77256ae	2332	#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	20:4263a77256ae	2333	#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	20:4263a77256ae	2334	#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	20:4263a77256ae	2335
bogdanm	20:4263a77256ae	2336	/***************** Bit definition for CAN_F11R1 register ****************/
bogdanm	20:4263a77256ae	2337	#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	20:4263a77256ae	2338	#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	20:4263a77256ae	2339	#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	20:4263a77256ae	2340	#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	20:4263a77256ae	2341	#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	20:4263a77256ae	2342	#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	20:4263a77256ae	2343	#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	20:4263a77256ae	2344	#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	20:4263a77256ae	2345	#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	20:4263a77256ae	2346	#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	20:4263a77256ae	2347	#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	20:4263a77256ae	2348	#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	20:4263a77256ae	2349	#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	20:4263a77256ae	2350	#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	20:4263a77256ae	2351	#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	20:4263a77256ae	2352	#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	20:4263a77256ae	2353	#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	20:4263a77256ae	2354	#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	20:4263a77256ae	2355	#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	20:4263a77256ae	2356	#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	20:4263a77256ae	2357	#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	20:4263a77256ae	2358	#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	20:4263a77256ae	2359	#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	20:4263a77256ae	2360	#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	20:4263a77256ae	2361	#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	20:4263a77256ae	2362	#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	20:4263a77256ae	2363	#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	20:4263a77256ae	2364	#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	20:4263a77256ae	2365	#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	20:4263a77256ae	2366	#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	20:4263a77256ae	2367	#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	20:4263a77256ae	2368	#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	20:4263a77256ae	2369
bogdanm	20:4263a77256ae	2370	/***************** Bit definition for CAN_F12R1 register ****************/
bogdanm	20:4263a77256ae	2371	#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	20:4263a77256ae	2372	#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	20:4263a77256ae	2373	#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	20:4263a77256ae	2374	#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	20:4263a77256ae	2375	#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	20:4263a77256ae	2376	#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	20:4263a77256ae	2377	#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	20:4263a77256ae	2378	#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	20:4263a77256ae	2379	#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	20:4263a77256ae	2380	#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	20:4263a77256ae	2381	#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	20:4263a77256ae	2382	#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	20:4263a77256ae	2383	#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	20:4263a77256ae	2384	#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	20:4263a77256ae	2385	#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	20:4263a77256ae	2386	#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	20:4263a77256ae	2387	#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	20:4263a77256ae	2388	#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	20:4263a77256ae	2389	#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	20:4263a77256ae	2390	#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	20:4263a77256ae	2391	#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	20:4263a77256ae	2392	#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	20:4263a77256ae	2393	#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	20:4263a77256ae	2394	#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	20:4263a77256ae	2395	#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	20:4263a77256ae	2396	#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	20:4263a77256ae	2397	#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	20:4263a77256ae	2398	#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	20:4263a77256ae	2399	#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	20:4263a77256ae	2400	#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	20:4263a77256ae	2401	#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	20:4263a77256ae	2402	#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	20:4263a77256ae	2403
bogdanm	20:4263a77256ae	2404	/***************** Bit definition for CAN_F13R1 register ****************/
bogdanm	20:4263a77256ae	2405	#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	20:4263a77256ae	2406	#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	20:4263a77256ae	2407	#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	20:4263a77256ae	2408	#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	20:4263a77256ae	2409	#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	20:4263a77256ae	2410	#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	20:4263a77256ae	2411	#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	20:4263a77256ae	2412	#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	20:4263a77256ae	2413	#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	20:4263a77256ae	2414	#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	20:4263a77256ae	2415	#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	20:4263a77256ae	2416	#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	20:4263a77256ae	2417	#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	20:4263a77256ae	2418	#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	20:4263a77256ae	2419	#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	20:4263a77256ae	2420	#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	20:4263a77256ae	2421	#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	20:4263a77256ae	2422	#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	20:4263a77256ae	2423	#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	20:4263a77256ae	2424	#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	20:4263a77256ae	2425	#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	20:4263a77256ae	2426	#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	20:4263a77256ae	2427	#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	20:4263a77256ae	2428	#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	20:4263a77256ae	2429	#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	20:4263a77256ae	2430	#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	20:4263a77256ae	2431	#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	20:4263a77256ae	2432	#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	20:4263a77256ae	2433	#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	20:4263a77256ae	2434	#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	20:4263a77256ae	2435	#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	20:4263a77256ae	2436	#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	20:4263a77256ae	2437
bogdanm	20:4263a77256ae	2438	/***************** Bit definition for CAN_F0R2 register *****************/
bogdanm	20:4263a77256ae	2439	#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	20:4263a77256ae	2440	#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	20:4263a77256ae	2441	#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	20:4263a77256ae	2442	#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	20:4263a77256ae	2443	#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	20:4263a77256ae	2444	#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	20:4263a77256ae	2445	#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	20:4263a77256ae	2446	#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	20:4263a77256ae	2447	#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	20:4263a77256ae	2448	#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	20:4263a77256ae	2449	#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	20:4263a77256ae	2450	#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	20:4263a77256ae	2451	#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	20:4263a77256ae	2452	#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	20:4263a77256ae	2453	#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	20:4263a77256ae	2454	#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	20:4263a77256ae	2455	#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	20:4263a77256ae	2456	#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	20:4263a77256ae	2457	#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	20:4263a77256ae	2458	#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	20:4263a77256ae	2459	#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	20:4263a77256ae	2460	#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	20:4263a77256ae	2461	#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	20:4263a77256ae	2462	#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	20:4263a77256ae	2463	#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	20:4263a77256ae	2464	#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	20:4263a77256ae	2465	#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	20:4263a77256ae	2466	#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	20:4263a77256ae	2467	#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	20:4263a77256ae	2468	#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	20:4263a77256ae	2469	#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	20:4263a77256ae	2470	#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	20:4263a77256ae	2471
bogdanm	20:4263a77256ae	2472	/***************** Bit definition for CAN_F1R2 register *****************/
bogdanm	20:4263a77256ae	2473	#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	20:4263a77256ae	2474	#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	20:4263a77256ae	2475	#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	20:4263a77256ae	2476	#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	20:4263a77256ae	2477	#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	20:4263a77256ae	2478	#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	20:4263a77256ae	2479	#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	20:4263a77256ae	2480	#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	20:4263a77256ae	2481	#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	20:4263a77256ae	2482	#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	20:4263a77256ae	2483	#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	20:4263a77256ae	2484	#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	20:4263a77256ae	2485	#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	20:4263a77256ae	2486	#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	20:4263a77256ae	2487	#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	20:4263a77256ae	2488	#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	20:4263a77256ae	2489	#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	20:4263a77256ae	2490	#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	20:4263a77256ae	2491	#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	20:4263a77256ae	2492	#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	20:4263a77256ae	2493	#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	20:4263a77256ae	2494	#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	20:4263a77256ae	2495	#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	20:4263a77256ae	2496	#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	20:4263a77256ae	2497	#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	20:4263a77256ae	2498	#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	20:4263a77256ae	2499	#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	20:4263a77256ae	2500	#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	20:4263a77256ae	2501	#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	20:4263a77256ae	2502	#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	20:4263a77256ae	2503	#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	20:4263a77256ae	2504	#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	20:4263a77256ae	2505
bogdanm	20:4263a77256ae	2506	/***************** Bit definition for CAN_F2R2 register *****************/
bogdanm	20:4263a77256ae	2507	#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	20:4263a77256ae	2508	#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	20:4263a77256ae	2509	#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	20:4263a77256ae	2510	#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	20:4263a77256ae	2511	#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	20:4263a77256ae	2512	#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	20:4263a77256ae	2513	#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	20:4263a77256ae	2514	#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	20:4263a77256ae	2515	#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	20:4263a77256ae	2516	#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	20:4263a77256ae	2517	#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	20:4263a77256ae	2518	#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	20:4263a77256ae	2519	#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	20:4263a77256ae	2520	#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	20:4263a77256ae	2521	#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	20:4263a77256ae	2522	#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	20:4263a77256ae	2523	#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	20:4263a77256ae	2524	#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	20:4263a77256ae	2525	#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	20:4263a77256ae	2526	#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	20:4263a77256ae	2527	#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	20:4263a77256ae	2528	#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	20:4263a77256ae	2529	#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	20:4263a77256ae	2530	#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	20:4263a77256ae	2531	#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	20:4263a77256ae	2532	#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	20:4263a77256ae	2533	#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	20:4263a77256ae	2534	#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	20:4263a77256ae	2535	#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	20:4263a77256ae	2536	#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	20:4263a77256ae	2537	#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	20:4263a77256ae	2538	#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	20:4263a77256ae	2539
bogdanm	20:4263a77256ae	2540	/***************** Bit definition for CAN_F3R2 register *****************/
bogdanm	20:4263a77256ae	2541	#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	20:4263a77256ae	2542	#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	20:4263a77256ae	2543	#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	20:4263a77256ae	2544	#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	20:4263a77256ae	2545	#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	20:4263a77256ae	2546	#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	20:4263a77256ae	2547	#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	20:4263a77256ae	2548	#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	20:4263a77256ae	2549	#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	20:4263a77256ae	2550	#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	20:4263a77256ae	2551	#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	20:4263a77256ae	2552	#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	20:4263a77256ae	2553	#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	20:4263a77256ae	2554	#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	20:4263a77256ae	2555	#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	20:4263a77256ae	2556	#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	20:4263a77256ae	2557	#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	20:4263a77256ae	2558	#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	20:4263a77256ae	2559	#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	20:4263a77256ae	2560	#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	20:4263a77256ae	2561	#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	20:4263a77256ae	2562	#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	20:4263a77256ae	2563	#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	20:4263a77256ae	2564	#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	20:4263a77256ae	2565	#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	20:4263a77256ae	2566	#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	20:4263a77256ae	2567	#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	20:4263a77256ae	2568	#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	20:4263a77256ae	2569	#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	20:4263a77256ae	2570	#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	20:4263a77256ae	2571	#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	20:4263a77256ae	2572	#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	20:4263a77256ae	2573
bogdanm	20:4263a77256ae	2574	/***************** Bit definition for CAN_F4R2 register *****************/
bogdanm	20:4263a77256ae	2575	#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	20:4263a77256ae	2576	#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	20:4263a77256ae	2577	#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	20:4263a77256ae	2578	#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	20:4263a77256ae	2579	#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	20:4263a77256ae	2580	#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	20:4263a77256ae	2581	#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	20:4263a77256ae	2582	#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	20:4263a77256ae	2583	#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	20:4263a77256ae	2584	#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	20:4263a77256ae	2585	#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	20:4263a77256ae	2586	#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	20:4263a77256ae	2587	#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	20:4263a77256ae	2588	#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	20:4263a77256ae	2589	#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	20:4263a77256ae	2590	#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	20:4263a77256ae	2591	#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	20:4263a77256ae	2592	#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	20:4263a77256ae	2593	#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	20:4263a77256ae	2594	#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	20:4263a77256ae	2595	#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	20:4263a77256ae	2596	#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	20:4263a77256ae	2597	#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	20:4263a77256ae	2598	#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	20:4263a77256ae	2599	#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	20:4263a77256ae	2600	#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	20:4263a77256ae	2601	#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	20:4263a77256ae	2602	#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	20:4263a77256ae	2603	#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	20:4263a77256ae	2604	#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	20:4263a77256ae	2605	#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	20:4263a77256ae	2606	#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	20:4263a77256ae	2607
bogdanm	20:4263a77256ae	2608	/***************** Bit definition for CAN_F5R2 register *****************/
bogdanm	20:4263a77256ae	2609	#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	20:4263a77256ae	2610	#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	20:4263a77256ae	2611	#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	20:4263a77256ae	2612	#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	20:4263a77256ae	2613	#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	20:4263a77256ae	2614	#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	20:4263a77256ae	2615	#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	20:4263a77256ae	2616	#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	20:4263a77256ae	2617	#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	20:4263a77256ae	2618	#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	20:4263a77256ae	2619	#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	20:4263a77256ae	2620	#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	20:4263a77256ae	2621	#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	20:4263a77256ae	2622	#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	20:4263a77256ae	2623	#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	20:4263a77256ae	2624	#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	20:4263a77256ae	2625	#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	20:4263a77256ae	2626	#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	20:4263a77256ae	2627	#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	20:4263a77256ae	2628	#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	20:4263a77256ae	2629	#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	20:4263a77256ae	2630	#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	20:4263a77256ae	2631	#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	20:4263a77256ae	2632	#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	20:4263a77256ae	2633	#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	20:4263a77256ae	2634	#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	20:4263a77256ae	2635	#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	20:4263a77256ae	2636	#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	20:4263a77256ae	2637	#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	20:4263a77256ae	2638	#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	20:4263a77256ae	2639	#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	20:4263a77256ae	2640	#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	20:4263a77256ae	2641
bogdanm	20:4263a77256ae	2642	/***************** Bit definition for CAN_F6R2 register *****************/
bogdanm	20:4263a77256ae	2643	#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	20:4263a77256ae	2644	#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	20:4263a77256ae	2645	#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	20:4263a77256ae	2646	#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	20:4263a77256ae	2647	#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	20:4263a77256ae	2648	#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	20:4263a77256ae	2649	#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	20:4263a77256ae	2650	#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	20:4263a77256ae	2651	#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	20:4263a77256ae	2652	#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	20:4263a77256ae	2653	#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	20:4263a77256ae	2654	#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	20:4263a77256ae	2655	#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	20:4263a77256ae	2656	#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	20:4263a77256ae	2657	#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	20:4263a77256ae	2658	#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	20:4263a77256ae	2659	#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	20:4263a77256ae	2660	#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	20:4263a77256ae	2661	#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	20:4263a77256ae	2662	#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	20:4263a77256ae	2663	#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	20:4263a77256ae	2664	#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	20:4263a77256ae	2665	#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	20:4263a77256ae	2666	#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	20:4263a77256ae	2667	#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	20:4263a77256ae	2668	#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	20:4263a77256ae	2669	#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	20:4263a77256ae	2670	#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	20:4263a77256ae	2671	#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	20:4263a77256ae	2672	#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	20:4263a77256ae	2673	#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	20:4263a77256ae	2674	#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	20:4263a77256ae	2675
bogdanm	20:4263a77256ae	2676	/***************** Bit definition for CAN_F7R2 register *****************/
bogdanm	20:4263a77256ae	2677	#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	20:4263a77256ae	2678	#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	20:4263a77256ae	2679	#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	20:4263a77256ae	2680	#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	20:4263a77256ae	2681	#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	20:4263a77256ae	2682	#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	20:4263a77256ae	2683	#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	20:4263a77256ae	2684	#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	20:4263a77256ae	2685	#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	20:4263a77256ae	2686	#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	20:4263a77256ae	2687	#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	20:4263a77256ae	2688	#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	20:4263a77256ae	2689	#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	20:4263a77256ae	2690	#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	20:4263a77256ae	2691	#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	20:4263a77256ae	2692	#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	20:4263a77256ae	2693	#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	20:4263a77256ae	2694	#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	20:4263a77256ae	2695	#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	20:4263a77256ae	2696	#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	20:4263a77256ae	2697	#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	20:4263a77256ae	2698	#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	20:4263a77256ae	2699	#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	20:4263a77256ae	2700	#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	20:4263a77256ae	2701	#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	20:4263a77256ae	2702	#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	20:4263a77256ae	2703	#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	20:4263a77256ae	2704	#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	20:4263a77256ae	2705	#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	20:4263a77256ae	2706	#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	20:4263a77256ae	2707	#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	20:4263a77256ae	2708	#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	20:4263a77256ae	2709
bogdanm	20:4263a77256ae	2710	/***************** Bit definition for CAN_F8R2 register *****************/
bogdanm	20:4263a77256ae	2711	#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	20:4263a77256ae	2712	#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	20:4263a77256ae	2713	#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	20:4263a77256ae	2714	#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	20:4263a77256ae	2715	#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	20:4263a77256ae	2716	#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	20:4263a77256ae	2717	#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	20:4263a77256ae	2718	#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	20:4263a77256ae	2719	#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	20:4263a77256ae	2720	#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	20:4263a77256ae	2721	#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	20:4263a77256ae	2722	#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	20:4263a77256ae	2723	#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	20:4263a77256ae	2724	#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	20:4263a77256ae	2725	#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	20:4263a77256ae	2726	#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	20:4263a77256ae	2727	#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	20:4263a77256ae	2728	#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	20:4263a77256ae	2729	#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	20:4263a77256ae	2730	#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	20:4263a77256ae	2731	#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	20:4263a77256ae	2732	#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	20:4263a77256ae	2733	#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	20:4263a77256ae	2734	#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	20:4263a77256ae	2735	#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	20:4263a77256ae	2736	#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	20:4263a77256ae	2737	#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	20:4263a77256ae	2738	#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	20:4263a77256ae	2739	#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	20:4263a77256ae	2740	#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	20:4263a77256ae	2741	#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	20:4263a77256ae	2742	#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	20:4263a77256ae	2743
bogdanm	20:4263a77256ae	2744	/***************** Bit definition for CAN_F9R2 register *****************/
bogdanm	20:4263a77256ae	2745	#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	20:4263a77256ae	2746	#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	20:4263a77256ae	2747	#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	20:4263a77256ae	2748	#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	20:4263a77256ae	2749	#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	20:4263a77256ae	2750	#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	20:4263a77256ae	2751	#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	20:4263a77256ae	2752	#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	20:4263a77256ae	2753	#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	20:4263a77256ae	2754	#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	20:4263a77256ae	2755	#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	20:4263a77256ae	2756	#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	20:4263a77256ae	2757	#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	20:4263a77256ae	2758	#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	20:4263a77256ae	2759	#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	20:4263a77256ae	2760	#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	20:4263a77256ae	2761	#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	20:4263a77256ae	2762	#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	20:4263a77256ae	2763	#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	20:4263a77256ae	2764	#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	20:4263a77256ae	2765	#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	20:4263a77256ae	2766	#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	20:4263a77256ae	2767	#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	20:4263a77256ae	2768	#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	20:4263a77256ae	2769	#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	20:4263a77256ae	2770	#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	20:4263a77256ae	2771	#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	20:4263a77256ae	2772	#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	20:4263a77256ae	2773	#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	20:4263a77256ae	2774	#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	20:4263a77256ae	2775	#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	20:4263a77256ae	2776	#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	20:4263a77256ae	2777
bogdanm	20:4263a77256ae	2778	/***************** Bit definition for CAN_F10R2 register ****************/
bogdanm	20:4263a77256ae	2779	#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	20:4263a77256ae	2780	#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	20:4263a77256ae	2781	#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	20:4263a77256ae	2782	#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	20:4263a77256ae	2783	#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	20:4263a77256ae	2784	#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	20:4263a77256ae	2785	#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	20:4263a77256ae	2786	#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	20:4263a77256ae	2787	#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	20:4263a77256ae	2788	#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	20:4263a77256ae	2789	#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	20:4263a77256ae	2790	#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	20:4263a77256ae	2791	#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	20:4263a77256ae	2792	#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	20:4263a77256ae	2793	#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	20:4263a77256ae	2794	#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	20:4263a77256ae	2795	#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	20:4263a77256ae	2796	#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	20:4263a77256ae	2797	#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	20:4263a77256ae	2798	#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	20:4263a77256ae	2799	#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	20:4263a77256ae	2800	#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	20:4263a77256ae	2801	#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	20:4263a77256ae	2802	#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	20:4263a77256ae	2803	#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	20:4263a77256ae	2804	#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	20:4263a77256ae	2805	#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	20:4263a77256ae	2806	#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	20:4263a77256ae	2807	#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	20:4263a77256ae	2808	#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	20:4263a77256ae	2809	#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	20:4263a77256ae	2810	#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	20:4263a77256ae	2811
bogdanm	20:4263a77256ae	2812	/***************** Bit definition for CAN_F11R2 register ****************/
bogdanm	20:4263a77256ae	2813	#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	20:4263a77256ae	2814	#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	20:4263a77256ae	2815	#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	20:4263a77256ae	2816	#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	20:4263a77256ae	2817	#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	20:4263a77256ae	2818	#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	20:4263a77256ae	2819	#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	20:4263a77256ae	2820	#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	20:4263a77256ae	2821	#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	20:4263a77256ae	2822	#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	20:4263a77256ae	2823	#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	20:4263a77256ae	2824	#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	20:4263a77256ae	2825	#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	20:4263a77256ae	2826	#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	20:4263a77256ae	2827	#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	20:4263a77256ae	2828	#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	20:4263a77256ae	2829	#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	20:4263a77256ae	2830	#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	20:4263a77256ae	2831	#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	20:4263a77256ae	2832	#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	20:4263a77256ae	2833	#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	20:4263a77256ae	2834	#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	20:4263a77256ae	2835	#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	20:4263a77256ae	2836	#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	20:4263a77256ae	2837	#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	20:4263a77256ae	2838	#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	20:4263a77256ae	2839	#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	20:4263a77256ae	2840	#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	20:4263a77256ae	2841	#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	20:4263a77256ae	2842	#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	20:4263a77256ae	2843	#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	20:4263a77256ae	2844	#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	20:4263a77256ae	2845
bogdanm	20:4263a77256ae	2846	/***************** Bit definition for CAN_F12R2 register ****************/
bogdanm	20:4263a77256ae	2847	#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	20:4263a77256ae	2848	#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	20:4263a77256ae	2849	#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	20:4263a77256ae	2850	#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	20:4263a77256ae	2851	#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	20:4263a77256ae	2852	#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	20:4263a77256ae	2853	#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	20:4263a77256ae	2854	#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	20:4263a77256ae	2855	#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	20:4263a77256ae	2856	#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	20:4263a77256ae	2857	#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	20:4263a77256ae	2858	#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	20:4263a77256ae	2859	#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	20:4263a77256ae	2860	#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	20:4263a77256ae	2861	#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	20:4263a77256ae	2862	#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	20:4263a77256ae	2863	#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	20:4263a77256ae	2864	#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	20:4263a77256ae	2865	#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	20:4263a77256ae	2866	#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	20:4263a77256ae	2867	#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	20:4263a77256ae	2868	#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	20:4263a77256ae	2869	#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	20:4263a77256ae	2870	#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	20:4263a77256ae	2871	#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	20:4263a77256ae	2872	#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	20:4263a77256ae	2873	#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	20:4263a77256ae	2874	#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	20:4263a77256ae	2875	#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	20:4263a77256ae	2876	#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	20:4263a77256ae	2877	#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	20:4263a77256ae	2878	#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	20:4263a77256ae	2879
bogdanm	20:4263a77256ae	2880	/***************** Bit definition for CAN_F13R2 register ****************/
bogdanm	20:4263a77256ae	2881	#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	20:4263a77256ae	2882	#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	20:4263a77256ae	2883	#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	20:4263a77256ae	2884	#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	20:4263a77256ae	2885	#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	20:4263a77256ae	2886	#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	20:4263a77256ae	2887	#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	20:4263a77256ae	2888	#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	20:4263a77256ae	2889	#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	20:4263a77256ae	2890	#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	20:4263a77256ae	2891	#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	20:4263a77256ae	2892	#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	20:4263a77256ae	2893	#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	20:4263a77256ae	2894	#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	20:4263a77256ae	2895	#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	20:4263a77256ae	2896	#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	20:4263a77256ae	2897	#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	20:4263a77256ae	2898	#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	20:4263a77256ae	2899	#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	20:4263a77256ae	2900	#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	20:4263a77256ae	2901	#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	20:4263a77256ae	2902	#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	20:4263a77256ae	2903	#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	20:4263a77256ae	2904	#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	20:4263a77256ae	2905	#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	20:4263a77256ae	2906	#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	20:4263a77256ae	2907	#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	20:4263a77256ae	2908	#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	20:4263a77256ae	2909	#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	20:4263a77256ae	2910	#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	20:4263a77256ae	2911	#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	20:4263a77256ae	2912	#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	20:4263a77256ae	2913
bogdanm	20:4263a77256ae	2914	/******************************************************************************/
bogdanm	20:4263a77256ae	2915	/* */
bogdanm	20:4263a77256ae	2916	/* CRC calculation unit */
bogdanm	20:4263a77256ae	2917	/* */
bogdanm	20:4263a77256ae	2918	/******************************************************************************/
bogdanm	20:4263a77256ae	2919	/***************** Bit definition for CRC_DR register *******************/
bogdanm	20:4263a77256ae	2920	#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /!< Data register bits /
bogdanm	20:4263a77256ae	2921
bogdanm	20:4263a77256ae	2922
bogdanm	20:4263a77256ae	2923	/***************** Bit definition for CRC_IDR register ******************/
bogdanm	20:4263a77256ae	2924	#define CRC_IDR_IDR ((uint8_t)0xFF) /!< General-purpose 8-bit data register bits /
bogdanm	20:4263a77256ae	2925
bogdanm	20:4263a77256ae	2926
bogdanm	20:4263a77256ae	2927	/****************** Bit definition for CRC_CR register ******************/
bogdanm	20:4263a77256ae	2928	#define CRC_CR_RESET ((uint8_t)0x01) /!< RESET bit /
bogdanm	20:4263a77256ae	2929
bogdanm	20:4263a77256ae	2930	/******************************************************************************/
bogdanm	20:4263a77256ae	2931	/* */
bogdanm	20:4263a77256ae	2932	/* Crypto Processor */
bogdanm	20:4263a77256ae	2933	/* */
bogdanm	20:4263a77256ae	2934	/******************************************************************************/
bogdanm	20:4263a77256ae	2935	/***************** Bits definition for CRYP_CR register ******************/
bogdanm	20:4263a77256ae	2936	#define CRYP_CR_ALGODIR ((uint32_t)0x00000004)
bogdanm	20:4263a77256ae	2937
bogdanm	20:4263a77256ae	2938	#define CRYP_CR_ALGOMODE ((uint32_t)0x00080038)
bogdanm	20:4263a77256ae	2939	#define CRYP_CR_ALGOMODE_0 ((uint32_t)0x00000008)
bogdanm	20:4263a77256ae	2940	#define CRYP_CR_ALGOMODE_1 ((uint32_t)0x00000010)
bogdanm	20:4263a77256ae	2941	#define CRYP_CR_ALGOMODE_2 ((uint32_t)0x00000020)
bogdanm	20:4263a77256ae	2942	#define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000)
bogdanm	20:4263a77256ae	2943	#define CRYP_CR_ALGOMODE_TDES_CBC ((uint32_t)0x00000008)
bogdanm	20:4263a77256ae	2944	#define CRYP_CR_ALGOMODE_DES_ECB ((uint32_t)0x00000010)
bogdanm	20:4263a77256ae	2945	#define CRYP_CR_ALGOMODE_DES_CBC ((uint32_t)0x00000018)
bogdanm	20:4263a77256ae	2946	#define CRYP_CR_ALGOMODE_AES_ECB ((uint32_t)0x00000020)
bogdanm	20:4263a77256ae	2947	#define CRYP_CR_ALGOMODE_AES_CBC ((uint32_t)0x00000028)
bogdanm	20:4263a77256ae	2948	#define CRYP_CR_ALGOMODE_AES_CTR ((uint32_t)0x00000030)
bogdanm	20:4263a77256ae	2949	#define CRYP_CR_ALGOMODE_AES_KEY ((uint32_t)0x00000038)
bogdanm	20:4263a77256ae	2950
bogdanm	20:4263a77256ae	2951	#define CRYP_CR_DATATYPE ((uint32_t)0x000000C0)
bogdanm	20:4263a77256ae	2952	#define CRYP_CR_DATATYPE_0 ((uint32_t)0x00000040)
bogdanm	20:4263a77256ae	2953	#define CRYP_CR_DATATYPE_1 ((uint32_t)0x00000080)
bogdanm	20:4263a77256ae	2954	#define CRYP_CR_KEYSIZE ((uint32_t)0x00000300)
bogdanm	20:4263a77256ae	2955	#define CRYP_CR_KEYSIZE_0 ((uint32_t)0x00000100)
bogdanm	20:4263a77256ae	2956	#define CRYP_CR_KEYSIZE_1 ((uint32_t)0x00000200)
bogdanm	20:4263a77256ae	2957	#define CRYP_CR_FFLUSH ((uint32_t)0x00004000)
bogdanm	20:4263a77256ae	2958	#define CRYP_CR_CRYPEN ((uint32_t)0x00008000)
bogdanm	20:4263a77256ae	2959
bogdanm	20:4263a77256ae	2960	#define CRYP_CR_GCM_CCMPH ((uint32_t)0x00030000)
bogdanm	20:4263a77256ae	2961	#define CRYP_CR_GCM_CCMPH_0 ((uint32_t)0x00010000)
bogdanm	20:4263a77256ae	2962	#define CRYP_CR_GCM_CCMPH_1 ((uint32_t)0x00020000)
bogdanm	20:4263a77256ae	2963	#define CRYP_CR_ALGOMODE_3 ((uint32_t)0x00080000)
bogdanm	20:4263a77256ae	2964
bogdanm	20:4263a77256ae	2965	/**************** Bits definition for CRYP_SR register *******************/
bogdanm	20:4263a77256ae	2966	#define CRYP_SR_IFEM ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	2967	#define CRYP_SR_IFNF ((uint32_t)0x00000002)
bogdanm	20:4263a77256ae	2968	#define CRYP_SR_OFNE ((uint32_t)0x00000004)
bogdanm	20:4263a77256ae	2969	#define CRYP_SR_OFFU ((uint32_t)0x00000008)
bogdanm	20:4263a77256ae	2970	#define CRYP_SR_BUSY ((uint32_t)0x00000010)
bogdanm	20:4263a77256ae	2971	/**************** Bits definition for CRYP_DMACR register ****************/
bogdanm	20:4263a77256ae	2972	#define CRYP_DMACR_DIEN ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	2973	#define CRYP_DMACR_DOEN ((uint32_t)0x00000002)
bogdanm	20:4263a77256ae	2974	/*************** Bits definition for CRYP_IMSCR register ****************/
bogdanm	20:4263a77256ae	2975	#define CRYP_IMSCR_INIM ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	2976	#define CRYP_IMSCR_OUTIM ((uint32_t)0x00000002)
bogdanm	20:4263a77256ae	2977	/**************** Bits definition for CRYP_RISR register *****************/
bogdanm	20:4263a77256ae	2978	#define CRYP_RISR_OUTRIS ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	2979	#define CRYP_RISR_INRIS ((uint32_t)0x00000002)
bogdanm	20:4263a77256ae	2980	/**************** Bits definition for CRYP_MISR register *****************/
bogdanm	20:4263a77256ae	2981	#define CRYP_MISR_INMIS ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	2982	#define CRYP_MISR_OUTMIS ((uint32_t)0x00000002)
bogdanm	20:4263a77256ae	2983
bogdanm	20:4263a77256ae	2984	/******************************************************************************/
bogdanm	20:4263a77256ae	2985	/* */
bogdanm	20:4263a77256ae	2986	/* Digital to Analog Converter */
bogdanm	20:4263a77256ae	2987	/* */
bogdanm	20:4263a77256ae	2988	/******************************************************************************/
bogdanm	20:4263a77256ae	2989	/****************** Bit definition for DAC_CR register ******************/
bogdanm	20:4263a77256ae	2990	#define DAC_CR_EN1 ((uint32_t)0x00000001) /!<DAC channel1 enable /
bogdanm	20:4263a77256ae	2991	#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /!<DAC channel1 output buffer disable /
bogdanm	20:4263a77256ae	2992	#define DAC_CR_TEN1 ((uint32_t)0x00000004) /!<DAC channel1 Trigger enable /
bogdanm	20:4263a77256ae	2993
bogdanm	20:4263a77256ae	2994	#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /!<TSEL1[2:0] (DAC channel1 Trigger selection) /
bogdanm	20:4263a77256ae	2995	#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /!<Bit 0 /
bogdanm	20:4263a77256ae	2996	#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /!<Bit 1 /
bogdanm	20:4263a77256ae	2997	#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /!<Bit 2 /
bogdanm	20:4263a77256ae	2998
bogdanm	20:4263a77256ae	2999	#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) /
bogdanm	20:4263a77256ae	3000	#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /!<Bit 0 /
bogdanm	20:4263a77256ae	3001	#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /!<Bit 1 /
bogdanm	20:4263a77256ae	3002
bogdanm	20:4263a77256ae	3003	#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) /
bogdanm	20:4263a77256ae	3004	#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /!<Bit 0 /
bogdanm	20:4263a77256ae	3005	#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /!<Bit 1 /
bogdanm	20:4263a77256ae	3006	#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /!<Bit 2 /
bogdanm	20:4263a77256ae	3007	#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /!<Bit 3 /
bogdanm	20:4263a77256ae	3008
bogdanm	20:4263a77256ae	3009	#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /!<DAC channel1 DMA enable /
bogdanm	20:4263a77256ae	3010	#define DAC_CR_EN2 ((uint32_t)0x00010000) /!<DAC channel2 enable /
bogdanm	20:4263a77256ae	3011	#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /!<DAC channel2 output buffer disable /
bogdanm	20:4263a77256ae	3012	#define DAC_CR_TEN2 ((uint32_t)0x00040000) /!<DAC channel2 Trigger enable /
bogdanm	20:4263a77256ae	3013
bogdanm	20:4263a77256ae	3014	#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /!<TSEL2[2:0] (DAC channel2 Trigger selection) /
bogdanm	20:4263a77256ae	3015	#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /!<Bit 0 /
bogdanm	20:4263a77256ae	3016	#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /!<Bit 1 /
bogdanm	20:4263a77256ae	3017	#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /!<Bit 2 /
bogdanm	20:4263a77256ae	3018
bogdanm	20:4263a77256ae	3019	#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) /
bogdanm	20:4263a77256ae	3020	#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /!<Bit 0 /
bogdanm	20:4263a77256ae	3021	#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /!<Bit 1 /
bogdanm	20:4263a77256ae	3022
bogdanm	20:4263a77256ae	3023	#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) /
bogdanm	20:4263a77256ae	3024	#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /!<Bit 0 /
bogdanm	20:4263a77256ae	3025	#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /!<Bit 1 /
bogdanm	20:4263a77256ae	3026	#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /!<Bit 2 /
bogdanm	20:4263a77256ae	3027	#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /!<Bit 3 /
bogdanm	20:4263a77256ae	3028
bogdanm	20:4263a77256ae	3029	#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /!<DAC channel2 DMA enabled /
bogdanm	20:4263a77256ae	3030
bogdanm	20:4263a77256ae	3031	/*************** Bit definition for DAC_SWTRIGR register ****************/
bogdanm	20:4263a77256ae	3032	#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /!<DAC channel1 software trigger /
bogdanm	20:4263a77256ae	3033	#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /!<DAC channel2 software trigger /
bogdanm	20:4263a77256ae	3034
bogdanm	20:4263a77256ae	3035	/*************** Bit definition for DAC_DHR12R1 register ****************/
bogdanm	20:4263a77256ae	3036	#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /!<DAC channel1 12-bit Right aligned data /
bogdanm	20:4263a77256ae	3037
bogdanm	20:4263a77256ae	3038	/*************** Bit definition for DAC_DHR12L1 register ****************/
bogdanm	20:4263a77256ae	3039	#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /!<DAC channel1 12-bit Left aligned data /
bogdanm	20:4263a77256ae	3040
bogdanm	20:4263a77256ae	3041	/**************** Bit definition for DAC_DHR8R1 register ****************/
bogdanm	20:4263a77256ae	3042	#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /!<DAC channel1 8-bit Right aligned data /
bogdanm	20:4263a77256ae	3043
bogdanm	20:4263a77256ae	3044	/*************** Bit definition for DAC_DHR12R2 register ****************/
bogdanm	20:4263a77256ae	3045	#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /!<DAC channel2 12-bit Right aligned data /
bogdanm	20:4263a77256ae	3046
bogdanm	20:4263a77256ae	3047	/*************** Bit definition for DAC_DHR12L2 register ****************/
bogdanm	20:4263a77256ae	3048	#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /!<DAC channel2 12-bit Left aligned data /
bogdanm	20:4263a77256ae	3049
bogdanm	20:4263a77256ae	3050	/**************** Bit definition for DAC_DHR8R2 register ****************/
bogdanm	20:4263a77256ae	3051	#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /!<DAC channel2 8-bit Right aligned data /
bogdanm	20:4263a77256ae	3052
bogdanm	20:4263a77256ae	3053	/*************** Bit definition for DAC_DHR12RD register ****************/
bogdanm	20:4263a77256ae	3054	#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /!<DAC channel1 12-bit Right aligned data /
bogdanm	20:4263a77256ae	3055	#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /!<DAC channel2 12-bit Right aligned data /
bogdanm	20:4263a77256ae	3056
bogdanm	20:4263a77256ae	3057	/*************** Bit definition for DAC_DHR12LD register ****************/
bogdanm	20:4263a77256ae	3058	#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /!<DAC channel1 12-bit Left aligned data /
bogdanm	20:4263a77256ae	3059	#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /!<DAC channel2 12-bit Left aligned data /
bogdanm	20:4263a77256ae	3060
bogdanm	20:4263a77256ae	3061	/**************** Bit definition for DAC_DHR8RD register ****************/
bogdanm	20:4263a77256ae	3062	#define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /!<DAC channel1 8-bit Right aligned data /
bogdanm	20:4263a77256ae	3063	#define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /!<DAC channel2 8-bit Right aligned data /
bogdanm	20:4263a77256ae	3064
bogdanm	20:4263a77256ae	3065	/***************** Bit definition for DAC_DOR1 register *****************/
bogdanm	20:4263a77256ae	3066	#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /!<DAC channel1 data output /
bogdanm	20:4263a77256ae	3067
bogdanm	20:4263a77256ae	3068	/***************** Bit definition for DAC_DOR2 register *****************/
bogdanm	20:4263a77256ae	3069	#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /!<DAC channel2 data output /
bogdanm	20:4263a77256ae	3070
bogdanm	20:4263a77256ae	3071	/****************** Bit definition for DAC_SR register ******************/
bogdanm	20:4263a77256ae	3072	#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /!<DAC channel1 DMA underrun flag /
bogdanm	20:4263a77256ae	3073	#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /!<DAC channel2 DMA underrun flag /
bogdanm	20:4263a77256ae	3074
bogdanm	20:4263a77256ae	3075	/******************************************************************************/
bogdanm	20:4263a77256ae	3076	/* */
bogdanm	20:4263a77256ae	3077	/* Debug MCU */
bogdanm	20:4263a77256ae	3078	/* */
bogdanm	20:4263a77256ae	3079	/******************************************************************************/
bogdanm	20:4263a77256ae	3080
bogdanm	20:4263a77256ae	3081	/******************************************************************************/
bogdanm	20:4263a77256ae	3082	/* */
bogdanm	20:4263a77256ae	3083	/* DCMI */
bogdanm	20:4263a77256ae	3084	/* */
bogdanm	20:4263a77256ae	3085	/******************************************************************************/
bogdanm	20:4263a77256ae	3086	/****************** Bits definition for DCMI_CR register ****************/
bogdanm	20:4263a77256ae	3087	#define DCMI_CR_CAPTURE ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	3088	#define DCMI_CR_CM ((uint32_t)0x00000002)
bogdanm	20:4263a77256ae	3089	#define DCMI_CR_CROP ((uint32_t)0x00000004)
bogdanm	20:4263a77256ae	3090	#define DCMI_CR_JPEG ((uint32_t)0x00000008)
bogdanm	20:4263a77256ae	3091	#define DCMI_CR_ESS ((uint32_t)0x00000010)
bogdanm	20:4263a77256ae	3092	#define DCMI_CR_PCKPOL ((uint32_t)0x00000020)
bogdanm	20:4263a77256ae	3093	#define DCMI_CR_HSPOL ((uint32_t)0x00000040)
bogdanm	20:4263a77256ae	3094	#define DCMI_CR_VSPOL ((uint32_t)0x00000080)
bogdanm	20:4263a77256ae	3095	#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100)
bogdanm	20:4263a77256ae	3096	#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200)
bogdanm	20:4263a77256ae	3097	#define DCMI_CR_EDM_0 ((uint32_t)0x00000400)
bogdanm	20:4263a77256ae	3098	#define DCMI_CR_EDM_1 ((uint32_t)0x00000800)
bogdanm	20:4263a77256ae	3099	#define DCMI_CR_CRE ((uint32_t)0x00001000)
bogdanm	20:4263a77256ae	3100	#define DCMI_CR_ENABLE ((uint32_t)0x00004000)
bogdanm	20:4263a77256ae	3101
bogdanm	20:4263a77256ae	3102	/****************** Bits definition for DCMI_SR register ****************/
bogdanm	20:4263a77256ae	3103	#define DCMI_SR_HSYNC ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	3104	#define DCMI_SR_VSYNC ((uint32_t)0x00000002)
bogdanm	20:4263a77256ae	3105	#define DCMI_SR_FNE ((uint32_t)0x00000004)
bogdanm	20:4263a77256ae	3106
bogdanm	20:4263a77256ae	3107	/****************** Bits definition for DCMI_RISR register **************/
bogdanm	20:4263a77256ae	3108	#define DCMI_RISR_FRAME_RIS ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	3109	#define DCMI_RISR_OVF_RIS ((uint32_t)0x00000002)
bogdanm	20:4263a77256ae	3110	#define DCMI_RISR_ERR_RIS ((uint32_t)0x00000004)
bogdanm	20:4263a77256ae	3111	#define DCMI_RISR_VSYNC_RIS ((uint32_t)0x00000008)
bogdanm	20:4263a77256ae	3112	#define DCMI_RISR_LINE_RIS ((uint32_t)0x00000010)
bogdanm	20:4263a77256ae	3113
bogdanm	20:4263a77256ae	3114	/****************** Bits definition for DCMI_IER register ***************/
bogdanm	20:4263a77256ae	3115	#define DCMI_IER_FRAME_IE ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	3116	#define DCMI_IER_OVF_IE ((uint32_t)0x00000002)
bogdanm	20:4263a77256ae	3117	#define DCMI_IER_ERR_IE ((uint32_t)0x00000004)
bogdanm	20:4263a77256ae	3118	#define DCMI_IER_VSYNC_IE ((uint32_t)0x00000008)
bogdanm	20:4263a77256ae	3119	#define DCMI_IER_LINE_IE ((uint32_t)0x00000010)
bogdanm	20:4263a77256ae	3120
bogdanm	20:4263a77256ae	3121	/****************** Bits definition for DCMI_MISR register **************/
bogdanm	20:4263a77256ae	3122	#define DCMI_MISR_FRAME_MIS ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	3123	#define DCMI_MISR_OVF_MIS ((uint32_t)0x00000002)
bogdanm	20:4263a77256ae	3124	#define DCMI_MISR_ERR_MIS ((uint32_t)0x00000004)
bogdanm	20:4263a77256ae	3125	#define DCMI_MISR_VSYNC_MIS ((uint32_t)0x00000008)
bogdanm	20:4263a77256ae	3126	#define DCMI_MISR_LINE_MIS ((uint32_t)0x00000010)
bogdanm	20:4263a77256ae	3127
bogdanm	20:4263a77256ae	3128	/****************** Bits definition for DCMI_ICR register ***************/
bogdanm	20:4263a77256ae	3129	#define DCMI_ICR_FRAME_ISC ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	3130	#define DCMI_ICR_OVF_ISC ((uint32_t)0x00000002)
bogdanm	20:4263a77256ae	3131	#define DCMI_ICR_ERR_ISC ((uint32_t)0x00000004)
bogdanm	20:4263a77256ae	3132	#define DCMI_ICR_VSYNC_ISC ((uint32_t)0x00000008)
bogdanm	20:4263a77256ae	3133	#define DCMI_ICR_LINE_ISC ((uint32_t)0x00000010)
bogdanm	20:4263a77256ae	3134
bogdanm	20:4263a77256ae	3135	/******************************************************************************/
bogdanm	20:4263a77256ae	3136	/* */
bogdanm	20:4263a77256ae	3137	/* DMA Controller */
bogdanm	20:4263a77256ae	3138	/* */
bogdanm	20:4263a77256ae	3139	/******************************************************************************/
bogdanm	20:4263a77256ae	3140	/****************** Bits definition for DMA_SxCR register ***************/
bogdanm	20:4263a77256ae	3141	#define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)
bogdanm	20:4263a77256ae	3142	#define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)
bogdanm	20:4263a77256ae	3143	#define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)
bogdanm	20:4263a77256ae	3144	#define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
bogdanm	20:4263a77256ae	3145	#define DMA_SxCR_MBURST ((uint32_t)0x01800000)
bogdanm	20:4263a77256ae	3146	#define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)
bogdanm	20:4263a77256ae	3147	#define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)
bogdanm	20:4263a77256ae	3148	#define DMA_SxCR_PBURST ((uint32_t)0x00600000)
bogdanm	20:4263a77256ae	3149	#define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)
bogdanm	20:4263a77256ae	3150	#define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)
bogdanm	20:4263a77256ae	3151	#define DMA_SxCR_ACK ((uint32_t)0x00100000)
bogdanm	20:4263a77256ae	3152	#define DMA_SxCR_CT ((uint32_t)0x00080000)
bogdanm	20:4263a77256ae	3153	#define DMA_SxCR_DBM ((uint32_t)0x00040000)
bogdanm	20:4263a77256ae	3154	#define DMA_SxCR_PL ((uint32_t)0x00030000)
bogdanm	20:4263a77256ae	3155	#define DMA_SxCR_PL_0 ((uint32_t)0x00010000)
bogdanm	20:4263a77256ae	3156	#define DMA_SxCR_PL_1 ((uint32_t)0x00020000)
bogdanm	20:4263a77256ae	3157	#define DMA_SxCR_PINCOS ((uint32_t)0x00008000)
bogdanm	20:4263a77256ae	3158	#define DMA_SxCR_MSIZE ((uint32_t)0x00006000)
bogdanm	20:4263a77256ae	3159	#define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)
bogdanm	20:4263a77256ae	3160	#define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)
bogdanm	20:4263a77256ae	3161	#define DMA_SxCR_PSIZE ((uint32_t)0x00001800)
bogdanm	20:4263a77256ae	3162	#define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)
bogdanm	20:4263a77256ae	3163	#define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)
bogdanm	20:4263a77256ae	3164	#define DMA_SxCR_MINC ((uint32_t)0x00000400)
bogdanm	20:4263a77256ae	3165	#define DMA_SxCR_PINC ((uint32_t)0x00000200)
bogdanm	20:4263a77256ae	3166	#define DMA_SxCR_CIRC ((uint32_t)0x00000100)
bogdanm	20:4263a77256ae	3167	#define DMA_SxCR_DIR ((uint32_t)0x000000C0)
bogdanm	20:4263a77256ae	3168	#define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)
bogdanm	20:4263a77256ae	3169	#define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)
bogdanm	20:4263a77256ae	3170	#define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)
bogdanm	20:4263a77256ae	3171	#define DMA_SxCR_TCIE ((uint32_t)0x00000010)
bogdanm	20:4263a77256ae	3172	#define DMA_SxCR_HTIE ((uint32_t)0x00000008)
bogdanm	20:4263a77256ae	3173	#define DMA_SxCR_TEIE ((uint32_t)0x00000004)
bogdanm	20:4263a77256ae	3174	#define DMA_SxCR_DMEIE ((uint32_t)0x00000002)
bogdanm	20:4263a77256ae	3175	#define DMA_SxCR_EN ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	3176
bogdanm	20:4263a77256ae	3177	/****************** Bits definition for DMA_SxCNDTR register ************/
bogdanm	20:4263a77256ae	3178	#define DMA_SxNDT ((uint32_t)0x0000FFFF)
bogdanm	20:4263a77256ae	3179	#define DMA_SxNDT_0 ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	3180	#define DMA_SxNDT_1 ((uint32_t)0x00000002)
bogdanm	20:4263a77256ae	3181	#define DMA_SxNDT_2 ((uint32_t)0x00000004)
bogdanm	20:4263a77256ae	3182	#define DMA_SxNDT_3 ((uint32_t)0x00000008)
bogdanm	20:4263a77256ae	3183	#define DMA_SxNDT_4 ((uint32_t)0x00000010)
bogdanm	20:4263a77256ae	3184	#define DMA_SxNDT_5 ((uint32_t)0x00000020)
bogdanm	20:4263a77256ae	3185	#define DMA_SxNDT_6 ((uint32_t)0x00000040)
bogdanm	20:4263a77256ae	3186	#define DMA_SxNDT_7 ((uint32_t)0x00000080)
bogdanm	20:4263a77256ae	3187	#define DMA_SxNDT_8 ((uint32_t)0x00000100)
bogdanm	20:4263a77256ae	3188	#define DMA_SxNDT_9 ((uint32_t)0x00000200)
bogdanm	20:4263a77256ae	3189	#define DMA_SxNDT_10 ((uint32_t)0x00000400)
bogdanm	20:4263a77256ae	3190	#define DMA_SxNDT_11 ((uint32_t)0x00000800)
bogdanm	20:4263a77256ae	3191	#define DMA_SxNDT_12 ((uint32_t)0x00001000)
bogdanm	20:4263a77256ae	3192	#define DMA_SxNDT_13 ((uint32_t)0x00002000)
bogdanm	20:4263a77256ae	3193	#define DMA_SxNDT_14 ((uint32_t)0x00004000)
bogdanm	20:4263a77256ae	3194	#define DMA_SxNDT_15 ((uint32_t)0x00008000)
bogdanm	20:4263a77256ae	3195
bogdanm	20:4263a77256ae	3196	/****************** Bits definition for DMA_SxFCR register **************/
bogdanm	20:4263a77256ae	3197	#define DMA_SxFCR_FEIE ((uint32_t)0x00000080)
bogdanm	20:4263a77256ae	3198	#define DMA_SxFCR_FS ((uint32_t)0x00000038)
bogdanm	20:4263a77256ae	3199	#define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)
bogdanm	20:4263a77256ae	3200	#define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)
bogdanm	20:4263a77256ae	3201	#define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)
bogdanm	20:4263a77256ae	3202	#define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)
bogdanm	20:4263a77256ae	3203	#define DMA_SxFCR_FTH ((uint32_t)0x00000003)
bogdanm	20:4263a77256ae	3204	#define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	3205	#define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)
bogdanm	20:4263a77256ae	3206
bogdanm	20:4263a77256ae	3207	/****************** Bits definition for DMA_LISR register ***************/
bogdanm	20:4263a77256ae	3208	#define DMA_LISR_TCIF3 ((uint32_t)0x08000000)
bogdanm	20:4263a77256ae	3209	#define DMA_LISR_HTIF3 ((uint32_t)0x04000000)
bogdanm	20:4263a77256ae	3210	#define DMA_LISR_TEIF3 ((uint32_t)0x02000000)
bogdanm	20:4263a77256ae	3211	#define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)
bogdanm	20:4263a77256ae	3212	#define DMA_LISR_FEIF3 ((uint32_t)0x00400000)
bogdanm	20:4263a77256ae	3213	#define DMA_LISR_TCIF2 ((uint32_t)0x00200000)
bogdanm	20:4263a77256ae	3214	#define DMA_LISR_HTIF2 ((uint32_t)0x00100000)
bogdanm	20:4263a77256ae	3215	#define DMA_LISR_TEIF2 ((uint32_t)0x00080000)
bogdanm	20:4263a77256ae	3216	#define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)
bogdanm	20:4263a77256ae	3217	#define DMA_LISR_FEIF2 ((uint32_t)0x00010000)
bogdanm	20:4263a77256ae	3218	#define DMA_LISR_TCIF1 ((uint32_t)0x00000800)
bogdanm	20:4263a77256ae	3219	#define DMA_LISR_HTIF1 ((uint32_t)0x00000400)
bogdanm	20:4263a77256ae	3220	#define DMA_LISR_TEIF1 ((uint32_t)0x00000200)
bogdanm	20:4263a77256ae	3221	#define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)
bogdanm	20:4263a77256ae	3222	#define DMA_LISR_FEIF1 ((uint32_t)0x00000040)
bogdanm	20:4263a77256ae	3223	#define DMA_LISR_TCIF0 ((uint32_t)0x00000020)
bogdanm	20:4263a77256ae	3224	#define DMA_LISR_HTIF0 ((uint32_t)0x00000010)
bogdanm	20:4263a77256ae	3225	#define DMA_LISR_TEIF0 ((uint32_t)0x00000008)
bogdanm	20:4263a77256ae	3226	#define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)
bogdanm	20:4263a77256ae	3227	#define DMA_LISR_FEIF0 ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	3228
bogdanm	20:4263a77256ae	3229	/****************** Bits definition for DMA_HISR register ***************/
bogdanm	20:4263a77256ae	3230	#define DMA_HISR_TCIF7 ((uint32_t)0x08000000)
bogdanm	20:4263a77256ae	3231	#define DMA_HISR_HTIF7 ((uint32_t)0x04000000)
bogdanm	20:4263a77256ae	3232	#define DMA_HISR_TEIF7 ((uint32_t)0x02000000)
bogdanm	20:4263a77256ae	3233	#define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)
bogdanm	20:4263a77256ae	3234	#define DMA_HISR_FEIF7 ((uint32_t)0x00400000)
bogdanm	20:4263a77256ae	3235	#define DMA_HISR_TCIF6 ((uint32_t)0x00200000)
bogdanm	20:4263a77256ae	3236	#define DMA_HISR_HTIF6 ((uint32_t)0x00100000)
bogdanm	20:4263a77256ae	3237	#define DMA_HISR_TEIF6 ((uint32_t)0x00080000)
bogdanm	20:4263a77256ae	3238	#define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)
bogdanm	20:4263a77256ae	3239	#define DMA_HISR_FEIF6 ((uint32_t)0x00010000)
bogdanm	20:4263a77256ae	3240	#define DMA_HISR_TCIF5 ((uint32_t)0x00000800)
bogdanm	20:4263a77256ae	3241	#define DMA_HISR_HTIF5 ((uint32_t)0x00000400)
bogdanm	20:4263a77256ae	3242	#define DMA_HISR_TEIF5 ((uint32_t)0x00000200)
bogdanm	20:4263a77256ae	3243	#define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)
bogdanm	20:4263a77256ae	3244	#define DMA_HISR_FEIF5 ((uint32_t)0x00000040)
bogdanm	20:4263a77256ae	3245	#define DMA_HISR_TCIF4 ((uint32_t)0x00000020)
bogdanm	20:4263a77256ae	3246	#define DMA_HISR_HTIF4 ((uint32_t)0x00000010)
bogdanm	20:4263a77256ae	3247	#define DMA_HISR_TEIF4 ((uint32_t)0x00000008)
bogdanm	20:4263a77256ae	3248	#define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)
bogdanm	20:4263a77256ae	3249	#define DMA_HISR_FEIF4 ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	3250
bogdanm	20:4263a77256ae	3251	/****************** Bits definition for DMA_LIFCR register **************/
bogdanm	20:4263a77256ae	3252	#define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)
bogdanm	20:4263a77256ae	3253	#define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)
bogdanm	20:4263a77256ae	3254	#define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)
bogdanm	20:4263a77256ae	3255	#define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)
bogdanm	20:4263a77256ae	3256	#define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)
bogdanm	20:4263a77256ae	3257	#define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)
bogdanm	20:4263a77256ae	3258	#define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)
bogdanm	20:4263a77256ae	3259	#define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)
bogdanm	20:4263a77256ae	3260	#define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)
bogdanm	20:4263a77256ae	3261	#define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)
bogdanm	20:4263a77256ae	3262	#define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)
bogdanm	20:4263a77256ae	3263	#define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)
bogdanm	20:4263a77256ae	3264	#define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)
bogdanm	20:4263a77256ae	3265	#define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)
bogdanm	20:4263a77256ae	3266	#define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)
bogdanm	20:4263a77256ae	3267	#define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)
bogdanm	20:4263a77256ae	3268	#define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)
bogdanm	20:4263a77256ae	3269	#define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)
bogdanm	20:4263a77256ae	3270	#define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)
bogdanm	20:4263a77256ae	3271	#define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	3272
bogdanm	20:4263a77256ae	3273	/****************** Bits definition for DMA_HIFCR register **************/
bogdanm	20:4263a77256ae	3274	#define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)
bogdanm	20:4263a77256ae	3275	#define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)
bogdanm	20:4263a77256ae	3276	#define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)
bogdanm	20:4263a77256ae	3277	#define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)
bogdanm	20:4263a77256ae	3278	#define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)
bogdanm	20:4263a77256ae	3279	#define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)
bogdanm	20:4263a77256ae	3280	#define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)
bogdanm	20:4263a77256ae	3281	#define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)
bogdanm	20:4263a77256ae	3282	#define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)
bogdanm	20:4263a77256ae	3283	#define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)
bogdanm	20:4263a77256ae	3284	#define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)
bogdanm	20:4263a77256ae	3285	#define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)
bogdanm	20:4263a77256ae	3286	#define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)
bogdanm	20:4263a77256ae	3287	#define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)
bogdanm	20:4263a77256ae	3288	#define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)
bogdanm	20:4263a77256ae	3289	#define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)
bogdanm	20:4263a77256ae	3290	#define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)
bogdanm	20:4263a77256ae	3291	#define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)
bogdanm	20:4263a77256ae	3292	#define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)
bogdanm	20:4263a77256ae	3293	#define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	3294
bogdanm	20:4263a77256ae	3295
bogdanm	20:4263a77256ae	3296	/******************************************************************************/
bogdanm	20:4263a77256ae	3297	/* */
bogdanm	20:4263a77256ae	3298	/* External Interrupt/Event Controller */
bogdanm	20:4263a77256ae	3299	/* */
bogdanm	20:4263a77256ae	3300	/******************************************************************************/
bogdanm	20:4263a77256ae	3301	/***************** Bit definition for EXTI_IMR register *****************/
bogdanm	20:4263a77256ae	3302	#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /!< Interrupt Mask on line 0 /
bogdanm	20:4263a77256ae	3303	#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /!< Interrupt Mask on line 1 /
bogdanm	20:4263a77256ae	3304	#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /!< Interrupt Mask on line 2 /
bogdanm	20:4263a77256ae	3305	#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /!< Interrupt Mask on line 3 /
bogdanm	20:4263a77256ae	3306	#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /!< Interrupt Mask on line 4 /
bogdanm	20:4263a77256ae	3307	#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /!< Interrupt Mask on line 5 /
bogdanm	20:4263a77256ae	3308	#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /!< Interrupt Mask on line 6 /
bogdanm	20:4263a77256ae	3309	#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /!< Interrupt Mask on line 7 /
bogdanm	20:4263a77256ae	3310	#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /!< Interrupt Mask on line 8 /
bogdanm	20:4263a77256ae	3311	#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /!< Interrupt Mask on line 9 /
bogdanm	20:4263a77256ae	3312	#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /!< Interrupt Mask on line 10 /
bogdanm	20:4263a77256ae	3313	#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /!< Interrupt Mask on line 11 /
bogdanm	20:4263a77256ae	3314	#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /!< Interrupt Mask on line 12 /
bogdanm	20:4263a77256ae	3315	#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /!< Interrupt Mask on line 13 /
bogdanm	20:4263a77256ae	3316	#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /!< Interrupt Mask on line 14 /
bogdanm	20:4263a77256ae	3317	#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /!< Interrupt Mask on line 15 /
bogdanm	20:4263a77256ae	3318	#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /!< Interrupt Mask on line 16 /
bogdanm	20:4263a77256ae	3319	#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /!< Interrupt Mask on line 17 /
bogdanm	20:4263a77256ae	3320	#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /!< Interrupt Mask on line 18 /
bogdanm	20:4263a77256ae	3321	#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /!< Interrupt Mask on line 19 /
bogdanm	20:4263a77256ae	3322
bogdanm	20:4263a77256ae	3323	/***************** Bit definition for EXTI_EMR register *****************/
bogdanm	20:4263a77256ae	3324	#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /!< Event Mask on line 0 /
bogdanm	20:4263a77256ae	3325	#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /!< Event Mask on line 1 /
bogdanm	20:4263a77256ae	3326	#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /!< Event Mask on line 2 /
bogdanm	20:4263a77256ae	3327	#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /!< Event Mask on line 3 /
bogdanm	20:4263a77256ae	3328	#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /!< Event Mask on line 4 /
bogdanm	20:4263a77256ae	3329	#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /!< Event Mask on line 5 /
bogdanm	20:4263a77256ae	3330	#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /!< Event Mask on line 6 /
bogdanm	20:4263a77256ae	3331	#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /!< Event Mask on line 7 /
bogdanm	20:4263a77256ae	3332	#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /!< Event Mask on line 8 /
bogdanm	20:4263a77256ae	3333	#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /!< Event Mask on line 9 /
bogdanm	20:4263a77256ae	3334	#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /!< Event Mask on line 10 /
bogdanm	20:4263a77256ae	3335	#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /!< Event Mask on line 11 /
bogdanm	20:4263a77256ae	3336	#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /!< Event Mask on line 12 /
bogdanm	20:4263a77256ae	3337	#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /!< Event Mask on line 13 /
bogdanm	20:4263a77256ae	3338	#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /!< Event Mask on line 14 /
bogdanm	20:4263a77256ae	3339	#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /!< Event Mask on line 15 /
bogdanm	20:4263a77256ae	3340	#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /!< Event Mask on line 16 /
bogdanm	20:4263a77256ae	3341	#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /!< Event Mask on line 17 /
bogdanm	20:4263a77256ae	3342	#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /!< Event Mask on line 18 /
bogdanm	20:4263a77256ae	3343	#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /!< Event Mask on line 19 /
bogdanm	20:4263a77256ae	3344
bogdanm	20:4263a77256ae	3345	/**************** Bit definition for EXTI_RTSR register *****************/
bogdanm	20:4263a77256ae	3346	#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /!< Rising trigger event configuration bit of line 0 /
bogdanm	20:4263a77256ae	3347	#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /!< Rising trigger event configuration bit of line 1 /
bogdanm	20:4263a77256ae	3348	#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /!< Rising trigger event configuration bit of line 2 /
bogdanm	20:4263a77256ae	3349	#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /!< Rising trigger event configuration bit of line 3 /
bogdanm	20:4263a77256ae	3350	#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /!< Rising trigger event configuration bit of line 4 /
bogdanm	20:4263a77256ae	3351	#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /!< Rising trigger event configuration bit of line 5 /
bogdanm	20:4263a77256ae	3352	#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /!< Rising trigger event configuration bit of line 6 /
bogdanm	20:4263a77256ae	3353	#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /!< Rising trigger event configuration bit of line 7 /
bogdanm	20:4263a77256ae	3354	#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /!< Rising trigger event configuration bit of line 8 /
bogdanm	20:4263a77256ae	3355	#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /!< Rising trigger event configuration bit of line 9 /
bogdanm	20:4263a77256ae	3356	#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /!< Rising trigger event configuration bit of line 10 /
bogdanm	20:4263a77256ae	3357	#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /!< Rising trigger event configuration bit of line 11 /
bogdanm	20:4263a77256ae	3358	#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /!< Rising trigger event configuration bit of line 12 /
bogdanm	20:4263a77256ae	3359	#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /!< Rising trigger event configuration bit of line 13 /
bogdanm	20:4263a77256ae	3360	#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /!< Rising trigger event configuration bit of line 14 /
bogdanm	20:4263a77256ae	3361	#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /!< Rising trigger event configuration bit of line 15 /
bogdanm	20:4263a77256ae	3362	#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /!< Rising trigger event configuration bit of line 16 /
bogdanm	20:4263a77256ae	3363	#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /!< Rising trigger event configuration bit of line 17 /
bogdanm	20:4263a77256ae	3364	#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /!< Rising trigger event configuration bit of line 18 /
bogdanm	20:4263a77256ae	3365	#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /!< Rising trigger event configuration bit of line 19 /
bogdanm	20:4263a77256ae	3366
bogdanm	20:4263a77256ae	3367	/**************** Bit definition for EXTI_FTSR register *****************/
bogdanm	20:4263a77256ae	3368	#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /!< Falling trigger event configuration bit of line 0 /
bogdanm	20:4263a77256ae	3369	#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /!< Falling trigger event configuration bit of line 1 /
bogdanm	20:4263a77256ae	3370	#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /!< Falling trigger event configuration bit of line 2 /
bogdanm	20:4263a77256ae	3371	#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /!< Falling trigger event configuration bit of line 3 /
bogdanm	20:4263a77256ae	3372	#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /!< Falling trigger event configuration bit of line 4 /
bogdanm	20:4263a77256ae	3373	#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /!< Falling trigger event configuration bit of line 5 /
bogdanm	20:4263a77256ae	3374	#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /!< Falling trigger event configuration bit of line 6 /
bogdanm	20:4263a77256ae	3375	#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /!< Falling trigger event configuration bit of line 7 /
bogdanm	20:4263a77256ae	3376	#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /!< Falling trigger event configuration bit of line 8 /
bogdanm	20:4263a77256ae	3377	#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /!< Falling trigger event configuration bit of line 9 /
bogdanm	20:4263a77256ae	3378	#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /!< Falling trigger event configuration bit of line 10 /
bogdanm	20:4263a77256ae	3379	#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /!< Falling trigger event configuration bit of line 11 /
bogdanm	20:4263a77256ae	3380	#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /!< Falling trigger event configuration bit of line 12 /
bogdanm	20:4263a77256ae	3381	#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /!< Falling trigger event configuration bit of line 13 /
bogdanm	20:4263a77256ae	3382	#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /!< Falling trigger event configuration bit of line 14 /
bogdanm	20:4263a77256ae	3383	#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /!< Falling trigger event configuration bit of line 15 /
bogdanm	20:4263a77256ae	3384	#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /!< Falling trigger event configuration bit of line 16 /
bogdanm	20:4263a77256ae	3385	#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /!< Falling trigger event configuration bit of line 17 /
bogdanm	20:4263a77256ae	3386	#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /!< Falling trigger event configuration bit of line 18 /
bogdanm	20:4263a77256ae	3387	#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /!< Falling trigger event configuration bit of line 19 /
bogdanm	20:4263a77256ae	3388
bogdanm	20:4263a77256ae	3389	/**************** Bit definition for EXTI_SWIER register ****************/
bogdanm	20:4263a77256ae	3390	#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /!< Software Interrupt on line 0 /
bogdanm	20:4263a77256ae	3391	#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /!< Software Interrupt on line 1 /
bogdanm	20:4263a77256ae	3392	#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /!< Software Interrupt on line 2 /
bogdanm	20:4263a77256ae	3393	#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /!< Software Interrupt on line 3 /
bogdanm	20:4263a77256ae	3394	#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /!< Software Interrupt on line 4 /
bogdanm	20:4263a77256ae	3395	#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /!< Software Interrupt on line 5 /
bogdanm	20:4263a77256ae	3396	#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /!< Software Interrupt on line 6 /
bogdanm	20:4263a77256ae	3397	#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /!< Software Interrupt on line 7 /
bogdanm	20:4263a77256ae	3398	#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /!< Software Interrupt on line 8 /
bogdanm	20:4263a77256ae	3399	#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /!< Software Interrupt on line 9 /
bogdanm	20:4263a77256ae	3400	#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /!< Software Interrupt on line 10 /
bogdanm	20:4263a77256ae	3401	#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /!< Software Interrupt on line 11 /
bogdanm	20:4263a77256ae	3402	#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /!< Software Interrupt on line 12 /
bogdanm	20:4263a77256ae	3403	#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /!< Software Interrupt on line 13 /
bogdanm	20:4263a77256ae	3404	#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /!< Software Interrupt on line 14 /
bogdanm	20:4263a77256ae	3405	#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /!< Software Interrupt on line 15 /
bogdanm	20:4263a77256ae	3406	#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /!< Software Interrupt on line 16 /
bogdanm	20:4263a77256ae	3407	#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /!< Software Interrupt on line 17 /
bogdanm	20:4263a77256ae	3408	#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /!< Software Interrupt on line 18 /
bogdanm	20:4263a77256ae	3409	#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /!< Software Interrupt on line 19 /
bogdanm	20:4263a77256ae	3410
bogdanm	20:4263a77256ae	3411	/***************** Bit definition for EXTI_PR register ******************/
bogdanm	20:4263a77256ae	3412	#define EXTI_PR_PR0 ((uint32_t)0x00000001) /!< Pending bit for line 0 /
bogdanm	20:4263a77256ae	3413	#define EXTI_PR_PR1 ((uint32_t)0x00000002) /!< Pending bit for line 1 /
bogdanm	20:4263a77256ae	3414	#define EXTI_PR_PR2 ((uint32_t)0x00000004) /!< Pending bit for line 2 /
bogdanm	20:4263a77256ae	3415	#define EXTI_PR_PR3 ((uint32_t)0x00000008) /!< Pending bit for line 3 /
bogdanm	20:4263a77256ae	3416	#define EXTI_PR_PR4 ((uint32_t)0x00000010) /!< Pending bit for line 4 /
bogdanm	20:4263a77256ae	3417	#define EXTI_PR_PR5 ((uint32_t)0x00000020) /!< Pending bit for line 5 /
bogdanm	20:4263a77256ae	3418	#define EXTI_PR_PR6 ((uint32_t)0x00000040) /!< Pending bit for line 6 /
bogdanm	20:4263a77256ae	3419	#define EXTI_PR_PR7 ((uint32_t)0x00000080) /!< Pending bit for line 7 /
bogdanm	20:4263a77256ae	3420	#define EXTI_PR_PR8 ((uint32_t)0x00000100) /!< Pending bit for line 8 /
bogdanm	20:4263a77256ae	3421	#define EXTI_PR_PR9 ((uint32_t)0x00000200) /!< Pending bit for line 9 /
bogdanm	20:4263a77256ae	3422	#define EXTI_PR_PR10 ((uint32_t)0x00000400) /!< Pending bit for line 10 /
bogdanm	20:4263a77256ae	3423	#define EXTI_PR_PR11 ((uint32_t)0x00000800) /!< Pending bit for line 11 /
bogdanm	20:4263a77256ae	3424	#define EXTI_PR_PR12 ((uint32_t)0x00001000) /!< Pending bit for line 12 /
bogdanm	20:4263a77256ae	3425	#define EXTI_PR_PR13 ((uint32_t)0x00002000) /!< Pending bit for line 13 /
bogdanm	20:4263a77256ae	3426	#define EXTI_PR_PR14 ((uint32_t)0x00004000) /!< Pending bit for line 14 /
bogdanm	20:4263a77256ae	3427	#define EXTI_PR_PR15 ((uint32_t)0x00008000) /!< Pending bit for line 15 /
bogdanm	20:4263a77256ae	3428	#define EXTI_PR_PR16 ((uint32_t)0x00010000) /!< Pending bit for line 16 /
bogdanm	20:4263a77256ae	3429	#define EXTI_PR_PR17 ((uint32_t)0x00020000) /!< Pending bit for line 17 /
bogdanm	20:4263a77256ae	3430	#define EXTI_PR_PR18 ((uint32_t)0x00040000) /!< Pending bit for line 18 /
bogdanm	20:4263a77256ae	3431	#define EXTI_PR_PR19 ((uint32_t)0x00080000) /!< Pending bit for line 19 /
bogdanm	20:4263a77256ae	3432
bogdanm	20:4263a77256ae	3433	/******************************************************************************/
bogdanm	20:4263a77256ae	3434	/* */
bogdanm	20:4263a77256ae	3435	/* FLASH */
bogdanm	20:4263a77256ae	3436	/* */
bogdanm	20:4263a77256ae	3437	/******************************************************************************/
bogdanm	20:4263a77256ae	3438	/***************** Bits definition for FLASH_ACR register ***************/
bogdanm	20:4263a77256ae	3439	#define FLASH_ACR_LATENCY ((uint32_t)0x0000000F)
bogdanm	20:4263a77256ae	3440	#define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)
bogdanm	20:4263a77256ae	3441	#define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	3442	#define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)
bogdanm	20:4263a77256ae	3443	#define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)
bogdanm	20:4263a77256ae	3444	#define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)
bogdanm	20:4263a77256ae	3445	#define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)
bogdanm	20:4263a77256ae	3446	#define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)
bogdanm	20:4263a77256ae	3447	#define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)
bogdanm	20:4263a77256ae	3448
bogdanm	20:4263a77256ae	3449	#define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)
bogdanm	20:4263a77256ae	3450	#define FLASH_ACR_ICEN ((uint32_t)0x00000200)
bogdanm	20:4263a77256ae	3451	#define FLASH_ACR_DCEN ((uint32_t)0x00000400)
bogdanm	20:4263a77256ae	3452	#define FLASH_ACR_ICRST ((uint32_t)0x00000800)
bogdanm	20:4263a77256ae	3453	#define FLASH_ACR_DCRST ((uint32_t)0x00001000)
bogdanm	20:4263a77256ae	3454	#define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
bogdanm	20:4263a77256ae	3455	#define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03)
bogdanm	20:4263a77256ae	3456
bogdanm	20:4263a77256ae	3457	/***************** Bits definition for FLASH_SR register ****************/
bogdanm	20:4263a77256ae	3458	#define FLASH_SR_EOP ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	3459	#define FLASH_SR_SOP ((uint32_t)0x00000002)
bogdanm	20:4263a77256ae	3460	#define FLASH_SR_WRPERR ((uint32_t)0x00000010)
bogdanm	20:4263a77256ae	3461	#define FLASH_SR_PGAERR ((uint32_t)0x00000020)
bogdanm	20:4263a77256ae	3462	#define FLASH_SR_PGPERR ((uint32_t)0x00000040)
bogdanm	20:4263a77256ae	3463	#define FLASH_SR_PGSERR ((uint32_t)0x00000080)
bogdanm	20:4263a77256ae	3464	#define FLASH_SR_BSY ((uint32_t)0x00010000)
bogdanm	20:4263a77256ae	3465
bogdanm	20:4263a77256ae	3466	/***************** Bits definition for FLASH_CR register ****************/
bogdanm	20:4263a77256ae	3467	#define FLASH_CR_PG ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	3468	#define FLASH_CR_SER ((uint32_t)0x00000002)
bogdanm	20:4263a77256ae	3469	#define FLASH_CR_MER ((uint32_t)0x00000004)
bogdanm	20:4263a77256ae	3470	#define FLASH_CR_MER1 FLASH_CR_MER
bogdanm	20:4263a77256ae	3471	#define FLASH_CR_SNB ((uint32_t)0x000000F8)
bogdanm	20:4263a77256ae	3472	#define FLASH_CR_SNB_0 ((uint32_t)0x00000008)
bogdanm	20:4263a77256ae	3473	#define FLASH_CR_SNB_1 ((uint32_t)0x00000010)
bogdanm	20:4263a77256ae	3474	#define FLASH_CR_SNB_2 ((uint32_t)0x00000020)
bogdanm	20:4263a77256ae	3475	#define FLASH_CR_SNB_3 ((uint32_t)0x00000040)
bogdanm	20:4263a77256ae	3476	#define FLASH_CR_SNB_4 ((uint32_t)0x00000040)
bogdanm	20:4263a77256ae	3477	#define FLASH_CR_PSIZE ((uint32_t)0x00000300)
bogdanm	20:4263a77256ae	3478	#define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)
bogdanm	20:4263a77256ae	3479	#define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)
bogdanm	20:4263a77256ae	3480	#define FLASH_CR_MER2 ((uint32_t)0x00008000)
bogdanm	20:4263a77256ae	3481	#define FLASH_CR_STRT ((uint32_t)0x00010000)
bogdanm	20:4263a77256ae	3482	#define FLASH_CR_EOPIE ((uint32_t)0x01000000)
bogdanm	20:4263a77256ae	3483	#define FLASH_CR_LOCK ((uint32_t)0x80000000)
bogdanm	20:4263a77256ae	3484
bogdanm	20:4263a77256ae	3485	/***************** Bits definition for FLASH_OPTCR register *************/
bogdanm	20:4263a77256ae	3486	#define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	3487	#define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)
bogdanm	20:4263a77256ae	3488	#define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)
bogdanm	20:4263a77256ae	3489	#define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)
bogdanm	20:4263a77256ae	3490	#define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)
bogdanm	20:4263a77256ae	3491	#define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020)
bogdanm	20:4263a77256ae	3492	#define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)
bogdanm	20:4263a77256ae	3493	#define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)
bogdanm	20:4263a77256ae	3494	#define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00)
bogdanm	20:4263a77256ae	3495	#define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)
bogdanm	20:4263a77256ae	3496	#define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)
bogdanm	20:4263a77256ae	3497	#define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)
bogdanm	20:4263a77256ae	3498	#define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)
bogdanm	20:4263a77256ae	3499	#define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)
bogdanm	20:4263a77256ae	3500	#define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)
bogdanm	20:4263a77256ae	3501	#define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)
bogdanm	20:4263a77256ae	3502	#define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)
bogdanm	20:4263a77256ae	3503	#define FLASH_OPTCR_nWRP ((uint32_t)0x0FFF0000)
bogdanm	20:4263a77256ae	3504	#define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)
bogdanm	20:4263a77256ae	3505	#define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)
bogdanm	20:4263a77256ae	3506	#define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)
bogdanm	20:4263a77256ae	3507	#define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)
bogdanm	20:4263a77256ae	3508	#define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)
bogdanm	20:4263a77256ae	3509	#define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)
bogdanm	20:4263a77256ae	3510	#define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)
bogdanm	20:4263a77256ae	3511	#define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)
bogdanm	20:4263a77256ae	3512	#define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000)
bogdanm	20:4263a77256ae	3513	#define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000)
bogdanm	20:4263a77256ae	3514	#define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000)
bogdanm	20:4263a77256ae	3515	#define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000)
bogdanm	20:4263a77256ae	3516
bogdanm	20:4263a77256ae	3517	/**************** Bits definition for FLASH_OPTCR1 register *************/
bogdanm	20:4263a77256ae	3518	#define FLASH_OPTCR1_nWRP ((uint32_t)0x0FFF0000)
bogdanm	20:4263a77256ae	3519	#define FLASH_OPTCR1_nWRP_0 ((uint32_t)0x00010000)
bogdanm	20:4263a77256ae	3520	#define FLASH_OPTCR1_nWRP_1 ((uint32_t)0x00020000)
bogdanm	20:4263a77256ae	3521	#define FLASH_OPTCR1_nWRP_2 ((uint32_t)0x00040000)
bogdanm	20:4263a77256ae	3522	#define FLASH_OPTCR1_nWRP_3 ((uint32_t)0x00080000)
bogdanm	20:4263a77256ae	3523	#define FLASH_OPTCR1_nWRP_4 ((uint32_t)0x00100000)
bogdanm	20:4263a77256ae	3524	#define FLASH_OPTCR1_nWRP_5 ((uint32_t)0x00200000)
bogdanm	20:4263a77256ae	3525	#define FLASH_OPTCR1_nWRP_6 ((uint32_t)0x00400000)
bogdanm	20:4263a77256ae	3526	#define FLASH_OPTCR1_nWRP_7 ((uint32_t)0x00800000)
bogdanm	20:4263a77256ae	3527	#define FLASH_OPTCR1_nWRP_8 ((uint32_t)0x01000000)
bogdanm	20:4263a77256ae	3528	#define FLASH_OPTCR1_nWRP_9 ((uint32_t)0x02000000)
bogdanm	20:4263a77256ae	3529	#define FLASH_OPTCR1_nWRP_10 ((uint32_t)0x04000000)
bogdanm	20:4263a77256ae	3530	#define FLASH_OPTCR1_nWRP_11 ((uint32_t)0x08000000)
bogdanm	20:4263a77256ae	3531
bogdanm	20:4263a77256ae	3532
bogdanm	20:4263a77256ae	3533	/******************************************************************************/
bogdanm	20:4263a77256ae	3534	/* */
bogdanm	20:4263a77256ae	3535	/* Flexible Static Memory Controller */
bogdanm	20:4263a77256ae	3536	/* */
bogdanm	20:4263a77256ae	3537	/******************************************************************************/
bogdanm	20:4263a77256ae	3538	/**************** Bit definition for FSMC_BCR1 register *****************/
bogdanm	20:4263a77256ae	3539	#define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /!<Memory bank enable bit /
bogdanm	20:4263a77256ae	3540	#define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /!<Address/data multiplexing enable bit /
bogdanm	20:4263a77256ae	3541
bogdanm	20:4263a77256ae	3542	#define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /!<MTYP[1:0] bits (Memory type) /
bogdanm	20:4263a77256ae	3543	#define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /!<Bit 0 /
bogdanm	20:4263a77256ae	3544	#define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /!<Bit 1 /
bogdanm	20:4263a77256ae	3545
bogdanm	20:4263a77256ae	3546	#define FSMC_BCR1_MWID ((uint32_t)0x00000030) /!<MWID[1:0] bits (Memory data bus width) /
bogdanm	20:4263a77256ae	3547	#define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	20:4263a77256ae	3548	#define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	20:4263a77256ae	3549
bogdanm	20:4263a77256ae	3550	#define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /!<Flash access enable /
bogdanm	20:4263a77256ae	3551	#define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /!<Burst enable bit /
bogdanm	20:4263a77256ae	3552	#define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /!<Wait signal polarity bit /
bogdanm	20:4263a77256ae	3553	#define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /!<Wrapped burst mode support /
bogdanm	20:4263a77256ae	3554	#define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /!<Wait timing configuration /
bogdanm	20:4263a77256ae	3555	#define FSMC_BCR1_WREN ((uint32_t)0x00001000) /!<Write enable bit /
bogdanm	20:4263a77256ae	3556	#define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /!<Wait enable bit /
bogdanm	20:4263a77256ae	3557	#define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /!<Extended mode enable /
bogdanm	20:4263a77256ae	3558	#define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /!<Asynchronous wait /
bogdanm	20:4263a77256ae	3559	#define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /!<Write burst enable /
bogdanm	20:4263a77256ae	3560
bogdanm	20:4263a77256ae	3561	/**************** Bit definition for FSMC_BCR2 register *****************/
bogdanm	20:4263a77256ae	3562	#define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /!<Memory bank enable bit /
bogdanm	20:4263a77256ae	3563	#define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /!<Address/data multiplexing enable bit /
bogdanm	20:4263a77256ae	3564
bogdanm	20:4263a77256ae	3565	#define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /!<MTYP[1:0] bits (Memory type) /
bogdanm	20:4263a77256ae	3566	#define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /!<Bit 0 /
bogdanm	20:4263a77256ae	3567	#define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /!<Bit 1 /
bogdanm	20:4263a77256ae	3568
bogdanm	20:4263a77256ae	3569	#define FSMC_BCR2_MWID ((uint32_t)0x00000030) /!<MWID[1:0] bits (Memory data bus width) /
bogdanm	20:4263a77256ae	3570	#define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	20:4263a77256ae	3571	#define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	20:4263a77256ae	3572
bogdanm	20:4263a77256ae	3573	#define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /!<Flash access enable /
bogdanm	20:4263a77256ae	3574	#define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /!<Burst enable bit /
bogdanm	20:4263a77256ae	3575	#define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /!<Wait signal polarity bit /
bogdanm	20:4263a77256ae	3576	#define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /!<Wrapped burst mode support /
bogdanm	20:4263a77256ae	3577	#define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /!<Wait timing configuration /
bogdanm	20:4263a77256ae	3578	#define FSMC_BCR2_WREN ((uint32_t)0x00001000) /!<Write enable bit /
bogdanm	20:4263a77256ae	3579	#define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /!<Wait enable bit /
bogdanm	20:4263a77256ae	3580	#define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /!<Extended mode enable /
bogdanm	20:4263a77256ae	3581	#define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /!<Asynchronous wait /
bogdanm	20:4263a77256ae	3582	#define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /!<Write burst enable /
bogdanm	20:4263a77256ae	3583
bogdanm	20:4263a77256ae	3584	/**************** Bit definition for FSMC_BCR3 register *****************/
bogdanm	20:4263a77256ae	3585	#define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /!<Memory bank enable bit /
bogdanm	20:4263a77256ae	3586	#define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /!<Address/data multiplexing enable bit /
bogdanm	20:4263a77256ae	3587
bogdanm	20:4263a77256ae	3588	#define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /!<MTYP[1:0] bits (Memory type) /
bogdanm	20:4263a77256ae	3589	#define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /!<Bit 0 /
bogdanm	20:4263a77256ae	3590	#define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /!<Bit 1 /
bogdanm	20:4263a77256ae	3591
bogdanm	20:4263a77256ae	3592	#define FSMC_BCR3_MWID ((uint32_t)0x00000030) /!<MWID[1:0] bits (Memory data bus width) /
bogdanm	20:4263a77256ae	3593	#define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	20:4263a77256ae	3594	#define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	20:4263a77256ae	3595
bogdanm	20:4263a77256ae	3596	#define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /!<Flash access enable /
bogdanm	20:4263a77256ae	3597	#define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /!<Burst enable bit /
bogdanm	20:4263a77256ae	3598	#define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /!<Wait signal polarity bit /
bogdanm	20:4263a77256ae	3599	#define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /!<Wrapped burst mode support /
bogdanm	20:4263a77256ae	3600	#define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /!<Wait timing configuration /
bogdanm	20:4263a77256ae	3601	#define FSMC_BCR3_WREN ((uint32_t)0x00001000) /!<Write enable bit /
bogdanm	20:4263a77256ae	3602	#define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /!<Wait enable bit /
bogdanm	20:4263a77256ae	3603	#define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /!<Extended mode enable /
bogdanm	20:4263a77256ae	3604	#define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /!<Asynchronous wait /
bogdanm	20:4263a77256ae	3605	#define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /!<Write burst enable /
bogdanm	20:4263a77256ae	3606
bogdanm	20:4263a77256ae	3607	/**************** Bit definition for FSMC_BCR4 register *****************/
bogdanm	20:4263a77256ae	3608	#define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /!<Memory bank enable bit /
bogdanm	20:4263a77256ae	3609	#define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /!<Address/data multiplexing enable bit /
bogdanm	20:4263a77256ae	3610
bogdanm	20:4263a77256ae	3611	#define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /!<MTYP[1:0] bits (Memory type) /
bogdanm	20:4263a77256ae	3612	#define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /!<Bit 0 /
bogdanm	20:4263a77256ae	3613	#define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /!<Bit 1 /
bogdanm	20:4263a77256ae	3614
bogdanm	20:4263a77256ae	3615	#define FSMC_BCR4_MWID ((uint32_t)0x00000030) /!<MWID[1:0] bits (Memory data bus width) /
bogdanm	20:4263a77256ae	3616	#define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	20:4263a77256ae	3617	#define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	20:4263a77256ae	3618
bogdanm	20:4263a77256ae	3619	#define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /!<Flash access enable /
bogdanm	20:4263a77256ae	3620	#define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /!<Burst enable bit /
bogdanm	20:4263a77256ae	3621	#define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /!<Wait signal polarity bit /
bogdanm	20:4263a77256ae	3622	#define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /!<Wrapped burst mode support /
bogdanm	20:4263a77256ae	3623	#define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /!<Wait timing configuration /
bogdanm	20:4263a77256ae	3624	#define FSMC_BCR4_WREN ((uint32_t)0x00001000) /!<Write enable bit /
bogdanm	20:4263a77256ae	3625	#define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /!<Wait enable bit /
bogdanm	20:4263a77256ae	3626	#define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /!<Extended mode enable /
bogdanm	20:4263a77256ae	3627	#define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /!<Asynchronous wait /
bogdanm	20:4263a77256ae	3628	#define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /!<Write burst enable /
bogdanm	20:4263a77256ae	3629
bogdanm	20:4263a77256ae	3630	/**************** Bit definition for FSMC_BTR1 register ****************/
bogdanm	20:4263a77256ae	3631	#define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /!<ADDSET[3:0] bits (Address setup phase duration) /
bogdanm	20:4263a77256ae	3632	#define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	20:4263a77256ae	3633	#define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	20:4263a77256ae	3634	#define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /!<Bit 2 /
bogdanm	20:4263a77256ae	3635	#define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /!<Bit 3 /
bogdanm	20:4263a77256ae	3636
bogdanm	20:4263a77256ae	3637	#define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /!<ADDHLD[3:0] bits (Address-hold phase duration) /
bogdanm	20:4263a77256ae	3638	#define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	20:4263a77256ae	3639	#define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	20:4263a77256ae	3640	#define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /!<Bit 2 /
bogdanm	20:4263a77256ae	3641	#define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /!<Bit 3 /
bogdanm	20:4263a77256ae	3642
bogdanm	20:4263a77256ae	3643	#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /!<DATAST [3:0] bits (Data-phase duration) /
bogdanm	20:4263a77256ae	3644	#define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /!<Bit 0 /
bogdanm	20:4263a77256ae	3645	#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /!<Bit 1 /
bogdanm	20:4263a77256ae	3646	#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /!<Bit 2 /
bogdanm	20:4263a77256ae	3647	#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /!<Bit 3 /
bogdanm	20:4263a77256ae	3648
bogdanm	20:4263a77256ae	3649	#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /!<BUSTURN[3:0] bits (Bus turnaround phase duration) /
bogdanm	20:4263a77256ae	3650	#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /!<Bit 0 /
bogdanm	20:4263a77256ae	3651	#define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /!<Bit 1 /
bogdanm	20:4263a77256ae	3652	#define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /!<Bit 2 /
bogdanm	20:4263a77256ae	3653	#define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /!<Bit 3 /
bogdanm	20:4263a77256ae	3654
bogdanm	20:4263a77256ae	3655	#define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /!<CLKDIV[3:0] bits (Clock divide ratio) /
bogdanm	20:4263a77256ae	3656	#define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /!<Bit 0 /
bogdanm	20:4263a77256ae	3657	#define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /!<Bit 1 /
bogdanm	20:4263a77256ae	3658	#define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /!<Bit 2 /
bogdanm	20:4263a77256ae	3659	#define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /!<Bit 3 /
bogdanm	20:4263a77256ae	3660
bogdanm	20:4263a77256ae	3661	#define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /!<DATLA[3:0] bits (Data latency) /
bogdanm	20:4263a77256ae	3662	#define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /!<Bit 0 /
bogdanm	20:4263a77256ae	3663	#define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /!<Bit 1 /
bogdanm	20:4263a77256ae	3664	#define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /!<Bit 2 /
bogdanm	20:4263a77256ae	3665	#define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /!<Bit 3 /
bogdanm	20:4263a77256ae	3666
bogdanm	20:4263a77256ae	3667	#define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /!<ACCMOD[1:0] bits (Access mode) /
bogdanm	20:4263a77256ae	3668	#define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /!<Bit 0 /
bogdanm	20:4263a77256ae	3669	#define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /!<Bit 1 /
bogdanm	20:4263a77256ae	3670
bogdanm	20:4263a77256ae	3671	/**************** Bit definition for FSMC_BTR2 register *****************/
bogdanm	20:4263a77256ae	3672	#define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /!<ADDSET[3:0] bits (Address setup phase duration) /
bogdanm	20:4263a77256ae	3673	#define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	20:4263a77256ae	3674	#define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	20:4263a77256ae	3675	#define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /!<Bit 2 /
bogdanm	20:4263a77256ae	3676	#define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /!<Bit 3 /
bogdanm	20:4263a77256ae	3677
bogdanm	20:4263a77256ae	3678	#define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /!<ADDHLD[3:0] bits (Address-hold phase duration) /
bogdanm	20:4263a77256ae	3679	#define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	20:4263a77256ae	3680	#define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	20:4263a77256ae	3681	#define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /!<Bit 2 /
bogdanm	20:4263a77256ae	3682	#define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /!<Bit 3 /
bogdanm	20:4263a77256ae	3683
bogdanm	20:4263a77256ae	3684	#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /!<DATAST [3:0] bits (Data-phase duration) /
bogdanm	20:4263a77256ae	3685	#define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /!<Bit 0 /
bogdanm	20:4263a77256ae	3686	#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /!<Bit 1 /
bogdanm	20:4263a77256ae	3687	#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /!<Bit 2 /
bogdanm	20:4263a77256ae	3688	#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /!<Bit 3 /
bogdanm	20:4263a77256ae	3689
bogdanm	20:4263a77256ae	3690	#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /!<BUSTURN[3:0] bits (Bus turnaround phase duration) /
bogdanm	20:4263a77256ae	3691	#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /!<Bit 0 /
bogdanm	20:4263a77256ae	3692	#define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /!<Bit 1 /
bogdanm	20:4263a77256ae	3693	#define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /!<Bit 2 /
bogdanm	20:4263a77256ae	3694	#define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /!<Bit 3 /
bogdanm	20:4263a77256ae	3695
bogdanm	20:4263a77256ae	3696	#define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /!<CLKDIV[3:0] bits (Clock divide ratio) /
bogdanm	20:4263a77256ae	3697	#define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /!<Bit 0 /
bogdanm	20:4263a77256ae	3698	#define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /!<Bit 1 /
bogdanm	20:4263a77256ae	3699	#define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /!<Bit 2 /
bogdanm	20:4263a77256ae	3700	#define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /!<Bit 3 /
bogdanm	20:4263a77256ae	3701
bogdanm	20:4263a77256ae	3702	#define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /!<DATLA[3:0] bits (Data latency) /
bogdanm	20:4263a77256ae	3703	#define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /!<Bit 0 /
bogdanm	20:4263a77256ae	3704	#define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /!<Bit 1 /
bogdanm	20:4263a77256ae	3705	#define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /!<Bit 2 /
bogdanm	20:4263a77256ae	3706	#define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /!<Bit 3 /
bogdanm	20:4263a77256ae	3707
bogdanm	20:4263a77256ae	3708	#define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /!<ACCMOD[1:0] bits (Access mode) /
bogdanm	20:4263a77256ae	3709	#define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /!<Bit 0 /
bogdanm	20:4263a77256ae	3710	#define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /!<Bit 1 /
bogdanm	20:4263a77256ae	3711
bogdanm	20:4263a77256ae	3712	/***************** Bit definition for FSMC_BTR3 register *****************/
bogdanm	20:4263a77256ae	3713	#define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /!<ADDSET[3:0] bits (Address setup phase duration) /
bogdanm	20:4263a77256ae	3714	#define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	20:4263a77256ae	3715	#define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	20:4263a77256ae	3716	#define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /!<Bit 2 /
bogdanm	20:4263a77256ae	3717	#define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /!<Bit 3 /
bogdanm	20:4263a77256ae	3718
bogdanm	20:4263a77256ae	3719	#define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /!<ADDHLD[3:0] bits (Address-hold phase duration) /
bogdanm	20:4263a77256ae	3720	#define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	20:4263a77256ae	3721	#define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	20:4263a77256ae	3722	#define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /!<Bit 2 /
bogdanm	20:4263a77256ae	3723	#define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /!<Bit 3 /
bogdanm	20:4263a77256ae	3724
bogdanm	20:4263a77256ae	3725	#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /!<DATAST [3:0] bits (Data-phase duration) /
bogdanm	20:4263a77256ae	3726	#define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /!<Bit 0 /
bogdanm	20:4263a77256ae	3727	#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /!<Bit 1 /
bogdanm	20:4263a77256ae	3728	#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /!<Bit 2 /
bogdanm	20:4263a77256ae	3729	#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /!<Bit 3 /
bogdanm	20:4263a77256ae	3730
bogdanm	20:4263a77256ae	3731	#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /!<BUSTURN[3:0] bits (Bus turnaround phase duration) /
bogdanm	20:4263a77256ae	3732	#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /!<Bit 0 /
bogdanm	20:4263a77256ae	3733	#define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /!<Bit 1 /
bogdanm	20:4263a77256ae	3734	#define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /!<Bit 2 /
bogdanm	20:4263a77256ae	3735	#define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /!<Bit 3 /
bogdanm	20:4263a77256ae	3736
bogdanm	20:4263a77256ae	3737	#define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /!<CLKDIV[3:0] bits (Clock divide ratio) /
bogdanm	20:4263a77256ae	3738	#define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /!<Bit 0 /
bogdanm	20:4263a77256ae	3739	#define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /!<Bit 1 /
bogdanm	20:4263a77256ae	3740	#define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /!<Bit 2 /
bogdanm	20:4263a77256ae	3741	#define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /!<Bit 3 /
bogdanm	20:4263a77256ae	3742
bogdanm	20:4263a77256ae	3743	#define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /!<DATLA[3:0] bits (Data latency) /
bogdanm	20:4263a77256ae	3744	#define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /!<Bit 0 /
bogdanm	20:4263a77256ae	3745	#define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /!<Bit 1 /
bogdanm	20:4263a77256ae	3746	#define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /!<Bit 2 /
bogdanm	20:4263a77256ae	3747	#define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /!<Bit 3 /
bogdanm	20:4263a77256ae	3748
bogdanm	20:4263a77256ae	3749	#define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /!<ACCMOD[1:0] bits (Access mode) /
bogdanm	20:4263a77256ae	3750	#define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /!<Bit 0 /
bogdanm	20:4263a77256ae	3751	#define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /!<Bit 1 /
bogdanm	20:4263a77256ae	3752
bogdanm	20:4263a77256ae	3753	/**************** Bit definition for FSMC_BTR4 register *****************/
bogdanm	20:4263a77256ae	3754	#define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /!<ADDSET[3:0] bits (Address setup phase duration) /
bogdanm	20:4263a77256ae	3755	#define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	20:4263a77256ae	3756	#define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	20:4263a77256ae	3757	#define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /!<Bit 2 /
bogdanm	20:4263a77256ae	3758	#define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /!<Bit 3 /
bogdanm	20:4263a77256ae	3759
bogdanm	20:4263a77256ae	3760	#define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /!<ADDHLD[3:0] bits (Address-hold phase duration) /
bogdanm	20:4263a77256ae	3761	#define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	20:4263a77256ae	3762	#define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	20:4263a77256ae	3763	#define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /!<Bit 2 /
bogdanm	20:4263a77256ae	3764	#define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /!<Bit 3 /
bogdanm	20:4263a77256ae	3765
bogdanm	20:4263a77256ae	3766	#define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /!<DATAST [3:0] bits (Data-phase duration) /
bogdanm	20:4263a77256ae	3767	#define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /!<Bit 0 /
bogdanm	20:4263a77256ae	3768	#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /!<Bit 1 /
bogdanm	20:4263a77256ae	3769	#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /!<Bit 2 /
bogdanm	20:4263a77256ae	3770	#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /!<Bit 3 /
bogdanm	20:4263a77256ae	3771
bogdanm	20:4263a77256ae	3772	#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /!<BUSTURN[3:0] bits (Bus turnaround phase duration) /
bogdanm	20:4263a77256ae	3773	#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /!<Bit 0 /
bogdanm	20:4263a77256ae	3774	#define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /!<Bit 1 /
bogdanm	20:4263a77256ae	3775	#define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /!<Bit 2 /
bogdanm	20:4263a77256ae	3776	#define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /!<Bit 3 /
bogdanm	20:4263a77256ae	3777
bogdanm	20:4263a77256ae	3778	#define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /!<CLKDIV[3:0] bits (Clock divide ratio) /
bogdanm	20:4263a77256ae	3779	#define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /!<Bit 0 /
bogdanm	20:4263a77256ae	3780	#define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /!<Bit 1 /
bogdanm	20:4263a77256ae	3781	#define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /!<Bit 2 /
bogdanm	20:4263a77256ae	3782	#define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /!<Bit 3 /
bogdanm	20:4263a77256ae	3783
bogdanm	20:4263a77256ae	3784	#define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /!<DATLA[3:0] bits (Data latency) /
bogdanm	20:4263a77256ae	3785	#define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /!<Bit 0 /
bogdanm	20:4263a77256ae	3786	#define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /!<Bit 1 /
bogdanm	20:4263a77256ae	3787	#define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /!<Bit 2 /
bogdanm	20:4263a77256ae	3788	#define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /!<Bit 3 /
bogdanm	20:4263a77256ae	3789
bogdanm	20:4263a77256ae	3790	#define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /!<ACCMOD[1:0] bits (Access mode) /
bogdanm	20:4263a77256ae	3791	#define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /!<Bit 0 /
bogdanm	20:4263a77256ae	3792	#define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /!<Bit 1 /
bogdanm	20:4263a77256ae	3793
bogdanm	20:4263a77256ae	3794	/**************** Bit definition for FSMC_BWTR1 register ****************/
bogdanm	20:4263a77256ae	3795	#define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /!<ADDSET[3:0] bits (Address setup phase duration) /
bogdanm	20:4263a77256ae	3796	#define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	20:4263a77256ae	3797	#define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	20:4263a77256ae	3798	#define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /!<Bit 2 /
bogdanm	20:4263a77256ae	3799	#define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /!<Bit 3 /
bogdanm	20:4263a77256ae	3800
bogdanm	20:4263a77256ae	3801	#define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /!<ADDHLD[3:0] bits (Address-hold phase duration) /
bogdanm	20:4263a77256ae	3802	#define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	20:4263a77256ae	3803	#define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	20:4263a77256ae	3804	#define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /!<Bit 2 /
bogdanm	20:4263a77256ae	3805	#define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /!<Bit 3 /
bogdanm	20:4263a77256ae	3806
bogdanm	20:4263a77256ae	3807	#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /!<DATAST [3:0] bits (Data-phase duration) /
bogdanm	20:4263a77256ae	3808	#define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /!<Bit 0 /
bogdanm	20:4263a77256ae	3809	#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /!<Bit 1 /
bogdanm	20:4263a77256ae	3810	#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /!<Bit 2 /
bogdanm	20:4263a77256ae	3811	#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /!<Bit 3 /
bogdanm	20:4263a77256ae	3812
bogdanm	20:4263a77256ae	3813	#define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /!<CLKDIV[3:0] bits (Clock divide ratio) /
bogdanm	20:4263a77256ae	3814	#define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /!<Bit 0 /
bogdanm	20:4263a77256ae	3815	#define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /!<Bit 1 /
bogdanm	20:4263a77256ae	3816	#define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /!<Bit 2 /
bogdanm	20:4263a77256ae	3817	#define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /!<Bit 3 /
bogdanm	20:4263a77256ae	3818
bogdanm	20:4263a77256ae	3819	#define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /!<DATLA[3:0] bits (Data latency) /
bogdanm	20:4263a77256ae	3820	#define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /!<Bit 0 /
bogdanm	20:4263a77256ae	3821	#define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /!<Bit 1 /
bogdanm	20:4263a77256ae	3822	#define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /!<Bit 2 /
bogdanm	20:4263a77256ae	3823	#define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /!<Bit 3 /
bogdanm	20:4263a77256ae	3824
bogdanm	20:4263a77256ae	3825	#define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /!<ACCMOD[1:0] bits (Access mode) /
bogdanm	20:4263a77256ae	3826	#define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /!<Bit 0 /
bogdanm	20:4263a77256ae	3827	#define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /!<Bit 1 /
bogdanm	20:4263a77256ae	3828
bogdanm	20:4263a77256ae	3829	/**************** Bit definition for FSMC_BWTR2 register ****************/
bogdanm	20:4263a77256ae	3830	#define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /!<ADDSET[3:0] bits (Address setup phase duration) /
bogdanm	20:4263a77256ae	3831	#define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	20:4263a77256ae	3832	#define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	20:4263a77256ae	3833	#define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /!<Bit 2 /
bogdanm	20:4263a77256ae	3834	#define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /!<Bit 3 /
bogdanm	20:4263a77256ae	3835
bogdanm	20:4263a77256ae	3836	#define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /!<ADDHLD[3:0] bits (Address-hold phase duration) /
bogdanm	20:4263a77256ae	3837	#define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	20:4263a77256ae	3838	#define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	20:4263a77256ae	3839	#define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /!<Bit 2 /
bogdanm	20:4263a77256ae	3840	#define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /!<Bit 3 /
bogdanm	20:4263a77256ae	3841
bogdanm	20:4263a77256ae	3842	#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /!<DATAST [3:0] bits (Data-phase duration) /
bogdanm	20:4263a77256ae	3843	#define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /!<Bit 0 /
bogdanm	20:4263a77256ae	3844	#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /!<Bit 1 /
bogdanm	20:4263a77256ae	3845	#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /!<Bit 2 /
bogdanm	20:4263a77256ae	3846	#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /!<Bit 3 /
bogdanm	20:4263a77256ae	3847
bogdanm	20:4263a77256ae	3848	#define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /!<CLKDIV[3:0] bits (Clock divide ratio) /
bogdanm	20:4263a77256ae	3849	#define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /!<Bit 0 /
bogdanm	20:4263a77256ae	3850	#define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /!<Bit 1/
bogdanm	20:4263a77256ae	3851	#define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /!<Bit 2 /
bogdanm	20:4263a77256ae	3852	#define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /!<Bit 3 /
bogdanm	20:4263a77256ae	3853
bogdanm	20:4263a77256ae	3854	#define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /!<DATLA[3:0] bits (Data latency) /
bogdanm	20:4263a77256ae	3855	#define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /!<Bit 0 /
bogdanm	20:4263a77256ae	3856	#define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /!<Bit 1 /
bogdanm	20:4263a77256ae	3857	#define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /!<Bit 2 /
bogdanm	20:4263a77256ae	3858	#define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /!<Bit 3 /
bogdanm	20:4263a77256ae	3859
bogdanm	20:4263a77256ae	3860	#define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /!<ACCMOD[1:0] bits (Access mode) /
bogdanm	20:4263a77256ae	3861	#define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /!<Bit 0 /
bogdanm	20:4263a77256ae	3862	#define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /!<Bit 1 /
bogdanm	20:4263a77256ae	3863
bogdanm	20:4263a77256ae	3864	/**************** Bit definition for FSMC_BWTR3 register ****************/
bogdanm	20:4263a77256ae	3865	#define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /!<ADDSET[3:0] bits (Address setup phase duration) /
bogdanm	20:4263a77256ae	3866	#define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	20:4263a77256ae	3867	#define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	20:4263a77256ae	3868	#define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /!<Bit 2 /
bogdanm	20:4263a77256ae	3869	#define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /!<Bit 3 /
bogdanm	20:4263a77256ae	3870
bogdanm	20:4263a77256ae	3871	#define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /!<ADDHLD[3:0] bits (Address-hold phase duration) /
bogdanm	20:4263a77256ae	3872	#define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	20:4263a77256ae	3873	#define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	20:4263a77256ae	3874	#define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /!<Bit 2 /
bogdanm	20:4263a77256ae	3875	#define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /!<Bit 3 /
bogdanm	20:4263a77256ae	3876
bogdanm	20:4263a77256ae	3877	#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /!<DATAST [3:0] bits (Data-phase duration) /
bogdanm	20:4263a77256ae	3878	#define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /!<Bit 0 /
bogdanm	20:4263a77256ae	3879	#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /!<Bit 1 /
bogdanm	20:4263a77256ae	3880	#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /!<Bit 2 /
bogdanm	20:4263a77256ae	3881	#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /!<Bit 3 /
bogdanm	20:4263a77256ae	3882
bogdanm	20:4263a77256ae	3883	#define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /!<CLKDIV[3:0] bits (Clock divide ratio) /
bogdanm	20:4263a77256ae	3884	#define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /!<Bit 0 /
bogdanm	20:4263a77256ae	3885	#define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /!<Bit 1 /
bogdanm	20:4263a77256ae	3886	#define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /!<Bit 2 /
bogdanm	20:4263a77256ae	3887	#define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /!<Bit 3 /
bogdanm	20:4263a77256ae	3888
bogdanm	20:4263a77256ae	3889	#define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /!<DATLA[3:0] bits (Data latency) /
bogdanm	20:4263a77256ae	3890	#define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /!<Bit 0 /
bogdanm	20:4263a77256ae	3891	#define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /!<Bit 1 /
bogdanm	20:4263a77256ae	3892	#define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /!<Bit 2 /
bogdanm	20:4263a77256ae	3893	#define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /!<Bit 3 /
bogdanm	20:4263a77256ae	3894
bogdanm	20:4263a77256ae	3895	#define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /!<ACCMOD[1:0] bits (Access mode) /
bogdanm	20:4263a77256ae	3896	#define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /!<Bit 0 /
bogdanm	20:4263a77256ae	3897	#define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /!<Bit 1 /
bogdanm	20:4263a77256ae	3898
bogdanm	20:4263a77256ae	3899	/**************** Bit definition for FSMC_BWTR4 register ****************/
bogdanm	20:4263a77256ae	3900	#define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /!<ADDSET[3:0] bits (Address setup phase duration) /
bogdanm	20:4263a77256ae	3901	#define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	20:4263a77256ae	3902	#define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	20:4263a77256ae	3903	#define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /!<Bit 2 /
bogdanm	20:4263a77256ae	3904	#define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /!<Bit 3 /
bogdanm	20:4263a77256ae	3905
bogdanm	20:4263a77256ae	3906	#define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /!<ADDHLD[3:0] bits (Address-hold phase duration) /
bogdanm	20:4263a77256ae	3907	#define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	20:4263a77256ae	3908	#define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	20:4263a77256ae	3909	#define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /!<Bit 2 /
bogdanm	20:4263a77256ae	3910	#define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /!<Bit 3 /
bogdanm	20:4263a77256ae	3911
bogdanm	20:4263a77256ae	3912	#define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /!<DATAST [3:0] bits (Data-phase duration) /
bogdanm	20:4263a77256ae	3913	#define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /!<Bit 0 /
bogdanm	20:4263a77256ae	3914	#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /!<Bit 1 /
bogdanm	20:4263a77256ae	3915	#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /!<Bit 2 /
bogdanm	20:4263a77256ae	3916	#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /!<Bit 3 /
bogdanm	20:4263a77256ae	3917
bogdanm	20:4263a77256ae	3918	#define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /!<CLKDIV[3:0] bits (Clock divide ratio) /
bogdanm	20:4263a77256ae	3919	#define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /!<Bit 0 /
bogdanm	20:4263a77256ae	3920	#define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /!<Bit 1 /
bogdanm	20:4263a77256ae	3921	#define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /!<Bit 2 /
bogdanm	20:4263a77256ae	3922	#define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /!<Bit 3 /
bogdanm	20:4263a77256ae	3923
bogdanm	20:4263a77256ae	3924	#define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /!<DATLA[3:0] bits (Data latency) /
bogdanm	20:4263a77256ae	3925	#define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /!<Bit 0 /
bogdanm	20:4263a77256ae	3926	#define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /!<Bit 1 /
bogdanm	20:4263a77256ae	3927	#define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /!<Bit 2 /
bogdanm	20:4263a77256ae	3928	#define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /!<Bit 3 /
bogdanm	20:4263a77256ae	3929
bogdanm	20:4263a77256ae	3930	#define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /!<ACCMOD[1:0] bits (Access mode) /
bogdanm	20:4263a77256ae	3931	#define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /!<Bit 0 /
bogdanm	20:4263a77256ae	3932	#define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /!<Bit 1 /
bogdanm	20:4263a77256ae	3933
bogdanm	20:4263a77256ae	3934	/**************** Bit definition for FSMC_PCR2 register *****************/
bogdanm	20:4263a77256ae	3935	#define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) /!<Wait feature enable bit /
bogdanm	20:4263a77256ae	3936	#define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) /!<PC Card/NAND Flash memory bank enable bit /
bogdanm	20:4263a77256ae	3937	#define FSMC_PCR2_PTYP ((uint32_t)0x00000008) /!<Memory type /
bogdanm	20:4263a77256ae	3938
bogdanm	20:4263a77256ae	3939	#define FSMC_PCR2_PWID ((uint32_t)0x00000030) /!<PWID[1:0] bits (NAND Flash databus width) /
bogdanm	20:4263a77256ae	3940	#define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	20:4263a77256ae	3941	#define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	20:4263a77256ae	3942
bogdanm	20:4263a77256ae	3943	#define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) /!<ECC computation logic enable bit /
bogdanm	20:4263a77256ae	3944
bogdanm	20:4263a77256ae	3945	#define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) /!<TCLR[3:0] bits (CLE to RE delay) /
bogdanm	20:4263a77256ae	3946	#define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /!<Bit 0 /
bogdanm	20:4263a77256ae	3947	#define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /!<Bit 1 /
bogdanm	20:4263a77256ae	3948	#define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /!<Bit 2 /
bogdanm	20:4263a77256ae	3949	#define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /!<Bit 3 /
bogdanm	20:4263a77256ae	3950
bogdanm	20:4263a77256ae	3951	#define FSMC_PCR2_TAR ((uint32_t)0x0001E000) /!<TAR[3:0] bits (ALE to RE delay) /
bogdanm	20:4263a77256ae	3952	#define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) /!<Bit 0 /
bogdanm	20:4263a77256ae	3953	#define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) /!<Bit 1 /
bogdanm	20:4263a77256ae	3954	#define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) /!<Bit 2 /
bogdanm	20:4263a77256ae	3955	#define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) /!<Bit 3 /
bogdanm	20:4263a77256ae	3956
bogdanm	20:4263a77256ae	3957	#define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) /!<ECCPS[1:0] bits (ECC page size) /
bogdanm	20:4263a77256ae	3958	#define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /!<Bit 0 /
bogdanm	20:4263a77256ae	3959	#define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /!<Bit 1 /
bogdanm	20:4263a77256ae	3960	#define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /!<Bit 2 /
bogdanm	20:4263a77256ae	3961
bogdanm	20:4263a77256ae	3962	/**************** Bit definition for FSMC_PCR3 register *****************/
bogdanm	20:4263a77256ae	3963	#define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) /!<Wait feature enable bit /
bogdanm	20:4263a77256ae	3964	#define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) /!<PC Card/NAND Flash memory bank enable bit /
bogdanm	20:4263a77256ae	3965	#define FSMC_PCR3_PTYP ((uint32_t)0x00000008) /!<Memory type /
bogdanm	20:4263a77256ae	3966
bogdanm	20:4263a77256ae	3967	#define FSMC_PCR3_PWID ((uint32_t)0x00000030) /!<PWID[1:0] bits (NAND Flash databus width) /
bogdanm	20:4263a77256ae	3968	#define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	20:4263a77256ae	3969	#define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	20:4263a77256ae	3970
bogdanm	20:4263a77256ae	3971	#define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) /!<ECC computation logic enable bit /
bogdanm	20:4263a77256ae	3972
bogdanm	20:4263a77256ae	3973	#define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) /!<TCLR[3:0] bits (CLE to RE delay) /
bogdanm	20:4263a77256ae	3974	#define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /!<Bit 0 /
bogdanm	20:4263a77256ae	3975	#define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /!<Bit 1 /
bogdanm	20:4263a77256ae	3976	#define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /!<Bit 2 /
bogdanm	20:4263a77256ae	3977	#define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /!<Bit 3 /
bogdanm	20:4263a77256ae	3978
bogdanm	20:4263a77256ae	3979	#define FSMC_PCR3_TAR ((uint32_t)0x0001E000) /!<TAR[3:0] bits (ALE to RE delay) /
bogdanm	20:4263a77256ae	3980	#define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) /!<Bit 0 /
bogdanm	20:4263a77256ae	3981	#define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) /!<Bit 1 /
bogdanm	20:4263a77256ae	3982	#define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) /!<Bit 2 /
bogdanm	20:4263a77256ae	3983	#define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) /!<Bit 3 /
bogdanm	20:4263a77256ae	3984
bogdanm	20:4263a77256ae	3985	#define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) /!<ECCPS[2:0] bits (ECC page size) /
bogdanm	20:4263a77256ae	3986	#define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /!<Bit 0 /
bogdanm	20:4263a77256ae	3987	#define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /!<Bit 1 /
bogdanm	20:4263a77256ae	3988	#define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /!<Bit 2 /
bogdanm	20:4263a77256ae	3989
bogdanm	20:4263a77256ae	3990	/**************** Bit definition for FSMC_PCR4 register *****************/
bogdanm	20:4263a77256ae	3991	#define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) /!<Wait feature enable bit /
bogdanm	20:4263a77256ae	3992	#define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) /!<PC Card/NAND Flash memory bank enable bit /
bogdanm	20:4263a77256ae	3993	#define FSMC_PCR4_PTYP ((uint32_t)0x00000008) /!<Memory type /
bogdanm	20:4263a77256ae	3994
bogdanm	20:4263a77256ae	3995	#define FSMC_PCR4_PWID ((uint32_t)0x00000030) /!<PWID[1:0] bits (NAND Flash databus width) /
bogdanm	20:4263a77256ae	3996	#define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	20:4263a77256ae	3997	#define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	20:4263a77256ae	3998
bogdanm	20:4263a77256ae	3999	#define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) /!<ECC computation logic enable bit /
bogdanm	20:4263a77256ae	4000
bogdanm	20:4263a77256ae	4001	#define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) /!<TCLR[3:0] bits (CLE to RE delay) /
bogdanm	20:4263a77256ae	4002	#define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /!<Bit 0 /
bogdanm	20:4263a77256ae	4003	#define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /!<Bit 1 /
bogdanm	20:4263a77256ae	4004	#define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /!<Bit 2 /
bogdanm	20:4263a77256ae	4005	#define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /!<Bit 3 /
bogdanm	20:4263a77256ae	4006
bogdanm	20:4263a77256ae	4007	#define FSMC_PCR4_TAR ((uint32_t)0x0001E000) /!<TAR[3:0] bits (ALE to RE delay) /
bogdanm	20:4263a77256ae	4008	#define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) /!<Bit 0 /
bogdanm	20:4263a77256ae	4009	#define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) /!<Bit 1 /
bogdanm	20:4263a77256ae	4010	#define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) /!<Bit 2 /
bogdanm	20:4263a77256ae	4011	#define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) /!<Bit 3 /
bogdanm	20:4263a77256ae	4012
bogdanm	20:4263a77256ae	4013	#define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) /!<ECCPS[2:0] bits (ECC page size) /
bogdanm	20:4263a77256ae	4014	#define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /!<Bit 0 /
bogdanm	20:4263a77256ae	4015	#define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /!<Bit 1 /
bogdanm	20:4263a77256ae	4016	#define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /!<Bit 2 /
bogdanm	20:4263a77256ae	4017
bogdanm	20:4263a77256ae	4018	/***************** Bit definition for FSMC_SR2 register *****************/
bogdanm	20:4263a77256ae	4019	#define FSMC_SR2_IRS ((uint8_t)0x01) /!<Interrupt Rising Edge status /
bogdanm	20:4263a77256ae	4020	#define FSMC_SR2_ILS ((uint8_t)0x02) /!<Interrupt Level status /
bogdanm	20:4263a77256ae	4021	#define FSMC_SR2_IFS ((uint8_t)0x04) /!<Interrupt Falling Edge status /
bogdanm	20:4263a77256ae	4022	#define FSMC_SR2_IREN ((uint8_t)0x08) /!<Interrupt Rising Edge detection Enable bit /
bogdanm	20:4263a77256ae	4023	#define FSMC_SR2_ILEN ((uint8_t)0x10) /!<Interrupt Level detection Enable bit /
bogdanm	20:4263a77256ae	4024	#define FSMC_SR2_IFEN ((uint8_t)0x20) /!<Interrupt Falling Edge detection Enable bit /
bogdanm	20:4263a77256ae	4025	#define FSMC_SR2_FEMPT ((uint8_t)0x40) /!<FIFO empty /
bogdanm	20:4263a77256ae	4026
bogdanm	20:4263a77256ae	4027	/***************** Bit definition for FSMC_SR3 register *****************/
bogdanm	20:4263a77256ae	4028	#define FSMC_SR3_IRS ((uint8_t)0x01) /!<Interrupt Rising Edge status /
bogdanm	20:4263a77256ae	4029	#define FSMC_SR3_ILS ((uint8_t)0x02) /!<Interrupt Level status /
bogdanm	20:4263a77256ae	4030	#define FSMC_SR3_IFS ((uint8_t)0x04) /!<Interrupt Falling Edge status /
bogdanm	20:4263a77256ae	4031	#define FSMC_SR3_IREN ((uint8_t)0x08) /!<Interrupt Rising Edge detection Enable bit /
bogdanm	20:4263a77256ae	4032	#define FSMC_SR3_ILEN ((uint8_t)0x10) /!<Interrupt Level detection Enable bit /
bogdanm	20:4263a77256ae	4033	#define FSMC_SR3_IFEN ((uint8_t)0x20) /!<Interrupt Falling Edge detection Enable bit /
bogdanm	20:4263a77256ae	4034	#define FSMC_SR3_FEMPT ((uint8_t)0x40) /!<FIFO empty /
bogdanm	20:4263a77256ae	4035
bogdanm	20:4263a77256ae	4036	/***************** Bit definition for FSMC_SR4 register *****************/
bogdanm	20:4263a77256ae	4037	#define FSMC_SR4_IRS ((uint8_t)0x01) /!<Interrupt Rising Edge status /
bogdanm	20:4263a77256ae	4038	#define FSMC_SR4_ILS ((uint8_t)0x02) /!<Interrupt Level status /
bogdanm	20:4263a77256ae	4039	#define FSMC_SR4_IFS ((uint8_t)0x04) /!<Interrupt Falling Edge status /
bogdanm	20:4263a77256ae	4040	#define FSMC_SR4_IREN ((uint8_t)0x08) /!<Interrupt Rising Edge detection Enable bit /
bogdanm	20:4263a77256ae	4041	#define FSMC_SR4_ILEN ((uint8_t)0x10) /!<Interrupt Level detection Enable bit /
bogdanm	20:4263a77256ae	4042	#define FSMC_SR4_IFEN ((uint8_t)0x20) /!<Interrupt Falling Edge detection Enable bit /
bogdanm	20:4263a77256ae	4043	#define FSMC_SR4_FEMPT ((uint8_t)0x40) /!<FIFO empty /
bogdanm	20:4263a77256ae	4044
bogdanm	20:4263a77256ae	4045	/**************** Bit definition for FSMC_PMEM2 register ****************/
bogdanm	20:4263a77256ae	4046	#define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /!<MEMSET2[7:0] bits (Common memory 2 setup time) /
bogdanm	20:4263a77256ae	4047	#define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	20:4263a77256ae	4048	#define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	20:4263a77256ae	4049	#define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /!<Bit 2 /
bogdanm	20:4263a77256ae	4050	#define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /!<Bit 3 /
bogdanm	20:4263a77256ae	4051	#define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /!<Bit 4 /
bogdanm	20:4263a77256ae	4052	#define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /!<Bit 5 /
bogdanm	20:4263a77256ae	4053	#define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /!<Bit 6 /
bogdanm	20:4263a77256ae	4054	#define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /!<Bit 7 /
bogdanm	20:4263a77256ae	4055
bogdanm	20:4263a77256ae	4056	#define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /!<MEMWAIT2[7:0] bits (Common memory 2 wait time) /
bogdanm	20:4263a77256ae	4057	#define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /!<Bit 0 /
bogdanm	20:4263a77256ae	4058	#define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /!<Bit 1 /
bogdanm	20:4263a77256ae	4059	#define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /!<Bit 2 /
bogdanm	20:4263a77256ae	4060	#define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /!<Bit 3 /
bogdanm	20:4263a77256ae	4061	#define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /!<Bit 4 /
bogdanm	20:4263a77256ae	4062	#define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /!<Bit 5 /
bogdanm	20:4263a77256ae	4063	#define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /!<Bit 6 /
bogdanm	20:4263a77256ae	4064	#define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /!<Bit 7 /
bogdanm	20:4263a77256ae	4065
bogdanm	20:4263a77256ae	4066	#define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /!<MEMHOLD2[7:0] bits (Common memory 2 hold time) /
bogdanm	20:4263a77256ae	4067	#define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /!<Bit 0 /
bogdanm	20:4263a77256ae	4068	#define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /!<Bit 1 /
bogdanm	20:4263a77256ae	4069	#define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /!<Bit 2 /
bogdanm	20:4263a77256ae	4070	#define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /!<Bit 3 /
bogdanm	20:4263a77256ae	4071	#define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /!<Bit 4 /
bogdanm	20:4263a77256ae	4072	#define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /!<Bit 5 /
bogdanm	20:4263a77256ae	4073	#define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /!<Bit 6 /
bogdanm	20:4263a77256ae	4074	#define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /!<Bit 7 /
bogdanm	20:4263a77256ae	4075
bogdanm	20:4263a77256ae	4076	#define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) /
bogdanm	20:4263a77256ae	4077	#define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /!<Bit 0 /
bogdanm	20:4263a77256ae	4078	#define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /!<Bit 1 /
bogdanm	20:4263a77256ae	4079	#define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /!<Bit 2 /
bogdanm	20:4263a77256ae	4080	#define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /!<Bit 3 /
bogdanm	20:4263a77256ae	4081	#define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /!<Bit 4 /
bogdanm	20:4263a77256ae	4082	#define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /!<Bit 5 /
bogdanm	20:4263a77256ae	4083	#define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /!<Bit 6 /
bogdanm	20:4263a77256ae	4084	#define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /!<Bit 7 /
bogdanm	20:4263a77256ae	4085
bogdanm	20:4263a77256ae	4086	/**************** Bit definition for FSMC_PMEM3 register ****************/
bogdanm	20:4263a77256ae	4087	#define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /!<MEMSET3[7:0] bits (Common memory 3 setup time) /
bogdanm	20:4263a77256ae	4088	#define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	20:4263a77256ae	4089	#define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	20:4263a77256ae	4090	#define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /!<Bit 2 /
bogdanm	20:4263a77256ae	4091	#define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /!<Bit 3 /
bogdanm	20:4263a77256ae	4092	#define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /!<Bit 4 /
bogdanm	20:4263a77256ae	4093	#define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /!<Bit 5 /
bogdanm	20:4263a77256ae	4094	#define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /!<Bit 6 /
bogdanm	20:4263a77256ae	4095	#define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /!<Bit 7 /
bogdanm	20:4263a77256ae	4096
bogdanm	20:4263a77256ae	4097	#define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /!<MEMWAIT3[7:0] bits (Common memory 3 wait time) /
bogdanm	20:4263a77256ae	4098	#define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /!<Bit 0 /
bogdanm	20:4263a77256ae	4099	#define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /!<Bit 1 /
bogdanm	20:4263a77256ae	4100	#define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /!<Bit 2 /
bogdanm	20:4263a77256ae	4101	#define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /!<Bit 3 /
bogdanm	20:4263a77256ae	4102	#define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /!<Bit 4 /
bogdanm	20:4263a77256ae	4103	#define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /!<Bit 5 /
bogdanm	20:4263a77256ae	4104	#define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /!<Bit 6 /
bogdanm	20:4263a77256ae	4105	#define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /!<Bit 7 /
bogdanm	20:4263a77256ae	4106
bogdanm	20:4263a77256ae	4107	#define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /!<MEMHOLD3[7:0] bits (Common memory 3 hold time) /
bogdanm	20:4263a77256ae	4108	#define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /!<Bit 0 /
bogdanm	20:4263a77256ae	4109	#define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /!<Bit 1 /
bogdanm	20:4263a77256ae	4110	#define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /!<Bit 2 /
bogdanm	20:4263a77256ae	4111	#define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /!<Bit 3 /
bogdanm	20:4263a77256ae	4112	#define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /!<Bit 4 /
bogdanm	20:4263a77256ae	4113	#define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /!<Bit 5 /
bogdanm	20:4263a77256ae	4114	#define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /!<Bit 6 /
bogdanm	20:4263a77256ae	4115	#define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /!<Bit 7 /
bogdanm	20:4263a77256ae	4116
bogdanm	20:4263a77256ae	4117	#define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) /
bogdanm	20:4263a77256ae	4118	#define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /!<Bit 0 /
bogdanm	20:4263a77256ae	4119	#define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /!<Bit 1 /
bogdanm	20:4263a77256ae	4120	#define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /!<Bit 2 /
bogdanm	20:4263a77256ae	4121	#define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /!<Bit 3 /
bogdanm	20:4263a77256ae	4122	#define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /!<Bit 4 /
bogdanm	20:4263a77256ae	4123	#define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /!<Bit 5 /
bogdanm	20:4263a77256ae	4124	#define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /!<Bit 6 /
bogdanm	20:4263a77256ae	4125	#define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /!<Bit 7 /
bogdanm	20:4263a77256ae	4126
bogdanm	20:4263a77256ae	4127	/**************** Bit definition for FSMC_PMEM4 register ****************/
bogdanm	20:4263a77256ae	4128	#define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /!<MEMSET4[7:0] bits (Common memory 4 setup time) /
bogdanm	20:4263a77256ae	4129	#define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	20:4263a77256ae	4130	#define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	20:4263a77256ae	4131	#define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /!<Bit 2 /
bogdanm	20:4263a77256ae	4132	#define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /!<Bit 3 /
bogdanm	20:4263a77256ae	4133	#define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /!<Bit 4 /
bogdanm	20:4263a77256ae	4134	#define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /!<Bit 5 /
bogdanm	20:4263a77256ae	4135	#define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /!<Bit 6 /
bogdanm	20:4263a77256ae	4136	#define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /!<Bit 7 /
bogdanm	20:4263a77256ae	4137
bogdanm	20:4263a77256ae	4138	#define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /!<MEMWAIT4[7:0] bits (Common memory 4 wait time) /
bogdanm	20:4263a77256ae	4139	#define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /!<Bit 0 /
bogdanm	20:4263a77256ae	4140	#define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /!<Bit 1 /
bogdanm	20:4263a77256ae	4141	#define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /!<Bit 2 /
bogdanm	20:4263a77256ae	4142	#define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /!<Bit 3 /
bogdanm	20:4263a77256ae	4143	#define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /!<Bit 4 /
bogdanm	20:4263a77256ae	4144	#define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /!<Bit 5 /
bogdanm	20:4263a77256ae	4145	#define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /!<Bit 6 /
bogdanm	20:4263a77256ae	4146	#define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /!<Bit 7 /
bogdanm	20:4263a77256ae	4147
bogdanm	20:4263a77256ae	4148	#define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /!<MEMHOLD4[7:0] bits (Common memory 4 hold time) /
bogdanm	20:4263a77256ae	4149	#define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /!<Bit 0 /
bogdanm	20:4263a77256ae	4150	#define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /!<Bit 1 /
bogdanm	20:4263a77256ae	4151	#define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /!<Bit 2 /
bogdanm	20:4263a77256ae	4152	#define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /!<Bit 3 /
bogdanm	20:4263a77256ae	4153	#define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /!<Bit 4 /
bogdanm	20:4263a77256ae	4154	#define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /!<Bit 5 /
bogdanm	20:4263a77256ae	4155	#define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /!<Bit 6 /
bogdanm	20:4263a77256ae	4156	#define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /!<Bit 7 /
bogdanm	20:4263a77256ae	4157
bogdanm	20:4263a77256ae	4158	#define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) /
bogdanm	20:4263a77256ae	4159	#define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /!<Bit 0 /
bogdanm	20:4263a77256ae	4160	#define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /!<Bit 1 /
bogdanm	20:4263a77256ae	4161	#define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /!<Bit 2 /
bogdanm	20:4263a77256ae	4162	#define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /!<Bit 3 /
bogdanm	20:4263a77256ae	4163	#define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /!<Bit 4 /
bogdanm	20:4263a77256ae	4164	#define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /!<Bit 5 /
bogdanm	20:4263a77256ae	4165	#define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /!<Bit 6 /
bogdanm	20:4263a77256ae	4166	#define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /!<Bit 7 /
bogdanm	20:4263a77256ae	4167
bogdanm	20:4263a77256ae	4168	/**************** Bit definition for FSMC_PATT2 register ****************/
bogdanm	20:4263a77256ae	4169	#define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /!<ATTSET2[7:0] bits (Attribute memory 2 setup time) /
bogdanm	20:4263a77256ae	4170	#define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	20:4263a77256ae	4171	#define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	20:4263a77256ae	4172	#define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /!<Bit 2 /
bogdanm	20:4263a77256ae	4173	#define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /!<Bit 3 /
bogdanm	20:4263a77256ae	4174	#define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /!<Bit 4 /
bogdanm	20:4263a77256ae	4175	#define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /!<Bit 5 /
bogdanm	20:4263a77256ae	4176	#define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /!<Bit 6 /
bogdanm	20:4263a77256ae	4177	#define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /!<Bit 7 /
bogdanm	20:4263a77256ae	4178
bogdanm	20:4263a77256ae	4179	#define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) /
bogdanm	20:4263a77256ae	4180	#define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /!<Bit 0 /
bogdanm	20:4263a77256ae	4181	#define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /!<Bit 1 /
bogdanm	20:4263a77256ae	4182	#define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /!<Bit 2 /
bogdanm	20:4263a77256ae	4183	#define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /!<Bit 3 /
bogdanm	20:4263a77256ae	4184	#define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /!<Bit 4 /
bogdanm	20:4263a77256ae	4185	#define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /!<Bit 5 /
bogdanm	20:4263a77256ae	4186	#define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /!<Bit 6 /
bogdanm	20:4263a77256ae	4187	#define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /!<Bit 7 /
bogdanm	20:4263a77256ae	4188
bogdanm	20:4263a77256ae	4189	#define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) /
bogdanm	20:4263a77256ae	4190	#define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /!<Bit 0 /
bogdanm	20:4263a77256ae	4191	#define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /!<Bit 1 /
bogdanm	20:4263a77256ae	4192	#define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /!<Bit 2 /
bogdanm	20:4263a77256ae	4193	#define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /!<Bit 3 /
bogdanm	20:4263a77256ae	4194	#define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /!<Bit 4 /
bogdanm	20:4263a77256ae	4195	#define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /!<Bit 5 /
bogdanm	20:4263a77256ae	4196	#define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /!<Bit 6 /
bogdanm	20:4263a77256ae	4197	#define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /!<Bit 7 /
bogdanm	20:4263a77256ae	4198
bogdanm	20:4263a77256ae	4199	#define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) /
bogdanm	20:4263a77256ae	4200	#define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /!<Bit 0 /
bogdanm	20:4263a77256ae	4201	#define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /!<Bit 1 /
bogdanm	20:4263a77256ae	4202	#define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /!<Bit 2 /
bogdanm	20:4263a77256ae	4203	#define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /!<Bit 3 /
bogdanm	20:4263a77256ae	4204	#define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /!<Bit 4 /
bogdanm	20:4263a77256ae	4205	#define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /!<Bit 5 /
bogdanm	20:4263a77256ae	4206	#define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /!<Bit 6 /
bogdanm	20:4263a77256ae	4207	#define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /!<Bit 7 /
bogdanm	20:4263a77256ae	4208
bogdanm	20:4263a77256ae	4209	/**************** Bit definition for FSMC_PATT3 register ****************/
bogdanm	20:4263a77256ae	4210	#define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /!<ATTSET3[7:0] bits (Attribute memory 3 setup time) /
bogdanm	20:4263a77256ae	4211	#define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	20:4263a77256ae	4212	#define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	20:4263a77256ae	4213	#define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /!<Bit 2 /
bogdanm	20:4263a77256ae	4214	#define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /!<Bit 3 /
bogdanm	20:4263a77256ae	4215	#define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /!<Bit 4 /
bogdanm	20:4263a77256ae	4216	#define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /!<Bit 5 /
bogdanm	20:4263a77256ae	4217	#define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /!<Bit 6 /
bogdanm	20:4263a77256ae	4218	#define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /!<Bit 7 /
bogdanm	20:4263a77256ae	4219
bogdanm	20:4263a77256ae	4220	#define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) /
bogdanm	20:4263a77256ae	4221	#define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /!<Bit 0 /
bogdanm	20:4263a77256ae	4222	#define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /!<Bit 1 /
bogdanm	20:4263a77256ae	4223	#define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /!<Bit 2 /
bogdanm	20:4263a77256ae	4224	#define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /!<Bit 3 /
bogdanm	20:4263a77256ae	4225	#define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /!<Bit 4 /
bogdanm	20:4263a77256ae	4226	#define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /!<Bit 5 /
bogdanm	20:4263a77256ae	4227	#define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /!<Bit 6 /
bogdanm	20:4263a77256ae	4228	#define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /!<Bit 7 /
bogdanm	20:4263a77256ae	4229
bogdanm	20:4263a77256ae	4230	#define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) /
bogdanm	20:4263a77256ae	4231	#define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /!<Bit 0 /
bogdanm	20:4263a77256ae	4232	#define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /!<Bit 1 /
bogdanm	20:4263a77256ae	4233	#define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /!<Bit 2 /
bogdanm	20:4263a77256ae	4234	#define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /!<Bit 3 /
bogdanm	20:4263a77256ae	4235	#define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /!<Bit 4 /
bogdanm	20:4263a77256ae	4236	#define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /!<Bit 5 /
bogdanm	20:4263a77256ae	4237	#define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /!<Bit 6 /
bogdanm	20:4263a77256ae	4238	#define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /!<Bit 7 /
bogdanm	20:4263a77256ae	4239
bogdanm	20:4263a77256ae	4240	#define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) /
bogdanm	20:4263a77256ae	4241	#define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /!<Bit 0 /
bogdanm	20:4263a77256ae	4242	#define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /!<Bit 1 /
bogdanm	20:4263a77256ae	4243	#define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /!<Bit 2 /
bogdanm	20:4263a77256ae	4244	#define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /!<Bit 3 /
bogdanm	20:4263a77256ae	4245	#define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /!<Bit 4 /
bogdanm	20:4263a77256ae	4246	#define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /!<Bit 5 /
bogdanm	20:4263a77256ae	4247	#define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /!<Bit 6 /
bogdanm	20:4263a77256ae	4248	#define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /!<Bit 7 /
bogdanm	20:4263a77256ae	4249
bogdanm	20:4263a77256ae	4250	/**************** Bit definition for FSMC_PATT4 register ****************/
bogdanm	20:4263a77256ae	4251	#define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /!<ATTSET4[7:0] bits (Attribute memory 4 setup time) /
bogdanm	20:4263a77256ae	4252	#define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	20:4263a77256ae	4253	#define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	20:4263a77256ae	4254	#define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /!<Bit 2 /
bogdanm	20:4263a77256ae	4255	#define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /!<Bit 3 /
bogdanm	20:4263a77256ae	4256	#define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /!<Bit 4 /
bogdanm	20:4263a77256ae	4257	#define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /!<Bit 5 /
bogdanm	20:4263a77256ae	4258	#define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /!<Bit 6 /
bogdanm	20:4263a77256ae	4259	#define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /!<Bit 7 /
bogdanm	20:4263a77256ae	4260
bogdanm	20:4263a77256ae	4261	#define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) /
bogdanm	20:4263a77256ae	4262	#define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /!<Bit 0 /
bogdanm	20:4263a77256ae	4263	#define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /!<Bit 1 /
bogdanm	20:4263a77256ae	4264	#define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /!<Bit 2 /
bogdanm	20:4263a77256ae	4265	#define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /!<Bit 3 /
bogdanm	20:4263a77256ae	4266	#define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /!<Bit 4 /
bogdanm	20:4263a77256ae	4267	#define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /!<Bit 5 /
bogdanm	20:4263a77256ae	4268	#define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /!<Bit 6 /
bogdanm	20:4263a77256ae	4269	#define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /!<Bit 7 /
bogdanm	20:4263a77256ae	4270
bogdanm	20:4263a77256ae	4271	#define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) /
bogdanm	20:4263a77256ae	4272	#define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /!<Bit 0 /
bogdanm	20:4263a77256ae	4273	#define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /!<Bit 1 /
bogdanm	20:4263a77256ae	4274	#define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /!<Bit 2 /
bogdanm	20:4263a77256ae	4275	#define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /!<Bit 3 /
bogdanm	20:4263a77256ae	4276	#define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /!<Bit 4 /
bogdanm	20:4263a77256ae	4277	#define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /!<Bit 5 /
bogdanm	20:4263a77256ae	4278	#define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /!<Bit 6 /
bogdanm	20:4263a77256ae	4279	#define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /!<Bit 7 /
bogdanm	20:4263a77256ae	4280
bogdanm	20:4263a77256ae	4281	#define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) /
bogdanm	20:4263a77256ae	4282	#define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /!<Bit 0 /
bogdanm	20:4263a77256ae	4283	#define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /!<Bit 1 /
bogdanm	20:4263a77256ae	4284	#define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /!<Bit 2 /
bogdanm	20:4263a77256ae	4285	#define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /!<Bit 3 /
bogdanm	20:4263a77256ae	4286	#define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /!<Bit 4 /
bogdanm	20:4263a77256ae	4287	#define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /!<Bit 5 /
bogdanm	20:4263a77256ae	4288	#define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /!<Bit 6 /
bogdanm	20:4263a77256ae	4289	#define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /!<Bit 7 /
bogdanm	20:4263a77256ae	4290
bogdanm	20:4263a77256ae	4291	/**************** Bit definition for FSMC_PIO4 register *****************/
bogdanm	20:4263a77256ae	4292	#define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /!<IOSET4[7:0] bits (I/O 4 setup time) /
bogdanm	20:4263a77256ae	4293	#define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	20:4263a77256ae	4294	#define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	20:4263a77256ae	4295	#define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /!<Bit 2 /
bogdanm	20:4263a77256ae	4296	#define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /!<Bit 3 /
bogdanm	20:4263a77256ae	4297	#define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /!<Bit 4 /
bogdanm	20:4263a77256ae	4298	#define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /!<Bit 5 /
bogdanm	20:4263a77256ae	4299	#define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /!<Bit 6 /
bogdanm	20:4263a77256ae	4300	#define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /!<Bit 7 /
bogdanm	20:4263a77256ae	4301
bogdanm	20:4263a77256ae	4302	#define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /!<IOWAIT4[7:0] bits (I/O 4 wait time) /
bogdanm	20:4263a77256ae	4303	#define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /!<Bit 0 /
bogdanm	20:4263a77256ae	4304	#define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /!<Bit 1 /
bogdanm	20:4263a77256ae	4305	#define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /!<Bit 2 /
bogdanm	20:4263a77256ae	4306	#define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /!<Bit 3 /
bogdanm	20:4263a77256ae	4307	#define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /!<Bit 4 /
bogdanm	20:4263a77256ae	4308	#define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /!<Bit 5 /
bogdanm	20:4263a77256ae	4309	#define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /!<Bit 6 /
bogdanm	20:4263a77256ae	4310	#define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /!<Bit 7 /
bogdanm	20:4263a77256ae	4311
bogdanm	20:4263a77256ae	4312	#define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /!<IOHOLD4[7:0] bits (I/O 4 hold time) /
bogdanm	20:4263a77256ae	4313	#define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /!<Bit 0 /
bogdanm	20:4263a77256ae	4314	#define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /!<Bit 1 /
bogdanm	20:4263a77256ae	4315	#define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /!<Bit 2 /
bogdanm	20:4263a77256ae	4316	#define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /!<Bit 3 /
bogdanm	20:4263a77256ae	4317	#define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /!<Bit 4 /
bogdanm	20:4263a77256ae	4318	#define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /!<Bit 5 /
bogdanm	20:4263a77256ae	4319	#define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /!<Bit 6 /
bogdanm	20:4263a77256ae	4320	#define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /!<Bit 7 /
bogdanm	20:4263a77256ae	4321
bogdanm	20:4263a77256ae	4322	#define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) /
bogdanm	20:4263a77256ae	4323	#define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /!<Bit 0 /
bogdanm	20:4263a77256ae	4324	#define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /!<Bit 1 /
bogdanm	20:4263a77256ae	4325	#define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /!<Bit 2 /
bogdanm	20:4263a77256ae	4326	#define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /!<Bit 3 /
bogdanm	20:4263a77256ae	4327	#define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /!<Bit 4 /
bogdanm	20:4263a77256ae	4328	#define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /!<Bit 5 /
bogdanm	20:4263a77256ae	4329	#define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /!<Bit 6 /
bogdanm	20:4263a77256ae	4330	#define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /!<Bit 7 /
bogdanm	20:4263a77256ae	4331
bogdanm	20:4263a77256ae	4332	/**************** Bit definition for FSMC_ECCR2 register ****************/
bogdanm	20:4263a77256ae	4333	#define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /!<ECC result /
bogdanm	20:4263a77256ae	4334
bogdanm	20:4263a77256ae	4335	/**************** Bit definition for FSMC_ECCR3 register ****************/
bogdanm	20:4263a77256ae	4336	#define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /!<ECC result /
bogdanm	20:4263a77256ae	4337
bogdanm	20:4263a77256ae	4338
bogdanm	20:4263a77256ae	4339	/******************************************************************************/
bogdanm	20:4263a77256ae	4340	/* */
bogdanm	20:4263a77256ae	4341	/* General Purpose I/O */
bogdanm	20:4263a77256ae	4342	/* */
bogdanm	20:4263a77256ae	4343	/******************************************************************************/
bogdanm	20:4263a77256ae	4344	/**************** Bits definition for GPIO_MODER register ***************/
bogdanm	20:4263a77256ae	4345	#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
bogdanm	20:4263a77256ae	4346	#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	4347	#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
bogdanm	20:4263a77256ae	4348
bogdanm	20:4263a77256ae	4349	#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
bogdanm	20:4263a77256ae	4350	#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
bogdanm	20:4263a77256ae	4351	#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
bogdanm	20:4263a77256ae	4352
bogdanm	20:4263a77256ae	4353	#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
bogdanm	20:4263a77256ae	4354	#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
bogdanm	20:4263a77256ae	4355	#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
bogdanm	20:4263a77256ae	4356
bogdanm	20:4263a77256ae	4357	#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
bogdanm	20:4263a77256ae	4358	#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
bogdanm	20:4263a77256ae	4359	#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
bogdanm	20:4263a77256ae	4360
bogdanm	20:4263a77256ae	4361	#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
bogdanm	20:4263a77256ae	4362	#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
bogdanm	20:4263a77256ae	4363	#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
bogdanm	20:4263a77256ae	4364
bogdanm	20:4263a77256ae	4365	#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
bogdanm	20:4263a77256ae	4366	#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
bogdanm	20:4263a77256ae	4367	#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
bogdanm	20:4263a77256ae	4368
bogdanm	20:4263a77256ae	4369	#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
bogdanm	20:4263a77256ae	4370	#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
bogdanm	20:4263a77256ae	4371	#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
bogdanm	20:4263a77256ae	4372
bogdanm	20:4263a77256ae	4373	#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
bogdanm	20:4263a77256ae	4374	#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
bogdanm	20:4263a77256ae	4375	#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
bogdanm	20:4263a77256ae	4376
bogdanm	20:4263a77256ae	4377	#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
bogdanm	20:4263a77256ae	4378	#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
bogdanm	20:4263a77256ae	4379	#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
bogdanm	20:4263a77256ae	4380
bogdanm	20:4263a77256ae	4381	#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
bogdanm	20:4263a77256ae	4382	#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
bogdanm	20:4263a77256ae	4383	#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
bogdanm	20:4263a77256ae	4384
bogdanm	20:4263a77256ae	4385	#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
bogdanm	20:4263a77256ae	4386	#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
bogdanm	20:4263a77256ae	4387	#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
bogdanm	20:4263a77256ae	4388
bogdanm	20:4263a77256ae	4389	#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
bogdanm	20:4263a77256ae	4390	#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
bogdanm	20:4263a77256ae	4391	#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
bogdanm	20:4263a77256ae	4392
bogdanm	20:4263a77256ae	4393	#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
bogdanm	20:4263a77256ae	4394	#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
bogdanm	20:4263a77256ae	4395	#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
bogdanm	20:4263a77256ae	4396
bogdanm	20:4263a77256ae	4397	#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
bogdanm	20:4263a77256ae	4398	#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
bogdanm	20:4263a77256ae	4399	#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
bogdanm	20:4263a77256ae	4400
bogdanm	20:4263a77256ae	4401	#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
bogdanm	20:4263a77256ae	4402	#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
bogdanm	20:4263a77256ae	4403	#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
bogdanm	20:4263a77256ae	4404
bogdanm	20:4263a77256ae	4405	#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
bogdanm	20:4263a77256ae	4406	#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
bogdanm	20:4263a77256ae	4407	#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
bogdanm	20:4263a77256ae	4408
bogdanm	20:4263a77256ae	4409	/**************** Bits definition for GPIO_OTYPER register **************/
bogdanm	20:4263a77256ae	4410	#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	4411	#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
bogdanm	20:4263a77256ae	4412	#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
bogdanm	20:4263a77256ae	4413	#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
bogdanm	20:4263a77256ae	4414	#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
bogdanm	20:4263a77256ae	4415	#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
bogdanm	20:4263a77256ae	4416	#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
bogdanm	20:4263a77256ae	4417	#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
bogdanm	20:4263a77256ae	4418	#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
bogdanm	20:4263a77256ae	4419	#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
bogdanm	20:4263a77256ae	4420	#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
bogdanm	20:4263a77256ae	4421	#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
bogdanm	20:4263a77256ae	4422	#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
bogdanm	20:4263a77256ae	4423	#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
bogdanm	20:4263a77256ae	4424	#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
bogdanm	20:4263a77256ae	4425	#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
bogdanm	20:4263a77256ae	4426
bogdanm	20:4263a77256ae	4427	/**************** Bits definition for GPIO_OSPEEDR register *************/
bogdanm	20:4263a77256ae	4428	#define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
bogdanm	20:4263a77256ae	4429	#define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	4430	#define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
bogdanm	20:4263a77256ae	4431
bogdanm	20:4263a77256ae	4432	#define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
bogdanm	20:4263a77256ae	4433	#define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
bogdanm	20:4263a77256ae	4434	#define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
bogdanm	20:4263a77256ae	4435
bogdanm	20:4263a77256ae	4436	#define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
bogdanm	20:4263a77256ae	4437	#define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
bogdanm	20:4263a77256ae	4438	#define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
bogdanm	20:4263a77256ae	4439
bogdanm	20:4263a77256ae	4440	#define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
bogdanm	20:4263a77256ae	4441	#define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
bogdanm	20:4263a77256ae	4442	#define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
bogdanm	20:4263a77256ae	4443
bogdanm	20:4263a77256ae	4444	#define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
bogdanm	20:4263a77256ae	4445	#define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
bogdanm	20:4263a77256ae	4446	#define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
bogdanm	20:4263a77256ae	4447
bogdanm	20:4263a77256ae	4448	#define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
bogdanm	20:4263a77256ae	4449	#define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
bogdanm	20:4263a77256ae	4450	#define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
bogdanm	20:4263a77256ae	4451
bogdanm	20:4263a77256ae	4452	#define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
bogdanm	20:4263a77256ae	4453	#define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
bogdanm	20:4263a77256ae	4454	#define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
bogdanm	20:4263a77256ae	4455
bogdanm	20:4263a77256ae	4456	#define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
bogdanm	20:4263a77256ae	4457	#define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
bogdanm	20:4263a77256ae	4458	#define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
bogdanm	20:4263a77256ae	4459
bogdanm	20:4263a77256ae	4460	#define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
bogdanm	20:4263a77256ae	4461	#define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
bogdanm	20:4263a77256ae	4462	#define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
bogdanm	20:4263a77256ae	4463
bogdanm	20:4263a77256ae	4464	#define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
bogdanm	20:4263a77256ae	4465	#define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
bogdanm	20:4263a77256ae	4466	#define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
bogdanm	20:4263a77256ae	4467
bogdanm	20:4263a77256ae	4468	#define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
bogdanm	20:4263a77256ae	4469	#define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
bogdanm	20:4263a77256ae	4470	#define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
bogdanm	20:4263a77256ae	4471
bogdanm	20:4263a77256ae	4472	#define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
bogdanm	20:4263a77256ae	4473	#define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
bogdanm	20:4263a77256ae	4474	#define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
bogdanm	20:4263a77256ae	4475
bogdanm	20:4263a77256ae	4476	#define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
bogdanm	20:4263a77256ae	4477	#define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
bogdanm	20:4263a77256ae	4478	#define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
bogdanm	20:4263a77256ae	4479
bogdanm	20:4263a77256ae	4480	#define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
bogdanm	20:4263a77256ae	4481	#define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
bogdanm	20:4263a77256ae	4482	#define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
bogdanm	20:4263a77256ae	4483
bogdanm	20:4263a77256ae	4484	#define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
bogdanm	20:4263a77256ae	4485	#define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
bogdanm	20:4263a77256ae	4486	#define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
bogdanm	20:4263a77256ae	4487
bogdanm	20:4263a77256ae	4488	#define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
bogdanm	20:4263a77256ae	4489	#define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
bogdanm	20:4263a77256ae	4490	#define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
bogdanm	20:4263a77256ae	4491
bogdanm	20:4263a77256ae	4492	/**************** Bits definition for GPIO_PUPDR register ***************/
bogdanm	20:4263a77256ae	4493	#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
bogdanm	20:4263a77256ae	4494	#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	4495	#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
bogdanm	20:4263a77256ae	4496
bogdanm	20:4263a77256ae	4497	#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
bogdanm	20:4263a77256ae	4498	#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
bogdanm	20:4263a77256ae	4499	#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
bogdanm	20:4263a77256ae	4500
bogdanm	20:4263a77256ae	4501	#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
bogdanm	20:4263a77256ae	4502	#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
bogdanm	20:4263a77256ae	4503	#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
bogdanm	20:4263a77256ae	4504
bogdanm	20:4263a77256ae	4505	#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
bogdanm	20:4263a77256ae	4506	#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
bogdanm	20:4263a77256ae	4507	#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
bogdanm	20:4263a77256ae	4508
bogdanm	20:4263a77256ae	4509	#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
bogdanm	20:4263a77256ae	4510	#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
bogdanm	20:4263a77256ae	4511	#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
bogdanm	20:4263a77256ae	4512
bogdanm	20:4263a77256ae	4513	#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
bogdanm	20:4263a77256ae	4514	#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
bogdanm	20:4263a77256ae	4515	#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
bogdanm	20:4263a77256ae	4516
bogdanm	20:4263a77256ae	4517	#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
bogdanm	20:4263a77256ae	4518	#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
bogdanm	20:4263a77256ae	4519	#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
bogdanm	20:4263a77256ae	4520
bogdanm	20:4263a77256ae	4521	#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
bogdanm	20:4263a77256ae	4522	#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
bogdanm	20:4263a77256ae	4523	#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
bogdanm	20:4263a77256ae	4524
bogdanm	20:4263a77256ae	4525	#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
bogdanm	20:4263a77256ae	4526	#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
bogdanm	20:4263a77256ae	4527	#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
bogdanm	20:4263a77256ae	4528
bogdanm	20:4263a77256ae	4529	#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
bogdanm	20:4263a77256ae	4530	#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
bogdanm	20:4263a77256ae	4531	#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
bogdanm	20:4263a77256ae	4532
bogdanm	20:4263a77256ae	4533	#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
bogdanm	20:4263a77256ae	4534	#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
bogdanm	20:4263a77256ae	4535	#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
bogdanm	20:4263a77256ae	4536
bogdanm	20:4263a77256ae	4537	#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
bogdanm	20:4263a77256ae	4538	#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
bogdanm	20:4263a77256ae	4539	#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
bogdanm	20:4263a77256ae	4540
bogdanm	20:4263a77256ae	4541	#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
bogdanm	20:4263a77256ae	4542	#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
bogdanm	20:4263a77256ae	4543	#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
bogdanm	20:4263a77256ae	4544
bogdanm	20:4263a77256ae	4545	#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
bogdanm	20:4263a77256ae	4546	#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
bogdanm	20:4263a77256ae	4547	#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
bogdanm	20:4263a77256ae	4548
bogdanm	20:4263a77256ae	4549	#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
bogdanm	20:4263a77256ae	4550	#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
bogdanm	20:4263a77256ae	4551	#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
bogdanm	20:4263a77256ae	4552
bogdanm	20:4263a77256ae	4553	#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
bogdanm	20:4263a77256ae	4554	#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
bogdanm	20:4263a77256ae	4555	#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
bogdanm	20:4263a77256ae	4556
bogdanm	20:4263a77256ae	4557	/**************** Bits definition for GPIO_IDR register *****************/
bogdanm	20:4263a77256ae	4558	#define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	4559	#define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
bogdanm	20:4263a77256ae	4560	#define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
bogdanm	20:4263a77256ae	4561	#define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
bogdanm	20:4263a77256ae	4562	#define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
bogdanm	20:4263a77256ae	4563	#define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
bogdanm	20:4263a77256ae	4564	#define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
bogdanm	20:4263a77256ae	4565	#define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
bogdanm	20:4263a77256ae	4566	#define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
bogdanm	20:4263a77256ae	4567	#define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
bogdanm	20:4263a77256ae	4568	#define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
bogdanm	20:4263a77256ae	4569	#define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
bogdanm	20:4263a77256ae	4570	#define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
bogdanm	20:4263a77256ae	4571	#define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
bogdanm	20:4263a77256ae	4572	#define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
bogdanm	20:4263a77256ae	4573	#define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
bogdanm	20:4263a77256ae	4574	/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
bogdanm	20:4263a77256ae	4575	#define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
bogdanm	20:4263a77256ae	4576	#define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
bogdanm	20:4263a77256ae	4577	#define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
bogdanm	20:4263a77256ae	4578	#define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
bogdanm	20:4263a77256ae	4579	#define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
bogdanm	20:4263a77256ae	4580	#define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
bogdanm	20:4263a77256ae	4581	#define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
bogdanm	20:4263a77256ae	4582	#define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
bogdanm	20:4263a77256ae	4583	#define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
bogdanm	20:4263a77256ae	4584	#define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
bogdanm	20:4263a77256ae	4585	#define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
bogdanm	20:4263a77256ae	4586	#define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
bogdanm	20:4263a77256ae	4587	#define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
bogdanm	20:4263a77256ae	4588	#define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
bogdanm	20:4263a77256ae	4589	#define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
bogdanm	20:4263a77256ae	4590	#define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
bogdanm	20:4263a77256ae	4591
bogdanm	20:4263a77256ae	4592	/**************** Bits definition for GPIO_ODR register *****************/
bogdanm	20:4263a77256ae	4593	#define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	4594	#define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
bogdanm	20:4263a77256ae	4595	#define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
bogdanm	20:4263a77256ae	4596	#define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
bogdanm	20:4263a77256ae	4597	#define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
bogdanm	20:4263a77256ae	4598	#define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
bogdanm	20:4263a77256ae	4599	#define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
bogdanm	20:4263a77256ae	4600	#define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
bogdanm	20:4263a77256ae	4601	#define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
bogdanm	20:4263a77256ae	4602	#define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
bogdanm	20:4263a77256ae	4603	#define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
bogdanm	20:4263a77256ae	4604	#define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
bogdanm	20:4263a77256ae	4605	#define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
bogdanm	20:4263a77256ae	4606	#define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
bogdanm	20:4263a77256ae	4607	#define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
bogdanm	20:4263a77256ae	4608	#define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
bogdanm	20:4263a77256ae	4609	/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
bogdanm	20:4263a77256ae	4610	#define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
bogdanm	20:4263a77256ae	4611	#define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
bogdanm	20:4263a77256ae	4612	#define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
bogdanm	20:4263a77256ae	4613	#define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
bogdanm	20:4263a77256ae	4614	#define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
bogdanm	20:4263a77256ae	4615	#define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
bogdanm	20:4263a77256ae	4616	#define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
bogdanm	20:4263a77256ae	4617	#define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
bogdanm	20:4263a77256ae	4618	#define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
bogdanm	20:4263a77256ae	4619	#define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
bogdanm	20:4263a77256ae	4620	#define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
bogdanm	20:4263a77256ae	4621	#define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
bogdanm	20:4263a77256ae	4622	#define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
bogdanm	20:4263a77256ae	4623	#define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
bogdanm	20:4263a77256ae	4624	#define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
bogdanm	20:4263a77256ae	4625	#define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
bogdanm	20:4263a77256ae	4626
bogdanm	20:4263a77256ae	4627	/**************** Bits definition for GPIO_BSRR register ****************/
bogdanm	20:4263a77256ae	4628	#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	4629	#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
bogdanm	20:4263a77256ae	4630	#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
bogdanm	20:4263a77256ae	4631	#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
bogdanm	20:4263a77256ae	4632	#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
bogdanm	20:4263a77256ae	4633	#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
bogdanm	20:4263a77256ae	4634	#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
bogdanm	20:4263a77256ae	4635	#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
bogdanm	20:4263a77256ae	4636	#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
bogdanm	20:4263a77256ae	4637	#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
bogdanm	20:4263a77256ae	4638	#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
bogdanm	20:4263a77256ae	4639	#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
bogdanm	20:4263a77256ae	4640	#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
bogdanm	20:4263a77256ae	4641	#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
bogdanm	20:4263a77256ae	4642	#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
bogdanm	20:4263a77256ae	4643	#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
bogdanm	20:4263a77256ae	4644	#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
bogdanm	20:4263a77256ae	4645	#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
bogdanm	20:4263a77256ae	4646	#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
bogdanm	20:4263a77256ae	4647	#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
bogdanm	20:4263a77256ae	4648	#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
bogdanm	20:4263a77256ae	4649	#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
bogdanm	20:4263a77256ae	4650	#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
bogdanm	20:4263a77256ae	4651	#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
bogdanm	20:4263a77256ae	4652	#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
bogdanm	20:4263a77256ae	4653	#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
bogdanm	20:4263a77256ae	4654	#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
bogdanm	20:4263a77256ae	4655	#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
bogdanm	20:4263a77256ae	4656	#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
bogdanm	20:4263a77256ae	4657	#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
bogdanm	20:4263a77256ae	4658	#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
bogdanm	20:4263a77256ae	4659	#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
bogdanm	20:4263a77256ae	4660
bogdanm	20:4263a77256ae	4661	/******************************************************************************/
bogdanm	20:4263a77256ae	4662	/* */
bogdanm	20:4263a77256ae	4663	/* HASH */
bogdanm	20:4263a77256ae	4664	/* */
bogdanm	20:4263a77256ae	4665	/******************************************************************************/
bogdanm	20:4263a77256ae	4666	/**************** Bits definition for HASH_CR register ******************/
bogdanm	20:4263a77256ae	4667	#define HASH_CR_INIT ((uint32_t)0x00000004)
bogdanm	20:4263a77256ae	4668	#define HASH_CR_DMAE ((uint32_t)0x00000008)
bogdanm	20:4263a77256ae	4669	#define HASH_CR_DATATYPE ((uint32_t)0x00000030)
bogdanm	20:4263a77256ae	4670	#define HASH_CR_DATATYPE_0 ((uint32_t)0x00000010)
bogdanm	20:4263a77256ae	4671	#define HASH_CR_DATATYPE_1 ((uint32_t)0x00000020)
bogdanm	20:4263a77256ae	4672	#define HASH_CR_MODE ((uint32_t)0x00000040)
bogdanm	20:4263a77256ae	4673	#define HASH_CR_ALGO ((uint32_t)0x00040080)
bogdanm	20:4263a77256ae	4674	#define HASH_CR_ALGO_0 ((uint32_t)0x00000080)
bogdanm	20:4263a77256ae	4675	#define HASH_CR_ALGO_1 ((uint32_t)0x00040000)
bogdanm	20:4263a77256ae	4676	#define HASH_CR_NBW ((uint32_t)0x00000F00)
bogdanm	20:4263a77256ae	4677	#define HASH_CR_NBW_0 ((uint32_t)0x00000100)
bogdanm	20:4263a77256ae	4678	#define HASH_CR_NBW_1 ((uint32_t)0x00000200)
bogdanm	20:4263a77256ae	4679	#define HASH_CR_NBW_2 ((uint32_t)0x00000400)
bogdanm	20:4263a77256ae	4680	#define HASH_CR_NBW_3 ((uint32_t)0x00000800)
bogdanm	20:4263a77256ae	4681	#define HASH_CR_DINNE ((uint32_t)0x00001000)
bogdanm	20:4263a77256ae	4682	#define HASH_CR_MDMAT ((uint32_t)0x00002000)
bogdanm	20:4263a77256ae	4683	#define HASH_CR_LKEY ((uint32_t)0x00010000)
bogdanm	20:4263a77256ae	4684
bogdanm	20:4263a77256ae	4685	/**************** Bits definition for HASH_STR register *****************/
bogdanm	20:4263a77256ae	4686	#define HASH_STR_NBW ((uint32_t)0x0000001F)
bogdanm	20:4263a77256ae	4687	#define HASH_STR_NBW_0 ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	4688	#define HASH_STR_NBW_1 ((uint32_t)0x00000002)
bogdanm	20:4263a77256ae	4689	#define HASH_STR_NBW_2 ((uint32_t)0x00000004)
bogdanm	20:4263a77256ae	4690	#define HASH_STR_NBW_3 ((uint32_t)0x00000008)
bogdanm	20:4263a77256ae	4691	#define HASH_STR_NBW_4 ((uint32_t)0x00000010)
bogdanm	20:4263a77256ae	4692	#define HASH_STR_DCAL ((uint32_t)0x00000100)
bogdanm	20:4263a77256ae	4693
bogdanm	20:4263a77256ae	4694	/**************** Bits definition for HASH_IMR register *****************/
bogdanm	20:4263a77256ae	4695	#define HASH_IMR_DINIM ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	4696	#define HASH_IMR_DCIM ((uint32_t)0x00000002)
bogdanm	20:4263a77256ae	4697
bogdanm	20:4263a77256ae	4698	/**************** Bits definition for HASH_SR register ******************/
bogdanm	20:4263a77256ae	4699	#define HASH_SR_DINIS ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	4700	#define HASH_SR_DCIS ((uint32_t)0x00000002)
bogdanm	20:4263a77256ae	4701	#define HASH_SR_DMAS ((uint32_t)0x00000004)
bogdanm	20:4263a77256ae	4702	#define HASH_SR_BUSY ((uint32_t)0x00000008)
bogdanm	20:4263a77256ae	4703
bogdanm	20:4263a77256ae	4704	/******************************************************************************/
bogdanm	20:4263a77256ae	4705	/* */
bogdanm	20:4263a77256ae	4706	/* Inter-integrated Circuit Interface */
bogdanm	20:4263a77256ae	4707	/* */
bogdanm	20:4263a77256ae	4708	/******************************************************************************/
bogdanm	20:4263a77256ae	4709	/***************** Bit definition for I2C_CR1 register ******************/
bogdanm	20:4263a77256ae	4710	#define I2C_CR1_PE ((uint16_t)0x0001) /!<Peripheral Enable /
bogdanm	20:4263a77256ae	4711	#define I2C_CR1_SMBUS ((uint16_t)0x0002) /!<SMBus Mode /
bogdanm	20:4263a77256ae	4712	#define I2C_CR1_SMBTYPE ((uint16_t)0x0008) /!<SMBus Type /
bogdanm	20:4263a77256ae	4713	#define I2C_CR1_ENARP ((uint16_t)0x0010) /!<ARP Enable /
bogdanm	20:4263a77256ae	4714	#define I2C_CR1_ENPEC ((uint16_t)0x0020) /!<PEC Enable /
bogdanm	20:4263a77256ae	4715	#define I2C_CR1_ENGC ((uint16_t)0x0040) /!<General Call Enable /
bogdanm	20:4263a77256ae	4716	#define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) /!<Clock Stretching Disable (Slave mode) /
bogdanm	20:4263a77256ae	4717	#define I2C_CR1_START ((uint16_t)0x0100) /!<Start Generation /
bogdanm	20:4263a77256ae	4718	#define I2C_CR1_STOP ((uint16_t)0x0200) /!<Stop Generation /
bogdanm	20:4263a77256ae	4719	#define I2C_CR1_ACK ((uint16_t)0x0400) /!<Acknowledge Enable /
bogdanm	20:4263a77256ae	4720	#define I2C_CR1_POS ((uint16_t)0x0800) /!<Acknowledge/PEC Position (for data reception) /
bogdanm	20:4263a77256ae	4721	#define I2C_CR1_PEC ((uint16_t)0x1000) /!<Packet Error Checking /
bogdanm	20:4263a77256ae	4722	#define I2C_CR1_ALERT ((uint16_t)0x2000) /!<SMBus Alert /
bogdanm	20:4263a77256ae	4723	#define I2C_CR1_SWRST ((uint16_t)0x8000) /!<Software Reset /
bogdanm	20:4263a77256ae	4724
bogdanm	20:4263a77256ae	4725	/***************** Bit definition for I2C_CR2 register ******************/
bogdanm	20:4263a77256ae	4726	#define I2C_CR2_FREQ ((uint16_t)0x003F) /!<FREQ[5:0] bits (Peripheral Clock Frequency) /
bogdanm	20:4263a77256ae	4727	#define I2C_CR2_FREQ_0 ((uint16_t)0x0001) /!<Bit 0 /
bogdanm	20:4263a77256ae	4728	#define I2C_CR2_FREQ_1 ((uint16_t)0x0002) /!<Bit 1 /
bogdanm	20:4263a77256ae	4729	#define I2C_CR2_FREQ_2 ((uint16_t)0x0004) /!<Bit 2 /
bogdanm	20:4263a77256ae	4730	#define I2C_CR2_FREQ_3 ((uint16_t)0x0008) /!<Bit 3 /
bogdanm	20:4263a77256ae	4731	#define I2C_CR2_FREQ_4 ((uint16_t)0x0010) /!<Bit 4 /
bogdanm	20:4263a77256ae	4732	#define I2C_CR2_FREQ_5 ((uint16_t)0x0020) /!<Bit 5 /
bogdanm	20:4263a77256ae	4733
bogdanm	20:4263a77256ae	4734	#define I2C_CR2_ITERREN ((uint16_t)0x0100) /!<Error Interrupt Enable /
bogdanm	20:4263a77256ae	4735	#define I2C_CR2_ITEVTEN ((uint16_t)0x0200) /!<Event Interrupt Enable /
bogdanm	20:4263a77256ae	4736	#define I2C_CR2_ITBUFEN ((uint16_t)0x0400) /!<Buffer Interrupt Enable /
bogdanm	20:4263a77256ae	4737	#define I2C_CR2_DMAEN ((uint16_t)0x0800) /!<DMA Requests Enable /
bogdanm	20:4263a77256ae	4738	#define I2C_CR2_LAST ((uint16_t)0x1000) /!<DMA Last Transfer /
bogdanm	20:4263a77256ae	4739
bogdanm	20:4263a77256ae	4740	/***************** Bit definition for I2C_OAR1 register *****************/
bogdanm	20:4263a77256ae	4741	#define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) /!<Interface Address /
bogdanm	20:4263a77256ae	4742	#define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) /!<Interface Address /
bogdanm	20:4263a77256ae	4743
bogdanm	20:4263a77256ae	4744	#define I2C_OAR1_ADD0 ((uint16_t)0x0001) /!<Bit 0 /
bogdanm	20:4263a77256ae	4745	#define I2C_OAR1_ADD1 ((uint16_t)0x0002) /!<Bit 1 /
bogdanm	20:4263a77256ae	4746	#define I2C_OAR1_ADD2 ((uint16_t)0x0004) /!<Bit 2 /
bogdanm	20:4263a77256ae	4747	#define I2C_OAR1_ADD3 ((uint16_t)0x0008) /!<Bit 3 /
bogdanm	20:4263a77256ae	4748	#define I2C_OAR1_ADD4 ((uint16_t)0x0010) /!<Bit 4 /
bogdanm	20:4263a77256ae	4749	#define I2C_OAR1_ADD5 ((uint16_t)0x0020) /!<Bit 5 /
bogdanm	20:4263a77256ae	4750	#define I2C_OAR1_ADD6 ((uint16_t)0x0040) /!<Bit 6 /
bogdanm	20:4263a77256ae	4751	#define I2C_OAR1_ADD7 ((uint16_t)0x0080) /!<Bit 7 /
bogdanm	20:4263a77256ae	4752	#define I2C_OAR1_ADD8 ((uint16_t)0x0100) /!<Bit 8 /
bogdanm	20:4263a77256ae	4753	#define I2C_OAR1_ADD9 ((uint16_t)0x0200) /!<Bit 9 /
bogdanm	20:4263a77256ae	4754
bogdanm	20:4263a77256ae	4755	#define I2C_OAR1_ADDMODE ((uint16_t)0x8000) /!<Addressing Mode (Slave mode) /
bogdanm	20:4263a77256ae	4756
bogdanm	20:4263a77256ae	4757	/***************** Bit definition for I2C_OAR2 register *****************/
bogdanm	20:4263a77256ae	4758	#define I2C_OAR2_ENDUAL ((uint8_t)0x01) /!<Dual addressing mode enable /
bogdanm	20:4263a77256ae	4759	#define I2C_OAR2_ADD2 ((uint8_t)0xFE) /!<Interface address /
bogdanm	20:4263a77256ae	4760
bogdanm	20:4263a77256ae	4761	/****************** Bit definition for I2C_DR register ******************/
bogdanm	20:4263a77256ae	4762	#define I2C_DR_DR ((uint8_t)0xFF) /!<8-bit Data Register /
bogdanm	20:4263a77256ae	4763
bogdanm	20:4263a77256ae	4764	/***************** Bit definition for I2C_SR1 register ******************/
bogdanm	20:4263a77256ae	4765	#define I2C_SR1_SB ((uint16_t)0x0001) /!<Start Bit (Master mode) /
bogdanm	20:4263a77256ae	4766	#define I2C_SR1_ADDR ((uint16_t)0x0002) /!<Address sent (master mode)/matched (slave mode) /
bogdanm	20:4263a77256ae	4767	#define I2C_SR1_BTF ((uint16_t)0x0004) /!<Byte Transfer Finished /
bogdanm	20:4263a77256ae	4768	#define I2C_SR1_ADD10 ((uint16_t)0x0008) /!<10-bit header sent (Master mode) /
bogdanm	20:4263a77256ae	4769	#define I2C_SR1_STOPF ((uint16_t)0x0010) /!<Stop detection (Slave mode) /
bogdanm	20:4263a77256ae	4770	#define I2C_SR1_RXNE ((uint16_t)0x0040) /!<Data Register not Empty (receivers) /
bogdanm	20:4263a77256ae	4771	#define I2C_SR1_TXE ((uint16_t)0x0080) /!<Data Register Empty (transmitters) /
bogdanm	20:4263a77256ae	4772	#define I2C_SR1_BERR ((uint16_t)0x0100) /!<Bus Error /
bogdanm	20:4263a77256ae	4773	#define I2C_SR1_ARLO ((uint16_t)0x0200) /!<Arbitration Lost (master mode) /
bogdanm	20:4263a77256ae	4774	#define I2C_SR1_AF ((uint16_t)0x0400) /!<Acknowledge Failure /
bogdanm	20:4263a77256ae	4775	#define I2C_SR1_OVR ((uint16_t)0x0800) /!<Overrun/Underrun /
bogdanm	20:4263a77256ae	4776	#define I2C_SR1_PECERR ((uint16_t)0x1000) /!<PEC Error in reception /
bogdanm	20:4263a77256ae	4777	#define I2C_SR1_TIMEOUT ((uint16_t)0x4000) /!<Timeout or Tlow Error /
bogdanm	20:4263a77256ae	4778	#define I2C_SR1_SMBALERT ((uint16_t)0x8000) /!<SMBus Alert /
bogdanm	20:4263a77256ae	4779
bogdanm	20:4263a77256ae	4780	/***************** Bit definition for I2C_SR2 register ******************/
bogdanm	20:4263a77256ae	4781	#define I2C_SR2_MSL ((uint16_t)0x0001) /!<Master/Slave /
bogdanm	20:4263a77256ae	4782	#define I2C_SR2_BUSY ((uint16_t)0x0002) /!<Bus Busy /
bogdanm	20:4263a77256ae	4783	#define I2C_SR2_TRA ((uint16_t)0x0004) /!<Transmitter/Receiver /
bogdanm	20:4263a77256ae	4784	#define I2C_SR2_GENCALL ((uint16_t)0x0010) /!<General Call Address (Slave mode) /
bogdanm	20:4263a77256ae	4785	#define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) /!<SMBus Device Default Address (Slave mode) /
bogdanm	20:4263a77256ae	4786	#define I2C_SR2_SMBHOST ((uint16_t)0x0040) /!<SMBus Host Header (Slave mode) /
bogdanm	20:4263a77256ae	4787	#define I2C_SR2_DUALF ((uint16_t)0x0080) /!<Dual Flag (Slave mode) /
bogdanm	20:4263a77256ae	4788	#define I2C_SR2_PEC ((uint16_t)0xFF00) /!<Packet Error Checking Register /
bogdanm	20:4263a77256ae	4789
bogdanm	20:4263a77256ae	4790	/***************** Bit definition for I2C_CCR register ******************/
bogdanm	20:4263a77256ae	4791	#define I2C_CCR_CCR ((uint16_t)0x0FFF) /!<Clock Control Register in Fast/Standard mode (Master mode) /
bogdanm	20:4263a77256ae	4792	#define I2C_CCR_DUTY ((uint16_t)0x4000) /!<Fast Mode Duty Cycle /
bogdanm	20:4263a77256ae	4793	#define I2C_CCR_FS ((uint16_t)0x8000) /!<I2C Master Mode Selection /
bogdanm	20:4263a77256ae	4794
bogdanm	20:4263a77256ae	4795	/**************** Bit definition for I2C_TRISE register *****************/
bogdanm	20:4263a77256ae	4796	#define I2C_TRISE_TRISE ((uint8_t)0x3F) /!<Maximum Rise Time in Fast/Standard mode (Master mode) /
bogdanm	20:4263a77256ae	4797
bogdanm	20:4263a77256ae	4798	/**************** Bit definition for I2C_FLTR register *****************/
bogdanm	20:4263a77256ae	4799	#define I2C_FLTR_DNF ((uint8_t)0x0F) /!<Digital Noise Filter /
bogdanm	20:4263a77256ae	4800	#define I2C_FLTR_ANOFF ((uint8_t)0x10) /!<Analog Noise Filter OFF /
bogdanm	20:4263a77256ae	4801
bogdanm	20:4263a77256ae	4802	/******************************************************************************/
bogdanm	20:4263a77256ae	4803	/* */
bogdanm	20:4263a77256ae	4804	/* Independent WATCHDOG */
bogdanm	20:4263a77256ae	4805	/* */
bogdanm	20:4263a77256ae	4806	/******************************************************************************/
bogdanm	20:4263a77256ae	4807	/***************** Bit definition for IWDG_KR register ******************/
bogdanm	20:4263a77256ae	4808	#define IWDG_KR_KEY ((uint16_t)0xFFFF) /!<Key value (write only, read 0000h) /
bogdanm	20:4263a77256ae	4809
bogdanm	20:4263a77256ae	4810	/***************** Bit definition for IWDG_PR register ******************/
bogdanm	20:4263a77256ae	4811	#define IWDG_PR_PR ((uint8_t)0x07) /!<PR[2:0] (Prescaler divider) /
bogdanm	20:4263a77256ae	4812	#define IWDG_PR_PR_0 ((uint8_t)0x01) /!<Bit 0 /
bogdanm	20:4263a77256ae	4813	#define IWDG_PR_PR_1 ((uint8_t)0x02) /!<Bit 1 /
bogdanm	20:4263a77256ae	4814	#define IWDG_PR_PR_2 ((uint8_t)0x04) /!<Bit 2 /
bogdanm	20:4263a77256ae	4815
bogdanm	20:4263a77256ae	4816	/***************** Bit definition for IWDG_RLR register *****************/
bogdanm	20:4263a77256ae	4817	#define IWDG_RLR_RL ((uint16_t)0x0FFF) /!<Watchdog counter reload value /
bogdanm	20:4263a77256ae	4818
bogdanm	20:4263a77256ae	4819	/***************** Bit definition for IWDG_SR register ******************/
bogdanm	20:4263a77256ae	4820	#define IWDG_SR_PVU ((uint8_t)0x01) /!<Watchdog prescaler value update /
bogdanm	20:4263a77256ae	4821	#define IWDG_SR_RVU ((uint8_t)0x02) /!<Watchdog counter reload value update /
bogdanm	20:4263a77256ae	4822
bogdanm	20:4263a77256ae	4823
bogdanm	20:4263a77256ae	4824	/******************************************************************************/
bogdanm	20:4263a77256ae	4825	/* */
bogdanm	20:4263a77256ae	4826	/* Power Control */
bogdanm	20:4263a77256ae	4827	/* */
bogdanm	20:4263a77256ae	4828	/******************************************************************************/
bogdanm	20:4263a77256ae	4829	/****************** Bit definition for PWR_CR register ******************/
bogdanm	20:4263a77256ae	4830	#define PWR_CR_LPDS ((uint32_t)0x00000001) /!< Low-Power Deepsleep /
bogdanm	20:4263a77256ae	4831	#define PWR_CR_PDDS ((uint32_t)0x00000002) /!< Power Down Deepsleep /
bogdanm	20:4263a77256ae	4832	#define PWR_CR_CWUF ((uint32_t)0x00000004) /!< Clear Wakeup Flag /
bogdanm	20:4263a77256ae	4833	#define PWR_CR_CSBF ((uint32_t)0x00000008) /!< Clear Standby Flag /
bogdanm	20:4263a77256ae	4834	#define PWR_CR_PVDE ((uint32_t)0x00000010) /!< Power Voltage Detector Enable /
bogdanm	20:4263a77256ae	4835
bogdanm	20:4263a77256ae	4836	#define PWR_CR_PLS ((uint32_t)0x000000E0) /!< PLS[2:0] bits (PVD Level Selection) /
bogdanm	20:4263a77256ae	4837	#define PWR_CR_PLS_0 ((uint32_t)0x00000020) /!< Bit 0 /
bogdanm	20:4263a77256ae	4838	#define PWR_CR_PLS_1 ((uint32_t)0x00000040) /!< Bit 1 /
bogdanm	20:4263a77256ae	4839	#define PWR_CR_PLS_2 ((uint32_t)0x00000080) /!< Bit 2 /
bogdanm	20:4263a77256ae	4840
bogdanm	20:4263a77256ae	4841	/!< PVD level configuration /
bogdanm	20:4263a77256ae	4842	#define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /!< PVD level 0 /
bogdanm	20:4263a77256ae	4843	#define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /!< PVD level 1 /
bogdanm	20:4263a77256ae	4844	#define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /!< PVD level 2 /
bogdanm	20:4263a77256ae	4845	#define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /!< PVD level 3 /
bogdanm	20:4263a77256ae	4846	#define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /!< PVD level 4 /
bogdanm	20:4263a77256ae	4847	#define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /!< PVD level 5 /
bogdanm	20:4263a77256ae	4848	#define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /!< PVD level 6 /
bogdanm	20:4263a77256ae	4849	#define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /!< PVD level 7 /
bogdanm	20:4263a77256ae	4850
bogdanm	20:4263a77256ae	4851	#define PWR_CR_DBP ((uint32_t)0x00000100) /!< Disable Backup Domain write protection /
bogdanm	20:4263a77256ae	4852	#define PWR_CR_FPDS ((uint32_t)0x00000200) /!< Flash power down in Stop mode /
bogdanm	20:4263a77256ae	4853	#define PWR_CR_LPLVDS ((uint32_t)0x00000400) /!< Low-Power Regulator Low Voltage Scaling in Stop mode /
bogdanm	20:4263a77256ae	4854	#define PWR_CR_MRLVDS ((uint32_t)0x00000800) /!< Main regulator Low Voltage Scaling in Stop mode /
bogdanm	20:4263a77256ae	4855
bogdanm	20:4263a77256ae	4856	#define PWR_CR_VOS ((uint32_t)0x0000C000) /!< VOS[1:0] bits (Regulator voltage scaling output selection) /
bogdanm	20:4263a77256ae	4857	#define PWR_CR_VOS_0 ((uint32_t)0x00004000) /!< Bit 0 /
bogdanm	20:4263a77256ae	4858	#define PWR_CR_VOS_1 ((uint32_t)0x00008000) /!< Bit 1 /
bogdanm	20:4263a77256ae	4859
bogdanm	20:4263a77256ae	4860	/* Legacy define */
bogdanm	20:4263a77256ae	4861	#define PWR_CR_PMODE PWR_CR_VOS
bogdanm	20:4263a77256ae	4862
bogdanm	20:4263a77256ae	4863	/***************** Bit definition for PWR_CSR register ******************/
bogdanm	20:4263a77256ae	4864	#define PWR_CSR_WUF ((uint32_t)0x00000001) /!< Wakeup Flag /
bogdanm	20:4263a77256ae	4865	#define PWR_CSR_SBF ((uint32_t)0x00000002) /!< Standby Flag /
bogdanm	20:4263a77256ae	4866	#define PWR_CSR_PVDO ((uint32_t)0x00000004) /!< PVD Output /
bogdanm	20:4263a77256ae	4867	#define PWR_CSR_BRR ((uint32_t)0x00000008) /!< Backup regulator ready /
bogdanm	20:4263a77256ae	4868	#define PWR_CSR_EWUP ((uint32_t)0x00000100) /!< Enable WKUP pin /
bogdanm	20:4263a77256ae	4869	#define PWR_CSR_BRE ((uint32_t)0x00000200) /!< Backup regulator enable /
bogdanm	20:4263a77256ae	4870	#define PWR_CSR_VOSRDY ((uint32_t)0x00004000) /!< Regulator voltage scaling output selection ready /
bogdanm	20:4263a77256ae	4871
bogdanm	20:4263a77256ae	4872	/* Legacy define */
bogdanm	20:4263a77256ae	4873	#define PWR_CSR_REGRDY PWR_CSR_VOSRDY
bogdanm	20:4263a77256ae	4874
bogdanm	20:4263a77256ae	4875	/******************************************************************************/
bogdanm	20:4263a77256ae	4876	/* */
bogdanm	20:4263a77256ae	4877	/* Reset and Clock Control */
bogdanm	20:4263a77256ae	4878	/* */
bogdanm	20:4263a77256ae	4879	/******************************************************************************/
bogdanm	20:4263a77256ae	4880	/****************** Bit definition for RCC_CR register ******************/
bogdanm	20:4263a77256ae	4881	#define RCC_CR_HSION ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	4882	#define RCC_CR_HSIRDY ((uint32_t)0x00000002)
bogdanm	20:4263a77256ae	4883
bogdanm	20:4263a77256ae	4884	#define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
bogdanm	20:4263a77256ae	4885	#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/!<Bit 0 /
bogdanm	20:4263a77256ae	4886	#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/!<Bit 1 /
bogdanm	20:4263a77256ae	4887	#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/!<Bit 2 /
bogdanm	20:4263a77256ae	4888	#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/!<Bit 3 /
bogdanm	20:4263a77256ae	4889	#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/!<Bit 4 /
bogdanm	20:4263a77256ae	4890
bogdanm	20:4263a77256ae	4891	#define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
bogdanm	20:4263a77256ae	4892	#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/!<Bit 0 /
bogdanm	20:4263a77256ae	4893	#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/!<Bit 1 /
bogdanm	20:4263a77256ae	4894	#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/!<Bit 2 /
bogdanm	20:4263a77256ae	4895	#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/!<Bit 3 /
bogdanm	20:4263a77256ae	4896	#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/!<Bit 4 /
bogdanm	20:4263a77256ae	4897	#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/!<Bit 5 /
bogdanm	20:4263a77256ae	4898	#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/!<Bit 6 /
bogdanm	20:4263a77256ae	4899	#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/!<Bit 7 /
bogdanm	20:4263a77256ae	4900
bogdanm	20:4263a77256ae	4901	#define RCC_CR_HSEON ((uint32_t)0x00010000)
bogdanm	20:4263a77256ae	4902	#define RCC_CR_HSERDY ((uint32_t)0x00020000)
bogdanm	20:4263a77256ae	4903	#define RCC_CR_HSEBYP ((uint32_t)0x00040000)
bogdanm	20:4263a77256ae	4904	#define RCC_CR_CSSON ((uint32_t)0x00080000)
bogdanm	20:4263a77256ae	4905	#define RCC_CR_PLLON ((uint32_t)0x01000000)
bogdanm	20:4263a77256ae	4906	#define RCC_CR_PLLRDY ((uint32_t)0x02000000)
bogdanm	20:4263a77256ae	4907	#define RCC_CR_PLLI2SON ((uint32_t)0x04000000)
bogdanm	20:4263a77256ae	4908	#define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)
bogdanm	20:4263a77256ae	4909
bogdanm	20:4263a77256ae	4910
bogdanm	20:4263a77256ae	4911	/****************** Bit definition for RCC_PLLCFGR register *************/
bogdanm	20:4263a77256ae	4912	#define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
bogdanm	20:4263a77256ae	4913	#define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	4914	#define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)
bogdanm	20:4263a77256ae	4915	#define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
bogdanm	20:4263a77256ae	4916	#define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
bogdanm	20:4263a77256ae	4917	#define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
bogdanm	20:4263a77256ae	4918	#define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)
bogdanm	20:4263a77256ae	4919
bogdanm	20:4263a77256ae	4920	#define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)
bogdanm	20:4263a77256ae	4921	#define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
bogdanm	20:4263a77256ae	4922	#define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
bogdanm	20:4263a77256ae	4923	#define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)
bogdanm	20:4263a77256ae	4924	#define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)
bogdanm	20:4263a77256ae	4925	#define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
bogdanm	20:4263a77256ae	4926	#define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)
bogdanm	20:4263a77256ae	4927	#define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)
bogdanm	20:4263a77256ae	4928	#define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
bogdanm	20:4263a77256ae	4929	#define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)
bogdanm	20:4263a77256ae	4930
bogdanm	20:4263a77256ae	4931	#define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)
bogdanm	20:4263a77256ae	4932	#define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)
bogdanm	20:4263a77256ae	4933	#define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)
bogdanm	20:4263a77256ae	4934
bogdanm	20:4263a77256ae	4935	#define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)
bogdanm	20:4263a77256ae	4936	#define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)
bogdanm	20:4263a77256ae	4937	#define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)
bogdanm	20:4263a77256ae	4938
bogdanm	20:4263a77256ae	4939	#define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)
bogdanm	20:4263a77256ae	4940	#define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)
bogdanm	20:4263a77256ae	4941	#define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
bogdanm	20:4263a77256ae	4942	#define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
bogdanm	20:4263a77256ae	4943	#define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)
bogdanm	20:4263a77256ae	4944
bogdanm	20:4263a77256ae	4945	/****************** Bit definition for RCC_CFGR register ****************/
bogdanm	20:4263a77256ae	4946	/!< SW configuration /
bogdanm	20:4263a77256ae	4947	#define RCC_CFGR_SW ((uint32_t)0x00000003) /!< SW[1:0] bits (System clock Switch) /
bogdanm	20:4263a77256ae	4948	#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /!< Bit 0 /
bogdanm	20:4263a77256ae	4949	#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /!< Bit 1 /
bogdanm	20:4263a77256ae	4950
bogdanm	20:4263a77256ae	4951	#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /!< HSI selected as system clock /
bogdanm	20:4263a77256ae	4952	#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /!< HSE selected as system clock /
bogdanm	20:4263a77256ae	4953	#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /!< PLL selected as system clock /
bogdanm	20:4263a77256ae	4954
bogdanm	20:4263a77256ae	4955	/!< SWS configuration /
bogdanm	20:4263a77256ae	4956	#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /!< SWS[1:0] bits (System Clock Switch Status) /
bogdanm	20:4263a77256ae	4957	#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /!< Bit 0 /
bogdanm	20:4263a77256ae	4958	#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /!< Bit 1 /
bogdanm	20:4263a77256ae	4959
bogdanm	20:4263a77256ae	4960	#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /!< HSI oscillator used as system clock /
bogdanm	20:4263a77256ae	4961	#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /!< HSE oscillator used as system clock /
bogdanm	20:4263a77256ae	4962	#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /!< PLL used as system clock /
bogdanm	20:4263a77256ae	4963
bogdanm	20:4263a77256ae	4964	/!< HPRE configuration /
bogdanm	20:4263a77256ae	4965	#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /!< HPRE[3:0] bits (AHB prescaler) /
bogdanm	20:4263a77256ae	4966	#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /!< Bit 0 /
bogdanm	20:4263a77256ae	4967	#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /!< Bit 1 /
bogdanm	20:4263a77256ae	4968	#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /!< Bit 2 /
bogdanm	20:4263a77256ae	4969	#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /!< Bit 3 /
bogdanm	20:4263a77256ae	4970
bogdanm	20:4263a77256ae	4971	#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /!< SYSCLK not divided /
bogdanm	20:4263a77256ae	4972	#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /!< SYSCLK divided by 2 /
bogdanm	20:4263a77256ae	4973	#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /!< SYSCLK divided by 4 /
bogdanm	20:4263a77256ae	4974	#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /!< SYSCLK divided by 8 /
bogdanm	20:4263a77256ae	4975	#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /!< SYSCLK divided by 16 /
bogdanm	20:4263a77256ae	4976	#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /!< SYSCLK divided by 64 /
bogdanm	20:4263a77256ae	4977	#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /!< SYSCLK divided by 128 /
bogdanm	20:4263a77256ae	4978	#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /!< SYSCLK divided by 256 /
bogdanm	20:4263a77256ae	4979	#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /!< SYSCLK divided by 512 /
bogdanm	20:4263a77256ae	4980
bogdanm	20:4263a77256ae	4981	/!< PPRE1 configuration /
bogdanm	20:4263a77256ae	4982	#define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /!< PRE1[2:0] bits (APB1 prescaler) /
bogdanm	20:4263a77256ae	4983	#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /!< Bit 0 /
bogdanm	20:4263a77256ae	4984	#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /!< Bit 1 /
bogdanm	20:4263a77256ae	4985	#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /!< Bit 2 /
bogdanm	20:4263a77256ae	4986
bogdanm	20:4263a77256ae	4987	#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /!< HCLK not divided /
bogdanm	20:4263a77256ae	4988	#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /!< HCLK divided by 2 /
bogdanm	20:4263a77256ae	4989	#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /!< HCLK divided by 4 /
bogdanm	20:4263a77256ae	4990	#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /!< HCLK divided by 8 /
bogdanm	20:4263a77256ae	4991	#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /!< HCLK divided by 16 /
bogdanm	20:4263a77256ae	4992
bogdanm	20:4263a77256ae	4993	/!< PPRE2 configuration /
bogdanm	20:4263a77256ae	4994	#define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /!< PRE2[2:0] bits (APB2 prescaler) /
bogdanm	20:4263a77256ae	4995	#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /!< Bit 0 /
bogdanm	20:4263a77256ae	4996	#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /!< Bit 1 /
bogdanm	20:4263a77256ae	4997	#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /!< Bit 2 /
bogdanm	20:4263a77256ae	4998
bogdanm	20:4263a77256ae	4999	#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /!< HCLK not divided /
bogdanm	20:4263a77256ae	5000	#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /!< HCLK divided by 2 /
bogdanm	20:4263a77256ae	5001	#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /!< HCLK divided by 4 /
bogdanm	20:4263a77256ae	5002	#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /!< HCLK divided by 8 /
bogdanm	20:4263a77256ae	5003	#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /!< HCLK divided by 16 /
bogdanm	20:4263a77256ae	5004
bogdanm	20:4263a77256ae	5005	/!< RTCPRE configuration /
bogdanm	20:4263a77256ae	5006	#define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
bogdanm	20:4263a77256ae	5007	#define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
bogdanm	20:4263a77256ae	5008	#define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)
bogdanm	20:4263a77256ae	5009	#define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)
bogdanm	20:4263a77256ae	5010	#define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
bogdanm	20:4263a77256ae	5011	#define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)
bogdanm	20:4263a77256ae	5012
bogdanm	20:4263a77256ae	5013	/!< MCO1 configuration /
bogdanm	20:4263a77256ae	5014	#define RCC_CFGR_MCO1 ((uint32_t)0x00600000)
bogdanm	20:4263a77256ae	5015	#define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)
bogdanm	20:4263a77256ae	5016	#define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)
bogdanm	20:4263a77256ae	5017
bogdanm	20:4263a77256ae	5018	#define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)
bogdanm	20:4263a77256ae	5019
bogdanm	20:4263a77256ae	5020	#define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)
bogdanm	20:4263a77256ae	5021	#define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
bogdanm	20:4263a77256ae	5022	#define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)
bogdanm	20:4263a77256ae	5023	#define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)
bogdanm	20:4263a77256ae	5024
bogdanm	20:4263a77256ae	5025	#define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)
bogdanm	20:4263a77256ae	5026	#define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)
bogdanm	20:4263a77256ae	5027	#define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
bogdanm	20:4263a77256ae	5028	#define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)
bogdanm	20:4263a77256ae	5029
bogdanm	20:4263a77256ae	5030	#define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)
bogdanm	20:4263a77256ae	5031	#define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)
bogdanm	20:4263a77256ae	5032	#define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)
bogdanm	20:4263a77256ae	5033
bogdanm	20:4263a77256ae	5034	/****************** Bit definition for RCC_CIR register *****************/
bogdanm	20:4263a77256ae	5035	#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	5036	#define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
bogdanm	20:4263a77256ae	5037	#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
bogdanm	20:4263a77256ae	5038	#define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
bogdanm	20:4263a77256ae	5039	#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
bogdanm	20:4263a77256ae	5040	#define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)
bogdanm	20:4263a77256ae	5041	#define RCC_CIR_CSSF ((uint32_t)0x00000080)
bogdanm	20:4263a77256ae	5042	#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
bogdanm	20:4263a77256ae	5043	#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
bogdanm	20:4263a77256ae	5044	#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
bogdanm	20:4263a77256ae	5045	#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
bogdanm	20:4263a77256ae	5046	#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
bogdanm	20:4263a77256ae	5047	#define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)
bogdanm	20:4263a77256ae	5048	#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
bogdanm	20:4263a77256ae	5049	#define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
bogdanm	20:4263a77256ae	5050	#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
bogdanm	20:4263a77256ae	5051	#define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
bogdanm	20:4263a77256ae	5052	#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
bogdanm	20:4263a77256ae	5053	#define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)
bogdanm	20:4263a77256ae	5054	#define RCC_CIR_CSSC ((uint32_t)0x00800000)
bogdanm	20:4263a77256ae	5055
bogdanm	20:4263a77256ae	5056	/****************** Bit definition for RCC_AHB1RSTR register ************/
bogdanm	20:4263a77256ae	5057	#define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	5058	#define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
bogdanm	20:4263a77256ae	5059	#define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
bogdanm	20:4263a77256ae	5060	#define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)
bogdanm	20:4263a77256ae	5061	#define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)
bogdanm	20:4263a77256ae	5062	#define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020)
bogdanm	20:4263a77256ae	5063	#define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040)
bogdanm	20:4263a77256ae	5064	#define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
bogdanm	20:4263a77256ae	5065	#define RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100)
bogdanm	20:4263a77256ae	5066	#define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
bogdanm	20:4263a77256ae	5067	#define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
bogdanm	20:4263a77256ae	5068	#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
bogdanm	20:4263a77256ae	5069	#define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)
bogdanm	20:4263a77256ae	5070	#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000)
bogdanm	20:4263a77256ae	5071
bogdanm	20:4263a77256ae	5072	/****************** Bit definition for RCC_AHB2RSTR register ************/
bogdanm	20:4263a77256ae	5073	#define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	5074	#define RCC_AHB2RSTR_CRYPRST ((uint32_t)0x00000010)
bogdanm	20:4263a77256ae	5075	#define RCC_AHB2RSTR_HASHRST ((uint32_t)0x00000020)
bogdanm	20:4263a77256ae	5076	/* maintained for legacy purpose */
bogdanm	20:4263a77256ae	5077	#define RCC_AHB2RSTR_HSAHRST RCC_AHB2RSTR_HASHRST
bogdanm	20:4263a77256ae	5078	#define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040)
bogdanm	20:4263a77256ae	5079	#define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)
bogdanm	20:4263a77256ae	5080
bogdanm	20:4263a77256ae	5081	/****************** Bit definition for RCC_AHB3RSTR register ************/
bogdanm	20:4263a77256ae	5082	#define RCC_AHB3RSTR_FSMCRST ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	5083
bogdanm	20:4263a77256ae	5084	/****************** Bit definition for RCC_APB1RSTR register ************/
bogdanm	20:4263a77256ae	5085	#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	5086	#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
bogdanm	20:4263a77256ae	5087	#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
bogdanm	20:4263a77256ae	5088	#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
bogdanm	20:4263a77256ae	5089	#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)
bogdanm	20:4263a77256ae	5090	#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)
bogdanm	20:4263a77256ae	5091	#define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040)
bogdanm	20:4263a77256ae	5092	#define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)
bogdanm	20:4263a77256ae	5093	#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100)
bogdanm	20:4263a77256ae	5094	#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)
bogdanm	20:4263a77256ae	5095	#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)
bogdanm	20:4263a77256ae	5096	#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)
bogdanm	20:4263a77256ae	5097	#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
bogdanm	20:4263a77256ae	5098	#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)
bogdanm	20:4263a77256ae	5099	#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)
bogdanm	20:4263a77256ae	5100	#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)
bogdanm	20:4263a77256ae	5101	#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
bogdanm	20:4263a77256ae	5102	#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
bogdanm	20:4263a77256ae	5103	#define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)
bogdanm	20:4263a77256ae	5104	#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000)
bogdanm	20:4263a77256ae	5105	#define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000)
bogdanm	20:4263a77256ae	5106	#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
bogdanm	20:4263a77256ae	5107	#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)
bogdanm	20:4263a77256ae	5108	#define RCC_APB1RSTR_UART7RST ((uint32_t)0x40000000)
bogdanm	20:4263a77256ae	5109	#define RCC_APB1RSTR_UART8RST ((uint32_t)0x80000000)
bogdanm	20:4263a77256ae	5110
bogdanm	20:4263a77256ae	5111	/****************** Bit definition for RCC_APB2RSTR register ************/
bogdanm	20:4263a77256ae	5112	#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	5113	#define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002)
bogdanm	20:4263a77256ae	5114	#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
bogdanm	20:4263a77256ae	5115	#define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
bogdanm	20:4263a77256ae	5116	#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
bogdanm	20:4263a77256ae	5117	#define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800)
bogdanm	20:4263a77256ae	5118	#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
bogdanm	20:4263a77256ae	5119	#define RCC_APB2RSTR_SPI4RST ((uint32_t)0x00002000)
bogdanm	20:4263a77256ae	5120	#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
bogdanm	20:4263a77256ae	5121	#define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
bogdanm	20:4263a77256ae	5122	#define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)
bogdanm	20:4263a77256ae	5123	#define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
bogdanm	20:4263a77256ae	5124	#define RCC_APB2RSTR_SPI5RST ((uint32_t)0x00100000)
bogdanm	20:4263a77256ae	5125	#define RCC_APB2RSTR_SPI6RST ((uint32_t)0x00200000)
bogdanm	20:4263a77256ae	5126
bogdanm	20:4263a77256ae	5127	/* Old SPI1RST bit definition, maintained for legacy purpose */
bogdanm	20:4263a77256ae	5128	#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
bogdanm	20:4263a77256ae	5129
bogdanm	20:4263a77256ae	5130	/****************** Bit definition for RCC_AHB1ENR register *************/
bogdanm	20:4263a77256ae	5131	#define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	5132	#define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
bogdanm	20:4263a77256ae	5133	#define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
bogdanm	20:4263a77256ae	5134	#define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)
bogdanm	20:4263a77256ae	5135	#define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)
bogdanm	20:4263a77256ae	5136	#define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020)
bogdanm	20:4263a77256ae	5137	#define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040)
bogdanm	20:4263a77256ae	5138	#define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
bogdanm	20:4263a77256ae	5139	#define RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100)
bogdanm	20:4263a77256ae	5140	#define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
bogdanm	20:4263a77256ae	5141	#define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)
bogdanm	20:4263a77256ae	5142	#define RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000)
bogdanm	20:4263a77256ae	5143	#define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
bogdanm	20:4263a77256ae	5144	#define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
bogdanm	20:4263a77256ae	5145	#define RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000)
bogdanm	20:4263a77256ae	5146	#define RCC_AHB1ENR_ETHMACTXEN ((uint32_t)0x04000000)
bogdanm	20:4263a77256ae	5147	#define RCC_AHB1ENR_ETHMACRXEN ((uint32_t)0x08000000)
bogdanm	20:4263a77256ae	5148	#define RCC_AHB1ENR_ETHMACPTPEN ((uint32_t)0x10000000)
bogdanm	20:4263a77256ae	5149	#define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000)
bogdanm	20:4263a77256ae	5150	#define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000)
bogdanm	20:4263a77256ae	5151
bogdanm	20:4263a77256ae	5152	/****************** Bit definition for RCC_AHB2ENR register *************/
bogdanm	20:4263a77256ae	5153	#define RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	5154	#define RCC_AHB2ENR_CRYPEN ((uint32_t)0x00000010)
bogdanm	20:4263a77256ae	5155	#define RCC_AHB2ENR_HASHEN ((uint32_t)0x00000020)
bogdanm	20:4263a77256ae	5156	#define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040)
bogdanm	20:4263a77256ae	5157	#define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)
bogdanm	20:4263a77256ae	5158
bogdanm	20:4263a77256ae	5159	/****************** Bit definition for RCC_AHB3ENR register *************/
bogdanm	20:4263a77256ae	5160	#define RCC_AHB3ENR_FSMCEN ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	5161
bogdanm	20:4263a77256ae	5162	/****************** Bit definition for RCC_APB1ENR register *************/
bogdanm	20:4263a77256ae	5163	#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	5164	#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
bogdanm	20:4263a77256ae	5165	#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
bogdanm	20:4263a77256ae	5166	#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
bogdanm	20:4263a77256ae	5167	#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)
bogdanm	20:4263a77256ae	5168	#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)
bogdanm	20:4263a77256ae	5169	#define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)
bogdanm	20:4263a77256ae	5170	#define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080)
bogdanm	20:4263a77256ae	5171	#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)
bogdanm	20:4263a77256ae	5172	#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
bogdanm	20:4263a77256ae	5173	#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
bogdanm	20:4263a77256ae	5174	#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
bogdanm	20:4263a77256ae	5175	#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
bogdanm	20:4263a77256ae	5176	#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)
bogdanm	20:4263a77256ae	5177	#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)
bogdanm	20:4263a77256ae	5178	#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)
bogdanm	20:4263a77256ae	5179	#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
bogdanm	20:4263a77256ae	5180	#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
bogdanm	20:4263a77256ae	5181	#define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)
bogdanm	20:4263a77256ae	5182	#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000)
bogdanm	20:4263a77256ae	5183	#define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000)
bogdanm	20:4263a77256ae	5184	#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
bogdanm	20:4263a77256ae	5185	#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)
bogdanm	20:4263a77256ae	5186	#define RCC_APB1ENR_UART7EN ((uint32_t)0x40000000)
bogdanm	20:4263a77256ae	5187	#define RCC_APB1ENR_UART8EN ((uint32_t)0x80000000)
bogdanm	20:4263a77256ae	5188
bogdanm	20:4263a77256ae	5189	/****************** Bit definition for RCC_APB2ENR register *************/
bogdanm	20:4263a77256ae	5190	#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	5191	#define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002)
bogdanm	20:4263a77256ae	5192	#define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
bogdanm	20:4263a77256ae	5193	#define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)
bogdanm	20:4263a77256ae	5194	#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
bogdanm	20:4263a77256ae	5195	#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200)
bogdanm	20:4263a77256ae	5196	#define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400)
bogdanm	20:4263a77256ae	5197	#define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800)
bogdanm	20:4263a77256ae	5198	#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
bogdanm	20:4263a77256ae	5199	#define RCC_APB2ENR_SPI4EN ((uint32_t)0x00002000)
bogdanm	20:4263a77256ae	5200	#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
bogdanm	20:4263a77256ae	5201	#define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)
bogdanm	20:4263a77256ae	5202	#define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)
bogdanm	20:4263a77256ae	5203	#define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
bogdanm	20:4263a77256ae	5204	#define RCC_APB2ENR_SPI5EN ((uint32_t)0x00100000)
bogdanm	20:4263a77256ae	5205	#define RCC_APB2ENR_SPI6EN ((uint32_t)0x00200000)
bogdanm	20:4263a77256ae	5206
bogdanm	20:4263a77256ae	5207	/****************** Bit definition for RCC_AHB1LPENR register ***********/
bogdanm	20:4263a77256ae	5208	#define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	5209	#define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)
bogdanm	20:4263a77256ae	5210	#define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)
bogdanm	20:4263a77256ae	5211	#define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)
bogdanm	20:4263a77256ae	5212	#define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)
bogdanm	20:4263a77256ae	5213	#define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020)
bogdanm	20:4263a77256ae	5214	#define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040)
bogdanm	20:4263a77256ae	5215	#define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
bogdanm	20:4263a77256ae	5216	#define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100)
bogdanm	20:4263a77256ae	5217	#define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)
bogdanm	20:4263a77256ae	5218	#define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)
bogdanm	20:4263a77256ae	5219	#define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
bogdanm	20:4263a77256ae	5220	#define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
bogdanm	20:4263a77256ae	5221	#define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
bogdanm	20:4263a77256ae	5222	#define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000)
bogdanm	20:4263a77256ae	5223	#define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
bogdanm	20:4263a77256ae	5224	#define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
bogdanm	20:4263a77256ae	5225	#define RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000)
bogdanm	20:4263a77256ae	5226	#define RCC_AHB1LPENR_ETHMACTXLPEN ((uint32_t)0x04000000)
bogdanm	20:4263a77256ae	5227	#define RCC_AHB1LPENR_ETHMACRXLPEN ((uint32_t)0x08000000)
bogdanm	20:4263a77256ae	5228	#define RCC_AHB1LPENR_ETHMACPTPLPEN ((uint32_t)0x10000000)
bogdanm	20:4263a77256ae	5229	#define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000)
bogdanm	20:4263a77256ae	5230	#define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000)
bogdanm	20:4263a77256ae	5231
bogdanm	20:4263a77256ae	5232	/****************** Bit definition for RCC_AHB2LPENR register ***********/
bogdanm	20:4263a77256ae	5233	#define RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	5234	#define RCC_AHB2LPENR_CRYPLPEN ((uint32_t)0x00000010)
bogdanm	20:4263a77256ae	5235	#define RCC_AHB2LPENR_HASHLPEN ((uint32_t)0x00000020)
bogdanm	20:4263a77256ae	5236	#define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040)
bogdanm	20:4263a77256ae	5237	#define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)
bogdanm	20:4263a77256ae	5238
bogdanm	20:4263a77256ae	5239	/****************** Bit definition for RCC_AHB3LPENR register ***********/
bogdanm	20:4263a77256ae	5240	#define RCC_AHB3LPENR_FSMCLPEN ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	5241
bogdanm	20:4263a77256ae	5242	/****************** Bit definition for RCC_APB1LPENR register ***********/
bogdanm	20:4263a77256ae	5243	#define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	5244	#define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)
bogdanm	20:4263a77256ae	5245	#define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)
bogdanm	20:4263a77256ae	5246	#define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
bogdanm	20:4263a77256ae	5247	#define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)
bogdanm	20:4263a77256ae	5248	#define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020)
bogdanm	20:4263a77256ae	5249	#define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040)
bogdanm	20:4263a77256ae	5250	#define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080)
bogdanm	20:4263a77256ae	5251	#define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100)
bogdanm	20:4263a77256ae	5252	#define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)
bogdanm	20:4263a77256ae	5253	#define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
bogdanm	20:4263a77256ae	5254	#define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)
bogdanm	20:4263a77256ae	5255	#define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
bogdanm	20:4263a77256ae	5256	#define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000)
bogdanm	20:4263a77256ae	5257	#define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000)
bogdanm	20:4263a77256ae	5258	#define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000)
bogdanm	20:4263a77256ae	5259	#define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
bogdanm	20:4263a77256ae	5260	#define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
bogdanm	20:4263a77256ae	5261	#define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)
bogdanm	20:4263a77256ae	5262	#define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000)
bogdanm	20:4263a77256ae	5263	#define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000)
bogdanm	20:4263a77256ae	5264	#define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)
bogdanm	20:4263a77256ae	5265	#define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)
bogdanm	20:4263a77256ae	5266	#define RCC_APB1LPENR_UART7LPEN ((uint32_t)0x40000000)
bogdanm	20:4263a77256ae	5267	#define RCC_APB1LPENR_UART8LPEN ((uint32_t)0x80000000)
bogdanm	20:4263a77256ae	5268
bogdanm	20:4263a77256ae	5269	/****************** Bit definition for RCC_APB2LPENR register ***********/
bogdanm	20:4263a77256ae	5270	#define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	5271	#define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002)
bogdanm	20:4263a77256ae	5272	#define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)
bogdanm	20:4263a77256ae	5273	#define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)
bogdanm	20:4263a77256ae	5274	#define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
bogdanm	20:4263a77256ae	5275	#define RCC_APB2LPENR_ADC2PEN ((uint32_t)0x00000200)
bogdanm	20:4263a77256ae	5276	#define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400)
bogdanm	20:4263a77256ae	5277	#define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800)
bogdanm	20:4263a77256ae	5278	#define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
bogdanm	20:4263a77256ae	5279	#define RCC_APB2LPENR_SPI4LPEN ((uint32_t)0x00002000)
bogdanm	20:4263a77256ae	5280	#define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
bogdanm	20:4263a77256ae	5281	#define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)
bogdanm	20:4263a77256ae	5282	#define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)
bogdanm	20:4263a77256ae	5283	#define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)
bogdanm	20:4263a77256ae	5284	#define RCC_APB2LPENR_SPI5LPEN ((uint32_t)0x00100000)
bogdanm	20:4263a77256ae	5285	#define RCC_APB2LPENR_SPI6LPEN ((uint32_t)0x00200000)
bogdanm	20:4263a77256ae	5286
bogdanm	20:4263a77256ae	5287	/****************** Bit definition for RCC_BDCR register ****************/
bogdanm	20:4263a77256ae	5288	#define RCC_BDCR_LSEON ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	5289	#define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
bogdanm	20:4263a77256ae	5290	#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
bogdanm	20:4263a77256ae	5291
bogdanm	20:4263a77256ae	5292	#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
bogdanm	20:4263a77256ae	5293	#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
bogdanm	20:4263a77256ae	5294	#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
bogdanm	20:4263a77256ae	5295
bogdanm	20:4263a77256ae	5296	#define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
bogdanm	20:4263a77256ae	5297	#define RCC_BDCR_BDRST ((uint32_t)0x00010000)
bogdanm	20:4263a77256ae	5298
bogdanm	20:4263a77256ae	5299	/****************** Bit definition for RCC_CSR register *****************/
bogdanm	20:4263a77256ae	5300	#define RCC_CSR_LSION ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	5301	#define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
bogdanm	20:4263a77256ae	5302	#define RCC_CSR_RMVF ((uint32_t)0x01000000)
bogdanm	20:4263a77256ae	5303	#define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
bogdanm	20:4263a77256ae	5304	#define RCC_CSR_PADRSTF ((uint32_t)0x04000000)
bogdanm	20:4263a77256ae	5305	#define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
bogdanm	20:4263a77256ae	5306	#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
bogdanm	20:4263a77256ae	5307	#define RCC_CSR_WDGRSTF ((uint32_t)0x20000000)
bogdanm	20:4263a77256ae	5308	#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
bogdanm	20:4263a77256ae	5309	#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
bogdanm	20:4263a77256ae	5310
bogdanm	20:4263a77256ae	5311	/****************** Bit definition for RCC_SSCGR register ***************/
bogdanm	20:4263a77256ae	5312	#define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
bogdanm	20:4263a77256ae	5313	#define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)
bogdanm	20:4263a77256ae	5314	#define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)
bogdanm	20:4263a77256ae	5315	#define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)
bogdanm	20:4263a77256ae	5316
bogdanm	20:4263a77256ae	5317	/****************** Bit definition for RCC_PLLI2SCFGR register **********/
bogdanm	20:4263a77256ae	5318	#define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)
bogdanm	20:4263a77256ae	5319	#define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)
bogdanm	20:4263a77256ae	5320
bogdanm	20:4263a77256ae	5321	/****************** Bit definition for RCC_DCKCFGR register *************/
bogdanm	20:4263a77256ae	5322	#define RCC_DCKCFGR_TIMPRE ((uint32_t)0x01000000)
bogdanm	20:4263a77256ae	5323
bogdanm	20:4263a77256ae	5324
bogdanm	20:4263a77256ae	5325	/******************************************************************************/
bogdanm	20:4263a77256ae	5326	/* */
bogdanm	20:4263a77256ae	5327	/* RNG */
bogdanm	20:4263a77256ae	5328	/* */
bogdanm	20:4263a77256ae	5329	/******************************************************************************/
bogdanm	20:4263a77256ae	5330	/****************** Bits definition for RNG_CR register *****************/
bogdanm	20:4263a77256ae	5331	#define RNG_CR_RNGEN ((uint32_t)0x00000004)
bogdanm	20:4263a77256ae	5332	#define RNG_CR_IE ((uint32_t)0x00000008)
bogdanm	20:4263a77256ae	5333
bogdanm	20:4263a77256ae	5334	/****************** Bits definition for RNG_SR register *****************/
bogdanm	20:4263a77256ae	5335	#define RNG_SR_DRDY ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	5336	#define RNG_SR_CECS ((uint32_t)0x00000002)
bogdanm	20:4263a77256ae	5337	#define RNG_SR_SECS ((uint32_t)0x00000004)
bogdanm	20:4263a77256ae	5338	#define RNG_SR_CEIS ((uint32_t)0x00000020)
bogdanm	20:4263a77256ae	5339	#define RNG_SR_SEIS ((uint32_t)0x00000040)
bogdanm	20:4263a77256ae	5340
bogdanm	20:4263a77256ae	5341	/******************************************************************************/
bogdanm	20:4263a77256ae	5342	/* */
bogdanm	20:4263a77256ae	5343	/* Real-Time Clock (RTC) */
bogdanm	20:4263a77256ae	5344	/* */
bogdanm	20:4263a77256ae	5345	/******************************************************************************/
bogdanm	20:4263a77256ae	5346	/****************** Bits definition for RTC_TR register *****************/
bogdanm	20:4263a77256ae	5347	#define RTC_TR_PM ((uint32_t)0x00400000)
bogdanm	20:4263a77256ae	5348	#define RTC_TR_HT ((uint32_t)0x00300000)
bogdanm	20:4263a77256ae	5349	#define RTC_TR_HT_0 ((uint32_t)0x00100000)
bogdanm	20:4263a77256ae	5350	#define RTC_TR_HT_1 ((uint32_t)0x00200000)
bogdanm	20:4263a77256ae	5351	#define RTC_TR_HU ((uint32_t)0x000F0000)
bogdanm	20:4263a77256ae	5352	#define RTC_TR_HU_0 ((uint32_t)0x00010000)
bogdanm	20:4263a77256ae	5353	#define RTC_TR_HU_1 ((uint32_t)0x00020000)
bogdanm	20:4263a77256ae	5354	#define RTC_TR_HU_2 ((uint32_t)0x00040000)
bogdanm	20:4263a77256ae	5355	#define RTC_TR_HU_3 ((uint32_t)0x00080000)
bogdanm	20:4263a77256ae	5356	#define RTC_TR_MNT ((uint32_t)0x00007000)
bogdanm	20:4263a77256ae	5357	#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
bogdanm	20:4263a77256ae	5358	#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
bogdanm	20:4263a77256ae	5359	#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
bogdanm	20:4263a77256ae	5360	#define RTC_TR_MNU ((uint32_t)0x00000F00)
bogdanm	20:4263a77256ae	5361	#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
bogdanm	20:4263a77256ae	5362	#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
bogdanm	20:4263a77256ae	5363	#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
bogdanm	20:4263a77256ae	5364	#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
bogdanm	20:4263a77256ae	5365	#define RTC_TR_ST ((uint32_t)0x00000070)
bogdanm	20:4263a77256ae	5366	#define RTC_TR_ST_0 ((uint32_t)0x00000010)
bogdanm	20:4263a77256ae	5367	#define RTC_TR_ST_1 ((uint32_t)0x00000020)
bogdanm	20:4263a77256ae	5368	#define RTC_TR_ST_2 ((uint32_t)0x00000040)
bogdanm	20:4263a77256ae	5369	#define RTC_TR_SU ((uint32_t)0x0000000F)
bogdanm	20:4263a77256ae	5370	#define RTC_TR_SU_0 ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	5371	#define RTC_TR_SU_1 ((uint32_t)0x00000002)
bogdanm	20:4263a77256ae	5372	#define RTC_TR_SU_2 ((uint32_t)0x00000004)
bogdanm	20:4263a77256ae	5373	#define RTC_TR_SU_3 ((uint32_t)0x00000008)
bogdanm	20:4263a77256ae	5374
bogdanm	20:4263a77256ae	5375	/****************** Bits definition for RTC_DR register *****************/
bogdanm	20:4263a77256ae	5376	#define RTC_DR_YT ((uint32_t)0x00F00000)
bogdanm	20:4263a77256ae	5377	#define RTC_DR_YT_0 ((uint32_t)0x00100000)
bogdanm	20:4263a77256ae	5378	#define RTC_DR_YT_1 ((uint32_t)0x00200000)
bogdanm	20:4263a77256ae	5379	#define RTC_DR_YT_2 ((uint32_t)0x00400000)
bogdanm	20:4263a77256ae	5380	#define RTC_DR_YT_3 ((uint32_t)0x00800000)
bogdanm	20:4263a77256ae	5381	#define RTC_DR_YU ((uint32_t)0x000F0000)
bogdanm	20:4263a77256ae	5382	#define RTC_DR_YU_0 ((uint32_t)0x00010000)
bogdanm	20:4263a77256ae	5383	#define RTC_DR_YU_1 ((uint32_t)0x00020000)
bogdanm	20:4263a77256ae	5384	#define RTC_DR_YU_2 ((uint32_t)0x00040000)
bogdanm	20:4263a77256ae	5385	#define RTC_DR_YU_3 ((uint32_t)0x00080000)
bogdanm	20:4263a77256ae	5386	#define RTC_DR_WDU ((uint32_t)0x0000E000)
bogdanm	20:4263a77256ae	5387	#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
bogdanm	20:4263a77256ae	5388	#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
bogdanm	20:4263a77256ae	5389	#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
bogdanm	20:4263a77256ae	5390	#define RTC_DR_MT ((uint32_t)0x00001000)
bogdanm	20:4263a77256ae	5391	#define RTC_DR_MU ((uint32_t)0x00000F00)
bogdanm	20:4263a77256ae	5392	#define RTC_DR_MU_0 ((uint32_t)0x00000100)
bogdanm	20:4263a77256ae	5393	#define RTC_DR_MU_1 ((uint32_t)0x00000200)
bogdanm	20:4263a77256ae	5394	#define RTC_DR_MU_2 ((uint32_t)0x00000400)
bogdanm	20:4263a77256ae	5395	#define RTC_DR_MU_3 ((uint32_t)0x00000800)
bogdanm	20:4263a77256ae	5396	#define RTC_DR_DT ((uint32_t)0x00000030)
bogdanm	20:4263a77256ae	5397	#define RTC_DR_DT_0 ((uint32_t)0x00000010)
bogdanm	20:4263a77256ae	5398	#define RTC_DR_DT_1 ((uint32_t)0x00000020)
bogdanm	20:4263a77256ae	5399	#define RTC_DR_DU ((uint32_t)0x0000000F)
bogdanm	20:4263a77256ae	5400	#define RTC_DR_DU_0 ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	5401	#define RTC_DR_DU_1 ((uint32_t)0x00000002)
bogdanm	20:4263a77256ae	5402	#define RTC_DR_DU_2 ((uint32_t)0x00000004)
bogdanm	20:4263a77256ae	5403	#define RTC_DR_DU_3 ((uint32_t)0x00000008)
bogdanm	20:4263a77256ae	5404
bogdanm	20:4263a77256ae	5405	/****************** Bits definition for RTC_CR register *****************/
bogdanm	20:4263a77256ae	5406	#define RTC_CR_COE ((uint32_t)0x00800000)
bogdanm	20:4263a77256ae	5407	#define RTC_CR_OSEL ((uint32_t)0x00600000)
bogdanm	20:4263a77256ae	5408	#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
bogdanm	20:4263a77256ae	5409	#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
bogdanm	20:4263a77256ae	5410	#define RTC_CR_POL ((uint32_t)0x00100000)
bogdanm	20:4263a77256ae	5411	#define RTC_CR_COSEL ((uint32_t)0x00080000)
bogdanm	20:4263a77256ae	5412	#define RTC_CR_BCK ((uint32_t)0x00040000)
bogdanm	20:4263a77256ae	5413	#define RTC_CR_SUB1H ((uint32_t)0x00020000)
bogdanm	20:4263a77256ae	5414	#define RTC_CR_ADD1H ((uint32_t)0x00010000)
bogdanm	20:4263a77256ae	5415	#define RTC_CR_TSIE ((uint32_t)0x00008000)
bogdanm	20:4263a77256ae	5416	#define RTC_CR_WUTIE ((uint32_t)0x00004000)
bogdanm	20:4263a77256ae	5417	#define RTC_CR_ALRBIE ((uint32_t)0x00002000)
bogdanm	20:4263a77256ae	5418	#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
bogdanm	20:4263a77256ae	5419	#define RTC_CR_TSE ((uint32_t)0x00000800)
bogdanm	20:4263a77256ae	5420	#define RTC_CR_WUTE ((uint32_t)0x00000400)
bogdanm	20:4263a77256ae	5421	#define RTC_CR_ALRBE ((uint32_t)0x00000200)
bogdanm	20:4263a77256ae	5422	#define RTC_CR_ALRAE ((uint32_t)0x00000100)
bogdanm	20:4263a77256ae	5423	#define RTC_CR_DCE ((uint32_t)0x00000080)
bogdanm	20:4263a77256ae	5424	#define RTC_CR_FMT ((uint32_t)0x00000040)
bogdanm	20:4263a77256ae	5425	#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
bogdanm	20:4263a77256ae	5426	#define RTC_CR_REFCKON ((uint32_t)0x00000010)
bogdanm	20:4263a77256ae	5427	#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
bogdanm	20:4263a77256ae	5428	#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
bogdanm	20:4263a77256ae	5429	#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	5430	#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
bogdanm	20:4263a77256ae	5431	#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
bogdanm	20:4263a77256ae	5432
bogdanm	20:4263a77256ae	5433	/****************** Bits definition for RTC_ISR register ****************/
bogdanm	20:4263a77256ae	5434	#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
bogdanm	20:4263a77256ae	5435	#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
bogdanm	20:4263a77256ae	5436	#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
bogdanm	20:4263a77256ae	5437	#define RTC_ISR_TSF ((uint32_t)0x00000800)
bogdanm	20:4263a77256ae	5438	#define RTC_ISR_WUTF ((uint32_t)0x00000400)
bogdanm	20:4263a77256ae	5439	#define RTC_ISR_ALRBF ((uint32_t)0x00000200)
bogdanm	20:4263a77256ae	5440	#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
bogdanm	20:4263a77256ae	5441	#define RTC_ISR_INIT ((uint32_t)0x00000080)
bogdanm	20:4263a77256ae	5442	#define RTC_ISR_INITF ((uint32_t)0x00000040)
bogdanm	20:4263a77256ae	5443	#define RTC_ISR_RSF ((uint32_t)0x00000020)
bogdanm	20:4263a77256ae	5444	#define RTC_ISR_INITS ((uint32_t)0x00000010)
bogdanm	20:4263a77256ae	5445	#define RTC_ISR_SHPF ((uint32_t)0x00000008)
bogdanm	20:4263a77256ae	5446	#define RTC_ISR_WUTWF ((uint32_t)0x00000004)
bogdanm	20:4263a77256ae	5447	#define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
bogdanm	20:4263a77256ae	5448	#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	5449
bogdanm	20:4263a77256ae	5450	/****************** Bits definition for RTC_PRER register ***************/
bogdanm	20:4263a77256ae	5451	#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
bogdanm	20:4263a77256ae	5452	#define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
bogdanm	20:4263a77256ae	5453
bogdanm	20:4263a77256ae	5454	/****************** Bits definition for RTC_WUTR register ***************/
bogdanm	20:4263a77256ae	5455	#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
bogdanm	20:4263a77256ae	5456
bogdanm	20:4263a77256ae	5457	/****************** Bits definition for RTC_CALIBR register *************/
bogdanm	20:4263a77256ae	5458	#define RTC_CALIBR_DCS ((uint32_t)0x00000080)
bogdanm	20:4263a77256ae	5459	#define RTC_CALIBR_DC ((uint32_t)0x0000001F)
bogdanm	20:4263a77256ae	5460
bogdanm	20:4263a77256ae	5461	/****************** Bits definition for RTC_ALRMAR register *************/
bogdanm	20:4263a77256ae	5462	#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
bogdanm	20:4263a77256ae	5463	#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
bogdanm	20:4263a77256ae	5464	#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
bogdanm	20:4263a77256ae	5465	#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
bogdanm	20:4263a77256ae	5466	#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
bogdanm	20:4263a77256ae	5467	#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
bogdanm	20:4263a77256ae	5468	#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
bogdanm	20:4263a77256ae	5469	#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
bogdanm	20:4263a77256ae	5470	#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
bogdanm	20:4263a77256ae	5471	#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
bogdanm	20:4263a77256ae	5472	#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
bogdanm	20:4263a77256ae	5473	#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
bogdanm	20:4263a77256ae	5474	#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
bogdanm	20:4263a77256ae	5475	#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
bogdanm	20:4263a77256ae	5476	#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
bogdanm	20:4263a77256ae	5477	#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
bogdanm	20:4263a77256ae	5478	#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
bogdanm	20:4263a77256ae	5479	#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
bogdanm	20:4263a77256ae	5480	#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
bogdanm	20:4263a77256ae	5481	#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
bogdanm	20:4263a77256ae	5482	#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
bogdanm	20:4263a77256ae	5483	#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
bogdanm	20:4263a77256ae	5484	#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
bogdanm	20:4263a77256ae	5485	#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
bogdanm	20:4263a77256ae	5486	#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
bogdanm	20:4263a77256ae	5487	#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
bogdanm	20:4263a77256ae	5488	#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
bogdanm	20:4263a77256ae	5489	#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
bogdanm	20:4263a77256ae	5490	#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
bogdanm	20:4263a77256ae	5491	#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
bogdanm	20:4263a77256ae	5492	#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
bogdanm	20:4263a77256ae	5493	#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
bogdanm	20:4263a77256ae	5494	#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
bogdanm	20:4263a77256ae	5495	#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
bogdanm	20:4263a77256ae	5496	#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
bogdanm	20:4263a77256ae	5497	#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
bogdanm	20:4263a77256ae	5498	#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	5499	#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
bogdanm	20:4263a77256ae	5500	#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
bogdanm	20:4263a77256ae	5501	#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
bogdanm	20:4263a77256ae	5502
bogdanm	20:4263a77256ae	5503	/****************** Bits definition for RTC_ALRMBR register *************/
bogdanm	20:4263a77256ae	5504	#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
bogdanm	20:4263a77256ae	5505	#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
bogdanm	20:4263a77256ae	5506	#define RTC_ALRMBR_DT ((uint32_t)0x30000000)
bogdanm	20:4263a77256ae	5507	#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
bogdanm	20:4263a77256ae	5508	#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
bogdanm	20:4263a77256ae	5509	#define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
bogdanm	20:4263a77256ae	5510	#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
bogdanm	20:4263a77256ae	5511	#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
bogdanm	20:4263a77256ae	5512	#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
bogdanm	20:4263a77256ae	5513	#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
bogdanm	20:4263a77256ae	5514	#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
bogdanm	20:4263a77256ae	5515	#define RTC_ALRMBR_PM ((uint32_t)0x00400000)
bogdanm	20:4263a77256ae	5516	#define RTC_ALRMBR_HT ((uint32_t)0x00300000)
bogdanm	20:4263a77256ae	5517	#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
bogdanm	20:4263a77256ae	5518	#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
bogdanm	20:4263a77256ae	5519	#define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
bogdanm	20:4263a77256ae	5520	#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
bogdanm	20:4263a77256ae	5521	#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
bogdanm	20:4263a77256ae	5522	#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
bogdanm	20:4263a77256ae	5523	#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
bogdanm	20:4263a77256ae	5524	#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
bogdanm	20:4263a77256ae	5525	#define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
bogdanm	20:4263a77256ae	5526	#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
bogdanm	20:4263a77256ae	5527	#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
bogdanm	20:4263a77256ae	5528	#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
bogdanm	20:4263a77256ae	5529	#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
bogdanm	20:4263a77256ae	5530	#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
bogdanm	20:4263a77256ae	5531	#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
bogdanm	20:4263a77256ae	5532	#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
bogdanm	20:4263a77256ae	5533	#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
bogdanm	20:4263a77256ae	5534	#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
bogdanm	20:4263a77256ae	5535	#define RTC_ALRMBR_ST ((uint32_t)0x00000070)
bogdanm	20:4263a77256ae	5536	#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
bogdanm	20:4263a77256ae	5537	#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
bogdanm	20:4263a77256ae	5538	#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
bogdanm	20:4263a77256ae	5539	#define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
bogdanm	20:4263a77256ae	5540	#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	5541	#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
bogdanm	20:4263a77256ae	5542	#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
bogdanm	20:4263a77256ae	5543	#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
bogdanm	20:4263a77256ae	5544
bogdanm	20:4263a77256ae	5545	/****************** Bits definition for RTC_WPR register ****************/
bogdanm	20:4263a77256ae	5546	#define RTC_WPR_KEY ((uint32_t)0x000000FF)
bogdanm	20:4263a77256ae	5547
bogdanm	20:4263a77256ae	5548	/****************** Bits definition for RTC_SSR register ****************/
bogdanm	20:4263a77256ae	5549	#define RTC_SSR_SS ((uint32_t)0x0000FFFF)
bogdanm	20:4263a77256ae	5550
bogdanm	20:4263a77256ae	5551	/****************** Bits definition for RTC_SHIFTR register *************/
bogdanm	20:4263a77256ae	5552	#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
bogdanm	20:4263a77256ae	5553	#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
bogdanm	20:4263a77256ae	5554
bogdanm	20:4263a77256ae	5555	/****************** Bits definition for RTC_TSTR register ***************/
bogdanm	20:4263a77256ae	5556	#define RTC_TSTR_PM ((uint32_t)0x00400000)
bogdanm	20:4263a77256ae	5557	#define RTC_TSTR_HT ((uint32_t)0x00300000)
bogdanm	20:4263a77256ae	5558	#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
bogdanm	20:4263a77256ae	5559	#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
bogdanm	20:4263a77256ae	5560	#define RTC_TSTR_HU ((uint32_t)0x000F0000)
bogdanm	20:4263a77256ae	5561	#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
bogdanm	20:4263a77256ae	5562	#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
bogdanm	20:4263a77256ae	5563	#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
bogdanm	20:4263a77256ae	5564	#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
bogdanm	20:4263a77256ae	5565	#define RTC_TSTR_MNT ((uint32_t)0x00007000)
bogdanm	20:4263a77256ae	5566	#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
bogdanm	20:4263a77256ae	5567	#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
bogdanm	20:4263a77256ae	5568	#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
bogdanm	20:4263a77256ae	5569	#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
bogdanm	20:4263a77256ae	5570	#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
bogdanm	20:4263a77256ae	5571	#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
bogdanm	20:4263a77256ae	5572	#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
bogdanm	20:4263a77256ae	5573	#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
bogdanm	20:4263a77256ae	5574	#define RTC_TSTR_ST ((uint32_t)0x00000070)
bogdanm	20:4263a77256ae	5575	#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
bogdanm	20:4263a77256ae	5576	#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
bogdanm	20:4263a77256ae	5577	#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
bogdanm	20:4263a77256ae	5578	#define RTC_TSTR_SU ((uint32_t)0x0000000F)
bogdanm	20:4263a77256ae	5579	#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	5580	#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
bogdanm	20:4263a77256ae	5581	#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
bogdanm	20:4263a77256ae	5582	#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
bogdanm	20:4263a77256ae	5583
bogdanm	20:4263a77256ae	5584	/****************** Bits definition for RTC_TSDR register ***************/
bogdanm	20:4263a77256ae	5585	#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
bogdanm	20:4263a77256ae	5586	#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
bogdanm	20:4263a77256ae	5587	#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
bogdanm	20:4263a77256ae	5588	#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
bogdanm	20:4263a77256ae	5589	#define RTC_TSDR_MT ((uint32_t)0x00001000)
bogdanm	20:4263a77256ae	5590	#define RTC_TSDR_MU ((uint32_t)0x00000F00)
bogdanm	20:4263a77256ae	5591	#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
bogdanm	20:4263a77256ae	5592	#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
bogdanm	20:4263a77256ae	5593	#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
bogdanm	20:4263a77256ae	5594	#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
bogdanm	20:4263a77256ae	5595	#define RTC_TSDR_DT ((uint32_t)0x00000030)
bogdanm	20:4263a77256ae	5596	#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
bogdanm	20:4263a77256ae	5597	#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
bogdanm	20:4263a77256ae	5598	#define RTC_TSDR_DU ((uint32_t)0x0000000F)
bogdanm	20:4263a77256ae	5599	#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	5600	#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
bogdanm	20:4263a77256ae	5601	#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
bogdanm	20:4263a77256ae	5602	#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
bogdanm	20:4263a77256ae	5603
bogdanm	20:4263a77256ae	5604	/****************** Bits definition for RTC_TSSSR register **************/
bogdanm	20:4263a77256ae	5605	#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
bogdanm	20:4263a77256ae	5606
bogdanm	20:4263a77256ae	5607	/****************** Bits definition for RTC_CAL register ***************/
bogdanm	20:4263a77256ae	5608	#define RTC_CALR_CALP ((uint32_t)0x00008000)
bogdanm	20:4263a77256ae	5609	#define RTC_CALR_CALW8 ((uint32_t)0x00004000)
bogdanm	20:4263a77256ae	5610	#define RTC_CALR_CALW16 ((uint32_t)0x00002000)
bogdanm	20:4263a77256ae	5611	#define RTC_CALR_CALM ((uint32_t)0x000001FF)
bogdanm	20:4263a77256ae	5612	#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	5613	#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
bogdanm	20:4263a77256ae	5614	#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
bogdanm	20:4263a77256ae	5615	#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
bogdanm	20:4263a77256ae	5616	#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
bogdanm	20:4263a77256ae	5617	#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
bogdanm	20:4263a77256ae	5618	#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
bogdanm	20:4263a77256ae	5619	#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
bogdanm	20:4263a77256ae	5620	#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
bogdanm	20:4263a77256ae	5621
bogdanm	20:4263a77256ae	5622	/****************** Bits definition for RTC_TAFCR register **************/
bogdanm	20:4263a77256ae	5623	#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
bogdanm	20:4263a77256ae	5624	#define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000)
bogdanm	20:4263a77256ae	5625	#define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000)
bogdanm	20:4263a77256ae	5626	#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
bogdanm	20:4263a77256ae	5627	#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
bogdanm	20:4263a77256ae	5628	#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
bogdanm	20:4263a77256ae	5629	#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
bogdanm	20:4263a77256ae	5630	#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
bogdanm	20:4263a77256ae	5631	#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
bogdanm	20:4263a77256ae	5632	#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
bogdanm	20:4263a77256ae	5633	#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
bogdanm	20:4263a77256ae	5634	#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
bogdanm	20:4263a77256ae	5635	#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
bogdanm	20:4263a77256ae	5636	#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
bogdanm	20:4263a77256ae	5637	#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
bogdanm	20:4263a77256ae	5638	#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
bogdanm	20:4263a77256ae	5639	#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
bogdanm	20:4263a77256ae	5640	#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	5641
bogdanm	20:4263a77256ae	5642	/****************** Bits definition for RTC_ALRMASSR register ***********/
bogdanm	20:4263a77256ae	5643	#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
bogdanm	20:4263a77256ae	5644	#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
bogdanm	20:4263a77256ae	5645	#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
bogdanm	20:4263a77256ae	5646	#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
bogdanm	20:4263a77256ae	5647	#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
bogdanm	20:4263a77256ae	5648	#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
bogdanm	20:4263a77256ae	5649
bogdanm	20:4263a77256ae	5650	/****************** Bits definition for RTC_ALRMBSSR register ***********/
bogdanm	20:4263a77256ae	5651	#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
bogdanm	20:4263a77256ae	5652	#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
bogdanm	20:4263a77256ae	5653	#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
bogdanm	20:4263a77256ae	5654	#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
bogdanm	20:4263a77256ae	5655	#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
bogdanm	20:4263a77256ae	5656	#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
bogdanm	20:4263a77256ae	5657
bogdanm	20:4263a77256ae	5658	/****************** Bits definition for RTC_BKP0R register **************/
bogdanm	20:4263a77256ae	5659	#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
bogdanm	20:4263a77256ae	5660
bogdanm	20:4263a77256ae	5661	/****************** Bits definition for RTC_BKP1R register **************/
bogdanm	20:4263a77256ae	5662	#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
bogdanm	20:4263a77256ae	5663
bogdanm	20:4263a77256ae	5664	/****************** Bits definition for RTC_BKP2R register **************/
bogdanm	20:4263a77256ae	5665	#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
bogdanm	20:4263a77256ae	5666
bogdanm	20:4263a77256ae	5667	/****************** Bits definition for RTC_BKP3R register **************/
bogdanm	20:4263a77256ae	5668	#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
bogdanm	20:4263a77256ae	5669
bogdanm	20:4263a77256ae	5670	/****************** Bits definition for RTC_BKP4R register **************/
bogdanm	20:4263a77256ae	5671	#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
bogdanm	20:4263a77256ae	5672
bogdanm	20:4263a77256ae	5673	/****************** Bits definition for RTC_BKP5R register **************/
bogdanm	20:4263a77256ae	5674	#define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
bogdanm	20:4263a77256ae	5675
bogdanm	20:4263a77256ae	5676	/****************** Bits definition for RTC_BKP6R register **************/
bogdanm	20:4263a77256ae	5677	#define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
bogdanm	20:4263a77256ae	5678
bogdanm	20:4263a77256ae	5679	/****************** Bits definition for RTC_BKP7R register **************/
bogdanm	20:4263a77256ae	5680	#define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
bogdanm	20:4263a77256ae	5681
bogdanm	20:4263a77256ae	5682	/****************** Bits definition for RTC_BKP8R register **************/
bogdanm	20:4263a77256ae	5683	#define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
bogdanm	20:4263a77256ae	5684
bogdanm	20:4263a77256ae	5685	/****************** Bits definition for RTC_BKP9R register **************/
bogdanm	20:4263a77256ae	5686	#define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
bogdanm	20:4263a77256ae	5687
bogdanm	20:4263a77256ae	5688	/****************** Bits definition for RTC_BKP10R register *************/
bogdanm	20:4263a77256ae	5689	#define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
bogdanm	20:4263a77256ae	5690
bogdanm	20:4263a77256ae	5691	/****************** Bits definition for RTC_BKP11R register *************/
bogdanm	20:4263a77256ae	5692	#define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
bogdanm	20:4263a77256ae	5693
bogdanm	20:4263a77256ae	5694	/****************** Bits definition for RTC_BKP12R register *************/
bogdanm	20:4263a77256ae	5695	#define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
bogdanm	20:4263a77256ae	5696
bogdanm	20:4263a77256ae	5697	/****************** Bits definition for RTC_BKP13R register *************/
bogdanm	20:4263a77256ae	5698	#define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
bogdanm	20:4263a77256ae	5699
bogdanm	20:4263a77256ae	5700	/****************** Bits definition for RTC_BKP14R register *************/
bogdanm	20:4263a77256ae	5701	#define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
bogdanm	20:4263a77256ae	5702
bogdanm	20:4263a77256ae	5703	/****************** Bits definition for RTC_BKP15R register *************/
bogdanm	20:4263a77256ae	5704	#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
bogdanm	20:4263a77256ae	5705
bogdanm	20:4263a77256ae	5706	/****************** Bits definition for RTC_BKP16R register *************/
bogdanm	20:4263a77256ae	5707	#define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
bogdanm	20:4263a77256ae	5708
bogdanm	20:4263a77256ae	5709	/****************** Bits definition for RTC_BKP17R register *************/
bogdanm	20:4263a77256ae	5710	#define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
bogdanm	20:4263a77256ae	5711
bogdanm	20:4263a77256ae	5712	/****************** Bits definition for RTC_BKP18R register *************/
bogdanm	20:4263a77256ae	5713	#define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
bogdanm	20:4263a77256ae	5714
bogdanm	20:4263a77256ae	5715	/****************** Bits definition for RTC_BKP19R register *************/
bogdanm	20:4263a77256ae	5716	#define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
bogdanm	20:4263a77256ae	5717
bogdanm	20:4263a77256ae	5718
bogdanm	20:4263a77256ae	5719	/******************************************************************************/
bogdanm	20:4263a77256ae	5720	/* */
bogdanm	20:4263a77256ae	5721	/* SD host Interface */
bogdanm	20:4263a77256ae	5722	/* */
bogdanm	20:4263a77256ae	5723	/******************************************************************************/
bogdanm	20:4263a77256ae	5724	/**************** Bit definition for SDIO_POWER register ****************/
bogdanm	20:4263a77256ae	5725	#define SDIO_POWER_PWRCTRL ((uint8_t)0x03) /!<PWRCTRL[1:0] bits (Power supply control bits) /
bogdanm	20:4263a77256ae	5726	#define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) /!<Bit 0 /
bogdanm	20:4263a77256ae	5727	#define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) /!<Bit 1 /
bogdanm	20:4263a77256ae	5728
bogdanm	20:4263a77256ae	5729	/**************** Bit definition for SDIO_CLKCR register ****************/
bogdanm	20:4263a77256ae	5730	#define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) /!<Clock divide factor /
bogdanm	20:4263a77256ae	5731	#define SDIO_CLKCR_CLKEN ((uint16_t)0x0100) /!<Clock enable bit /
bogdanm	20:4263a77256ae	5732	#define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) /!<Power saving configuration bit /
bogdanm	20:4263a77256ae	5733	#define SDIO_CLKCR_BYPASS ((uint16_t)0x0400) /!<Clock divider bypass enable bit /
bogdanm	20:4263a77256ae	5734
bogdanm	20:4263a77256ae	5735	#define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) /!<WIDBUS[1:0] bits (Wide bus mode enable bit) /
bogdanm	20:4263a77256ae	5736	#define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) /!<Bit 0 /
bogdanm	20:4263a77256ae	5737	#define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) /!<Bit 1 /
bogdanm	20:4263a77256ae	5738
bogdanm	20:4263a77256ae	5739	#define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) /!<SDIO_CK dephasing selection bit /
bogdanm	20:4263a77256ae	5740	#define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) /!<HW Flow Control enable /
bogdanm	20:4263a77256ae	5741
bogdanm	20:4263a77256ae	5742	/***************** Bit definition for SDIO_ARG register *****************/
bogdanm	20:4263a77256ae	5743	#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /!<Command argument /
bogdanm	20:4263a77256ae	5744
bogdanm	20:4263a77256ae	5745	/***************** Bit definition for SDIO_CMD register *****************/
bogdanm	20:4263a77256ae	5746	#define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) /!<Command Index /
bogdanm	20:4263a77256ae	5747
bogdanm	20:4263a77256ae	5748	#define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) /!<WAITRESP[1:0] bits (Wait for response bits) /
bogdanm	20:4263a77256ae	5749	#define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) /!< Bit 0 /
bogdanm	20:4263a77256ae	5750	#define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) /!< Bit 1 /
bogdanm	20:4263a77256ae	5751
bogdanm	20:4263a77256ae	5752	#define SDIO_CMD_WAITINT ((uint16_t)0x0100) /!<CPSM Waits for Interrupt Request /
bogdanm	20:4263a77256ae	5753	#define SDIO_CMD_WAITPEND ((uint16_t)0x0200) /!<CPSM Waits for ends of data transfer (CmdPend internal signal) /
bogdanm	20:4263a77256ae	5754	#define SDIO_CMD_CPSMEN ((uint16_t)0x0400) /!<Command path state machine (CPSM) Enable bit /
bogdanm	20:4263a77256ae	5755	#define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) /!<SD I/O suspend command /
bogdanm	20:4263a77256ae	5756	#define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) /!<Enable CMD completion /
bogdanm	20:4263a77256ae	5757	#define SDIO_CMD_NIEN ((uint16_t)0x2000) /!<Not Interrupt Enable /
bogdanm	20:4263a77256ae	5758	#define SDIO_CMD_CEATACMD ((uint16_t)0x4000) /!<CE-ATA command /
bogdanm	20:4263a77256ae	5759
bogdanm	20:4263a77256ae	5760	/*************** Bit definition for SDIO_RESPCMD register ***************/
bogdanm	20:4263a77256ae	5761	#define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) /!<Response command index /
bogdanm	20:4263a77256ae	5762
bogdanm	20:4263a77256ae	5763	/**************** Bit definition for SDIO_RESP0 register ****************/
bogdanm	20:4263a77256ae	5764	#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /!<Card Status /
bogdanm	20:4263a77256ae	5765
bogdanm	20:4263a77256ae	5766	/**************** Bit definition for SDIO_RESP1 register ****************/
bogdanm	20:4263a77256ae	5767	#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /!<Card Status /
bogdanm	20:4263a77256ae	5768
bogdanm	20:4263a77256ae	5769	/**************** Bit definition for SDIO_RESP2 register ****************/
bogdanm	20:4263a77256ae	5770	#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /!<Card Status /
bogdanm	20:4263a77256ae	5771
bogdanm	20:4263a77256ae	5772	/**************** Bit definition for SDIO_RESP3 register ****************/
bogdanm	20:4263a77256ae	5773	#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /!<Card Status /
bogdanm	20:4263a77256ae	5774
bogdanm	20:4263a77256ae	5775	/**************** Bit definition for SDIO_RESP4 register ****************/
bogdanm	20:4263a77256ae	5776	#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /!<Card Status /
bogdanm	20:4263a77256ae	5777
bogdanm	20:4263a77256ae	5778	/**************** Bit definition for SDIO_DTIMER register ***************/
bogdanm	20:4263a77256ae	5779	#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /!<Data timeout period. /
bogdanm	20:4263a77256ae	5780
bogdanm	20:4263a77256ae	5781	/**************** Bit definition for SDIO_DLEN register *****************/
bogdanm	20:4263a77256ae	5782	#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /!<Data length value /
bogdanm	20:4263a77256ae	5783
bogdanm	20:4263a77256ae	5784	/**************** Bit definition for SDIO_DCTRL register ****************/
bogdanm	20:4263a77256ae	5785	#define SDIO_DCTRL_DTEN ((uint16_t)0x0001) /!<Data transfer enabled bit /
bogdanm	20:4263a77256ae	5786	#define SDIO_DCTRL_DTDIR ((uint16_t)0x0002) /!<Data transfer direction selection /
bogdanm	20:4263a77256ae	5787	#define SDIO_DCTRL_DTMODE ((uint16_t)0x0004) /!<Data transfer mode selection /
bogdanm	20:4263a77256ae	5788	#define SDIO_DCTRL_DMAEN ((uint16_t)0x0008) /!<DMA enabled bit /
bogdanm	20:4263a77256ae	5789
bogdanm	20:4263a77256ae	5790	#define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) /!<DBLOCKSIZE[3:0] bits (Data block size) /
bogdanm	20:4263a77256ae	5791	#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) /!<Bit 0 /
bogdanm	20:4263a77256ae	5792	#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) /!<Bit 1 /
bogdanm	20:4263a77256ae	5793	#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) /!<Bit 2 /
bogdanm	20:4263a77256ae	5794	#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) /!<Bit 3 /
bogdanm	20:4263a77256ae	5795
bogdanm	20:4263a77256ae	5796	#define SDIO_DCTRL_RWSTART ((uint16_t)0x0100) /!<Read wait start /
bogdanm	20:4263a77256ae	5797	#define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) /!<Read wait stop /
bogdanm	20:4263a77256ae	5798	#define SDIO_DCTRL_RWMOD ((uint16_t)0x0400) /!<Read wait mode /
bogdanm	20:4263a77256ae	5799	#define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) /!<SD I/O enable functions /
bogdanm	20:4263a77256ae	5800
bogdanm	20:4263a77256ae	5801	/**************** Bit definition for SDIO_DCOUNT register ***************/
bogdanm	20:4263a77256ae	5802	#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /!<Data count value /
bogdanm	20:4263a77256ae	5803
bogdanm	20:4263a77256ae	5804	/**************** Bit definition for SDIO_STA register ******************/
bogdanm	20:4263a77256ae	5805	#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /!<Command response received (CRC check failed) /
bogdanm	20:4263a77256ae	5806	#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /!<Data block sent/received (CRC check failed) /
bogdanm	20:4263a77256ae	5807	#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /!<Command response timeout /
bogdanm	20:4263a77256ae	5808	#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /!<Data timeout /
bogdanm	20:4263a77256ae	5809	#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /!<Transmit FIFO underrun error /
bogdanm	20:4263a77256ae	5810	#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /!<Received FIFO overrun error /
bogdanm	20:4263a77256ae	5811	#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /!<Command response received (CRC check passed) /
bogdanm	20:4263a77256ae	5812	#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /!<Command sent (no response required) /
bogdanm	20:4263a77256ae	5813	#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /!<Data end (data counter, SDIDCOUNT, is zero) /
bogdanm	20:4263a77256ae	5814	#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /!<Start bit not detected on all data signals in wide bus mode /
bogdanm	20:4263a77256ae	5815	#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /!<Data block sent/received (CRC check passed) /
bogdanm	20:4263a77256ae	5816	#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /!<Command transfer in progress /
bogdanm	20:4263a77256ae	5817	#define SDIO_STA_TXACT ((uint32_t)0x00001000) /!<Data transmit in progress /
bogdanm	20:4263a77256ae	5818	#define SDIO_STA_RXACT ((uint32_t)0x00002000) /!<Data receive in progress /
bogdanm	20:4263a77256ae	5819	#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO /
bogdanm	20:4263a77256ae	5820	#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /!<Receive FIFO Half Full: there are at least 8 words in the FIFO /
bogdanm	20:4263a77256ae	5821	#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /!<Transmit FIFO full /
bogdanm	20:4263a77256ae	5822	#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /!<Receive FIFO full /
bogdanm	20:4263a77256ae	5823	#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /!<Transmit FIFO empty /
bogdanm	20:4263a77256ae	5824	#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /!<Receive FIFO empty /
bogdanm	20:4263a77256ae	5825	#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /!<Data available in transmit FIFO /
bogdanm	20:4263a77256ae	5826	#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /!<Data available in receive FIFO /
bogdanm	20:4263a77256ae	5827	#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /!<SDIO interrupt received /
bogdanm	20:4263a77256ae	5828	#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /!<CE-ATA command completion signal received for CMD61 /
bogdanm	20:4263a77256ae	5829
bogdanm	20:4263a77256ae	5830	/***************** Bit definition for SDIO_ICR register *****************/
bogdanm	20:4263a77256ae	5831	#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /!<CCRCFAIL flag clear bit /
bogdanm	20:4263a77256ae	5832	#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /!<DCRCFAIL flag clear bit /
bogdanm	20:4263a77256ae	5833	#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /!<CTIMEOUT flag clear bit /
bogdanm	20:4263a77256ae	5834	#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /!<DTIMEOUT flag clear bit /
bogdanm	20:4263a77256ae	5835	#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /!<TXUNDERR flag clear bit /
bogdanm	20:4263a77256ae	5836	#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /!<RXOVERR flag clear bit /
bogdanm	20:4263a77256ae	5837	#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /!<CMDREND flag clear bit /
bogdanm	20:4263a77256ae	5838	#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /!<CMDSENT flag clear bit /
bogdanm	20:4263a77256ae	5839	#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /!<DATAEND flag clear bit /
bogdanm	20:4263a77256ae	5840	#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /!<STBITERR flag clear bit /
bogdanm	20:4263a77256ae	5841	#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /!<DBCKEND flag clear bit /
bogdanm	20:4263a77256ae	5842	#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /!<SDIOIT flag clear bit /
bogdanm	20:4263a77256ae	5843	#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /!<CEATAEND flag clear bit /
bogdanm	20:4263a77256ae	5844
bogdanm	20:4263a77256ae	5845	/**************** Bit definition for SDIO_MASK register *****************/
bogdanm	20:4263a77256ae	5846	#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /!<Command CRC Fail Interrupt Enable /
bogdanm	20:4263a77256ae	5847	#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /!<Data CRC Fail Interrupt Enable /
bogdanm	20:4263a77256ae	5848	#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /!<Command TimeOut Interrupt Enable /
bogdanm	20:4263a77256ae	5849	#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /!<Data TimeOut Interrupt Enable /
bogdanm	20:4263a77256ae	5850	#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /!<Tx FIFO UnderRun Error Interrupt Enable /
bogdanm	20:4263a77256ae	5851	#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /!<Rx FIFO OverRun Error Interrupt Enable /
bogdanm	20:4263a77256ae	5852	#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /!<Command Response Received Interrupt Enable /
bogdanm	20:4263a77256ae	5853	#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /!<Command Sent Interrupt Enable /
bogdanm	20:4263a77256ae	5854	#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /!<Data End Interrupt Enable /
bogdanm	20:4263a77256ae	5855	#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /!<Start Bit Error Interrupt Enable /
bogdanm	20:4263a77256ae	5856	#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /!<Data Block End Interrupt Enable /
bogdanm	20:4263a77256ae	5857	#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /!<CCommand Acting Interrupt Enable /
bogdanm	20:4263a77256ae	5858	#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /!<Data Transmit Acting Interrupt Enable /
bogdanm	20:4263a77256ae	5859	#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /!<Data receive acting interrupt enabled /
bogdanm	20:4263a77256ae	5860	#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /!<Tx FIFO Half Empty interrupt Enable /
bogdanm	20:4263a77256ae	5861	#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /!<Rx FIFO Half Full interrupt Enable /
bogdanm	20:4263a77256ae	5862	#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /!<Tx FIFO Full interrupt Enable /
bogdanm	20:4263a77256ae	5863	#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /!<Rx FIFO Full interrupt Enable /
bogdanm	20:4263a77256ae	5864	#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /!<Tx FIFO Empty interrupt Enable /
bogdanm	20:4263a77256ae	5865	#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /!<Rx FIFO Empty interrupt Enable /
bogdanm	20:4263a77256ae	5866	#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /!<Data available in Tx FIFO interrupt Enable /
bogdanm	20:4263a77256ae	5867	#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /!<Data available in Rx FIFO interrupt Enable /
bogdanm	20:4263a77256ae	5868	#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /!<SDIO Mode Interrupt Received interrupt Enable /
bogdanm	20:4263a77256ae	5869	#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /!<CE-ATA command completion signal received Interrupt Enable /
bogdanm	20:4263a77256ae	5870
bogdanm	20:4263a77256ae	5871	/*************** Bit definition for SDIO_FIFOCNT register ***************/
bogdanm	20:4263a77256ae	5872	#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /!<Remaining number of words to be written to or read from the FIFO /
bogdanm	20:4263a77256ae	5873
bogdanm	20:4263a77256ae	5874	/**************** Bit definition for SDIO_FIFO register *****************/
bogdanm	20:4263a77256ae	5875	#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /!<Receive and transmit FIFO data /
bogdanm	20:4263a77256ae	5876
bogdanm	20:4263a77256ae	5877	/******************************************************************************/
bogdanm	20:4263a77256ae	5878	/* */
bogdanm	20:4263a77256ae	5879	/* Serial Peripheral Interface */
bogdanm	20:4263a77256ae	5880	/* */
bogdanm	20:4263a77256ae	5881	/******************************************************************************/
bogdanm	20:4263a77256ae	5882	/***************** Bit definition for SPI_CR1 register ******************/
bogdanm	20:4263a77256ae	5883	#define SPI_CR1_CPHA ((uint16_t)0x0001) /!<Clock Phase /
bogdanm	20:4263a77256ae	5884	#define SPI_CR1_CPOL ((uint16_t)0x0002) /!<Clock Polarity /
bogdanm	20:4263a77256ae	5885	#define SPI_CR1_MSTR ((uint16_t)0x0004) /!<Master Selection /
bogdanm	20:4263a77256ae	5886
bogdanm	20:4263a77256ae	5887	#define SPI_CR1_BR ((uint16_t)0x0038) /!<BR[2:0] bits (Baud Rate Control) /
bogdanm	20:4263a77256ae	5888	#define SPI_CR1_BR_0 ((uint16_t)0x0008) /!<Bit 0 /
bogdanm	20:4263a77256ae	5889	#define SPI_CR1_BR_1 ((uint16_t)0x0010) /!<Bit 1 /
bogdanm	20:4263a77256ae	5890	#define SPI_CR1_BR_2 ((uint16_t)0x0020) /!<Bit 2 /
bogdanm	20:4263a77256ae	5891
bogdanm	20:4263a77256ae	5892	#define SPI_CR1_SPE ((uint16_t)0x0040) /!<SPI Enable /
bogdanm	20:4263a77256ae	5893	#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /!<Frame Format /
bogdanm	20:4263a77256ae	5894	#define SPI_CR1_SSI ((uint16_t)0x0100) /!<Internal slave select /
bogdanm	20:4263a77256ae	5895	#define SPI_CR1_SSM ((uint16_t)0x0200) /!<Software slave management /
bogdanm	20:4263a77256ae	5896	#define SPI_CR1_RXONLY ((uint16_t)0x0400) /!<Receive only /
bogdanm	20:4263a77256ae	5897	#define SPI_CR1_DFF ((uint16_t)0x0800) /!<Data Frame Format /
bogdanm	20:4263a77256ae	5898	#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /!<Transmit CRC next /
bogdanm	20:4263a77256ae	5899	#define SPI_CR1_CRCEN ((uint16_t)0x2000) /!<Hardware CRC calculation enable /
bogdanm	20:4263a77256ae	5900	#define SPI_CR1_BIDIOE ((uint16_t)0x4000) /!<Output enable in bidirectional mode /
bogdanm	20:4263a77256ae	5901	#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /!<Bidirectional data mode enable /
bogdanm	20:4263a77256ae	5902
bogdanm	20:4263a77256ae	5903	/***************** Bit definition for SPI_CR2 register ******************/
bogdanm	20:4263a77256ae	5904	#define SPI_CR2_RXDMAEN ((uint8_t)0x01) /!<Rx Buffer DMA Enable /
bogdanm	20:4263a77256ae	5905	#define SPI_CR2_TXDMAEN ((uint8_t)0x02) /!<Tx Buffer DMA Enable /
bogdanm	20:4263a77256ae	5906	#define SPI_CR2_SSOE ((uint8_t)0x04) /!<SS Output Enable /
bogdanm	20:4263a77256ae	5907	#define SPI_CR2_ERRIE ((uint8_t)0x20) /!<Error Interrupt Enable /
bogdanm	20:4263a77256ae	5908	#define SPI_CR2_RXNEIE ((uint8_t)0x40) /!<RX buffer Not Empty Interrupt Enable /
bogdanm	20:4263a77256ae	5909	#define SPI_CR2_TXEIE ((uint8_t)0x80) /!<Tx buffer Empty Interrupt Enable /
bogdanm	20:4263a77256ae	5910
bogdanm	20:4263a77256ae	5911	/****************** Bit definition for SPI_SR register ******************/
bogdanm	20:4263a77256ae	5912	#define SPI_SR_RXNE ((uint8_t)0x01) /!<Receive buffer Not Empty /
bogdanm	20:4263a77256ae	5913	#define SPI_SR_TXE ((uint8_t)0x02) /!<Transmit buffer Empty /
bogdanm	20:4263a77256ae	5914	#define SPI_SR_CHSIDE ((uint8_t)0x04) /!<Channel side /
bogdanm	20:4263a77256ae	5915	#define SPI_SR_UDR ((uint8_t)0x08) /!<Underrun flag /
bogdanm	20:4263a77256ae	5916	#define SPI_SR_CRCERR ((uint8_t)0x10) /!<CRC Error flag /
bogdanm	20:4263a77256ae	5917	#define SPI_SR_MODF ((uint8_t)0x20) /!<Mode fault /
bogdanm	20:4263a77256ae	5918	#define SPI_SR_OVR ((uint8_t)0x40) /!<Overrun flag /
bogdanm	20:4263a77256ae	5919	#define SPI_SR_BSY ((uint8_t)0x80) /!<Busy flag /
bogdanm	20:4263a77256ae	5920
bogdanm	20:4263a77256ae	5921	/****************** Bit definition for SPI_DR register ******************/
bogdanm	20:4263a77256ae	5922	#define SPI_DR_DR ((uint16_t)0xFFFF) /!<Data Register /
bogdanm	20:4263a77256ae	5923
bogdanm	20:4263a77256ae	5924	/***************** Bit definition for SPI_CRCPR register ****************/
bogdanm	20:4263a77256ae	5925	#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /!<CRC polynomial register /
bogdanm	20:4263a77256ae	5926
bogdanm	20:4263a77256ae	5927	/**************** Bit definition for SPI_RXCRCR register ****************/
bogdanm	20:4263a77256ae	5928	#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /!<Rx CRC Register /
bogdanm	20:4263a77256ae	5929
bogdanm	20:4263a77256ae	5930	/**************** Bit definition for SPI_TXCRCR register ****************/
bogdanm	20:4263a77256ae	5931	#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /!<Tx CRC Register /
bogdanm	20:4263a77256ae	5932
bogdanm	20:4263a77256ae	5933	/**************** Bit definition for SPI_I2SCFGR register ***************/
bogdanm	20:4263a77256ae	5934	#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /!<Channel length (number of bits per audio channel) /
bogdanm	20:4263a77256ae	5935
bogdanm	20:4263a77256ae	5936	#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /!<DATLEN[1:0] bits (Data length to be transferred) /
bogdanm	20:4263a77256ae	5937	#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /!<Bit 0 /
bogdanm	20:4263a77256ae	5938	#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /!<Bit 1 /
bogdanm	20:4263a77256ae	5939
bogdanm	20:4263a77256ae	5940	#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /!<steady state clock polarity /
bogdanm	20:4263a77256ae	5941
bogdanm	20:4263a77256ae	5942	#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /!<I2SSTD[1:0] bits (I2S standard selection) /
bogdanm	20:4263a77256ae	5943	#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /!<Bit 0 /
bogdanm	20:4263a77256ae	5944	#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /!<Bit 1 /
bogdanm	20:4263a77256ae	5945
bogdanm	20:4263a77256ae	5946	#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /!<PCM frame synchronization /
bogdanm	20:4263a77256ae	5947
bogdanm	20:4263a77256ae	5948	#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /!<I2SCFG[1:0] bits (I2S configuration mode) /
bogdanm	20:4263a77256ae	5949	#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /!<Bit 0 /
bogdanm	20:4263a77256ae	5950	#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /!<Bit 1 /
bogdanm	20:4263a77256ae	5951
bogdanm	20:4263a77256ae	5952	#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /!<I2S Enable /
bogdanm	20:4263a77256ae	5953	#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /!<I2S mode selection /
bogdanm	20:4263a77256ae	5954
bogdanm	20:4263a77256ae	5955	/**************** Bit definition for SPI_I2SPR register *****************/
bogdanm	20:4263a77256ae	5956	#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /!<I2S Linear prescaler /
bogdanm	20:4263a77256ae	5957	#define SPI_I2SPR_ODD ((uint16_t)0x0100) /!<Odd factor for the prescaler /
bogdanm	20:4263a77256ae	5958	#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /!<Master Clock Output Enable /
bogdanm	20:4263a77256ae	5959
bogdanm	20:4263a77256ae	5960	/******************************************************************************/
bogdanm	20:4263a77256ae	5961	/* */
bogdanm	20:4263a77256ae	5962	/* SYSCFG */
bogdanm	20:4263a77256ae	5963	/* */
bogdanm	20:4263a77256ae	5964	/******************************************************************************/
bogdanm	20:4263a77256ae	5965	/**************** Bit definition for SYSCFG_MEMRMP register *************/
bogdanm	20:4263a77256ae	5966	#define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000007) /!< SYSCFG_Memory Remap Config /
bogdanm	20:4263a77256ae	5967	#define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	5968	#define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002)
bogdanm	20:4263a77256ae	5969	#define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004)
bogdanm	20:4263a77256ae	5970
bogdanm	20:4263a77256ae	5971	#define SYSCFG_MEMRMP_UFB_MODE ((uint32_t)0x00000100) /!< User Flash Bank mode /
bogdanm	20:4263a77256ae	5972
bogdanm	20:4263a77256ae	5973	/**************** Bit definition for SYSCFG_PMC register ****************/
bogdanm	20:4263a77256ae	5974	#define SYSCFG_PMC_MII_RMII_SEL ((uint32_t)0x00800000) /!<Ethernet PHY interface selection /
bogdanm	20:4263a77256ae	5975	/* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
bogdanm	20:4263a77256ae	5976	#define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
bogdanm	20:4263a77256ae	5977
bogdanm	20:4263a77256ae	5978	/*************** Bit definition for SYSCFG_EXTICR1 register *************/
bogdanm	20:4263a77256ae	5979	#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /!<EXTI 0 configuration /
bogdanm	20:4263a77256ae	5980	#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /!<EXTI 1 configuration /
bogdanm	20:4263a77256ae	5981	#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /!<EXTI 2 configuration /
bogdanm	20:4263a77256ae	5982	#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /!<EXTI 3 configuration /
bogdanm	20:4263a77256ae	5983	/**
bogdanm	20:4263a77256ae	5984	* @brief EXTI0 configuration
bogdanm	20:4263a77256ae	5985	*/
bogdanm	20:4263a77256ae	5986	#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /!<PA[0] pin /
bogdanm	20:4263a77256ae	5987	#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /!<PB[0] pin /
bogdanm	20:4263a77256ae	5988	#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /!<PC[0] pin /
bogdanm	20:4263a77256ae	5989	#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /!<PD[0] pin /
bogdanm	20:4263a77256ae	5990	#define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /!<PE[0] pin /
bogdanm	20:4263a77256ae	5991	#define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /!<PF[0] pin /
bogdanm	20:4263a77256ae	5992	#define SYSCFG_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /!<PG[0] pin /
bogdanm	20:4263a77256ae	5993	#define SYSCFG_EXTICR1_EXTI0_PH ((uint16_t)0x0007) /!<PH[0] pin /
bogdanm	20:4263a77256ae	5994	#define SYSCFG_EXTICR1_EXTI0_PI ((uint16_t)0x0008) /!<PI[0] pin /
bogdanm	20:4263a77256ae	5995
bogdanm	20:4263a77256ae	5996	/**
bogdanm	20:4263a77256ae	5997	* @brief EXTI1 configuration
bogdanm	20:4263a77256ae	5998	*/
bogdanm	20:4263a77256ae	5999	#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /!<PA[1] pin /
bogdanm	20:4263a77256ae	6000	#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /!<PB[1] pin /
bogdanm	20:4263a77256ae	6001	#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /!<PC[1] pin /
bogdanm	20:4263a77256ae	6002	#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /!<PD[1] pin /
bogdanm	20:4263a77256ae	6003	#define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /!<PE[1] pin /
bogdanm	20:4263a77256ae	6004	#define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /!<PF[1] pin /
bogdanm	20:4263a77256ae	6005	#define SYSCFG_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /!<PG[1] pin /
bogdanm	20:4263a77256ae	6006	#define SYSCFG_EXTICR1_EXTI1_PH ((uint16_t)0x0070) /!<PH[1] pin /
bogdanm	20:4263a77256ae	6007	#define SYSCFG_EXTICR1_EXTI1_PI ((uint16_t)0x0080) /!<PI[1] pin /
bogdanm	20:4263a77256ae	6008
bogdanm	20:4263a77256ae	6009	/**
bogdanm	20:4263a77256ae	6010	* @brief EXTI2 configuration
bogdanm	20:4263a77256ae	6011	*/
bogdanm	20:4263a77256ae	6012	#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /!<PA[2] pin /
bogdanm	20:4263a77256ae	6013	#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /!<PB[2] pin /
bogdanm	20:4263a77256ae	6014	#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /!<PC[2] pin /
bogdanm	20:4263a77256ae	6015	#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /!<PD[2] pin /
bogdanm	20:4263a77256ae	6016	#define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /!<PE[2] pin /
bogdanm	20:4263a77256ae	6017	#define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /!<PF[2] pin /
bogdanm	20:4263a77256ae	6018	#define SYSCFG_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /!<PG[2] pin /
bogdanm	20:4263a77256ae	6019	#define SYSCFG_EXTICR1_EXTI2_PH ((uint16_t)0x0700) /!<PH[2] pin /
bogdanm	20:4263a77256ae	6020	#define SYSCFG_EXTICR1_EXTI2_PI ((uint16_t)0x0800) /!<PI[2] pin /
bogdanm	20:4263a77256ae	6021
bogdanm	20:4263a77256ae	6022	/**
bogdanm	20:4263a77256ae	6023	* @brief EXTI3 configuration
bogdanm	20:4263a77256ae	6024	*/
bogdanm	20:4263a77256ae	6025	#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /!<PA[3] pin /
bogdanm	20:4263a77256ae	6026	#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /!<PB[3] pin /
bogdanm	20:4263a77256ae	6027	#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /!<PC[3] pin /
bogdanm	20:4263a77256ae	6028	#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /!<PD[3] pin /
bogdanm	20:4263a77256ae	6029	#define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /!<PE[3] pin /
bogdanm	20:4263a77256ae	6030	#define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /!<PF[3] pin /
bogdanm	20:4263a77256ae	6031	#define SYSCFG_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /!<PG[3] pin /
bogdanm	20:4263a77256ae	6032	#define SYSCFG_EXTICR1_EXTI3_PH ((uint16_t)0x7000) /!<PH[3] pin /
bogdanm	20:4263a77256ae	6033	#define SYSCFG_EXTICR1_EXTI3_PI ((uint16_t)0x8000) /!<PI[3] pin /
bogdanm	20:4263a77256ae	6034
bogdanm	20:4263a77256ae	6035	/*************** Bit definition for SYSCFG_EXTICR2 register *************/
bogdanm	20:4263a77256ae	6036	#define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /!<EXTI 4 configuration /
bogdanm	20:4263a77256ae	6037	#define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /!<EXTI 5 configuration /
bogdanm	20:4263a77256ae	6038	#define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /!<EXTI 6 configuration /
bogdanm	20:4263a77256ae	6039	#define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /!<EXTI 7 configuration /
bogdanm	20:4263a77256ae	6040	/**
bogdanm	20:4263a77256ae	6041	* @brief EXTI4 configuration
bogdanm	20:4263a77256ae	6042	*/
bogdanm	20:4263a77256ae	6043	#define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /!<PA[4] pin /
bogdanm	20:4263a77256ae	6044	#define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /!<PB[4] pin /
bogdanm	20:4263a77256ae	6045	#define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /!<PC[4] pin /
bogdanm	20:4263a77256ae	6046	#define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /!<PD[4] pin /
bogdanm	20:4263a77256ae	6047	#define SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /!<PE[4] pin /
bogdanm	20:4263a77256ae	6048	#define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /!<PF[4] pin /
bogdanm	20:4263a77256ae	6049	#define SYSCFG_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /!<PG[4] pin /
bogdanm	20:4263a77256ae	6050	#define SYSCFG_EXTICR2_EXTI4_PH ((uint16_t)0x0007) /!<PH[4] pin /
bogdanm	20:4263a77256ae	6051	#define SYSCFG_EXTICR2_EXTI4_PI ((uint16_t)0x0008) /!<PI[4] pin /
bogdanm	20:4263a77256ae	6052
bogdanm	20:4263a77256ae	6053	/**
bogdanm	20:4263a77256ae	6054	* @brief EXTI5 configuration
bogdanm	20:4263a77256ae	6055	*/
bogdanm	20:4263a77256ae	6056	#define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /!<PA[5] pin /
bogdanm	20:4263a77256ae	6057	#define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /!<PB[5] pin /
bogdanm	20:4263a77256ae	6058	#define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /!<PC[5] pin /
bogdanm	20:4263a77256ae	6059	#define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /!<PD[5] pin /
bogdanm	20:4263a77256ae	6060	#define SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /!<PE[5] pin /
bogdanm	20:4263a77256ae	6061	#define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /!<PF[5] pin /
bogdanm	20:4263a77256ae	6062	#define SYSCFG_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /!<PG[5] pin /
bogdanm	20:4263a77256ae	6063	#define SYSCFG_EXTICR2_EXTI5_PH ((uint16_t)0x0070) /!<PH[5] pin /
bogdanm	20:4263a77256ae	6064	#define SYSCFG_EXTICR2_EXTI5_PI ((uint16_t)0x0080) /!<PI[5] pin /
bogdanm	20:4263a77256ae	6065
bogdanm	20:4263a77256ae	6066	/**
bogdanm	20:4263a77256ae	6067	* @brief EXTI6 configuration
bogdanm	20:4263a77256ae	6068	*/
bogdanm	20:4263a77256ae	6069	#define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /!<PA[6] pin /
bogdanm	20:4263a77256ae	6070	#define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /!<PB[6] pin /
bogdanm	20:4263a77256ae	6071	#define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /!<PC[6] pin /
bogdanm	20:4263a77256ae	6072	#define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /!<PD[6] pin /
bogdanm	20:4263a77256ae	6073	#define SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /!<PE[6] pin /
bogdanm	20:4263a77256ae	6074	#define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /!<PF[6] pin /
bogdanm	20:4263a77256ae	6075	#define SYSCFG_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /!<PG[6] pin /
bogdanm	20:4263a77256ae	6076	#define SYSCFG_EXTICR2_EXTI6_PH ((uint16_t)0x0700) /!<PH[6] pin /
bogdanm	20:4263a77256ae	6077	#define SYSCFG_EXTICR2_EXTI6_PI ((uint16_t)0x0800) /!<PI[6] pin /
bogdanm	20:4263a77256ae	6078
bogdanm	20:4263a77256ae	6079	/**
bogdanm	20:4263a77256ae	6080	* @brief EXTI7 configuration
bogdanm	20:4263a77256ae	6081	*/
bogdanm	20:4263a77256ae	6082	#define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /!<PA[7] pin /
bogdanm	20:4263a77256ae	6083	#define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /!<PB[7] pin /
bogdanm	20:4263a77256ae	6084	#define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /!<PC[7] pin /
bogdanm	20:4263a77256ae	6085	#define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /!<PD[7] pin /
bogdanm	20:4263a77256ae	6086	#define SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /!<PE[7] pin /
bogdanm	20:4263a77256ae	6087	#define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /!<PF[7] pin /
bogdanm	20:4263a77256ae	6088	#define SYSCFG_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /!<PG[7] pin /
bogdanm	20:4263a77256ae	6089	#define SYSCFG_EXTICR2_EXTI7_PH ((uint16_t)0x7000) /!<PH[7] pin /
bogdanm	20:4263a77256ae	6090	#define SYSCFG_EXTICR2_EXTI7_PI ((uint16_t)0x8000) /!<PI[7] pin /
bogdanm	20:4263a77256ae	6091
bogdanm	20:4263a77256ae	6092	/*************** Bit definition for SYSCFG_EXTICR3 register *************/
bogdanm	20:4263a77256ae	6093	#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /!<EXTI 8 configuration /
bogdanm	20:4263a77256ae	6094	#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /!<EXTI 9 configuration /
bogdanm	20:4263a77256ae	6095	#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /!<EXTI 10 configuration /
bogdanm	20:4263a77256ae	6096	#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /!<EXTI 11 configuration /
bogdanm	20:4263a77256ae	6097
bogdanm	20:4263a77256ae	6098	/**
bogdanm	20:4263a77256ae	6099	* @brief EXTI8 configuration
bogdanm	20:4263a77256ae	6100	*/
bogdanm	20:4263a77256ae	6101	#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /!<PA[8] pin /
bogdanm	20:4263a77256ae	6102	#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /!<PB[8] pin /
bogdanm	20:4263a77256ae	6103	#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /!<PC[8] pin /
bogdanm	20:4263a77256ae	6104	#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /!<PD[8] pin /
bogdanm	20:4263a77256ae	6105	#define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /!<PE[8] pin /
bogdanm	20:4263a77256ae	6106	#define SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /!<PF[8] pin /
bogdanm	20:4263a77256ae	6107	#define SYSCFG_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /!<PG[8] pin /
bogdanm	20:4263a77256ae	6108	#define SYSCFG_EXTICR3_EXTI8_PH ((uint16_t)0x0007) /!<PH[8] pin /
bogdanm	20:4263a77256ae	6109	#define SYSCFG_EXTICR3_EXTI8_PI ((uint16_t)0x0008) /!<PI[8] pin /
bogdanm	20:4263a77256ae	6110
bogdanm	20:4263a77256ae	6111	/**
bogdanm	20:4263a77256ae	6112	* @brief EXTI9 configuration
bogdanm	20:4263a77256ae	6113	*/
bogdanm	20:4263a77256ae	6114	#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /!<PA[9] pin /
bogdanm	20:4263a77256ae	6115	#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /!<PB[9] pin /
bogdanm	20:4263a77256ae	6116	#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /!<PC[9] pin /
bogdanm	20:4263a77256ae	6117	#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /!<PD[9] pin /
bogdanm	20:4263a77256ae	6118	#define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /!<PE[9] pin /
bogdanm	20:4263a77256ae	6119	#define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /!<PF[9] pin /
bogdanm	20:4263a77256ae	6120	#define SYSCFG_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /!<PG[9] pin /
bogdanm	20:4263a77256ae	6121	#define SYSCFG_EXTICR3_EXTI9_PH ((uint16_t)0x0070) /!<PH[9] pin /
bogdanm	20:4263a77256ae	6122	#define SYSCFG_EXTICR3_EXTI9_PI ((uint16_t)0x0080) /!<PI[9] pin /
bogdanm	20:4263a77256ae	6123
bogdanm	20:4263a77256ae	6124	/**
bogdanm	20:4263a77256ae	6125	* @brief EXTI10 configuration
bogdanm	20:4263a77256ae	6126	*/
bogdanm	20:4263a77256ae	6127	#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /!<PA[10] pin /
bogdanm	20:4263a77256ae	6128	#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /!<PB[10] pin /
bogdanm	20:4263a77256ae	6129	#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /!<PC[10] pin /
bogdanm	20:4263a77256ae	6130	#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /!<PD[10] pin /
bogdanm	20:4263a77256ae	6131	#define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /!<PE[10] pin /
bogdanm	20:4263a77256ae	6132	#define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /!<PF[10] pin /
bogdanm	20:4263a77256ae	6133	#define SYSCFG_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /!<PG[10] pin /
bogdanm	20:4263a77256ae	6134	#define SYSCFG_EXTICR3_EXTI10_PH ((uint16_t)0x0700) /!<PH[10] pin /
bogdanm	20:4263a77256ae	6135	#define SYSCFG_EXTICR3_EXTI10_PI ((uint16_t)0x0800) /!<PI[10] pin /
bogdanm	20:4263a77256ae	6136
bogdanm	20:4263a77256ae	6137	/**
bogdanm	20:4263a77256ae	6138	* @brief EXTI11 configuration
bogdanm	20:4263a77256ae	6139	*/
bogdanm	20:4263a77256ae	6140	#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /!<PA[11] pin /
bogdanm	20:4263a77256ae	6141	#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /!<PB[11] pin /
bogdanm	20:4263a77256ae	6142	#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /!<PC[11] pin /
bogdanm	20:4263a77256ae	6143	#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /!<PD[11] pin /
bogdanm	20:4263a77256ae	6144	#define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /!<PE[11] pin /
bogdanm	20:4263a77256ae	6145	#define SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /!<PF[11] pin /
bogdanm	20:4263a77256ae	6146	#define SYSCFG_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /!<PG[11] pin /
bogdanm	20:4263a77256ae	6147	#define SYSCFG_EXTICR3_EXTI11_PH ((uint16_t)0x7000) /!<PH[11] pin /
bogdanm	20:4263a77256ae	6148	#define SYSCFG_EXTICR3_EXTI11_PI ((uint16_t)0x8000) /!<PI[11] pin /
bogdanm	20:4263a77256ae	6149
bogdanm	20:4263a77256ae	6150	/*************** Bit definition for SYSCFG_EXTICR4 register *************/
bogdanm	20:4263a77256ae	6151	#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /!<EXTI 12 configuration /
bogdanm	20:4263a77256ae	6152	#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /!<EXTI 13 configuration /
bogdanm	20:4263a77256ae	6153	#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /!<EXTI 14 configuration /
bogdanm	20:4263a77256ae	6154	#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /!<EXTI 15 configuration /
bogdanm	20:4263a77256ae	6155	/**
bogdanm	20:4263a77256ae	6156	* @brief EXTI12 configuration
bogdanm	20:4263a77256ae	6157	*/
bogdanm	20:4263a77256ae	6158	#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /!<PA[12] pin /
bogdanm	20:4263a77256ae	6159	#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /!<PB[12] pin /
bogdanm	20:4263a77256ae	6160	#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /!<PC[12] pin /
bogdanm	20:4263a77256ae	6161	#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /!<PD[12] pin /
bogdanm	20:4263a77256ae	6162	#define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /!<PE[12] pin /
bogdanm	20:4263a77256ae	6163	#define SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /!<PF[12] pin /
bogdanm	20:4263a77256ae	6164	#define SYSCFG_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /!<PG[12] pin /
bogdanm	20:4263a77256ae	6165	#define SYSCFG_EXTICR4_EXTI12_PH ((uint16_t)0x0007) /!<PH[12] pin /
bogdanm	20:4263a77256ae	6166
bogdanm	20:4263a77256ae	6167	/**
bogdanm	20:4263a77256ae	6168	* @brief EXTI13 configuration
bogdanm	20:4263a77256ae	6169	*/
bogdanm	20:4263a77256ae	6170	#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /!<PA[13] pin /
bogdanm	20:4263a77256ae	6171	#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /!<PB[13] pin /
bogdanm	20:4263a77256ae	6172	#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /!<PC[13] pin /
bogdanm	20:4263a77256ae	6173	#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /!<PD[13] pin /
bogdanm	20:4263a77256ae	6174	#define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /!<PE[13] pin /
bogdanm	20:4263a77256ae	6175	#define SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /!<PF[13] pin /
bogdanm	20:4263a77256ae	6176	#define SYSCFG_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /!<PG[13] pin /
bogdanm	20:4263a77256ae	6177	#define SYSCFG_EXTICR4_EXTI13_PH ((uint16_t)0x0070) /!<PH[13] pin /
bogdanm	20:4263a77256ae	6178
bogdanm	20:4263a77256ae	6179	/**
bogdanm	20:4263a77256ae	6180	* @brief EXTI14 configuration
bogdanm	20:4263a77256ae	6181	*/
bogdanm	20:4263a77256ae	6182	#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /!<PA[14] pin /
bogdanm	20:4263a77256ae	6183	#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /!<PB[14] pin /
bogdanm	20:4263a77256ae	6184	#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /!<PC[14] pin /
bogdanm	20:4263a77256ae	6185	#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /!<PD[14] pin /
bogdanm	20:4263a77256ae	6186	#define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /!<PE[14] pin /
bogdanm	20:4263a77256ae	6187	#define SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /!<PF[14] pin /
bogdanm	20:4263a77256ae	6188	#define SYSCFG_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /!<PG[14] pin /
bogdanm	20:4263a77256ae	6189	#define SYSCFG_EXTICR4_EXTI14_PH ((uint16_t)0x0700) /!<PH[14] pin /
bogdanm	20:4263a77256ae	6190
bogdanm	20:4263a77256ae	6191	/**
bogdanm	20:4263a77256ae	6192	* @brief EXTI15 configuration
bogdanm	20:4263a77256ae	6193	*/
bogdanm	20:4263a77256ae	6194	#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /!<PA[15] pin /
bogdanm	20:4263a77256ae	6195	#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /!<PB[15] pin /
bogdanm	20:4263a77256ae	6196	#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /!<PC[15] pin /
bogdanm	20:4263a77256ae	6197	#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /!<PD[15] pin /
bogdanm	20:4263a77256ae	6198	#define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /!<PE[15] pin /
bogdanm	20:4263a77256ae	6199	#define SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /!<PF[15] pin /
bogdanm	20:4263a77256ae	6200	#define SYSCFG_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /!<PG[15] pin /
bogdanm	20:4263a77256ae	6201	#define SYSCFG_EXTICR4_EXTI15_PH ((uint16_t)0x7000) /!<PH[15] pin /
bogdanm	20:4263a77256ae	6202
bogdanm	20:4263a77256ae	6203	/**************** Bit definition for SYSCFG_CMPCR register **************/
bogdanm	20:4263a77256ae	6204	#define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /!<Compensation cell ready flag /
bogdanm	20:4263a77256ae	6205	#define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /!<Compensation cell power-down /
bogdanm	20:4263a77256ae	6206
bogdanm	20:4263a77256ae	6207	/******************************************************************************/
bogdanm	20:4263a77256ae	6208	/* */
bogdanm	20:4263a77256ae	6209	/* TIM */
bogdanm	20:4263a77256ae	6210	/* */
bogdanm	20:4263a77256ae	6211	/******************************************************************************/
bogdanm	20:4263a77256ae	6212	/***************** Bit definition for TIM_CR1 register ******************/
bogdanm	20:4263a77256ae	6213	#define TIM_CR1_CEN ((uint16_t)0x0001) /!<Counter enable /
bogdanm	20:4263a77256ae	6214	#define TIM_CR1_UDIS ((uint16_t)0x0002) /!<Update disable /
bogdanm	20:4263a77256ae	6215	#define TIM_CR1_URS ((uint16_t)0x0004) /!<Update request source /
bogdanm	20:4263a77256ae	6216	#define TIM_CR1_OPM ((uint16_t)0x0008) /!<One pulse mode /
bogdanm	20:4263a77256ae	6217	#define TIM_CR1_DIR ((uint16_t)0x0010) /!<Direction /
bogdanm	20:4263a77256ae	6218
bogdanm	20:4263a77256ae	6219	#define TIM_CR1_CMS ((uint16_t)0x0060) /!<CMS[1:0] bits (Center-aligned mode selection) /
bogdanm	20:4263a77256ae	6220	#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /!<Bit 0 /
bogdanm	20:4263a77256ae	6221	#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /!<Bit 1 /
bogdanm	20:4263a77256ae	6222
bogdanm	20:4263a77256ae	6223	#define TIM_CR1_ARPE ((uint16_t)0x0080) /!<Auto-reload preload enable /
bogdanm	20:4263a77256ae	6224
bogdanm	20:4263a77256ae	6225	#define TIM_CR1_CKD ((uint16_t)0x0300) /!<CKD[1:0] bits (clock division) /
bogdanm	20:4263a77256ae	6226	#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /!<Bit 0 /
bogdanm	20:4263a77256ae	6227	#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /!<Bit 1 /
bogdanm	20:4263a77256ae	6228
bogdanm	20:4263a77256ae	6229	/***************** Bit definition for TIM_CR2 register ******************/
bogdanm	20:4263a77256ae	6230	#define TIM_CR2_CCPC ((uint16_t)0x0001) /!<Capture/Compare Preloaded Control /
bogdanm	20:4263a77256ae	6231	#define TIM_CR2_CCUS ((uint16_t)0x0004) /!<Capture/Compare Control Update Selection /
bogdanm	20:4263a77256ae	6232	#define TIM_CR2_CCDS ((uint16_t)0x0008) /!<Capture/Compare DMA Selection /
bogdanm	20:4263a77256ae	6233
bogdanm	20:4263a77256ae	6234	#define TIM_CR2_MMS ((uint16_t)0x0070) /!<MMS[2:0] bits (Master Mode Selection) /
bogdanm	20:4263a77256ae	6235	#define TIM_CR2_MMS_0 ((uint16_t)0x0010) /!<Bit 0 /
bogdanm	20:4263a77256ae	6236	#define TIM_CR2_MMS_1 ((uint16_t)0x0020) /!<Bit 1 /
bogdanm	20:4263a77256ae	6237	#define TIM_CR2_MMS_2 ((uint16_t)0x0040) /!<Bit 2 /
bogdanm	20:4263a77256ae	6238
bogdanm	20:4263a77256ae	6239	#define TIM_CR2_TI1S ((uint16_t)0x0080) /!<TI1 Selection /
bogdanm	20:4263a77256ae	6240	#define TIM_CR2_OIS1 ((uint16_t)0x0100) /!<Output Idle state 1 (OC1 output) /
bogdanm	20:4263a77256ae	6241	#define TIM_CR2_OIS1N ((uint16_t)0x0200) /!<Output Idle state 1 (OC1N output) /
bogdanm	20:4263a77256ae	6242	#define TIM_CR2_OIS2 ((uint16_t)0x0400) /!<Output Idle state 2 (OC2 output) /
bogdanm	20:4263a77256ae	6243	#define TIM_CR2_OIS2N ((uint16_t)0x0800) /!<Output Idle state 2 (OC2N output) /
bogdanm	20:4263a77256ae	6244	#define TIM_CR2_OIS3 ((uint16_t)0x1000) /!<Output Idle state 3 (OC3 output) /
bogdanm	20:4263a77256ae	6245	#define TIM_CR2_OIS3N ((uint16_t)0x2000) /!<Output Idle state 3 (OC3N output) /
bogdanm	20:4263a77256ae	6246	#define TIM_CR2_OIS4 ((uint16_t)0x4000) /!<Output Idle state 4 (OC4 output) /
bogdanm	20:4263a77256ae	6247
bogdanm	20:4263a77256ae	6248	/***************** Bit definition for TIM_SMCR register *****************/
bogdanm	20:4263a77256ae	6249	#define TIM_SMCR_SMS ((uint16_t)0x0007) /!<SMS[2:0] bits (Slave mode selection) /
bogdanm	20:4263a77256ae	6250	#define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /!<Bit 0 /
bogdanm	20:4263a77256ae	6251	#define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /!<Bit 1 /
bogdanm	20:4263a77256ae	6252	#define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /!<Bit 2 /
bogdanm	20:4263a77256ae	6253
bogdanm	20:4263a77256ae	6254	#define TIM_SMCR_TS ((uint16_t)0x0070) /!<TS[2:0] bits (Trigger selection) /
bogdanm	20:4263a77256ae	6255	#define TIM_SMCR_TS_0 ((uint16_t)0x0010) /!<Bit 0 /
bogdanm	20:4263a77256ae	6256	#define TIM_SMCR_TS_1 ((uint16_t)0x0020) /!<Bit 1 /
bogdanm	20:4263a77256ae	6257	#define TIM_SMCR_TS_2 ((uint16_t)0x0040) /!<Bit 2 /
bogdanm	20:4263a77256ae	6258
bogdanm	20:4263a77256ae	6259	#define TIM_SMCR_MSM ((uint16_t)0x0080) /!<Master/slave mode /
bogdanm	20:4263a77256ae	6260
bogdanm	20:4263a77256ae	6261	#define TIM_SMCR_ETF ((uint16_t)0x0F00) /!<ETF[3:0] bits (External trigger filter) /
bogdanm	20:4263a77256ae	6262	#define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /!<Bit 0 /
bogdanm	20:4263a77256ae	6263	#define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /!<Bit 1 /
bogdanm	20:4263a77256ae	6264	#define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /!<Bit 2 /
bogdanm	20:4263a77256ae	6265	#define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /!<Bit 3 /
bogdanm	20:4263a77256ae	6266
bogdanm	20:4263a77256ae	6267	#define TIM_SMCR_ETPS ((uint16_t)0x3000) /!<ETPS[1:0] bits (External trigger prescaler) /
bogdanm	20:4263a77256ae	6268	#define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /!<Bit 0 /
bogdanm	20:4263a77256ae	6269	#define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /!<Bit 1 /
bogdanm	20:4263a77256ae	6270
bogdanm	20:4263a77256ae	6271	#define TIM_SMCR_ECE ((uint16_t)0x4000) /!<External clock enable /
bogdanm	20:4263a77256ae	6272	#define TIM_SMCR_ETP ((uint16_t)0x8000) /!<External trigger polarity /
bogdanm	20:4263a77256ae	6273
bogdanm	20:4263a77256ae	6274	/***************** Bit definition for TIM_DIER register *****************/
bogdanm	20:4263a77256ae	6275	#define TIM_DIER_UIE ((uint16_t)0x0001) /!<Update interrupt enable /
bogdanm	20:4263a77256ae	6276	#define TIM_DIER_CC1IE ((uint16_t)0x0002) /!<Capture/Compare 1 interrupt enable /
bogdanm	20:4263a77256ae	6277	#define TIM_DIER_CC2IE ((uint16_t)0x0004) /!<Capture/Compare 2 interrupt enable /
bogdanm	20:4263a77256ae	6278	#define TIM_DIER_CC3IE ((uint16_t)0x0008) /!<Capture/Compare 3 interrupt enable /
bogdanm	20:4263a77256ae	6279	#define TIM_DIER_CC4IE ((uint16_t)0x0010) /!<Capture/Compare 4 interrupt enable /
bogdanm	20:4263a77256ae	6280	#define TIM_DIER_COMIE ((uint16_t)0x0020) /!<COM interrupt enable /
bogdanm	20:4263a77256ae	6281	#define TIM_DIER_TIE ((uint16_t)0x0040) /!<Trigger interrupt enable /
bogdanm	20:4263a77256ae	6282	#define TIM_DIER_BIE ((uint16_t)0x0080) /!<Break interrupt enable /
bogdanm	20:4263a77256ae	6283	#define TIM_DIER_UDE ((uint16_t)0x0100) /!<Update DMA request enable /
bogdanm	20:4263a77256ae	6284	#define TIM_DIER_CC1DE ((uint16_t)0x0200) /!<Capture/Compare 1 DMA request enable /
bogdanm	20:4263a77256ae	6285	#define TIM_DIER_CC2DE ((uint16_t)0x0400) /!<Capture/Compare 2 DMA request enable /
bogdanm	20:4263a77256ae	6286	#define TIM_DIER_CC3DE ((uint16_t)0x0800) /!<Capture/Compare 3 DMA request enable /
bogdanm	20:4263a77256ae	6287	#define TIM_DIER_CC4DE ((uint16_t)0x1000) /!<Capture/Compare 4 DMA request enable /
bogdanm	20:4263a77256ae	6288	#define TIM_DIER_COMDE ((uint16_t)0x2000) /!<COM DMA request enable /
bogdanm	20:4263a77256ae	6289	#define TIM_DIER_TDE ((uint16_t)0x4000) /!<Trigger DMA request enable /
bogdanm	20:4263a77256ae	6290
bogdanm	20:4263a77256ae	6291	/****************** Bit definition for TIM_SR register ******************/
bogdanm	20:4263a77256ae	6292	#define TIM_SR_UIF ((uint16_t)0x0001) /!<Update interrupt Flag /
bogdanm	20:4263a77256ae	6293	#define TIM_SR_CC1IF ((uint16_t)0x0002) /!<Capture/Compare 1 interrupt Flag /
bogdanm	20:4263a77256ae	6294	#define TIM_SR_CC2IF ((uint16_t)0x0004) /!<Capture/Compare 2 interrupt Flag /
bogdanm	20:4263a77256ae	6295	#define TIM_SR_CC3IF ((uint16_t)0x0008) /!<Capture/Compare 3 interrupt Flag /
bogdanm	20:4263a77256ae	6296	#define TIM_SR_CC4IF ((uint16_t)0x0010) /!<Capture/Compare 4 interrupt Flag /
bogdanm	20:4263a77256ae	6297	#define TIM_SR_COMIF ((uint16_t)0x0020) /!<COM interrupt Flag /
bogdanm	20:4263a77256ae	6298	#define TIM_SR_TIF ((uint16_t)0x0040) /!<Trigger interrupt Flag /
bogdanm	20:4263a77256ae	6299	#define TIM_SR_BIF ((uint16_t)0x0080) /!<Break interrupt Flag /
bogdanm	20:4263a77256ae	6300	#define TIM_SR_CC1OF ((uint16_t)0x0200) /!<Capture/Compare 1 Overcapture Flag /
bogdanm	20:4263a77256ae	6301	#define TIM_SR_CC2OF ((uint16_t)0x0400) /!<Capture/Compare 2 Overcapture Flag /
bogdanm	20:4263a77256ae	6302	#define TIM_SR_CC3OF ((uint16_t)0x0800) /!<Capture/Compare 3 Overcapture Flag /
bogdanm	20:4263a77256ae	6303	#define TIM_SR_CC4OF ((uint16_t)0x1000) /!<Capture/Compare 4 Overcapture Flag /
bogdanm	20:4263a77256ae	6304
bogdanm	20:4263a77256ae	6305	/***************** Bit definition for TIM_EGR register ******************/
bogdanm	20:4263a77256ae	6306	#define TIM_EGR_UG ((uint8_t)0x01) /!<Update Generation /
bogdanm	20:4263a77256ae	6307	#define TIM_EGR_CC1G ((uint8_t)0x02) /!<Capture/Compare 1 Generation /
bogdanm	20:4263a77256ae	6308	#define TIM_EGR_CC2G ((uint8_t)0x04) /!<Capture/Compare 2 Generation /
bogdanm	20:4263a77256ae	6309	#define TIM_EGR_CC3G ((uint8_t)0x08) /!<Capture/Compare 3 Generation /
bogdanm	20:4263a77256ae	6310	#define TIM_EGR_CC4G ((uint8_t)0x10) /!<Capture/Compare 4 Generation /
bogdanm	20:4263a77256ae	6311	#define TIM_EGR_COMG ((uint8_t)0x20) /!<Capture/Compare Control Update Generation /
bogdanm	20:4263a77256ae	6312	#define TIM_EGR_TG ((uint8_t)0x40) /!<Trigger Generation /
bogdanm	20:4263a77256ae	6313	#define TIM_EGR_BG ((uint8_t)0x80) /!<Break Generation /
bogdanm	20:4263a77256ae	6314
bogdanm	20:4263a77256ae	6315	/**************** Bit definition for TIM_CCMR1 register *****************/
bogdanm	20:4263a77256ae	6316	#define TIM_CCMR1_CC1S ((uint16_t)0x0003) /!<CC1S[1:0] bits (Capture/Compare 1 Selection) /
bogdanm	20:4263a77256ae	6317	#define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /!<Bit 0 /
bogdanm	20:4263a77256ae	6318	#define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /!<Bit 1 /
bogdanm	20:4263a77256ae	6319
bogdanm	20:4263a77256ae	6320	#define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /!<Output Compare 1 Fast enable /
bogdanm	20:4263a77256ae	6321	#define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /!<Output Compare 1 Preload enable /
bogdanm	20:4263a77256ae	6322
bogdanm	20:4263a77256ae	6323	#define TIM_CCMR1_OC1M ((uint16_t)0x0070) /!<OC1M[2:0] bits (Output Compare 1 Mode) /
bogdanm	20:4263a77256ae	6324	#define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /!<Bit 0 /
bogdanm	20:4263a77256ae	6325	#define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /!<Bit 1 /
bogdanm	20:4263a77256ae	6326	#define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /!<Bit 2 /
bogdanm	20:4263a77256ae	6327
bogdanm	20:4263a77256ae	6328	#define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /!<Output Compare 1Clear Enable /
bogdanm	20:4263a77256ae	6329
bogdanm	20:4263a77256ae	6330	#define TIM_CCMR1_CC2S ((uint16_t)0x0300) /!<CC2S[1:0] bits (Capture/Compare 2 Selection) /
bogdanm	20:4263a77256ae	6331	#define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /!<Bit 0 /
bogdanm	20:4263a77256ae	6332	#define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /!<Bit 1 /
bogdanm	20:4263a77256ae	6333
bogdanm	20:4263a77256ae	6334	#define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /!<Output Compare 2 Fast enable /
bogdanm	20:4263a77256ae	6335	#define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /!<Output Compare 2 Preload enable /
bogdanm	20:4263a77256ae	6336
bogdanm	20:4263a77256ae	6337	#define TIM_CCMR1_OC2M ((uint16_t)0x7000) /!<OC2M[2:0] bits (Output Compare 2 Mode) /
bogdanm	20:4263a77256ae	6338	#define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /!<Bit 0 /
bogdanm	20:4263a77256ae	6339	#define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /!<Bit 1 /
bogdanm	20:4263a77256ae	6340	#define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /!<Bit 2 /
bogdanm	20:4263a77256ae	6341
bogdanm	20:4263a77256ae	6342	#define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /!<Output Compare 2 Clear Enable /
bogdanm	20:4263a77256ae	6343
bogdanm	20:4263a77256ae	6344	/----------------------------------------------------------------------------/
bogdanm	20:4263a77256ae	6345
bogdanm	20:4263a77256ae	6346	#define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) /
bogdanm	20:4263a77256ae	6347	#define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /!<Bit 0 /
bogdanm	20:4263a77256ae	6348	#define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /!<Bit 1 /
bogdanm	20:4263a77256ae	6349
bogdanm	20:4263a77256ae	6350	#define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /!<IC1F[3:0] bits (Input Capture 1 Filter) /
bogdanm	20:4263a77256ae	6351	#define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /!<Bit 0 /
bogdanm	20:4263a77256ae	6352	#define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /!<Bit 1 /
bogdanm	20:4263a77256ae	6353	#define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /!<Bit 2 /
bogdanm	20:4263a77256ae	6354	#define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /!<Bit 3 /
bogdanm	20:4263a77256ae	6355
bogdanm	20:4263a77256ae	6356	#define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) /
bogdanm	20:4263a77256ae	6357	#define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /!<Bit 0 /
bogdanm	20:4263a77256ae	6358	#define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /!<Bit 1 /
bogdanm	20:4263a77256ae	6359
bogdanm	20:4263a77256ae	6360	#define TIM_CCMR1_IC2F ((uint16_t)0xF000) /!<IC2F[3:0] bits (Input Capture 2 Filter) /
bogdanm	20:4263a77256ae	6361	#define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /!<Bit 0 /
bogdanm	20:4263a77256ae	6362	#define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /!<Bit 1 /
bogdanm	20:4263a77256ae	6363	#define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /!<Bit 2 /
bogdanm	20:4263a77256ae	6364	#define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /!<Bit 3 /
bogdanm	20:4263a77256ae	6365
bogdanm	20:4263a77256ae	6366	/**************** Bit definition for TIM_CCMR2 register *****************/
bogdanm	20:4263a77256ae	6367	#define TIM_CCMR2_CC3S ((uint16_t)0x0003) /!<CC3S[1:0] bits (Capture/Compare 3 Selection) /
bogdanm	20:4263a77256ae	6368	#define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /!<Bit 0 /
bogdanm	20:4263a77256ae	6369	#define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /!<Bit 1 /
bogdanm	20:4263a77256ae	6370
bogdanm	20:4263a77256ae	6371	#define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /!<Output Compare 3 Fast enable /
bogdanm	20:4263a77256ae	6372	#define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /!<Output Compare 3 Preload enable /
bogdanm	20:4263a77256ae	6373
bogdanm	20:4263a77256ae	6374	#define TIM_CCMR2_OC3M ((uint16_t)0x0070) /!<OC3M[2:0] bits (Output Compare 3 Mode) /
bogdanm	20:4263a77256ae	6375	#define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /!<Bit 0 /
bogdanm	20:4263a77256ae	6376	#define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /!<Bit 1 /
bogdanm	20:4263a77256ae	6377	#define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /!<Bit 2 /
bogdanm	20:4263a77256ae	6378
bogdanm	20:4263a77256ae	6379	#define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /!<Output Compare 3 Clear Enable /
bogdanm	20:4263a77256ae	6380
bogdanm	20:4263a77256ae	6381	#define TIM_CCMR2_CC4S ((uint16_t)0x0300) /!<CC4S[1:0] bits (Capture/Compare 4 Selection) /
bogdanm	20:4263a77256ae	6382	#define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /!<Bit 0 /
bogdanm	20:4263a77256ae	6383	#define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /!<Bit 1 /
bogdanm	20:4263a77256ae	6384
bogdanm	20:4263a77256ae	6385	#define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /!<Output Compare 4 Fast enable /
bogdanm	20:4263a77256ae	6386	#define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /!<Output Compare 4 Preload enable /
bogdanm	20:4263a77256ae	6387
bogdanm	20:4263a77256ae	6388	#define TIM_CCMR2_OC4M ((uint16_t)0x7000) /!<OC4M[2:0] bits (Output Compare 4 Mode) /
bogdanm	20:4263a77256ae	6389	#define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /!<Bit 0 /
bogdanm	20:4263a77256ae	6390	#define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /!<Bit 1 /
bogdanm	20:4263a77256ae	6391	#define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /!<Bit 2 /
bogdanm	20:4263a77256ae	6392
bogdanm	20:4263a77256ae	6393	#define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /!<Output Compare 4 Clear Enable /
bogdanm	20:4263a77256ae	6394
bogdanm	20:4263a77256ae	6395	/----------------------------------------------------------------------------/
bogdanm	20:4263a77256ae	6396
bogdanm	20:4263a77256ae	6397	#define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) /
bogdanm	20:4263a77256ae	6398	#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /!<Bit 0 /
bogdanm	20:4263a77256ae	6399	#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /!<Bit 1 /
bogdanm	20:4263a77256ae	6400
bogdanm	20:4263a77256ae	6401	#define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /!<IC3F[3:0] bits (Input Capture 3 Filter) /
bogdanm	20:4263a77256ae	6402	#define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /!<Bit 0 /
bogdanm	20:4263a77256ae	6403	#define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /!<Bit 1 /
bogdanm	20:4263a77256ae	6404	#define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /!<Bit 2 /
bogdanm	20:4263a77256ae	6405	#define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /!<Bit 3 /
bogdanm	20:4263a77256ae	6406
bogdanm	20:4263a77256ae	6407	#define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) /
bogdanm	20:4263a77256ae	6408	#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /!<Bit 0 /
bogdanm	20:4263a77256ae	6409	#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /!<Bit 1 /
bogdanm	20:4263a77256ae	6410
bogdanm	20:4263a77256ae	6411	#define TIM_CCMR2_IC4F ((uint16_t)0xF000) /!<IC4F[3:0] bits (Input Capture 4 Filter) /
bogdanm	20:4263a77256ae	6412	#define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /!<Bit 0 /
bogdanm	20:4263a77256ae	6413	#define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /!<Bit 1 /
bogdanm	20:4263a77256ae	6414	#define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /!<Bit 2 /
bogdanm	20:4263a77256ae	6415	#define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /!<Bit 3 /
bogdanm	20:4263a77256ae	6416
bogdanm	20:4263a77256ae	6417	/***************** Bit definition for TIM_CCER register *****************/
bogdanm	20:4263a77256ae	6418	#define TIM_CCER_CC1E ((uint16_t)0x0001) /!<Capture/Compare 1 output enable /
bogdanm	20:4263a77256ae	6419	#define TIM_CCER_CC1P ((uint16_t)0x0002) /!<Capture/Compare 1 output Polarity /
bogdanm	20:4263a77256ae	6420	#define TIM_CCER_CC1NE ((uint16_t)0x0004) /!<Capture/Compare 1 Complementary output enable /
bogdanm	20:4263a77256ae	6421	#define TIM_CCER_CC1NP ((uint16_t)0x0008) /!<Capture/Compare 1 Complementary output Polarity /
bogdanm	20:4263a77256ae	6422	#define TIM_CCER_CC2E ((uint16_t)0x0010) /!<Capture/Compare 2 output enable /
bogdanm	20:4263a77256ae	6423	#define TIM_CCER_CC2P ((uint16_t)0x0020) /!<Capture/Compare 2 output Polarity /
bogdanm	20:4263a77256ae	6424	#define TIM_CCER_CC2NE ((uint16_t)0x0040) /!<Capture/Compare 2 Complementary output enable /
bogdanm	20:4263a77256ae	6425	#define TIM_CCER_CC2NP ((uint16_t)0x0080) /!<Capture/Compare 2 Complementary output Polarity /
bogdanm	20:4263a77256ae	6426	#define TIM_CCER_CC3E ((uint16_t)0x0100) /!<Capture/Compare 3 output enable /
bogdanm	20:4263a77256ae	6427	#define TIM_CCER_CC3P ((uint16_t)0x0200) /!<Capture/Compare 3 output Polarity /
bogdanm	20:4263a77256ae	6428	#define TIM_CCER_CC3NE ((uint16_t)0x0400) /!<Capture/Compare 3 Complementary output enable /
bogdanm	20:4263a77256ae	6429	#define TIM_CCER_CC3NP ((uint16_t)0x0800) /!<Capture/Compare 3 Complementary output Polarity /
bogdanm	20:4263a77256ae	6430	#define TIM_CCER_CC4E ((uint16_t)0x1000) /!<Capture/Compare 4 output enable /
bogdanm	20:4263a77256ae	6431	#define TIM_CCER_CC4P ((uint16_t)0x2000) /!<Capture/Compare 4 output Polarity /
bogdanm	20:4263a77256ae	6432	#define TIM_CCER_CC4NP ((uint16_t)0x8000) /!<Capture/Compare 4 Complementary output Polarity /
bogdanm	20:4263a77256ae	6433
bogdanm	20:4263a77256ae	6434	/***************** Bit definition for TIM_CNT register ******************/
bogdanm	20:4263a77256ae	6435	#define TIM_CNT_CNT ((uint16_t)0xFFFF) /!<Counter Value /
bogdanm	20:4263a77256ae	6436
bogdanm	20:4263a77256ae	6437	/***************** Bit definition for TIM_PSC register ******************/
bogdanm	20:4263a77256ae	6438	#define TIM_PSC_PSC ((uint16_t)0xFFFF) /!<Prescaler Value /
bogdanm	20:4263a77256ae	6439
bogdanm	20:4263a77256ae	6440	/***************** Bit definition for TIM_ARR register ******************/
bogdanm	20:4263a77256ae	6441	#define TIM_ARR_ARR ((uint16_t)0xFFFF) /!<actual auto-reload Value /
bogdanm	20:4263a77256ae	6442
bogdanm	20:4263a77256ae	6443	/***************** Bit definition for TIM_RCR register ******************/
bogdanm	20:4263a77256ae	6444	#define TIM_RCR_REP ((uint8_t)0xFF) /!<Repetition Counter Value /
bogdanm	20:4263a77256ae	6445
bogdanm	20:4263a77256ae	6446	/***************** Bit definition for TIM_CCR1 register *****************/
bogdanm	20:4263a77256ae	6447	#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /!<Capture/Compare 1 Value /
bogdanm	20:4263a77256ae	6448
bogdanm	20:4263a77256ae	6449	/***************** Bit definition for TIM_CCR2 register *****************/
bogdanm	20:4263a77256ae	6450	#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /!<Capture/Compare 2 Value /
bogdanm	20:4263a77256ae	6451
bogdanm	20:4263a77256ae	6452	/***************** Bit definition for TIM_CCR3 register *****************/
bogdanm	20:4263a77256ae	6453	#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /!<Capture/Compare 3 Value /
bogdanm	20:4263a77256ae	6454
bogdanm	20:4263a77256ae	6455	/***************** Bit definition for TIM_CCR4 register *****************/
bogdanm	20:4263a77256ae	6456	#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /!<Capture/Compare 4 Value /
bogdanm	20:4263a77256ae	6457
bogdanm	20:4263a77256ae	6458	/***************** Bit definition for TIM_BDTR register *****************/
bogdanm	20:4263a77256ae	6459	#define TIM_BDTR_DTG ((uint16_t)0x00FF) /!<DTG[0:7] bits (Dead-Time Generator set-up) /
bogdanm	20:4263a77256ae	6460	#define TIM_BDTR_DTG_0 ((uint16_t)0x0001) /!<Bit 0 /
bogdanm	20:4263a77256ae	6461	#define TIM_BDTR_DTG_1 ((uint16_t)0x0002) /!<Bit 1 /
bogdanm	20:4263a77256ae	6462	#define TIM_BDTR_DTG_2 ((uint16_t)0x0004) /!<Bit 2 /
bogdanm	20:4263a77256ae	6463	#define TIM_BDTR_DTG_3 ((uint16_t)0x0008) /!<Bit 3 /
bogdanm	20:4263a77256ae	6464	#define TIM_BDTR_DTG_4 ((uint16_t)0x0010) /!<Bit 4 /
bogdanm	20:4263a77256ae	6465	#define TIM_BDTR_DTG_5 ((uint16_t)0x0020) /!<Bit 5 /
bogdanm	20:4263a77256ae	6466	#define TIM_BDTR_DTG_6 ((uint16_t)0x0040) /!<Bit 6 /
bogdanm	20:4263a77256ae	6467	#define TIM_BDTR_DTG_7 ((uint16_t)0x0080) /!<Bit 7 /
bogdanm	20:4263a77256ae	6468
bogdanm	20:4263a77256ae	6469	#define TIM_BDTR_LOCK ((uint16_t)0x0300) /!<LOCK[1:0] bits (Lock Configuration) /
bogdanm	20:4263a77256ae	6470	#define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) /!<Bit 0 /
bogdanm	20:4263a77256ae	6471	#define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) /!<Bit 1 /
bogdanm	20:4263a77256ae	6472
bogdanm	20:4263a77256ae	6473	#define TIM_BDTR_OSSI ((uint16_t)0x0400) /!<Off-State Selection for Idle mode /
bogdanm	20:4263a77256ae	6474	#define TIM_BDTR_OSSR ((uint16_t)0x0800) /!<Off-State Selection for Run mode /
bogdanm	20:4263a77256ae	6475	#define TIM_BDTR_BKE ((uint16_t)0x1000) /!<Break enable /
bogdanm	20:4263a77256ae	6476	#define TIM_BDTR_BKP ((uint16_t)0x2000) /!<Break Polarity /
bogdanm	20:4263a77256ae	6477	#define TIM_BDTR_AOE ((uint16_t)0x4000) /!<Automatic Output enable /
bogdanm	20:4263a77256ae	6478	#define TIM_BDTR_MOE ((uint16_t)0x8000) /!<Main Output enable /
bogdanm	20:4263a77256ae	6479
bogdanm	20:4263a77256ae	6480	/***************** Bit definition for TIM_DCR register ******************/
bogdanm	20:4263a77256ae	6481	#define TIM_DCR_DBA ((uint16_t)0x001F) /!<DBA[4:0] bits (DMA Base Address) /
bogdanm	20:4263a77256ae	6482	#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /!<Bit 0 /
bogdanm	20:4263a77256ae	6483	#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /!<Bit 1 /
bogdanm	20:4263a77256ae	6484	#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /!<Bit 2 /
bogdanm	20:4263a77256ae	6485	#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /!<Bit 3 /
bogdanm	20:4263a77256ae	6486	#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /!<Bit 4 /
bogdanm	20:4263a77256ae	6487
bogdanm	20:4263a77256ae	6488	#define TIM_DCR_DBL ((uint16_t)0x1F00) /!<DBL[4:0] bits (DMA Burst Length) /
bogdanm	20:4263a77256ae	6489	#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /!<Bit 0 /
bogdanm	20:4263a77256ae	6490	#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /!<Bit 1 /
bogdanm	20:4263a77256ae	6491	#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /!<Bit 2 /
bogdanm	20:4263a77256ae	6492	#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /!<Bit 3 /
bogdanm	20:4263a77256ae	6493	#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /!<Bit 4 /
bogdanm	20:4263a77256ae	6494
bogdanm	20:4263a77256ae	6495	/***************** Bit definition for TIM_DMAR register *****************/
bogdanm	20:4263a77256ae	6496	#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /!<DMA register for burst accesses /
bogdanm	20:4263a77256ae	6497
bogdanm	20:4263a77256ae	6498	/***************** Bit definition for TIM_OR register *******************/
bogdanm	20:4263a77256ae	6499	#define TIM_OR_TI4_RMP ((uint16_t)0x00C0) /!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) /
bogdanm	20:4263a77256ae	6500	#define TIM_OR_TI4_RMP_0 ((uint16_t)0x0040) /!<Bit 0 /
bogdanm	20:4263a77256ae	6501	#define TIM_OR_TI4_RMP_1 ((uint16_t)0x0080) /!<Bit 1 /
bogdanm	20:4263a77256ae	6502	#define TIM_OR_ITR1_RMP ((uint16_t)0x0C00) /!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) /
bogdanm	20:4263a77256ae	6503	#define TIM_OR_ITR1_RMP_0 ((uint16_t)0x0400) /!<Bit 0 /
bogdanm	20:4263a77256ae	6504	#define TIM_OR_ITR1_RMP_1 ((uint16_t)0x0800) /!<Bit 1 /
bogdanm	20:4263a77256ae	6505
bogdanm	20:4263a77256ae	6506
bogdanm	20:4263a77256ae	6507	/******************************************************************************/
bogdanm	20:4263a77256ae	6508	/* */
bogdanm	20:4263a77256ae	6509	/* Universal Synchronous Asynchronous Receiver Transmitter */
bogdanm	20:4263a77256ae	6510	/* */
bogdanm	20:4263a77256ae	6511	/******************************************************************************/
bogdanm	20:4263a77256ae	6512	/***************** Bit definition for USART_SR register *****************/
bogdanm	20:4263a77256ae	6513	#define USART_SR_PE ((uint16_t)0x0001) /!<Parity Error /
bogdanm	20:4263a77256ae	6514	#define USART_SR_FE ((uint16_t)0x0002) /!<Framing Error /
bogdanm	20:4263a77256ae	6515	#define USART_SR_NE ((uint16_t)0x0004) /!<Noise Error Flag /
bogdanm	20:4263a77256ae	6516	#define USART_SR_ORE ((uint16_t)0x0008) /!<OverRun Error /
bogdanm	20:4263a77256ae	6517	#define USART_SR_IDLE ((uint16_t)0x0010) /!<IDLE line detected /
bogdanm	20:4263a77256ae	6518	#define USART_SR_RXNE ((uint16_t)0x0020) /!<Read Data Register Not Empty /
bogdanm	20:4263a77256ae	6519	#define USART_SR_TC ((uint16_t)0x0040) /!<Transmission Complete /
bogdanm	20:4263a77256ae	6520	#define USART_SR_TXE ((uint16_t)0x0080) /!<Transmit Data Register Empty /
bogdanm	20:4263a77256ae	6521	#define USART_SR_LBD ((uint16_t)0x0100) /!<LIN Break Detection Flag /
bogdanm	20:4263a77256ae	6522	#define USART_SR_CTS ((uint16_t)0x0200) /!<CTS Flag /
bogdanm	20:4263a77256ae	6523
bogdanm	20:4263a77256ae	6524	/***************** Bit definition for USART_DR register *****************/
bogdanm	20:4263a77256ae	6525	#define USART_DR_DR ((uint16_t)0x01FF) /!<Data value /
bogdanm	20:4263a77256ae	6526
bogdanm	20:4263a77256ae	6527	/**************** Bit definition for USART_BRR register *****************/
bogdanm	20:4263a77256ae	6528	#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /!<Fraction of USARTDIV /
bogdanm	20:4263a77256ae	6529	#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /!<Mantissa of USARTDIV /
bogdanm	20:4263a77256ae	6530
bogdanm	20:4263a77256ae	6531	/**************** Bit definition for USART_CR1 register *****************/
bogdanm	20:4263a77256ae	6532	#define USART_CR1_SBK ((uint16_t)0x0001) /!<Send Break /
bogdanm	20:4263a77256ae	6533	#define USART_CR1_RWU ((uint16_t)0x0002) /!<Receiver wakeup /
bogdanm	20:4263a77256ae	6534	#define USART_CR1_RE ((uint16_t)0x0004) /!<Receiver Enable /
bogdanm	20:4263a77256ae	6535	#define USART_CR1_TE ((uint16_t)0x0008) /!<Transmitter Enable /
bogdanm	20:4263a77256ae	6536	#define USART_CR1_IDLEIE ((uint16_t)0x0010) /!<IDLE Interrupt Enable /
bogdanm	20:4263a77256ae	6537	#define USART_CR1_RXNEIE ((uint16_t)0x0020) /!<RXNE Interrupt Enable /
bogdanm	20:4263a77256ae	6538	#define USART_CR1_TCIE ((uint16_t)0x0040) /!<Transmission Complete Interrupt Enable /
bogdanm	20:4263a77256ae	6539	#define USART_CR1_TXEIE ((uint16_t)0x0080) /!<PE Interrupt Enable /
bogdanm	20:4263a77256ae	6540	#define USART_CR1_PEIE ((uint16_t)0x0100) /!<PE Interrupt Enable /
bogdanm	20:4263a77256ae	6541	#define USART_CR1_PS ((uint16_t)0x0200) /!<Parity Selection /
bogdanm	20:4263a77256ae	6542	#define USART_CR1_PCE ((uint16_t)0x0400) /!<Parity Control Enable /
bogdanm	20:4263a77256ae	6543	#define USART_CR1_WAKE ((uint16_t)0x0800) /!<Wakeup method /
bogdanm	20:4263a77256ae	6544	#define USART_CR1_M ((uint16_t)0x1000) /!<Word length /
bogdanm	20:4263a77256ae	6545	#define USART_CR1_UE ((uint16_t)0x2000) /!<USART Enable /
bogdanm	20:4263a77256ae	6546	#define USART_CR1_OVER8 ((uint16_t)0x8000) /!<USART Oversampling by 8 enable /
bogdanm	20:4263a77256ae	6547
bogdanm	20:4263a77256ae	6548	/**************** Bit definition for USART_CR2 register *****************/
bogdanm	20:4263a77256ae	6549	#define USART_CR2_ADD ((uint16_t)0x000F) /!<Address of the USART node /
bogdanm	20:4263a77256ae	6550	#define USART_CR2_LBDL ((uint16_t)0x0020) /!<LIN Break Detection Length /
bogdanm	20:4263a77256ae	6551	#define USART_CR2_LBDIE ((uint16_t)0x0040) /!<LIN Break Detection Interrupt Enable /
bogdanm	20:4263a77256ae	6552	#define USART_CR2_LBCL ((uint16_t)0x0100) /!<Last Bit Clock pulse /
bogdanm	20:4263a77256ae	6553	#define USART_CR2_CPHA ((uint16_t)0x0200) /!<Clock Phase /
bogdanm	20:4263a77256ae	6554	#define USART_CR2_CPOL ((uint16_t)0x0400) /!<Clock Polarity /
bogdanm	20:4263a77256ae	6555	#define USART_CR2_CLKEN ((uint16_t)0x0800) /!<Clock Enable /
bogdanm	20:4263a77256ae	6556
bogdanm	20:4263a77256ae	6557	#define USART_CR2_STOP ((uint16_t)0x3000) /!<STOP[1:0] bits (STOP bits) /
bogdanm	20:4263a77256ae	6558	#define USART_CR2_STOP_0 ((uint16_t)0x1000) /!<Bit 0 /
bogdanm	20:4263a77256ae	6559	#define USART_CR2_STOP_1 ((uint16_t)0x2000) /!<Bit 1 /
bogdanm	20:4263a77256ae	6560
bogdanm	20:4263a77256ae	6561	#define USART_CR2_LINEN ((uint16_t)0x4000) /!<LIN mode enable /
bogdanm	20:4263a77256ae	6562
bogdanm	20:4263a77256ae	6563	/**************** Bit definition for USART_CR3 register *****************/
bogdanm	20:4263a77256ae	6564	#define USART_CR3_EIE ((uint16_t)0x0001) /!<Error Interrupt Enable /
bogdanm	20:4263a77256ae	6565	#define USART_CR3_IREN ((uint16_t)0x0002) /!<IrDA mode Enable /
bogdanm	20:4263a77256ae	6566	#define USART_CR3_IRLP ((uint16_t)0x0004) /!<IrDA Low-Power /
bogdanm	20:4263a77256ae	6567	#define USART_CR3_HDSEL ((uint16_t)0x0008) /!<Half-Duplex Selection /
bogdanm	20:4263a77256ae	6568	#define USART_CR3_NACK ((uint16_t)0x0010) /!<Smartcard NACK enable /
bogdanm	20:4263a77256ae	6569	#define USART_CR3_SCEN ((uint16_t)0x0020) /!<Smartcard mode enable /
bogdanm	20:4263a77256ae	6570	#define USART_CR3_DMAR ((uint16_t)0x0040) /!<DMA Enable Receiver /
bogdanm	20:4263a77256ae	6571	#define USART_CR3_DMAT ((uint16_t)0x0080) /!<DMA Enable Transmitter /
bogdanm	20:4263a77256ae	6572	#define USART_CR3_RTSE ((uint16_t)0x0100) /!<RTS Enable /
bogdanm	20:4263a77256ae	6573	#define USART_CR3_CTSE ((uint16_t)0x0200) /!<CTS Enable /
bogdanm	20:4263a77256ae	6574	#define USART_CR3_CTSIE ((uint16_t)0x0400) /!<CTS Interrupt Enable /
bogdanm	20:4263a77256ae	6575	#define USART_CR3_ONEBIT ((uint16_t)0x0800) /!<USART One bit method enable /
bogdanm	20:4263a77256ae	6576
bogdanm	20:4263a77256ae	6577	/**************** Bit definition for USART_GTPR register ****************/
bogdanm	20:4263a77256ae	6578	#define USART_GTPR_PSC ((uint16_t)0x00FF) /!<PSC[7:0] bits (Prescaler value) /
bogdanm	20:4263a77256ae	6579	#define USART_GTPR_PSC_0 ((uint16_t)0x0001) /!<Bit 0 /
bogdanm	20:4263a77256ae	6580	#define USART_GTPR_PSC_1 ((uint16_t)0x0002) /!<Bit 1 /
bogdanm	20:4263a77256ae	6581	#define USART_GTPR_PSC_2 ((uint16_t)0x0004) /!<Bit 2 /
bogdanm	20:4263a77256ae	6582	#define USART_GTPR_PSC_3 ((uint16_t)0x0008) /!<Bit 3 /
bogdanm	20:4263a77256ae	6583	#define USART_GTPR_PSC_4 ((uint16_t)0x0010) /!<Bit 4 /
bogdanm	20:4263a77256ae	6584	#define USART_GTPR_PSC_5 ((uint16_t)0x0020) /!<Bit 5 /
bogdanm	20:4263a77256ae	6585	#define USART_GTPR_PSC_6 ((uint16_t)0x0040) /!<Bit 6 /
bogdanm	20:4263a77256ae	6586	#define USART_GTPR_PSC_7 ((uint16_t)0x0080) /!<Bit 7 /
bogdanm	20:4263a77256ae	6587
bogdanm	20:4263a77256ae	6588	#define USART_GTPR_GT ((uint16_t)0xFF00) /!<Guard time value /
bogdanm	20:4263a77256ae	6589
bogdanm	20:4263a77256ae	6590	/******************************************************************************/
bogdanm	20:4263a77256ae	6591	/* */
bogdanm	20:4263a77256ae	6592	/* Window WATCHDOG */
bogdanm	20:4263a77256ae	6593	/* */
bogdanm	20:4263a77256ae	6594	/******************************************************************************/
bogdanm	20:4263a77256ae	6595	/***************** Bit definition for WWDG_CR register ******************/
bogdanm	20:4263a77256ae	6596	#define WWDG_CR_T ((uint8_t)0x7F) /!<T[6:0] bits (7-Bit counter (MSB to LSB)) /
bogdanm	20:4263a77256ae	6597	#define WWDG_CR_T0 ((uint8_t)0x01) /!<Bit 0 /
bogdanm	20:4263a77256ae	6598	#define WWDG_CR_T1 ((uint8_t)0x02) /!<Bit 1 /
bogdanm	20:4263a77256ae	6599	#define WWDG_CR_T2 ((uint8_t)0x04) /!<Bit 2 /
bogdanm	20:4263a77256ae	6600	#define WWDG_CR_T3 ((uint8_t)0x08) /!<Bit 3 /
bogdanm	20:4263a77256ae	6601	#define WWDG_CR_T4 ((uint8_t)0x10) /!<Bit 4 /
bogdanm	20:4263a77256ae	6602	#define WWDG_CR_T5 ((uint8_t)0x20) /!<Bit 5 /
bogdanm	20:4263a77256ae	6603	#define WWDG_CR_T6 ((uint8_t)0x40) /!<Bit 6 /
bogdanm	20:4263a77256ae	6604
bogdanm	20:4263a77256ae	6605	#define WWDG_CR_WDGA ((uint8_t)0x80) /!<Activation bit /
bogdanm	20:4263a77256ae	6606
bogdanm	20:4263a77256ae	6607	/***************** Bit definition for WWDG_CFR register *****************/
bogdanm	20:4263a77256ae	6608	#define WWDG_CFR_W ((uint16_t)0x007F) /!<W[6:0] bits (7-bit window value) /
bogdanm	20:4263a77256ae	6609	#define WWDG_CFR_W0 ((uint16_t)0x0001) /!<Bit 0 /
bogdanm	20:4263a77256ae	6610	#define WWDG_CFR_W1 ((uint16_t)0x0002) /!<Bit 1 /
bogdanm	20:4263a77256ae	6611	#define WWDG_CFR_W2 ((uint16_t)0x0004) /!<Bit 2 /
bogdanm	20:4263a77256ae	6612	#define WWDG_CFR_W3 ((uint16_t)0x0008) /!<Bit 3 /
bogdanm	20:4263a77256ae	6613	#define WWDG_CFR_W4 ((uint16_t)0x0010) /!<Bit 4 /
bogdanm	20:4263a77256ae	6614	#define WWDG_CFR_W5 ((uint16_t)0x0020) /!<Bit 5 /
bogdanm	20:4263a77256ae	6615	#define WWDG_CFR_W6 ((uint16_t)0x0040) /!<Bit 6 /
bogdanm	20:4263a77256ae	6616
bogdanm	20:4263a77256ae	6617	#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /!<WDGTB[1:0] bits (Timer Base) /
bogdanm	20:4263a77256ae	6618	#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /!<Bit 0 /
bogdanm	20:4263a77256ae	6619	#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /!<Bit 1 /
bogdanm	20:4263a77256ae	6620
bogdanm	20:4263a77256ae	6621	#define WWDG_CFR_EWI ((uint16_t)0x0200) /!<Early Wakeup Interrupt /
bogdanm	20:4263a77256ae	6622
bogdanm	20:4263a77256ae	6623	/***************** Bit definition for WWDG_SR register ******************/
bogdanm	20:4263a77256ae	6624	#define WWDG_SR_EWIF ((uint8_t)0x01) /!<Early Wakeup Interrupt Flag /
bogdanm	20:4263a77256ae	6625
bogdanm	20:4263a77256ae	6626
bogdanm	20:4263a77256ae	6627	/******************************************************************************/
bogdanm	20:4263a77256ae	6628	/* */
bogdanm	20:4263a77256ae	6629	/* DBG */
bogdanm	20:4263a77256ae	6630	/* */
bogdanm	20:4263a77256ae	6631	/******************************************************************************/
bogdanm	20:4263a77256ae	6632	/****************** Bit definition for DBGMCU_IDCODE register ***********/
bogdanm	20:4263a77256ae	6633	#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
bogdanm	20:4263a77256ae	6634	#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
bogdanm	20:4263a77256ae	6635
bogdanm	20:4263a77256ae	6636	/****************** Bit definition for DBGMCU_CR register ***************/
bogdanm	20:4263a77256ae	6637	#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	6638	#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
bogdanm	20:4263a77256ae	6639	#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
bogdanm	20:4263a77256ae	6640	#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
bogdanm	20:4263a77256ae	6641
bogdanm	20:4263a77256ae	6642	#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
bogdanm	20:4263a77256ae	6643	#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/!<Bit 0 /
bogdanm	20:4263a77256ae	6644	#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/!<Bit 1 /
bogdanm	20:4263a77256ae	6645
bogdanm	20:4263a77256ae	6646	/****************** Bit definition for DBGMCU_APB1_FZ register **********/
bogdanm	20:4263a77256ae	6647	#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	6648	#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
bogdanm	20:4263a77256ae	6649	#define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
bogdanm	20:4263a77256ae	6650	#define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)
bogdanm	20:4263a77256ae	6651	#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
bogdanm	20:4263a77256ae	6652	#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
bogdanm	20:4263a77256ae	6653	#define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040)
bogdanm	20:4263a77256ae	6654	#define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080)
bogdanm	20:4263a77256ae	6655	#define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100)
bogdanm	20:4263a77256ae	6656	#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
bogdanm	20:4263a77256ae	6657	#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
bogdanm	20:4263a77256ae	6658	#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
bogdanm	20:4263a77256ae	6659	#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
bogdanm	20:4263a77256ae	6660	#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
bogdanm	20:4263a77256ae	6661	#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)
bogdanm	20:4263a77256ae	6662	#define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
bogdanm	20:4263a77256ae	6663	#define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)
bogdanm	20:4263a77256ae	6664	/* Old IWDGSTOP bit definition, maintained for legacy purpose */
bogdanm	20:4263a77256ae	6665	#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
bogdanm	20:4263a77256ae	6666
bogdanm	20:4263a77256ae	6667	/****************** Bit definition for DBGMCU_APB2_FZ register **********/
bogdanm	20:4263a77256ae	6668	#define DBGMCU_APB1_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
bogdanm	20:4263a77256ae	6669	#define DBGMCU_APB1_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
bogdanm	20:4263a77256ae	6670	#define DBGMCU_APB1_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)
bogdanm	20:4263a77256ae	6671	#define DBGMCU_APB1_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000)
bogdanm	20:4263a77256ae	6672	#define DBGMCU_APB1_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)
bogdanm	20:4263a77256ae	6673
bogdanm	20:4263a77256ae	6674	/******************************************************************************/
bogdanm	20:4263a77256ae	6675	/* */
bogdanm	20:4263a77256ae	6676	/* Ethernet MAC Registers bits definitions */
bogdanm	20:4263a77256ae	6677	/* */
bogdanm	20:4263a77256ae	6678	/******************************************************************************/
bogdanm	20:4263a77256ae	6679	/* Bit definition for Ethernet MAC Control Register register */
bogdanm	20:4263a77256ae	6680	#define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */
bogdanm	20:4263a77256ae	6681	#define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */
bogdanm	20:4263a77256ae	6682	#define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */
bogdanm	20:4263a77256ae	6683	#define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */
bogdanm	20:4263a77256ae	6684	#define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */
bogdanm	20:4263a77256ae	6685	#define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */
bogdanm	20:4263a77256ae	6686	#define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */
bogdanm	20:4263a77256ae	6687	#define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */
bogdanm	20:4263a77256ae	6688	#define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */
bogdanm	20:4263a77256ae	6689	#define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */
bogdanm	20:4263a77256ae	6690	#define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */
bogdanm	20:4263a77256ae	6691	#define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */
bogdanm	20:4263a77256ae	6692	#define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */
bogdanm	20:4263a77256ae	6693	#define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */
bogdanm	20:4263a77256ae	6694	#define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */
bogdanm	20:4263a77256ae	6695	#define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */
bogdanm	20:4263a77256ae	6696	#define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */
bogdanm	20:4263a77256ae	6697	#define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */
bogdanm	20:4263a77256ae	6698	#define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */
bogdanm	20:4263a77256ae	6699	#define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling
bogdanm	20:4263a77256ae	6700	a transmission attempt during retries after a collision: 0 =< r <2^k */
bogdanm	20:4263a77256ae	6701	#define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */
bogdanm	20:4263a77256ae	6702	#define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */
bogdanm	20:4263a77256ae	6703	#define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */
bogdanm	20:4263a77256ae	6704	#define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */
bogdanm	20:4263a77256ae	6705	#define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */
bogdanm	20:4263a77256ae	6706	#define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */
bogdanm	20:4263a77256ae	6707	#define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */
bogdanm	20:4263a77256ae	6708
bogdanm	20:4263a77256ae	6709	/* Bit definition for Ethernet MAC Frame Filter Register */
bogdanm	20:4263a77256ae	6710	#define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */
bogdanm	20:4263a77256ae	6711	#define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */
bogdanm	20:4263a77256ae	6712	#define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */
bogdanm	20:4263a77256ae	6713	#define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */
bogdanm	20:4263a77256ae	6714	#define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */
bogdanm	20:4263a77256ae	6715	#define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */
bogdanm	20:4263a77256ae	6716	#define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
bogdanm	20:4263a77256ae	6717	#define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
bogdanm	20:4263a77256ae	6718	#define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */
bogdanm	20:4263a77256ae	6719	#define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */
bogdanm	20:4263a77256ae	6720	#define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */
bogdanm	20:4263a77256ae	6721	#define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */
bogdanm	20:4263a77256ae	6722	#define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */
bogdanm	20:4263a77256ae	6723	#define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */
bogdanm	20:4263a77256ae	6724
bogdanm	20:4263a77256ae	6725	/* Bit definition for Ethernet MAC Hash Table High Register */
bogdanm	20:4263a77256ae	6726	#define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */
bogdanm	20:4263a77256ae	6727
bogdanm	20:4263a77256ae	6728	/* Bit definition for Ethernet MAC Hash Table Low Register */
bogdanm	20:4263a77256ae	6729	#define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */
bogdanm	20:4263a77256ae	6730
bogdanm	20:4263a77256ae	6731	/* Bit definition for Ethernet MAC MII Address Register */
bogdanm	20:4263a77256ae	6732	#define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */
bogdanm	20:4263a77256ae	6733	#define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */
bogdanm	20:4263a77256ae	6734	#define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */
bogdanm	20:4263a77256ae	6735	#define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
bogdanm	20:4263a77256ae	6736	#define ETH_MACMIIAR_CR_Div62 ((uint32_t)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
bogdanm	20:4263a77256ae	6737	#define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
bogdanm	20:4263a77256ae	6738	#define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
bogdanm	20:4263a77256ae	6739	#define ETH_MACMIIAR_CR_Div102 ((uint32_t)0x00000010) /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
bogdanm	20:4263a77256ae	6740	#define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */
bogdanm	20:4263a77256ae	6741	#define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */
bogdanm	20:4263a77256ae	6742
bogdanm	20:4263a77256ae	6743	/* Bit definition for Ethernet MAC MII Data Register */
bogdanm	20:4263a77256ae	6744	#define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */
bogdanm	20:4263a77256ae	6745
bogdanm	20:4263a77256ae	6746	/* Bit definition for Ethernet MAC Flow Control Register */
bogdanm	20:4263a77256ae	6747	#define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */
bogdanm	20:4263a77256ae	6748	#define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */
bogdanm	20:4263a77256ae	6749	#define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */
bogdanm	20:4263a77256ae	6750	#define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
bogdanm	20:4263a77256ae	6751	#define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */
bogdanm	20:4263a77256ae	6752	#define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */
bogdanm	20:4263a77256ae	6753	#define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */
bogdanm	20:4263a77256ae	6754	#define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */
bogdanm	20:4263a77256ae	6755	#define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */
bogdanm	20:4263a77256ae	6756	#define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */
bogdanm	20:4263a77256ae	6757	#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */
bogdanm	20:4263a77256ae	6758
bogdanm	20:4263a77256ae	6759	/* Bit definition for Ethernet MAC VLAN Tag Register */
bogdanm	20:4263a77256ae	6760	#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */
bogdanm	20:4263a77256ae	6761	#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */
bogdanm	20:4263a77256ae	6762
bogdanm	20:4263a77256ae	6763	/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
bogdanm	20:4263a77256ae	6764	#define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */
bogdanm	20:4263a77256ae	6765	/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
bogdanm	20:4263a77256ae	6766	Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
bogdanm	20:4263a77256ae	6767	/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
bogdanm	20:4263a77256ae	6768	Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
bogdanm	20:4263a77256ae	6769	Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
bogdanm	20:4263a77256ae	6770	Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
bogdanm	20:4263a77256ae	6771	Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
bogdanm	20:4263a77256ae	6772	RSVD - Filter1 Command - RSVD - Filter0 Command
bogdanm	20:4263a77256ae	6773	Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
bogdanm	20:4263a77256ae	6774	Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
bogdanm	20:4263a77256ae	6775	Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
bogdanm	20:4263a77256ae	6776
bogdanm	20:4263a77256ae	6777	/* Bit definition for Ethernet MAC PMT Control and Status Register */
bogdanm	20:4263a77256ae	6778	#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */
bogdanm	20:4263a77256ae	6779	#define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */
bogdanm	20:4263a77256ae	6780	#define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */
bogdanm	20:4263a77256ae	6781	#define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */
bogdanm	20:4263a77256ae	6782	#define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */
bogdanm	20:4263a77256ae	6783	#define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */
bogdanm	20:4263a77256ae	6784	#define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */
bogdanm	20:4263a77256ae	6785
bogdanm	20:4263a77256ae	6786	/* Bit definition for Ethernet MAC Status Register */
bogdanm	20:4263a77256ae	6787	#define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */
bogdanm	20:4263a77256ae	6788	#define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */
bogdanm	20:4263a77256ae	6789	#define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */
bogdanm	20:4263a77256ae	6790	#define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */
bogdanm	20:4263a77256ae	6791	#define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */
bogdanm	20:4263a77256ae	6792
bogdanm	20:4263a77256ae	6793	/* Bit definition for Ethernet MAC Interrupt Mask Register */
bogdanm	20:4263a77256ae	6794	#define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */
bogdanm	20:4263a77256ae	6795	#define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */
bogdanm	20:4263a77256ae	6796
bogdanm	20:4263a77256ae	6797	/* Bit definition for Ethernet MAC Address0 High Register */
bogdanm	20:4263a77256ae	6798	#define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */
bogdanm	20:4263a77256ae	6799
bogdanm	20:4263a77256ae	6800	/* Bit definition for Ethernet MAC Address0 Low Register */
bogdanm	20:4263a77256ae	6801	#define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */
bogdanm	20:4263a77256ae	6802
bogdanm	20:4263a77256ae	6803	/* Bit definition for Ethernet MAC Address1 High Register */
bogdanm	20:4263a77256ae	6804	#define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */
bogdanm	20:4263a77256ae	6805	#define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */
bogdanm	20:4263a77256ae	6806	#define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
bogdanm	20:4263a77256ae	6807	#define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
bogdanm	20:4263a77256ae	6808	#define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
bogdanm	20:4263a77256ae	6809	#define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
bogdanm	20:4263a77256ae	6810	#define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
bogdanm	20:4263a77256ae	6811	#define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
bogdanm	20:4263a77256ae	6812	#define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
bogdanm	20:4263a77256ae	6813	#define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */
bogdanm	20:4263a77256ae	6814
bogdanm	20:4263a77256ae	6815	/* Bit definition for Ethernet MAC Address1 Low Register */
bogdanm	20:4263a77256ae	6816	#define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */
bogdanm	20:4263a77256ae	6817
bogdanm	20:4263a77256ae	6818	/* Bit definition for Ethernet MAC Address2 High Register */
bogdanm	20:4263a77256ae	6819	#define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */
bogdanm	20:4263a77256ae	6820	#define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */
bogdanm	20:4263a77256ae	6821	#define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
bogdanm	20:4263a77256ae	6822	#define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
bogdanm	20:4263a77256ae	6823	#define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
bogdanm	20:4263a77256ae	6824	#define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
bogdanm	20:4263a77256ae	6825	#define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
bogdanm	20:4263a77256ae	6826	#define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
bogdanm	20:4263a77256ae	6827	#define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
bogdanm	20:4263a77256ae	6828	#define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */
bogdanm	20:4263a77256ae	6829
bogdanm	20:4263a77256ae	6830	/* Bit definition for Ethernet MAC Address2 Low Register */
bogdanm	20:4263a77256ae	6831	#define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */
bogdanm	20:4263a77256ae	6832
bogdanm	20:4263a77256ae	6833	/* Bit definition for Ethernet MAC Address3 High Register */
bogdanm	20:4263a77256ae	6834	#define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */
bogdanm	20:4263a77256ae	6835	#define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */
bogdanm	20:4263a77256ae	6836	#define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
bogdanm	20:4263a77256ae	6837	#define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
bogdanm	20:4263a77256ae	6838	#define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
bogdanm	20:4263a77256ae	6839	#define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
bogdanm	20:4263a77256ae	6840	#define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
bogdanm	20:4263a77256ae	6841	#define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
bogdanm	20:4263a77256ae	6842	#define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
bogdanm	20:4263a77256ae	6843	#define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */
bogdanm	20:4263a77256ae	6844
bogdanm	20:4263a77256ae	6845	/* Bit definition for Ethernet MAC Address3 Low Register */
bogdanm	20:4263a77256ae	6846	#define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */
bogdanm	20:4263a77256ae	6847
bogdanm	20:4263a77256ae	6848	/******************************************************************************/
bogdanm	20:4263a77256ae	6849	/* Ethernet MMC Registers bits definition */
bogdanm	20:4263a77256ae	6850	/******************************************************************************/
bogdanm	20:4263a77256ae	6851
bogdanm	20:4263a77256ae	6852	/* Bit definition for Ethernet MMC Contol Register */
bogdanm	20:4263a77256ae	6853	#define ETH_MMCCR_MCFHP ((uint32_t)0x00000020) /* MMC counter Full-Half preset */
bogdanm	20:4263a77256ae	6854	#define ETH_MMCCR_MCP ((uint32_t)0x00000010) /* MMC counter preset */
bogdanm	20:4263a77256ae	6855	#define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */
bogdanm	20:4263a77256ae	6856	#define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */
bogdanm	20:4263a77256ae	6857	#define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */
bogdanm	20:4263a77256ae	6858	#define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */
bogdanm	20:4263a77256ae	6859
bogdanm	20:4263a77256ae	6860	/* Bit definition for Ethernet MMC Receive Interrupt Register */
bogdanm	20:4263a77256ae	6861	#define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */
bogdanm	20:4263a77256ae	6862	#define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */
bogdanm	20:4263a77256ae	6863	#define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */
bogdanm	20:4263a77256ae	6864
bogdanm	20:4263a77256ae	6865	/* Bit definition for Ethernet MMC Transmit Interrupt Register */
bogdanm	20:4263a77256ae	6866	#define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */
bogdanm	20:4263a77256ae	6867	#define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */
bogdanm	20:4263a77256ae	6868	#define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */
bogdanm	20:4263a77256ae	6869
bogdanm	20:4263a77256ae	6870	/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
bogdanm	20:4263a77256ae	6871	#define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
bogdanm	20:4263a77256ae	6872	#define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
bogdanm	20:4263a77256ae	6873	#define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
bogdanm	20:4263a77256ae	6874
bogdanm	20:4263a77256ae	6875	/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
bogdanm	20:4263a77256ae	6876	#define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
bogdanm	20:4263a77256ae	6877	#define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
bogdanm	20:4263a77256ae	6878	#define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
bogdanm	20:4263a77256ae	6879
bogdanm	20:4263a77256ae	6880	/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
bogdanm	20:4263a77256ae	6881	#define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
bogdanm	20:4263a77256ae	6882
bogdanm	20:4263a77256ae	6883	/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
bogdanm	20:4263a77256ae	6884	#define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
bogdanm	20:4263a77256ae	6885
bogdanm	20:4263a77256ae	6886	/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
bogdanm	20:4263a77256ae	6887	#define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */
bogdanm	20:4263a77256ae	6888
bogdanm	20:4263a77256ae	6889	/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
bogdanm	20:4263a77256ae	6890	#define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */
bogdanm	20:4263a77256ae	6891
bogdanm	20:4263a77256ae	6892	/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
bogdanm	20:4263a77256ae	6893	#define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */
bogdanm	20:4263a77256ae	6894
bogdanm	20:4263a77256ae	6895	/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
bogdanm	20:4263a77256ae	6896	#define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */
bogdanm	20:4263a77256ae	6897
bogdanm	20:4263a77256ae	6898	/******************************************************************************/
bogdanm	20:4263a77256ae	6899	/* Ethernet PTP Registers bits definition */
bogdanm	20:4263a77256ae	6900	/******************************************************************************/
bogdanm	20:4263a77256ae	6901
bogdanm	20:4263a77256ae	6902	/* Bit definition for Ethernet PTP Time Stamp Contol Register */
bogdanm	20:4263a77256ae	6903	#define ETH_PTPTSCR_TSCNT ((uint32_t)0x00030000) /* Time stamp clock node type */
bogdanm	20:4263a77256ae	6904	#define ETH_PTPTSSR_TSSMRME ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */
bogdanm	20:4263a77256ae	6905	#define ETH_PTPTSSR_TSSEME ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */
bogdanm	20:4263a77256ae	6906	#define ETH_PTPTSSR_TSSIPV4FE ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */
bogdanm	20:4263a77256ae	6907	#define ETH_PTPTSSR_TSSIPV6FE ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */
bogdanm	20:4263a77256ae	6908	#define ETH_PTPTSSR_TSSPTPOEFE ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */
bogdanm	20:4263a77256ae	6909	#define ETH_PTPTSSR_TSPTPPSV2E ((uint32_t)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */
bogdanm	20:4263a77256ae	6910	#define ETH_PTPTSSR_TSSSR ((uint32_t)0x00000200) /* Time stamp Sub-seconds rollover */
bogdanm	20:4263a77256ae	6911	#define ETH_PTPTSSR_TSSARFE ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */
bogdanm	20:4263a77256ae	6912
bogdanm	20:4263a77256ae	6913	#define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */
bogdanm	20:4263a77256ae	6914	#define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */
bogdanm	20:4263a77256ae	6915	#define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */
bogdanm	20:4263a77256ae	6916	#define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */
bogdanm	20:4263a77256ae	6917	#define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */
bogdanm	20:4263a77256ae	6918	#define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */
bogdanm	20:4263a77256ae	6919
bogdanm	20:4263a77256ae	6920	/* Bit definition for Ethernet PTP Sub-Second Increment Register */
bogdanm	20:4263a77256ae	6921	#define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */
bogdanm	20:4263a77256ae	6922
bogdanm	20:4263a77256ae	6923	/* Bit definition for Ethernet PTP Time Stamp High Register */
bogdanm	20:4263a77256ae	6924	#define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */
bogdanm	20:4263a77256ae	6925
bogdanm	20:4263a77256ae	6926	/* Bit definition for Ethernet PTP Time Stamp Low Register */
bogdanm	20:4263a77256ae	6927	#define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */
bogdanm	20:4263a77256ae	6928	#define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */
bogdanm	20:4263a77256ae	6929
bogdanm	20:4263a77256ae	6930	/* Bit definition for Ethernet PTP Time Stamp High Update Register */
bogdanm	20:4263a77256ae	6931	#define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */
bogdanm	20:4263a77256ae	6932
bogdanm	20:4263a77256ae	6933	/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
bogdanm	20:4263a77256ae	6934	#define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */
bogdanm	20:4263a77256ae	6935	#define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */
bogdanm	20:4263a77256ae	6936
bogdanm	20:4263a77256ae	6937	/* Bit definition for Ethernet PTP Time Stamp Addend Register */
bogdanm	20:4263a77256ae	6938	#define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */
bogdanm	20:4263a77256ae	6939
bogdanm	20:4263a77256ae	6940	/* Bit definition for Ethernet PTP Target Time High Register */
bogdanm	20:4263a77256ae	6941	#define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */
bogdanm	20:4263a77256ae	6942
bogdanm	20:4263a77256ae	6943	/* Bit definition for Ethernet PTP Target Time Low Register */
bogdanm	20:4263a77256ae	6944	#define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */
bogdanm	20:4263a77256ae	6945
bogdanm	20:4263a77256ae	6946	/* Bit definition for Ethernet PTP Time Stamp Status Register */
bogdanm	20:4263a77256ae	6947	#define ETH_PTPTSSR_TSTTR ((uint32_t)0x00000020) /* Time stamp target time reached */
bogdanm	20:4263a77256ae	6948	#define ETH_PTPTSSR_TSSO ((uint32_t)0x00000010) /* Time stamp seconds overflow */
bogdanm	20:4263a77256ae	6949
bogdanm	20:4263a77256ae	6950	/******************************************************************************/
bogdanm	20:4263a77256ae	6951	/* Ethernet DMA Registers bits definition */
bogdanm	20:4263a77256ae	6952	/******************************************************************************/
bogdanm	20:4263a77256ae	6953
bogdanm	20:4263a77256ae	6954	/* Bit definition for Ethernet DMA Bus Mode Register */
bogdanm	20:4263a77256ae	6955	#define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */
bogdanm	20:4263a77256ae	6956	#define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */
bogdanm	20:4263a77256ae	6957	#define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */
bogdanm	20:4263a77256ae	6958	#define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */
bogdanm	20:4263a77256ae	6959	#define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
bogdanm	20:4263a77256ae	6960	#define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
bogdanm	20:4263a77256ae	6961	#define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
bogdanm	20:4263a77256ae	6962	#define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
bogdanm	20:4263a77256ae	6963	#define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
bogdanm	20:4263a77256ae	6964	#define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
bogdanm	20:4263a77256ae	6965	#define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
bogdanm	20:4263a77256ae	6966	#define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
bogdanm	20:4263a77256ae	6967	#define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
bogdanm	20:4263a77256ae	6968	#define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
bogdanm	20:4263a77256ae	6969	#define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
bogdanm	20:4263a77256ae	6970	#define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
bogdanm	20:4263a77256ae	6971	#define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */
bogdanm	20:4263a77256ae	6972	#define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
bogdanm	20:4263a77256ae	6973	#define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */
bogdanm	20:4263a77256ae	6974	#define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */
bogdanm	20:4263a77256ae	6975	#define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */
bogdanm	20:4263a77256ae	6976	#define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
bogdanm	20:4263a77256ae	6977	#define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */
bogdanm	20:4263a77256ae	6978	#define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
bogdanm	20:4263a77256ae	6979	#define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
bogdanm	20:4263a77256ae	6980	#define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
bogdanm	20:4263a77256ae	6981	#define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
bogdanm	20:4263a77256ae	6982	#define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
bogdanm	20:4263a77256ae	6983	#define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
bogdanm	20:4263a77256ae	6984	#define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
bogdanm	20:4263a77256ae	6985	#define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
bogdanm	20:4263a77256ae	6986	#define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
bogdanm	20:4263a77256ae	6987	#define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
bogdanm	20:4263a77256ae	6988	#define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
bogdanm	20:4263a77256ae	6989	#define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
bogdanm	20:4263a77256ae	6990	#define ETH_DMABMR_EDE ((uint32_t)0x00000080) /* Enhanced Descriptor Enable */
bogdanm	20:4263a77256ae	6991	#define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */
bogdanm	20:4263a77256ae	6992	#define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */
bogdanm	20:4263a77256ae	6993	#define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */
bogdanm	20:4263a77256ae	6994
bogdanm	20:4263a77256ae	6995	/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
bogdanm	20:4263a77256ae	6996	#define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */
bogdanm	20:4263a77256ae	6997
bogdanm	20:4263a77256ae	6998	/* Bit definition for Ethernet DMA Receive Poll Demand Register */
bogdanm	20:4263a77256ae	6999	#define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */
bogdanm	20:4263a77256ae	7000
bogdanm	20:4263a77256ae	7001	/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
bogdanm	20:4263a77256ae	7002	#define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */
bogdanm	20:4263a77256ae	7003
bogdanm	20:4263a77256ae	7004	/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
bogdanm	20:4263a77256ae	7005	#define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */
bogdanm	20:4263a77256ae	7006
bogdanm	20:4263a77256ae	7007	/* Bit definition for Ethernet DMA Status Register */
bogdanm	20:4263a77256ae	7008	#define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */
bogdanm	20:4263a77256ae	7009	#define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */
bogdanm	20:4263a77256ae	7010	#define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */
bogdanm	20:4263a77256ae	7011	#define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */
bogdanm	20:4263a77256ae	7012	/* combination with EBS[2:0] for GetFlagStatus function */
bogdanm	20:4263a77256ae	7013	#define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */
bogdanm	20:4263a77256ae	7014	#define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */
bogdanm	20:4263a77256ae	7015	#define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */
bogdanm	20:4263a77256ae	7016	#define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */
bogdanm	20:4263a77256ae	7017	#define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */
bogdanm	20:4263a77256ae	7018	#define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */
bogdanm	20:4263a77256ae	7019	#define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */
bogdanm	20:4263a77256ae	7020	#define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */
bogdanm	20:4263a77256ae	7021	#define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */
bogdanm	20:4263a77256ae	7022	#define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */
bogdanm	20:4263a77256ae	7023	#define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */
bogdanm	20:4263a77256ae	7024	#define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
bogdanm	20:4263a77256ae	7025	#define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */
bogdanm	20:4263a77256ae	7026	#define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */
bogdanm	20:4263a77256ae	7027	#define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */
bogdanm	20:4263a77256ae	7028	#define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */
bogdanm	20:4263a77256ae	7029	#define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */
bogdanm	20:4263a77256ae	7030	#define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */
bogdanm	20:4263a77256ae	7031	#define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */
bogdanm	20:4263a77256ae	7032	#define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */
bogdanm	20:4263a77256ae	7033	#define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */
bogdanm	20:4263a77256ae	7034	#define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */
bogdanm	20:4263a77256ae	7035	#define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */
bogdanm	20:4263a77256ae	7036	#define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */
bogdanm	20:4263a77256ae	7037	#define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */
bogdanm	20:4263a77256ae	7038	#define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */
bogdanm	20:4263a77256ae	7039	#define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */
bogdanm	20:4263a77256ae	7040	#define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */
bogdanm	20:4263a77256ae	7041	#define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */
bogdanm	20:4263a77256ae	7042	#define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */
bogdanm	20:4263a77256ae	7043	#define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */
bogdanm	20:4263a77256ae	7044	#define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */
bogdanm	20:4263a77256ae	7045
bogdanm	20:4263a77256ae	7046	/* Bit definition for Ethernet DMA Operation Mode Register */
bogdanm	20:4263a77256ae	7047	#define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */
bogdanm	20:4263a77256ae	7048	#define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */
bogdanm	20:4263a77256ae	7049	#define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */
bogdanm	20:4263a77256ae	7050	#define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */
bogdanm	20:4263a77256ae	7051	#define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */
bogdanm	20:4263a77256ae	7052	#define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */
bogdanm	20:4263a77256ae	7053	#define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */
bogdanm	20:4263a77256ae	7054	#define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */
bogdanm	20:4263a77256ae	7055	#define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */
bogdanm	20:4263a77256ae	7056	#define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */
bogdanm	20:4263a77256ae	7057	#define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */
bogdanm	20:4263a77256ae	7058	#define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */
bogdanm	20:4263a77256ae	7059	#define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */
bogdanm	20:4263a77256ae	7060	#define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */
bogdanm	20:4263a77256ae	7061	#define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */
bogdanm	20:4263a77256ae	7062	#define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */
bogdanm	20:4263a77256ae	7063	#define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */
bogdanm	20:4263a77256ae	7064	#define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */
bogdanm	20:4263a77256ae	7065	#define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */
bogdanm	20:4263a77256ae	7066	#define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */
bogdanm	20:4263a77256ae	7067	#define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */
bogdanm	20:4263a77256ae	7068	#define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */
bogdanm	20:4263a77256ae	7069	#define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */
bogdanm	20:4263a77256ae	7070	#define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */
bogdanm	20:4263a77256ae	7071
bogdanm	20:4263a77256ae	7072	/* Bit definition for Ethernet DMA Interrupt Enable Register */
bogdanm	20:4263a77256ae	7073	#define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */
bogdanm	20:4263a77256ae	7074	#define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */
bogdanm	20:4263a77256ae	7075	#define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */
bogdanm	20:4263a77256ae	7076	#define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */
bogdanm	20:4263a77256ae	7077	#define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */
bogdanm	20:4263a77256ae	7078	#define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */
bogdanm	20:4263a77256ae	7079	#define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */
bogdanm	20:4263a77256ae	7080	#define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */
bogdanm	20:4263a77256ae	7081	#define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */
bogdanm	20:4263a77256ae	7082	#define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */
bogdanm	20:4263a77256ae	7083	#define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */
bogdanm	20:4263a77256ae	7084	#define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */
bogdanm	20:4263a77256ae	7085	#define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */
bogdanm	20:4263a77256ae	7086	#define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */
bogdanm	20:4263a77256ae	7087	#define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */
bogdanm	20:4263a77256ae	7088
bogdanm	20:4263a77256ae	7089	/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
bogdanm	20:4263a77256ae	7090	#define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */
bogdanm	20:4263a77256ae	7091	#define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */
bogdanm	20:4263a77256ae	7092	#define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */
bogdanm	20:4263a77256ae	7093	#define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */
bogdanm	20:4263a77256ae	7094
bogdanm	20:4263a77256ae	7095	/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
bogdanm	20:4263a77256ae	7096	#define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */
bogdanm	20:4263a77256ae	7097
bogdanm	20:4263a77256ae	7098	/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
bogdanm	20:4263a77256ae	7099	#define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */
bogdanm	20:4263a77256ae	7100
bogdanm	20:4263a77256ae	7101	/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
bogdanm	20:4263a77256ae	7102	#define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */
bogdanm	20:4263a77256ae	7103
bogdanm	20:4263a77256ae	7104	/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
bogdanm	20:4263a77256ae	7105	#define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */
bogdanm	20:4263a77256ae	7106
bogdanm	20:4263a77256ae	7107	/**
bogdanm	20:4263a77256ae	7108	*
bogdanm	20:4263a77256ae	7109	*/
bogdanm	20:4263a77256ae	7110
bogdanm	20:4263a77256ae	7111	/**
bogdanm	20:4263a77256ae	7112	* @}
bogdanm	20:4263a77256ae	7113	*/
bogdanm	20:4263a77256ae	7114
bogdanm	20:4263a77256ae	7115	#ifdef USE_STDPERIPH_DRIVER
bogdanm	20:4263a77256ae	7116	#include "stm32f4xx_conf.h"
bogdanm	20:4263a77256ae	7117	#endif /* USE_STDPERIPH_DRIVER */
bogdanm	20:4263a77256ae	7118
bogdanm	20:4263a77256ae	7119	/** @addtogroup Exported_macro
bogdanm	20:4263a77256ae	7120	* @{
bogdanm	20:4263a77256ae	7121	*/
bogdanm	20:4263a77256ae	7122
bogdanm	20:4263a77256ae	7123	#define SET_BIT(REG, BIT) ((REG) \|= (BIT))
bogdanm	20:4263a77256ae	7124
bogdanm	20:4263a77256ae	7125	#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
bogdanm	20:4263a77256ae	7126
bogdanm	20:4263a77256ae	7127	#define READ_BIT(REG, BIT) ((REG) & (BIT))
bogdanm	20:4263a77256ae	7128
bogdanm	20:4263a77256ae	7129	#define CLEAR_REG(REG) ((REG) = (0x0))
bogdanm	20:4263a77256ae	7130
bogdanm	20:4263a77256ae	7131	#define WRITE_REG(REG, VAL) ((REG) = (VAL))
bogdanm	20:4263a77256ae	7132
bogdanm	20:4263a77256ae	7133	#define READ_REG(REG) ((REG))
bogdanm	20:4263a77256ae	7134
bogdanm	20:4263a77256ae	7135	#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) \| (SETMASK)))
bogdanm	20:4263a77256ae	7136
bogdanm	20:4263a77256ae	7137	/**
bogdanm	20:4263a77256ae	7138	* @}
bogdanm	20:4263a77256ae	7139	*/
bogdanm	20:4263a77256ae	7140
bogdanm	20:4263a77256ae	7141	#ifdef __cplusplus
bogdanm	20:4263a77256ae	7142	}
bogdanm	20:4263a77256ae	7143	#endif /* __cplusplus */
bogdanm	20:4263a77256ae	7144
bogdanm	20:4263a77256ae	7145	#endif /* __STM32F4xx_H */
bogdanm	20:4263a77256ae	7146
bogdanm	20:4263a77256ae	7147	/**
bogdanm	20:4263a77256ae	7148	* @}
bogdanm	20:4263a77256ae	7149	*/
bogdanm	20:4263a77256ae	7150
bogdanm	20:4263a77256ae	7151	/**
bogdanm	20:4263a77256ae	7152	* @}
bogdanm	20:4263a77256ae	7153	*/
bogdanm	20:4263a77256ae	7154
bogdanm	20:4263a77256ae	7155	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	26 Nov 2015
Imports:	17
Forks:	0
Commits:	638
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32F4XX/stm32f4xx.h@637:ed69428d4850, 2015-12-22 (annotated)

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