Add non blocking connect support for hiddevice
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USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/userdef/usb1_function_dmacdrv.c@46:378357d7e90d, 2015-03-31 (annotated)
- Committer:
- mbed_official
- Date:
- Tue Mar 31 16:15:39 2015 +0100
- Revision:
- 46:378357d7e90d
Synchronized with git revision 251f3f8b55a4dc98b831c80e032464ed45cce309
Full URL: https://github.com/mbedmicro/mbed/commit/251f3f8b55a4dc98b831c80e032464ed45cce309/
[RZ/A1H]Add some function(USB 2port, NVIC wrapper) and modify some settings(OS, Terminal).
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
mbed_official | 46:378357d7e90d | 1 | /******************************************************************************* |
mbed_official | 46:378357d7e90d | 2 | * DISCLAIMER |
mbed_official | 46:378357d7e90d | 3 | * This software is supplied by Renesas Electronics Corporation and is only |
mbed_official | 46:378357d7e90d | 4 | * intended for use with Renesas products. No other uses are authorized. This |
mbed_official | 46:378357d7e90d | 5 | * software is owned by Renesas Electronics Corporation and is protected under |
mbed_official | 46:378357d7e90d | 6 | * all applicable laws, including copyright laws. |
mbed_official | 46:378357d7e90d | 7 | * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING |
mbed_official | 46:378357d7e90d | 8 | * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT |
mbed_official | 46:378357d7e90d | 9 | * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE |
mbed_official | 46:378357d7e90d | 10 | * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. |
mbed_official | 46:378357d7e90d | 11 | * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS |
mbed_official | 46:378357d7e90d | 12 | * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE |
mbed_official | 46:378357d7e90d | 13 | * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR |
mbed_official | 46:378357d7e90d | 14 | * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE |
mbed_official | 46:378357d7e90d | 15 | * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. |
mbed_official | 46:378357d7e90d | 16 | * Renesas reserves the right, without notice, to make changes to this software |
mbed_official | 46:378357d7e90d | 17 | * and to discontinue the availability of this software. By using this software, |
mbed_official | 46:378357d7e90d | 18 | * you agree to the additional terms and conditions found by accessing the |
mbed_official | 46:378357d7e90d | 19 | * following link: |
mbed_official | 46:378357d7e90d | 20 | * http://www.renesas.com/disclaimer |
mbed_official | 46:378357d7e90d | 21 | * Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. |
mbed_official | 46:378357d7e90d | 22 | *******************************************************************************/ |
mbed_official | 46:378357d7e90d | 23 | /******************************************************************************* |
mbed_official | 46:378357d7e90d | 24 | * File Name : usb1_function_dmacdrv.c |
mbed_official | 46:378357d7e90d | 25 | * $Rev: 1116 $ |
mbed_official | 46:378357d7e90d | 26 | * $Date:: 2014-07-09 16:29:19 +0900#$ |
mbed_official | 46:378357d7e90d | 27 | * Device(s) : RZ/A1H |
mbed_official | 46:378357d7e90d | 28 | * Tool-Chain : |
mbed_official | 46:378357d7e90d | 29 | * OS : None |
mbed_official | 46:378357d7e90d | 30 | * H/W Platform : |
mbed_official | 46:378357d7e90d | 31 | * Description : RZ/A1H R7S72100 USB Sample Program |
mbed_official | 46:378357d7e90d | 32 | * Operation : |
mbed_official | 46:378357d7e90d | 33 | * Limitations : |
mbed_official | 46:378357d7e90d | 34 | *******************************************************************************/ |
mbed_official | 46:378357d7e90d | 35 | |
mbed_official | 46:378357d7e90d | 36 | |
mbed_official | 46:378357d7e90d | 37 | /******************************************************************************* |
mbed_official | 46:378357d7e90d | 38 | Includes <System Includes> , "Project Includes" |
mbed_official | 46:378357d7e90d | 39 | *******************************************************************************/ |
mbed_official | 46:378357d7e90d | 40 | #include <stdio.h> |
mbed_official | 46:378357d7e90d | 41 | #include "r_typedefs.h" |
mbed_official | 46:378357d7e90d | 42 | #include "iodefine.h" |
mbed_official | 46:378357d7e90d | 43 | #include "rza_io_regrw.h" |
mbed_official | 46:378357d7e90d | 44 | #include "usb1_function_dmacdrv.h" |
mbed_official | 46:378357d7e90d | 45 | |
mbed_official | 46:378357d7e90d | 46 | |
mbed_official | 46:378357d7e90d | 47 | /******************************************************************************* |
mbed_official | 46:378357d7e90d | 48 | Typedef definitions |
mbed_official | 46:378357d7e90d | 49 | *******************************************************************************/ |
mbed_official | 46:378357d7e90d | 50 | |
mbed_official | 46:378357d7e90d | 51 | |
mbed_official | 46:378357d7e90d | 52 | /******************************************************************************* |
mbed_official | 46:378357d7e90d | 53 | Macro definitions |
mbed_official | 46:378357d7e90d | 54 | *******************************************************************************/ |
mbed_official | 46:378357d7e90d | 55 | #define DMAC_INDEFINE (255) /* Macro definition when REQD bit is not used */ |
mbed_official | 46:378357d7e90d | 56 | |
mbed_official | 46:378357d7e90d | 57 | /* ==== Request setting information for on-chip peripheral module ==== */ |
mbed_official | 46:378357d7e90d | 58 | typedef enum dmac_peri_req_reg_type |
mbed_official | 46:378357d7e90d | 59 | { |
mbed_official | 46:378357d7e90d | 60 | DMAC_REQ_MID, |
mbed_official | 46:378357d7e90d | 61 | DMAC_REQ_RID, |
mbed_official | 46:378357d7e90d | 62 | DMAC_REQ_AM, |
mbed_official | 46:378357d7e90d | 63 | DMAC_REQ_LVL, |
mbed_official | 46:378357d7e90d | 64 | DMAC_REQ_REQD |
mbed_official | 46:378357d7e90d | 65 | } dmac_peri_req_reg_type_t; |
mbed_official | 46:378357d7e90d | 66 | |
mbed_official | 46:378357d7e90d | 67 | |
mbed_official | 46:378357d7e90d | 68 | /******************************************************************************* |
mbed_official | 46:378357d7e90d | 69 | Imported global variables and functions (from other files) |
mbed_official | 46:378357d7e90d | 70 | *******************************************************************************/ |
mbed_official | 46:378357d7e90d | 71 | |
mbed_official | 46:378357d7e90d | 72 | |
mbed_official | 46:378357d7e90d | 73 | /******************************************************************************* |
mbed_official | 46:378357d7e90d | 74 | Exported global variables and functions (to be accessed by other files) |
mbed_official | 46:378357d7e90d | 75 | *******************************************************************************/ |
mbed_official | 46:378357d7e90d | 76 | |
mbed_official | 46:378357d7e90d | 77 | |
mbed_official | 46:378357d7e90d | 78 | /******************************************************************************* |
mbed_official | 46:378357d7e90d | 79 | Private global variables and functions |
mbed_official | 46:378357d7e90d | 80 | *******************************************************************************/ |
mbed_official | 46:378357d7e90d | 81 | /* ==== Prototype declaration ==== */ |
mbed_official | 46:378357d7e90d | 82 | |
mbed_official | 46:378357d7e90d | 83 | /* ==== Global variable ==== */ |
mbed_official | 46:378357d7e90d | 84 | /* On-chip peripheral module request setting table */ |
mbed_official | 46:378357d7e90d | 85 | static const uint8_t usb1_function_dmac_peri_req_init_table[8][5] = |
mbed_official | 46:378357d7e90d | 86 | { |
mbed_official | 46:378357d7e90d | 87 | /* MID,RID,AM,LVL,REQD */ |
mbed_official | 46:378357d7e90d | 88 | {32, 3, 2, 1, 1}, /* USB_0 channel 0 transmit FIFO empty */ |
mbed_official | 46:378357d7e90d | 89 | {32, 3, 2, 1, 0}, /* USB_0 channel 0 receive FIFO full */ |
mbed_official | 46:378357d7e90d | 90 | {33, 3, 2, 1, 1}, /* USB_0 channel 1 transmit FIFO empty */ |
mbed_official | 46:378357d7e90d | 91 | {33, 3, 2, 1, 0}, /* USB_0 channel 1 receive FIFO full */ |
mbed_official | 46:378357d7e90d | 92 | {34, 3, 2, 1, 1}, /* USB_1 channel 0 transmit FIFO empty */ |
mbed_official | 46:378357d7e90d | 93 | {34, 3, 2, 1, 0}, /* USB_1 channel 0 receive FIFO full */ |
mbed_official | 46:378357d7e90d | 94 | {35, 3, 2, 1, 1}, /* USB_1 channel 1 transmit FIFO empty */ |
mbed_official | 46:378357d7e90d | 95 | {35, 3, 2, 1, 0}, /* USB_1 channel 1 receive FIFO full */ |
mbed_official | 46:378357d7e90d | 96 | }; |
mbed_official | 46:378357d7e90d | 97 | |
mbed_official | 46:378357d7e90d | 98 | |
mbed_official | 46:378357d7e90d | 99 | /******************************************************************************* |
mbed_official | 46:378357d7e90d | 100 | * Function Name: usb1_function_DMAC3_PeriReqInit |
mbed_official | 46:378357d7e90d | 101 | * Description : Sets the register mode for DMA mode and the on-chip peripheral |
mbed_official | 46:378357d7e90d | 102 | * : module request for transfer request for DMAC channel 1. |
mbed_official | 46:378357d7e90d | 103 | * : Executes DMAC initial setting using the DMA information |
mbed_official | 46:378357d7e90d | 104 | * : specified by the argument *trans_info and the enabled/disabled |
mbed_official | 46:378357d7e90d | 105 | * : continuous transfer specified by the argument continuation. |
mbed_official | 46:378357d7e90d | 106 | * : Registers DMAC channel 1 interrupt handler function and sets |
mbed_official | 46:378357d7e90d | 107 | * : the interrupt priority level. Then enables transfer completion |
mbed_official | 46:378357d7e90d | 108 | * : interrupt. |
mbed_official | 46:378357d7e90d | 109 | * Arguments : dmac_transinfo_t *trans_info : Setting information to DMAC register |
mbed_official | 46:378357d7e90d | 110 | * : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER) |
mbed_official | 46:378357d7e90d | 111 | * : uint32_t continuation : Set continuous transfer to be valid |
mbed_official | 46:378357d7e90d | 112 | * : after DMA transfer has been completed |
mbed_official | 46:378357d7e90d | 113 | * : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer |
mbed_official | 46:378357d7e90d | 114 | * : DMAC_SAMPLE_SINGLE : Do not execute continuous transfer |
mbed_official | 46:378357d7e90d | 115 | * : uint32_t request_factor : Factor for on-chip peripheral module request |
mbed_official | 46:378357d7e90d | 116 | * : DMAC_REQ_OSTM0TINT : OSTM_0 compare match |
mbed_official | 46:378357d7e90d | 117 | * : DMAC_REQ_OSTM1TINT : OSTM_1 compare match |
mbed_official | 46:378357d7e90d | 118 | * : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match |
mbed_official | 46:378357d7e90d | 119 | * : : |
mbed_official | 46:378357d7e90d | 120 | * : uint32_t req_direction: Setting value of CHCFG_n register REQD bit |
mbed_official | 46:378357d7e90d | 121 | * Return Value : none |
mbed_official | 46:378357d7e90d | 122 | *******************************************************************************/ |
mbed_official | 46:378357d7e90d | 123 | void usb1_function_DMAC3_PeriReqInit (const dmac_transinfo_t * trans_info, |
mbed_official | 46:378357d7e90d | 124 | uint32_t dmamode, uint32_t continuation, |
mbed_official | 46:378357d7e90d | 125 | uint32_t request_factor, uint32_t req_direction) |
mbed_official | 46:378357d7e90d | 126 | { |
mbed_official | 46:378357d7e90d | 127 | /* ==== Register mode ==== */ |
mbed_official | 46:378357d7e90d | 128 | if (DMAC_MODE_REGISTER == dmamode) |
mbed_official | 46:378357d7e90d | 129 | { |
mbed_official | 46:378357d7e90d | 130 | /* ==== Next0 register set ==== */ |
mbed_official | 46:378357d7e90d | 131 | DMAC3.N0SA_n = trans_info->src_addr; /* Start address of transfer source */ |
mbed_official | 46:378357d7e90d | 132 | DMAC3.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */ |
mbed_official | 46:378357d7e90d | 133 | DMAC3.N0TB_n = trans_info->count; /* Total transfer byte count */ |
mbed_official | 46:378357d7e90d | 134 | |
mbed_official | 46:378357d7e90d | 135 | /* DAD : Transfer destination address counting direction */ |
mbed_official | 46:378357d7e90d | 136 | /* SAD : Transfer source address counting direction */ |
mbed_official | 46:378357d7e90d | 137 | /* DDS : Transfer destination transfer size */ |
mbed_official | 46:378357d7e90d | 138 | /* SDS : Transfer source transfer size */ |
mbed_official | 46:378357d7e90d | 139 | RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, |
mbed_official | 46:378357d7e90d | 140 | trans_info->daddr_dir, |
mbed_official | 46:378357d7e90d | 141 | DMAC3_CHCFG_n_DAD_SHIFT, |
mbed_official | 46:378357d7e90d | 142 | DMAC3_CHCFG_n_DAD); |
mbed_official | 46:378357d7e90d | 143 | RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, |
mbed_official | 46:378357d7e90d | 144 | trans_info->saddr_dir, |
mbed_official | 46:378357d7e90d | 145 | DMAC3_CHCFG_n_SAD_SHIFT, |
mbed_official | 46:378357d7e90d | 146 | DMAC3_CHCFG_n_SAD); |
mbed_official | 46:378357d7e90d | 147 | RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, |
mbed_official | 46:378357d7e90d | 148 | trans_info->dst_size, |
mbed_official | 46:378357d7e90d | 149 | DMAC3_CHCFG_n_DDS_SHIFT, |
mbed_official | 46:378357d7e90d | 150 | DMAC3_CHCFG_n_DDS); |
mbed_official | 46:378357d7e90d | 151 | RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, |
mbed_official | 46:378357d7e90d | 152 | trans_info->src_size, |
mbed_official | 46:378357d7e90d | 153 | DMAC3_CHCFG_n_SDS_SHIFT, |
mbed_official | 46:378357d7e90d | 154 | DMAC3_CHCFG_n_SDS); |
mbed_official | 46:378357d7e90d | 155 | |
mbed_official | 46:378357d7e90d | 156 | /* DMS : Register mode */ |
mbed_official | 46:378357d7e90d | 157 | /* RSEL : Select Next0 register set */ |
mbed_official | 46:378357d7e90d | 158 | /* SBE : No discharge of buffer data when aborted */ |
mbed_official | 46:378357d7e90d | 159 | /* DEM : No DMA interrupt mask */ |
mbed_official | 46:378357d7e90d | 160 | RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, |
mbed_official | 46:378357d7e90d | 161 | 0, |
mbed_official | 46:378357d7e90d | 162 | DMAC3_CHCFG_n_DMS_SHIFT, |
mbed_official | 46:378357d7e90d | 163 | DMAC3_CHCFG_n_DMS); |
mbed_official | 46:378357d7e90d | 164 | RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, |
mbed_official | 46:378357d7e90d | 165 | 0, |
mbed_official | 46:378357d7e90d | 166 | DMAC3_CHCFG_n_RSEL_SHIFT, |
mbed_official | 46:378357d7e90d | 167 | DMAC3_CHCFG_n_RSEL); |
mbed_official | 46:378357d7e90d | 168 | RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, |
mbed_official | 46:378357d7e90d | 169 | 0, |
mbed_official | 46:378357d7e90d | 170 | DMAC3_CHCFG_n_SBE_SHIFT, |
mbed_official | 46:378357d7e90d | 171 | DMAC3_CHCFG_n_SBE); |
mbed_official | 46:378357d7e90d | 172 | RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, |
mbed_official | 46:378357d7e90d | 173 | 0, |
mbed_official | 46:378357d7e90d | 174 | DMAC3_CHCFG_n_DEM_SHIFT, |
mbed_official | 46:378357d7e90d | 175 | DMAC3_CHCFG_n_DEM); |
mbed_official | 46:378357d7e90d | 176 | |
mbed_official | 46:378357d7e90d | 177 | /* ---- Continuous transfer ---- */ |
mbed_official | 46:378357d7e90d | 178 | if (DMAC_SAMPLE_CONTINUATION == continuation) |
mbed_official | 46:378357d7e90d | 179 | { |
mbed_official | 46:378357d7e90d | 180 | /* REN : Execute continuous transfer */ |
mbed_official | 46:378357d7e90d | 181 | /* RSW : Change register set when DMA transfer is completed. */ |
mbed_official | 46:378357d7e90d | 182 | RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, |
mbed_official | 46:378357d7e90d | 183 | 1, |
mbed_official | 46:378357d7e90d | 184 | DMAC3_CHCFG_n_REN_SHIFT, |
mbed_official | 46:378357d7e90d | 185 | DMAC3_CHCFG_n_REN); |
mbed_official | 46:378357d7e90d | 186 | RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, |
mbed_official | 46:378357d7e90d | 187 | 1, |
mbed_official | 46:378357d7e90d | 188 | DMAC3_CHCFG_n_RSW_SHIFT, |
mbed_official | 46:378357d7e90d | 189 | DMAC3_CHCFG_n_RSW); |
mbed_official | 46:378357d7e90d | 190 | } |
mbed_official | 46:378357d7e90d | 191 | /* ---- Single transfer ---- */ |
mbed_official | 46:378357d7e90d | 192 | else |
mbed_official | 46:378357d7e90d | 193 | { |
mbed_official | 46:378357d7e90d | 194 | /* REN : Do not execute continuous transfer */ |
mbed_official | 46:378357d7e90d | 195 | /* RSW : Do not change register set when DMA transfer is completed. */ |
mbed_official | 46:378357d7e90d | 196 | RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, |
mbed_official | 46:378357d7e90d | 197 | 0, |
mbed_official | 46:378357d7e90d | 198 | DMAC3_CHCFG_n_REN_SHIFT, |
mbed_official | 46:378357d7e90d | 199 | DMAC3_CHCFG_n_REN); |
mbed_official | 46:378357d7e90d | 200 | RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, |
mbed_official | 46:378357d7e90d | 201 | 0, |
mbed_official | 46:378357d7e90d | 202 | DMAC3_CHCFG_n_RSW_SHIFT, |
mbed_official | 46:378357d7e90d | 203 | DMAC3_CHCFG_n_RSW); |
mbed_official | 46:378357d7e90d | 204 | } |
mbed_official | 46:378357d7e90d | 205 | |
mbed_official | 46:378357d7e90d | 206 | /* TM : Single transfer */ |
mbed_official | 46:378357d7e90d | 207 | /* SEL : Channel setting */ |
mbed_official | 46:378357d7e90d | 208 | /* HIEN, LOEN : On-chip peripheral module request */ |
mbed_official | 46:378357d7e90d | 209 | RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, |
mbed_official | 46:378357d7e90d | 210 | 0, |
mbed_official | 46:378357d7e90d | 211 | DMAC3_CHCFG_n_TM_SHIFT, |
mbed_official | 46:378357d7e90d | 212 | DMAC3_CHCFG_n_TM); |
mbed_official | 46:378357d7e90d | 213 | RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, |
mbed_official | 46:378357d7e90d | 214 | 3, |
mbed_official | 46:378357d7e90d | 215 | DMAC3_CHCFG_n_SEL_SHIFT, |
mbed_official | 46:378357d7e90d | 216 | DMAC3_CHCFG_n_SEL); |
mbed_official | 46:378357d7e90d | 217 | RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, |
mbed_official | 46:378357d7e90d | 218 | 1, |
mbed_official | 46:378357d7e90d | 219 | DMAC3_CHCFG_n_HIEN_SHIFT, |
mbed_official | 46:378357d7e90d | 220 | DMAC3_CHCFG_n_HIEN); |
mbed_official | 46:378357d7e90d | 221 | RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, |
mbed_official | 46:378357d7e90d | 222 | 0, |
mbed_official | 46:378357d7e90d | 223 | DMAC3_CHCFG_n_LOEN_SHIFT, |
mbed_official | 46:378357d7e90d | 224 | DMAC3_CHCFG_n_LOEN); |
mbed_official | 46:378357d7e90d | 225 | |
mbed_official | 46:378357d7e90d | 226 | /* ---- Set factor by specified on-chip peripheral module request ---- */ |
mbed_official | 46:378357d7e90d | 227 | RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, |
mbed_official | 46:378357d7e90d | 228 | usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM], |
mbed_official | 46:378357d7e90d | 229 | DMAC3_CHCFG_n_AM_SHIFT, |
mbed_official | 46:378357d7e90d | 230 | DMAC3_CHCFG_n_AM); |
mbed_official | 46:378357d7e90d | 231 | RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, |
mbed_official | 46:378357d7e90d | 232 | usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL], |
mbed_official | 46:378357d7e90d | 233 | DMAC3_CHCFG_n_LVL_SHIFT, |
mbed_official | 46:378357d7e90d | 234 | DMAC3_CHCFG_n_LVL); |
mbed_official | 46:378357d7e90d | 235 | |
mbed_official | 46:378357d7e90d | 236 | if (usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE) |
mbed_official | 46:378357d7e90d | 237 | { |
mbed_official | 46:378357d7e90d | 238 | RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, |
mbed_official | 46:378357d7e90d | 239 | usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD], |
mbed_official | 46:378357d7e90d | 240 | DMAC3_CHCFG_n_REQD_SHIFT, |
mbed_official | 46:378357d7e90d | 241 | DMAC3_CHCFG_n_REQD); |
mbed_official | 46:378357d7e90d | 242 | } |
mbed_official | 46:378357d7e90d | 243 | else |
mbed_official | 46:378357d7e90d | 244 | { |
mbed_official | 46:378357d7e90d | 245 | RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, |
mbed_official | 46:378357d7e90d | 246 | req_direction, |
mbed_official | 46:378357d7e90d | 247 | DMAC3_CHCFG_n_REQD_SHIFT, |
mbed_official | 46:378357d7e90d | 248 | DMAC3_CHCFG_n_REQD); |
mbed_official | 46:378357d7e90d | 249 | } |
mbed_official | 46:378357d7e90d | 250 | |
mbed_official | 46:378357d7e90d | 251 | RZA_IO_RegWrite_32(&DMAC23.DMARS, |
mbed_official | 46:378357d7e90d | 252 | usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID], |
mbed_official | 46:378357d7e90d | 253 | DMAC23_DMARS_CH3_RID_SHIFT, |
mbed_official | 46:378357d7e90d | 254 | DMAC23_DMARS_CH3_RID); |
mbed_official | 46:378357d7e90d | 255 | RZA_IO_RegWrite_32(&DMAC23.DMARS, |
mbed_official | 46:378357d7e90d | 256 | usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID], |
mbed_official | 46:378357d7e90d | 257 | DMAC23_DMARS_CH3_MID_SHIFT, |
mbed_official | 46:378357d7e90d | 258 | DMAC23_DMARS_CH3_MID); |
mbed_official | 46:378357d7e90d | 259 | |
mbed_official | 46:378357d7e90d | 260 | /* PR : Round robin mode */ |
mbed_official | 46:378357d7e90d | 261 | RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7, |
mbed_official | 46:378357d7e90d | 262 | 1, |
mbed_official | 46:378357d7e90d | 263 | DMAC07_DCTRL_0_7_PR_SHIFT, |
mbed_official | 46:378357d7e90d | 264 | DMAC07_DCTRL_0_7_PR); |
mbed_official | 46:378357d7e90d | 265 | } |
mbed_official | 46:378357d7e90d | 266 | } |
mbed_official | 46:378357d7e90d | 267 | |
mbed_official | 46:378357d7e90d | 268 | /******************************************************************************* |
mbed_official | 46:378357d7e90d | 269 | * Function Name: usb1_function_DMAC3_Open |
mbed_official | 46:378357d7e90d | 270 | * Description : Enables DMAC channel 3 transfer. |
mbed_official | 46:378357d7e90d | 271 | * Arguments : uint32_t req : DMAC request mode |
mbed_official | 46:378357d7e90d | 272 | * Return Value : 0 : Succeeded in enabling DMA transfer |
mbed_official | 46:378357d7e90d | 273 | * : -1 : Failed to enable DMA transfer (due to DMA operation) |
mbed_official | 46:378357d7e90d | 274 | *******************************************************************************/ |
mbed_official | 46:378357d7e90d | 275 | int32_t usb1_function_DMAC3_Open (uint32_t req) |
mbed_official | 46:378357d7e90d | 276 | { |
mbed_official | 46:378357d7e90d | 277 | int32_t ret; |
mbed_official | 46:378357d7e90d | 278 | volatile uint8_t dummy; |
mbed_official | 46:378357d7e90d | 279 | |
mbed_official | 46:378357d7e90d | 280 | /* Transferable? */ |
mbed_official | 46:378357d7e90d | 281 | if ((0 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n, |
mbed_official | 46:378357d7e90d | 282 | DMAC3_CHSTAT_n_EN_SHIFT, |
mbed_official | 46:378357d7e90d | 283 | DMAC3_CHSTAT_n_EN)) && |
mbed_official | 46:378357d7e90d | 284 | (0 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n, |
mbed_official | 46:378357d7e90d | 285 | DMAC3_CHSTAT_n_TACT_SHIFT, |
mbed_official | 46:378357d7e90d | 286 | DMAC3_CHSTAT_n_TACT))) |
mbed_official | 46:378357d7e90d | 287 | { |
mbed_official | 46:378357d7e90d | 288 | /* Clear Channel Status Register */ |
mbed_official | 46:378357d7e90d | 289 | RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n, |
mbed_official | 46:378357d7e90d | 290 | 1, |
mbed_official | 46:378357d7e90d | 291 | DMAC3_CHCTRL_n_SWRST_SHIFT, |
mbed_official | 46:378357d7e90d | 292 | DMAC3_CHCTRL_n_SWRST); |
mbed_official | 46:378357d7e90d | 293 | dummy = RZA_IO_RegRead_32(&DMAC3.CHCTRL_n, |
mbed_official | 46:378357d7e90d | 294 | DMAC3_CHCTRL_n_SWRST_SHIFT, |
mbed_official | 46:378357d7e90d | 295 | DMAC3_CHCTRL_n_SWRST); |
mbed_official | 46:378357d7e90d | 296 | /* Enable DMA transfer */ |
mbed_official | 46:378357d7e90d | 297 | RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n, |
mbed_official | 46:378357d7e90d | 298 | 1, |
mbed_official | 46:378357d7e90d | 299 | DMAC3_CHCTRL_n_SETEN_SHIFT, |
mbed_official | 46:378357d7e90d | 300 | DMAC3_CHCTRL_n_SETEN); |
mbed_official | 46:378357d7e90d | 301 | |
mbed_official | 46:378357d7e90d | 302 | /* ---- Request by software ---- */ |
mbed_official | 46:378357d7e90d | 303 | if (DMAC_REQ_MODE_SOFT == req) |
mbed_official | 46:378357d7e90d | 304 | { |
mbed_official | 46:378357d7e90d | 305 | /* DMA transfer Request by software */ |
mbed_official | 46:378357d7e90d | 306 | RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n, |
mbed_official | 46:378357d7e90d | 307 | 1, |
mbed_official | 46:378357d7e90d | 308 | DMAC3_CHCTRL_n_STG_SHIFT, |
mbed_official | 46:378357d7e90d | 309 | DMAC3_CHCTRL_n_STG); |
mbed_official | 46:378357d7e90d | 310 | } |
mbed_official | 46:378357d7e90d | 311 | |
mbed_official | 46:378357d7e90d | 312 | ret = 0; |
mbed_official | 46:378357d7e90d | 313 | } |
mbed_official | 46:378357d7e90d | 314 | else |
mbed_official | 46:378357d7e90d | 315 | { |
mbed_official | 46:378357d7e90d | 316 | ret = -1; |
mbed_official | 46:378357d7e90d | 317 | } |
mbed_official | 46:378357d7e90d | 318 | |
mbed_official | 46:378357d7e90d | 319 | return ret; |
mbed_official | 46:378357d7e90d | 320 | } |
mbed_official | 46:378357d7e90d | 321 | |
mbed_official | 46:378357d7e90d | 322 | /******************************************************************************* |
mbed_official | 46:378357d7e90d | 323 | * Function Name: usb1_function_DMAC3_Close |
mbed_official | 46:378357d7e90d | 324 | * Description : Aborts DMAC channel 3 transfer. Returns the remaining transfer |
mbed_official | 46:378357d7e90d | 325 | * : byte count at the time of DMA transfer abort to the argument |
mbed_official | 46:378357d7e90d | 326 | * : *remain. |
mbed_official | 46:378357d7e90d | 327 | * Arguments : uint32_t * remain : Remaining transfer byte count when |
mbed_official | 46:378357d7e90d | 328 | * : : DMA transfer is aborted |
mbed_official | 46:378357d7e90d | 329 | * Return Value : none |
mbed_official | 46:378357d7e90d | 330 | *******************************************************************************/ |
mbed_official | 46:378357d7e90d | 331 | void usb1_function_DMAC3_Close (uint32_t * remain) |
mbed_official | 46:378357d7e90d | 332 | { |
mbed_official | 46:378357d7e90d | 333 | |
mbed_official | 46:378357d7e90d | 334 | /* ==== Abort transfer ==== */ |
mbed_official | 46:378357d7e90d | 335 | RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n, |
mbed_official | 46:378357d7e90d | 336 | 1, |
mbed_official | 46:378357d7e90d | 337 | DMAC3_CHCTRL_n_CLREN_SHIFT, |
mbed_official | 46:378357d7e90d | 338 | DMAC3_CHCTRL_n_CLREN); |
mbed_official | 46:378357d7e90d | 339 | |
mbed_official | 46:378357d7e90d | 340 | while (1 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n, |
mbed_official | 46:378357d7e90d | 341 | DMAC3_CHSTAT_n_TACT_SHIFT, |
mbed_official | 46:378357d7e90d | 342 | DMAC3_CHSTAT_n_TACT)) |
mbed_official | 46:378357d7e90d | 343 | { |
mbed_official | 46:378357d7e90d | 344 | /* Loop until transfer is aborted */ |
mbed_official | 46:378357d7e90d | 345 | } |
mbed_official | 46:378357d7e90d | 346 | |
mbed_official | 46:378357d7e90d | 347 | while (1 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n, |
mbed_official | 46:378357d7e90d | 348 | DMAC3_CHSTAT_n_EN_SHIFT, |
mbed_official | 46:378357d7e90d | 349 | DMAC3_CHSTAT_n_EN)) |
mbed_official | 46:378357d7e90d | 350 | { |
mbed_official | 46:378357d7e90d | 351 | /* Loop until 0 is set in EN before checking the remaining transfer byte count */ |
mbed_official | 46:378357d7e90d | 352 | } |
mbed_official | 46:378357d7e90d | 353 | /* ==== Obtain remaining transfer byte count ==== */ |
mbed_official | 46:378357d7e90d | 354 | *remain = DMAC3.CRTB_n; |
mbed_official | 46:378357d7e90d | 355 | } |
mbed_official | 46:378357d7e90d | 356 | |
mbed_official | 46:378357d7e90d | 357 | /******************************************************************************* |
mbed_official | 46:378357d7e90d | 358 | * Function Name: usb1_function_DMAC3_Load_Set |
mbed_official | 46:378357d7e90d | 359 | * Description : Sets the transfer source address, transfer destination |
mbed_official | 46:378357d7e90d | 360 | * : address, and total transfer byte count respectively |
mbed_official | 46:378357d7e90d | 361 | * : specified by the argument src_addr, dst_addr, and count to |
mbed_official | 46:378357d7e90d | 362 | * : DMAC channel 3 as DMA transfer information. |
mbed_official | 46:378357d7e90d | 363 | * : Sets the register set selected by the CHCFG_n register |
mbed_official | 46:378357d7e90d | 364 | * : RSEL bit from the Next0 or Next1 register set. |
mbed_official | 46:378357d7e90d | 365 | * : This function should be called when DMA transfer of DMAC |
mbed_official | 46:378357d7e90d | 366 | * : channel 3 is aboted. |
mbed_official | 46:378357d7e90d | 367 | * Arguments : uint32_t src_addr : Transfer source address |
mbed_official | 46:378357d7e90d | 368 | * : uint32_t dst_addr : Transfer destination address |
mbed_official | 46:378357d7e90d | 369 | * : uint32_t count : Total transfer byte count |
mbed_official | 46:378357d7e90d | 370 | * Return Value : none |
mbed_official | 46:378357d7e90d | 371 | *******************************************************************************/ |
mbed_official | 46:378357d7e90d | 372 | void usb1_function_DMAC3_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count) |
mbed_official | 46:378357d7e90d | 373 | { |
mbed_official | 46:378357d7e90d | 374 | uint8_t reg_set; |
mbed_official | 46:378357d7e90d | 375 | |
mbed_official | 46:378357d7e90d | 376 | /* Obtain register set in use */ |
mbed_official | 46:378357d7e90d | 377 | reg_set = RZA_IO_RegRead_32(&DMAC3.CHSTAT_n, |
mbed_official | 46:378357d7e90d | 378 | DMAC3_CHSTAT_n_SR_SHIFT, |
mbed_official | 46:378357d7e90d | 379 | DMAC3_CHSTAT_n_SR); |
mbed_official | 46:378357d7e90d | 380 | |
mbed_official | 46:378357d7e90d | 381 | /* ==== Load ==== */ |
mbed_official | 46:378357d7e90d | 382 | if (0 == reg_set) |
mbed_official | 46:378357d7e90d | 383 | { |
mbed_official | 46:378357d7e90d | 384 | /* ---- Next0 Register Set ---- */ |
mbed_official | 46:378357d7e90d | 385 | DMAC3.N0SA_n = src_addr; /* Start address of transfer source */ |
mbed_official | 46:378357d7e90d | 386 | DMAC3.N0DA_n = dst_addr; /* Start address of transfer destination */ |
mbed_official | 46:378357d7e90d | 387 | DMAC3.N0TB_n = count; /* Total transfer byte count */ |
mbed_official | 46:378357d7e90d | 388 | } |
mbed_official | 46:378357d7e90d | 389 | else |
mbed_official | 46:378357d7e90d | 390 | { |
mbed_official | 46:378357d7e90d | 391 | /* ---- Next1 Register Set ---- */ |
mbed_official | 46:378357d7e90d | 392 | DMAC3.N1SA_n = src_addr; /* Start address of transfer source */ |
mbed_official | 46:378357d7e90d | 393 | DMAC3.N1DA_n = dst_addr; /* Start address of transfer destination */ |
mbed_official | 46:378357d7e90d | 394 | DMAC3.N1TB_n = count; /* Total transfer byte count */ |
mbed_official | 46:378357d7e90d | 395 | } |
mbed_official | 46:378357d7e90d | 396 | } |
mbed_official | 46:378357d7e90d | 397 | |
mbed_official | 46:378357d7e90d | 398 | /******************************************************************************* |
mbed_official | 46:378357d7e90d | 399 | * Function Name: usb1_function_DMAC4_PeriReqInit |
mbed_official | 46:378357d7e90d | 400 | * Description : Sets the register mode for DMA mode and the on-chip peripheral |
mbed_official | 46:378357d7e90d | 401 | * : module request for transfer request for DMAC channel 2. |
mbed_official | 46:378357d7e90d | 402 | * : Executes DMAC initial setting using the DMA information |
mbed_official | 46:378357d7e90d | 403 | * : specified by the argument *trans_info and the enabled/disabled |
mbed_official | 46:378357d7e90d | 404 | * : continuous transfer specified by the argument continuation. |
mbed_official | 46:378357d7e90d | 405 | * : Registers DMAC channel 2 interrupt handler function and sets |
mbed_official | 46:378357d7e90d | 406 | * : the interrupt priority level. Then enables transfer completion |
mbed_official | 46:378357d7e90d | 407 | * : interrupt. |
mbed_official | 46:378357d7e90d | 408 | * Arguments : dmac_transinfo_t * trans_info : Setting information to DMAC |
mbed_official | 46:378357d7e90d | 409 | * : : register |
mbed_official | 46:378357d7e90d | 410 | * : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER) |
mbed_official | 46:378357d7e90d | 411 | * : uint32_t continuation : Set continuous transfer to be valid |
mbed_official | 46:378357d7e90d | 412 | * : : after DMA transfer has been completed |
mbed_official | 46:378357d7e90d | 413 | * : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer |
mbed_official | 46:378357d7e90d | 414 | * : DMAC_SAMPLE_SINGLE : Do not execute continuous |
mbed_official | 46:378357d7e90d | 415 | * : : transfer |
mbed_official | 46:378357d7e90d | 416 | * : uint32_t request_factor : Factor for on-chip peripheral module |
mbed_official | 46:378357d7e90d | 417 | * : : request |
mbed_official | 46:378357d7e90d | 418 | * : DMAC_REQ_OSTM0TINT : OSTM_0 compare match |
mbed_official | 46:378357d7e90d | 419 | * : DMAC_REQ_OSTM1TINT : OSTM_1 compare match |
mbed_official | 46:378357d7e90d | 420 | * : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match |
mbed_official | 46:378357d7e90d | 421 | * : : |
mbed_official | 46:378357d7e90d | 422 | * : uint32_t req_direction : Setting value of CHCFG_n register |
mbed_official | 46:378357d7e90d | 423 | * : : REQD bit |
mbed_official | 46:378357d7e90d | 424 | *******************************************************************************/ |
mbed_official | 46:378357d7e90d | 425 | void usb1_function_DMAC4_PeriReqInit (const dmac_transinfo_t * trans_info, |
mbed_official | 46:378357d7e90d | 426 | uint32_t dmamode, uint32_t continuation, |
mbed_official | 46:378357d7e90d | 427 | uint32_t request_factor, uint32_t req_direction) |
mbed_official | 46:378357d7e90d | 428 | { |
mbed_official | 46:378357d7e90d | 429 | /* ==== Register mode ==== */ |
mbed_official | 46:378357d7e90d | 430 | if (DMAC_MODE_REGISTER == dmamode) |
mbed_official | 46:378357d7e90d | 431 | { |
mbed_official | 46:378357d7e90d | 432 | /* ==== Next0 register set ==== */ |
mbed_official | 46:378357d7e90d | 433 | DMAC4.N0SA_n = trans_info->src_addr; /* Start address of transfer source */ |
mbed_official | 46:378357d7e90d | 434 | DMAC4.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */ |
mbed_official | 46:378357d7e90d | 435 | DMAC4.N0TB_n = trans_info->count; /* Total transfer byte count */ |
mbed_official | 46:378357d7e90d | 436 | |
mbed_official | 46:378357d7e90d | 437 | /* DAD : Transfer destination address counting direction */ |
mbed_official | 46:378357d7e90d | 438 | /* SAD : Transfer source address counting direction */ |
mbed_official | 46:378357d7e90d | 439 | /* DDS : Transfer destination transfer size */ |
mbed_official | 46:378357d7e90d | 440 | /* SDS : Transfer source transfer size */ |
mbed_official | 46:378357d7e90d | 441 | RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, |
mbed_official | 46:378357d7e90d | 442 | trans_info->daddr_dir, |
mbed_official | 46:378357d7e90d | 443 | DMAC4_CHCFG_n_DAD_SHIFT, |
mbed_official | 46:378357d7e90d | 444 | DMAC4_CHCFG_n_DAD); |
mbed_official | 46:378357d7e90d | 445 | RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, |
mbed_official | 46:378357d7e90d | 446 | trans_info->saddr_dir, |
mbed_official | 46:378357d7e90d | 447 | DMAC4_CHCFG_n_SAD_SHIFT, |
mbed_official | 46:378357d7e90d | 448 | DMAC4_CHCFG_n_SAD); |
mbed_official | 46:378357d7e90d | 449 | RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, |
mbed_official | 46:378357d7e90d | 450 | trans_info->dst_size, |
mbed_official | 46:378357d7e90d | 451 | DMAC4_CHCFG_n_DDS_SHIFT, |
mbed_official | 46:378357d7e90d | 452 | DMAC4_CHCFG_n_DDS); |
mbed_official | 46:378357d7e90d | 453 | RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, |
mbed_official | 46:378357d7e90d | 454 | trans_info->src_size, |
mbed_official | 46:378357d7e90d | 455 | DMAC4_CHCFG_n_SDS_SHIFT, |
mbed_official | 46:378357d7e90d | 456 | DMAC4_CHCFG_n_SDS); |
mbed_official | 46:378357d7e90d | 457 | |
mbed_official | 46:378357d7e90d | 458 | /* DMS : Register mode */ |
mbed_official | 46:378357d7e90d | 459 | /* RSEL : Select Next0 register set */ |
mbed_official | 46:378357d7e90d | 460 | /* SBE : No discharge of buffer data when aborted */ |
mbed_official | 46:378357d7e90d | 461 | /* DEM : No DMA interrupt mask */ |
mbed_official | 46:378357d7e90d | 462 | RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, |
mbed_official | 46:378357d7e90d | 463 | 0, |
mbed_official | 46:378357d7e90d | 464 | DMAC4_CHCFG_n_DMS_SHIFT, |
mbed_official | 46:378357d7e90d | 465 | DMAC4_CHCFG_n_DMS); |
mbed_official | 46:378357d7e90d | 466 | RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, |
mbed_official | 46:378357d7e90d | 467 | 0, |
mbed_official | 46:378357d7e90d | 468 | DMAC4_CHCFG_n_RSEL_SHIFT, |
mbed_official | 46:378357d7e90d | 469 | DMAC4_CHCFG_n_RSEL); |
mbed_official | 46:378357d7e90d | 470 | RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, |
mbed_official | 46:378357d7e90d | 471 | 0, |
mbed_official | 46:378357d7e90d | 472 | DMAC4_CHCFG_n_SBE_SHIFT, |
mbed_official | 46:378357d7e90d | 473 | DMAC4_CHCFG_n_SBE); |
mbed_official | 46:378357d7e90d | 474 | RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, |
mbed_official | 46:378357d7e90d | 475 | 0, |
mbed_official | 46:378357d7e90d | 476 | DMAC4_CHCFG_n_DEM_SHIFT, |
mbed_official | 46:378357d7e90d | 477 | DMAC4_CHCFG_n_DEM); |
mbed_official | 46:378357d7e90d | 478 | |
mbed_official | 46:378357d7e90d | 479 | /* ---- Continuous transfer ---- */ |
mbed_official | 46:378357d7e90d | 480 | if (DMAC_SAMPLE_CONTINUATION == continuation) |
mbed_official | 46:378357d7e90d | 481 | { |
mbed_official | 46:378357d7e90d | 482 | /* REN : Execute continuous transfer */ |
mbed_official | 46:378357d7e90d | 483 | /* RSW : Change register set when DMA transfer is completed. */ |
mbed_official | 46:378357d7e90d | 484 | RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, |
mbed_official | 46:378357d7e90d | 485 | 1, |
mbed_official | 46:378357d7e90d | 486 | DMAC4_CHCFG_n_REN_SHIFT, |
mbed_official | 46:378357d7e90d | 487 | DMAC4_CHCFG_n_REN); |
mbed_official | 46:378357d7e90d | 488 | RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, |
mbed_official | 46:378357d7e90d | 489 | 1, |
mbed_official | 46:378357d7e90d | 490 | DMAC4_CHCFG_n_RSW_SHIFT, |
mbed_official | 46:378357d7e90d | 491 | DMAC4_CHCFG_n_RSW); |
mbed_official | 46:378357d7e90d | 492 | } |
mbed_official | 46:378357d7e90d | 493 | /* ---- Single transfer ---- */ |
mbed_official | 46:378357d7e90d | 494 | else |
mbed_official | 46:378357d7e90d | 495 | { |
mbed_official | 46:378357d7e90d | 496 | /* REN : Do not execute continuous transfer */ |
mbed_official | 46:378357d7e90d | 497 | /* RSW : Do not change register set when DMA transfer is completed. */ |
mbed_official | 46:378357d7e90d | 498 | RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, |
mbed_official | 46:378357d7e90d | 499 | 0, |
mbed_official | 46:378357d7e90d | 500 | DMAC4_CHCFG_n_REN_SHIFT, |
mbed_official | 46:378357d7e90d | 501 | DMAC4_CHCFG_n_REN); |
mbed_official | 46:378357d7e90d | 502 | RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, |
mbed_official | 46:378357d7e90d | 503 | 0, |
mbed_official | 46:378357d7e90d | 504 | DMAC4_CHCFG_n_RSW_SHIFT, |
mbed_official | 46:378357d7e90d | 505 | DMAC4_CHCFG_n_RSW); |
mbed_official | 46:378357d7e90d | 506 | } |
mbed_official | 46:378357d7e90d | 507 | |
mbed_official | 46:378357d7e90d | 508 | /* TM : Single transfer */ |
mbed_official | 46:378357d7e90d | 509 | /* SEL : Channel setting */ |
mbed_official | 46:378357d7e90d | 510 | /* HIEN, LOEN : On-chip peripheral module request */ |
mbed_official | 46:378357d7e90d | 511 | RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, |
mbed_official | 46:378357d7e90d | 512 | 0, |
mbed_official | 46:378357d7e90d | 513 | DMAC4_CHCFG_n_TM_SHIFT, |
mbed_official | 46:378357d7e90d | 514 | DMAC4_CHCFG_n_TM); |
mbed_official | 46:378357d7e90d | 515 | RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, |
mbed_official | 46:378357d7e90d | 516 | 4, |
mbed_official | 46:378357d7e90d | 517 | DMAC4_CHCFG_n_SEL_SHIFT, |
mbed_official | 46:378357d7e90d | 518 | DMAC4_CHCFG_n_SEL); |
mbed_official | 46:378357d7e90d | 519 | RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, |
mbed_official | 46:378357d7e90d | 520 | 1, |
mbed_official | 46:378357d7e90d | 521 | DMAC4_CHCFG_n_HIEN_SHIFT, |
mbed_official | 46:378357d7e90d | 522 | DMAC4_CHCFG_n_HIEN); |
mbed_official | 46:378357d7e90d | 523 | RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, |
mbed_official | 46:378357d7e90d | 524 | 0, |
mbed_official | 46:378357d7e90d | 525 | DMAC4_CHCFG_n_LOEN_SHIFT, |
mbed_official | 46:378357d7e90d | 526 | DMAC4_CHCFG_n_LOEN); |
mbed_official | 46:378357d7e90d | 527 | |
mbed_official | 46:378357d7e90d | 528 | /* ---- Set factor by specified on-chip peripheral module request ---- */ |
mbed_official | 46:378357d7e90d | 529 | RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, |
mbed_official | 46:378357d7e90d | 530 | usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM], |
mbed_official | 46:378357d7e90d | 531 | DMAC4_CHCFG_n_AM_SHIFT, |
mbed_official | 46:378357d7e90d | 532 | DMAC4_CHCFG_n_AM); |
mbed_official | 46:378357d7e90d | 533 | RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, |
mbed_official | 46:378357d7e90d | 534 | usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL], |
mbed_official | 46:378357d7e90d | 535 | DMAC4_CHCFG_n_LVL_SHIFT, |
mbed_official | 46:378357d7e90d | 536 | DMAC4_CHCFG_n_LVL); |
mbed_official | 46:378357d7e90d | 537 | if (usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE) |
mbed_official | 46:378357d7e90d | 538 | { |
mbed_official | 46:378357d7e90d | 539 | RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, |
mbed_official | 46:378357d7e90d | 540 | usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD], |
mbed_official | 46:378357d7e90d | 541 | DMAC4_CHCFG_n_REQD_SHIFT, |
mbed_official | 46:378357d7e90d | 542 | DMAC4_CHCFG_n_REQD); |
mbed_official | 46:378357d7e90d | 543 | } |
mbed_official | 46:378357d7e90d | 544 | else |
mbed_official | 46:378357d7e90d | 545 | { |
mbed_official | 46:378357d7e90d | 546 | RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, |
mbed_official | 46:378357d7e90d | 547 | req_direction, |
mbed_official | 46:378357d7e90d | 548 | DMAC4_CHCFG_n_REQD_SHIFT, |
mbed_official | 46:378357d7e90d | 549 | DMAC4_CHCFG_n_REQD); |
mbed_official | 46:378357d7e90d | 550 | } |
mbed_official | 46:378357d7e90d | 551 | RZA_IO_RegWrite_32(&DMAC45.DMARS, |
mbed_official | 46:378357d7e90d | 552 | usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID], |
mbed_official | 46:378357d7e90d | 553 | DMAC45_DMARS_CH4_RID_SHIFT, |
mbed_official | 46:378357d7e90d | 554 | DMAC45_DMARS_CH4_RID); |
mbed_official | 46:378357d7e90d | 555 | RZA_IO_RegWrite_32(&DMAC45.DMARS, |
mbed_official | 46:378357d7e90d | 556 | usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID], |
mbed_official | 46:378357d7e90d | 557 | DMAC45_DMARS_CH4_MID_SHIFT, |
mbed_official | 46:378357d7e90d | 558 | DMAC45_DMARS_CH4_MID); |
mbed_official | 46:378357d7e90d | 559 | |
mbed_official | 46:378357d7e90d | 560 | /* PR : Round robin mode */ |
mbed_official | 46:378357d7e90d | 561 | RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7, |
mbed_official | 46:378357d7e90d | 562 | 1, |
mbed_official | 46:378357d7e90d | 563 | DMAC07_DCTRL_0_7_PR_SHIFT, |
mbed_official | 46:378357d7e90d | 564 | DMAC07_DCTRL_0_7_PR); |
mbed_official | 46:378357d7e90d | 565 | } |
mbed_official | 46:378357d7e90d | 566 | } |
mbed_official | 46:378357d7e90d | 567 | |
mbed_official | 46:378357d7e90d | 568 | /******************************************************************************* |
mbed_official | 46:378357d7e90d | 569 | * Function Name: usb1_function_DMAC4_Open |
mbed_official | 46:378357d7e90d | 570 | * Description : Enables DMAC channel 4 transfer. |
mbed_official | 46:378357d7e90d | 571 | * Arguments : uint32_t req : DMAC request mode |
mbed_official | 46:378357d7e90d | 572 | * Return Value : 0 : Succeeded in enabling DMA transfer |
mbed_official | 46:378357d7e90d | 573 | * : -1 : Failed to enable DMA transfer (due to DMA operation) |
mbed_official | 46:378357d7e90d | 574 | *******************************************************************************/ |
mbed_official | 46:378357d7e90d | 575 | int32_t usb1_function_DMAC4_Open (uint32_t req) |
mbed_official | 46:378357d7e90d | 576 | { |
mbed_official | 46:378357d7e90d | 577 | int32_t ret; |
mbed_official | 46:378357d7e90d | 578 | volatile uint8_t dummy; |
mbed_official | 46:378357d7e90d | 579 | |
mbed_official | 46:378357d7e90d | 580 | /* Transferable? */ |
mbed_official | 46:378357d7e90d | 581 | if ((0 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n, |
mbed_official | 46:378357d7e90d | 582 | DMAC4_CHSTAT_n_EN_SHIFT, |
mbed_official | 46:378357d7e90d | 583 | DMAC4_CHSTAT_n_EN)) && |
mbed_official | 46:378357d7e90d | 584 | (0 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n, |
mbed_official | 46:378357d7e90d | 585 | DMAC4_CHSTAT_n_TACT_SHIFT, |
mbed_official | 46:378357d7e90d | 586 | DMAC4_CHSTAT_n_TACT))) |
mbed_official | 46:378357d7e90d | 587 | { |
mbed_official | 46:378357d7e90d | 588 | /* Clear Channel Status Register */ |
mbed_official | 46:378357d7e90d | 589 | RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n, |
mbed_official | 46:378357d7e90d | 590 | 1, |
mbed_official | 46:378357d7e90d | 591 | DMAC4_CHCTRL_n_SWRST_SHIFT, |
mbed_official | 46:378357d7e90d | 592 | DMAC4_CHCTRL_n_SWRST); |
mbed_official | 46:378357d7e90d | 593 | dummy = RZA_IO_RegRead_32(&DMAC4.CHCTRL_n, |
mbed_official | 46:378357d7e90d | 594 | DMAC4_CHCTRL_n_SWRST_SHIFT, |
mbed_official | 46:378357d7e90d | 595 | DMAC4_CHCTRL_n_SWRST); |
mbed_official | 46:378357d7e90d | 596 | /* Enable DMA transfer */ |
mbed_official | 46:378357d7e90d | 597 | RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n, |
mbed_official | 46:378357d7e90d | 598 | 1, |
mbed_official | 46:378357d7e90d | 599 | DMAC4_CHCTRL_n_SETEN_SHIFT, |
mbed_official | 46:378357d7e90d | 600 | DMAC4_CHCTRL_n_SETEN); |
mbed_official | 46:378357d7e90d | 601 | |
mbed_official | 46:378357d7e90d | 602 | /* ---- Request by software ---- */ |
mbed_official | 46:378357d7e90d | 603 | if (DMAC_REQ_MODE_SOFT == req) |
mbed_official | 46:378357d7e90d | 604 | { |
mbed_official | 46:378357d7e90d | 605 | /* DMA transfer Request by software */ |
mbed_official | 46:378357d7e90d | 606 | RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n, |
mbed_official | 46:378357d7e90d | 607 | 1, |
mbed_official | 46:378357d7e90d | 608 | DMAC4_CHCTRL_n_STG_SHIFT, |
mbed_official | 46:378357d7e90d | 609 | DMAC4_CHCTRL_n_STG); |
mbed_official | 46:378357d7e90d | 610 | } |
mbed_official | 46:378357d7e90d | 611 | |
mbed_official | 46:378357d7e90d | 612 | ret = 0; |
mbed_official | 46:378357d7e90d | 613 | } |
mbed_official | 46:378357d7e90d | 614 | else |
mbed_official | 46:378357d7e90d | 615 | { |
mbed_official | 46:378357d7e90d | 616 | ret = -1; |
mbed_official | 46:378357d7e90d | 617 | } |
mbed_official | 46:378357d7e90d | 618 | |
mbed_official | 46:378357d7e90d | 619 | return ret; |
mbed_official | 46:378357d7e90d | 620 | } |
mbed_official | 46:378357d7e90d | 621 | |
mbed_official | 46:378357d7e90d | 622 | /******************************************************************************* |
mbed_official | 46:378357d7e90d | 623 | * Function Name: usb1_function_DMAC4_Close |
mbed_official | 46:378357d7e90d | 624 | * Description : Aborts DMAC channel 4 transfer. Returns the remaining transfer |
mbed_official | 46:378357d7e90d | 625 | * : byte count at the time of DMA transfer abort to the argument |
mbed_official | 46:378357d7e90d | 626 | * : *remain. |
mbed_official | 46:378357d7e90d | 627 | * Arguments : uint32_t * remain : Remaining transfer byte count when |
mbed_official | 46:378357d7e90d | 628 | * : : DMA transfer is aborted |
mbed_official | 46:378357d7e90d | 629 | * Return Value : none |
mbed_official | 46:378357d7e90d | 630 | *******************************************************************************/ |
mbed_official | 46:378357d7e90d | 631 | void usb1_function_DMAC4_Close (uint32_t * remain) |
mbed_official | 46:378357d7e90d | 632 | { |
mbed_official | 46:378357d7e90d | 633 | |
mbed_official | 46:378357d7e90d | 634 | /* ==== Abort transfer ==== */ |
mbed_official | 46:378357d7e90d | 635 | RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n, |
mbed_official | 46:378357d7e90d | 636 | 1, |
mbed_official | 46:378357d7e90d | 637 | DMAC4_CHCTRL_n_CLREN_SHIFT, |
mbed_official | 46:378357d7e90d | 638 | DMAC4_CHCTRL_n_CLREN); |
mbed_official | 46:378357d7e90d | 639 | |
mbed_official | 46:378357d7e90d | 640 | while (1 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n, |
mbed_official | 46:378357d7e90d | 641 | DMAC4_CHSTAT_n_TACT_SHIFT, |
mbed_official | 46:378357d7e90d | 642 | DMAC4_CHSTAT_n_TACT)) |
mbed_official | 46:378357d7e90d | 643 | { |
mbed_official | 46:378357d7e90d | 644 | /* Loop until transfer is aborted */ |
mbed_official | 46:378357d7e90d | 645 | } |
mbed_official | 46:378357d7e90d | 646 | |
mbed_official | 46:378357d7e90d | 647 | while (1 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n, |
mbed_official | 46:378357d7e90d | 648 | DMAC4_CHSTAT_n_EN_SHIFT, |
mbed_official | 46:378357d7e90d | 649 | DMAC4_CHSTAT_n_EN)) |
mbed_official | 46:378357d7e90d | 650 | { |
mbed_official | 46:378357d7e90d | 651 | /* Loop until 0 is set in EN before checking the remaining transfer byte count */ |
mbed_official | 46:378357d7e90d | 652 | } |
mbed_official | 46:378357d7e90d | 653 | /* ==== Obtain remaining transfer byte count ==== */ |
mbed_official | 46:378357d7e90d | 654 | *remain = DMAC4.CRTB_n; |
mbed_official | 46:378357d7e90d | 655 | } |
mbed_official | 46:378357d7e90d | 656 | |
mbed_official | 46:378357d7e90d | 657 | /******************************************************************************* |
mbed_official | 46:378357d7e90d | 658 | * Function Name: usb1_function_DMAC4_Load_Set |
mbed_official | 46:378357d7e90d | 659 | * Description : Sets the transfer source address, transfer destination |
mbed_official | 46:378357d7e90d | 660 | * : address, and total transfer byte count respectively |
mbed_official | 46:378357d7e90d | 661 | * : specified by the argument src_addr, dst_addr, and count to |
mbed_official | 46:378357d7e90d | 662 | * : DMAC channel 4 as DMA transfer information. |
mbed_official | 46:378357d7e90d | 663 | * : Sets the register set selected by the CHCFG_n register |
mbed_official | 46:378357d7e90d | 664 | * : RSEL bit from the Next0 or Next1 register set. |
mbed_official | 46:378357d7e90d | 665 | * : This function should be called when DMA transfer of DMAC |
mbed_official | 46:378357d7e90d | 666 | * : channel 4 is aboted. |
mbed_official | 46:378357d7e90d | 667 | * Arguments : uint32_t src_addr : Transfer source address |
mbed_official | 46:378357d7e90d | 668 | * : uint32_t dst_addr : Transfer destination address |
mbed_official | 46:378357d7e90d | 669 | * : uint32_t count : Total transfer byte count |
mbed_official | 46:378357d7e90d | 670 | * Return Value : none |
mbed_official | 46:378357d7e90d | 671 | *******************************************************************************/ |
mbed_official | 46:378357d7e90d | 672 | void usb1_function_DMAC4_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count) |
mbed_official | 46:378357d7e90d | 673 | { |
mbed_official | 46:378357d7e90d | 674 | uint8_t reg_set; |
mbed_official | 46:378357d7e90d | 675 | |
mbed_official | 46:378357d7e90d | 676 | /* Obtain register set in use */ |
mbed_official | 46:378357d7e90d | 677 | reg_set = RZA_IO_RegRead_32(&DMAC4.CHSTAT_n, |
mbed_official | 46:378357d7e90d | 678 | DMAC4_CHSTAT_n_SR_SHIFT, |
mbed_official | 46:378357d7e90d | 679 | DMAC4_CHSTAT_n_SR); |
mbed_official | 46:378357d7e90d | 680 | |
mbed_official | 46:378357d7e90d | 681 | /* ==== Load ==== */ |
mbed_official | 46:378357d7e90d | 682 | if (0 == reg_set) |
mbed_official | 46:378357d7e90d | 683 | { |
mbed_official | 46:378357d7e90d | 684 | /* ---- Next0 Register Set ---- */ |
mbed_official | 46:378357d7e90d | 685 | DMAC4.N0SA_n = src_addr; /* Start address of transfer source */ |
mbed_official | 46:378357d7e90d | 686 | DMAC4.N0DA_n = dst_addr; /* Start address of transfer destination */ |
mbed_official | 46:378357d7e90d | 687 | DMAC4.N0TB_n = count; /* Total transfer byte count */ |
mbed_official | 46:378357d7e90d | 688 | } |
mbed_official | 46:378357d7e90d | 689 | else |
mbed_official | 46:378357d7e90d | 690 | { |
mbed_official | 46:378357d7e90d | 691 | /* ---- Next1 Register Set ---- */ |
mbed_official | 46:378357d7e90d | 692 | DMAC4.N1SA_n = src_addr; /* Start address of transfer source */ |
mbed_official | 46:378357d7e90d | 693 | DMAC4.N1DA_n = dst_addr; /* Start address of transfer destination */ |
mbed_official | 46:378357d7e90d | 694 | DMAC4.N1TB_n = count; /* Total transfer byte count */ |
mbed_official | 46:378357d7e90d | 695 | } |
mbed_official | 46:378357d7e90d | 696 | } |
mbed_official | 46:378357d7e90d | 697 | |
mbed_official | 46:378357d7e90d | 698 | /* End of File */ |