Jack Hansdampf / HSAnalogIn_GSOE

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HSAnalogIn.cpp@0:08cfedb7969f, 2020-05-19 (annotated)

Committer:
jack1930
Date:
Tue May 19 11:53:25 2020 +0000
Revision:
0:08cfedb7969f
High Speed Analog In STM32L152RET Interrupt

Who changed what in which revision?

UserRevisionLine numberNew contents of line
jack1930 0:08cfedb7969f 1 #include "HSAnalogIn.h"
jack1930 0:08cfedb7969f 2
jack1930 0:08cfedb7969f 3
jack1930 0:08cfedb7969f 4 #define BDC_CR1_OVRIE 0
jack1930 0:08cfedb7969f 5 #define BDC_CR1_RES 0b00 //12-bit (TCONV = 12 BDCgCLK cycles)
jack1930 0:08cfedb7969f 6 #define BDC_CR1_AWDEN 0 //Analog watchdog disabled on regular channels
jack1930 0:08cfedb7969f 7 #define BDC_CR1_JAWDEN 0 // Analog watchdog disabled on injected channels
jack1930 0:08cfedb7969f 8 #define BDC_CR1_PDI 0 //The BDCg is powered up when waiting for a start event
jack1930 0:08cfedb7969f 9 #define BDC_CR1_PDD 0 //The BDCg is powered up during the delay
jack1930 0:08cfedb7969f 10 #define BDC_CR1_DISCNUM 0b000 // 1 channel
jack1930 0:08cfedb7969f 11 #define BDC_CR1_JDISCEN 0 //Discontinuous mode on injected channels disabled
jack1930 0:08cfedb7969f 12 #define BDC_CR1_DISCEN 0 //Discontinuous mode on regular channels disabled
jack1930 0:08cfedb7969f 13 #define BDC_CR1_JAUTO 0 // Automatic injected group conversion disabled
jack1930 0:08cfedb7969f 14 #define BDC_CR1_AWDSGL 0 //Analog watchdog enabled on all channels
jack1930 0:08cfedb7969f 15 #define BDC_CR1_SCAN 0 //Scan mode disabled
jack1930 0:08cfedb7969f 16 #define BDC_CR1_JEOCIE 0 //JEOC interrupt disabled
jack1930 0:08cfedb7969f 17 #define BDC_CR1_AWDIE 0 // Analog watchdog interrupt disabled
jack1930 0:08cfedb7969f 18 #define BDC_CR1_EOCIE 0 //EOC interrupt disabled
jack1930 0:08cfedb7969f 19 #define BDC_CR1_AWDCH 0b00000 //BDCg analog input BDC_IN0
jack1930 0:08cfedb7969f 20
jack1930 0:08cfedb7969f 21
jack1930 0:08cfedb7969f 22
jack1930 0:08cfedb7969f 23 #define BDC_CR2_SWSTART 0
jack1930 0:08cfedb7969f 24 #define BDC_CR2_EXTEN 0b00
jack1930 0:08cfedb7969f 25 #define BDC_CR2_EXTSEL 0b0000
jack1930 0:08cfedb7969f 26 #define BDC_CR2_JSWSTART 0
jack1930 0:08cfedb7969f 27 #define BDC_CR2_JEXTEN 0b00
jack1930 0:08cfedb7969f 28 #define BDC_CR2_JEXTSEL 0b0000
jack1930 0:08cfedb7969f 29 #define BDC_CR2_ALIGN 1
jack1930 0:08cfedb7969f 30 #define BDC_CR2_EOCS 0 //EOC set at End of each conversion
jack1930 0:08cfedb7969f 31 #define BDC_CR2_DDS 0 //No DMA request
jack1930 0:08cfedb7969f 32 #define BDC_CR2_DMA 0 //DMA disabled
jack1930 0:08cfedb7969f 33 #define BDC_CR2_DELS 0b001 //Until the converted data have been read (DR read or EOC=0 for regular conversions)
jack1930 0:08cfedb7969f 34 #define BDC_CR2_BDC_CFG 0 //Bank A selected for channels BDCgg_IN0..31
jack1930 0:08cfedb7969f 35 #define BDC_CR2_CONT 0 // Single conversion mode
jack1930 0:08cfedb7969f 36 #define BDC_CR2_ADON 1 // Enable BDCgg: conversions can start as soon as a start event (hardware or software) is received.
jack1930 0:08cfedb7969f 37
jack1930 0:08cfedb7969f 38
jack1930 0:08cfedb7969f 39
jack1930 0:08cfedb7969f 40
jack1930 0:08cfedb7969f 41 HSAnalogIn::HSAnalogIn(int Pin)
jack1930 0:08cfedb7969f 42 {
jack1930 0:08cfedb7969f 43 //Analog init
jack1930 0:08cfedb7969f 44
jack1930 0:08cfedb7969f 45 myPin=Pin;
jack1930 0:08cfedb7969f 46 RCC->APB2ENR|=(1<<9);
jack1930 0:08cfedb7969f 47 RCC->AHBENR|=0b111;
jack1930 0:08cfedb7969f 48 RCC->CR|=1; //HSI On
jack1930 0:08cfedb7969f 49 while ((RCC->CR&0b10)==0);
jack1930 0:08cfedb7969f 50
jack1930 0:08cfedb7969f 51 ADC1->CR1= (BDC_CR1_OVRIE<<26)+(BDC_CR1_RES<<24)+(BDC_CR1_AWDEN<<23)+(BDC_CR1_JAWDEN<<22)+(BDC_CR1_PDI<<17)+(BDC_CR1_PDD<<16)+(BDC_CR1_DISCNUM<<13)+(BDC_CR1_JDISCEN<<12)+(BDC_CR1_DISCEN<<11)+(BDC_CR1_JAUTO<<10)+(BDC_CR1_AWDSGL<<9)+(BDC_CR1_SCAN<<8)+(BDC_CR1_JEOCIE<<7)+(BDC_CR1_AWDIE<<6)+(BDC_CR1_EOCIE<<5)+(BDC_CR1_AWDCH);
jack1930 0:08cfedb7969f 52
jack1930 0:08cfedb7969f 53 ADC1->CR2=(BDC_CR2_SWSTART<<30)+(BDC_CR2_EXTEN<<28)+(BDC_CR2_EXTSEL<<24)+(BDC_CR2_JSWSTART<<22)+(BDC_CR2_JEXTEN<<20)+(BDC_CR2_JEXTSEL<<16)+(BDC_CR2_ALIGN<<11)+(BDC_CR2_EOCS<<10)+(BDC_CR2_DDS<<9)+(BDC_CR2_DMA<<8)+(BDC_CR2_DELS<<4)+(BDC_CR2_BDC_CFG<<2)+(BDC_CR2_CONT<<1)+(BDC_CR2_ADON);
jack1930 0:08cfedb7969f 54 switch ((int)Pin) //0-15 PA, 16-31 PB, 32-47 PC
jack1930 0:08cfedb7969f 55 {
jack1930 0:08cfedb7969f 56 case 0: BDCin=0; GPIOA->MODER|=0b11; break;//PA_0 .. PA_7
jack1930 0:08cfedb7969f 57 case 1: BDCin=1; GPIOA->MODER|=0b11<<2; break;
jack1930 0:08cfedb7969f 58 case 2: BDCin=2; GPIOA->MODER|=0b11<<4; break;
jack1930 0:08cfedb7969f 59 case 3: BDCin=3; GPIOA->MODER|=0b11<<6; break;
jack1930 0:08cfedb7969f 60 case 4: BDCin=4; GPIOA->MODER|=0b11<<8; break;
jack1930 0:08cfedb7969f 61 case 5: BDCin=5; GPIOA->MODER|=0b11<<10; break;
jack1930 0:08cfedb7969f 62 case 6: BDCin=6; GPIOA->MODER|=0b11<<12; break;
jack1930 0:08cfedb7969f 63 case 7: BDCin=7; GPIOA->MODER|=0b11<<14; break;
jack1930 0:08cfedb7969f 64 case 16: //PB_0
jack1930 0:08cfedb7969f 65 BDCin=8; GPIOB->MODER|=0b11; break;
jack1930 0:08cfedb7969f 66 case 17: //PB_1
jack1930 0:08cfedb7969f 67 BDCin=9; GPIOB->MODER|=0b11<<2; break;
jack1930 0:08cfedb7969f 68 case 18: //PB_2
jack1930 0:08cfedb7969f 69 BDCin=0; GPIOB->MODER|=0b11<<4; gruppe=1; break;
jack1930 0:08cfedb7969f 70 case 28: //PB_12
jack1930 0:08cfedb7969f 71 BDCin=18; GPIOB->MODER|=0b11<<24; break;
jack1930 0:08cfedb7969f 72 case 29: //PB_13
jack1930 0:08cfedb7969f 73 BDCin=19; GPIOB->MODER|=0b11<<26; break;
jack1930 0:08cfedb7969f 74 case 30: //PB_14
jack1930 0:08cfedb7969f 75 BDCin=20; GPIOB->MODER|=0b11<<28; break;
jack1930 0:08cfedb7969f 76 case 31: //PB_15
jack1930 0:08cfedb7969f 77 BDCin=21; GPIOB->MODER|=0b11<<30; break;
jack1930 0:08cfedb7969f 78 case 32: //PC_0
jack1930 0:08cfedb7969f 79 BDCin=10; GPIOC->MODER|=0b11; break;
jack1930 0:08cfedb7969f 80 case 33: //PC_1
jack1930 0:08cfedb7969f 81 BDCin=11; GPIOC->MODER|=0b11<<2; break;
jack1930 0:08cfedb7969f 82 case 34: //PC_2
jack1930 0:08cfedb7969f 83 BDCin=12; GPIOC->MODER|=0b11<<4; break;
jack1930 0:08cfedb7969f 84 case 35: //PC_3
jack1930 0:08cfedb7969f 85 BDCin=13; GPIOC->MODER|=0b11<<6; break;
jack1930 0:08cfedb7969f 86 case 36: //PC_4
jack1930 0:08cfedb7969f 87 BDCin=14; GPIOC->MODER|=0b11<<8; break;
jack1930 0:08cfedb7969f 88 case 37: //PC_5
jack1930 0:08cfedb7969f 89 BDCin=15; GPIOC->MODER|=0b11<<10; break;
jack1930 0:08cfedb7969f 90 };
jack1930 0:08cfedb7969f 91
jack1930 0:08cfedb7969f 92 };
jack1930 0:08cfedb7969f 93
jack1930 0:08cfedb7969f 94 float HSAnalogIn::read()
jack1930 0:08cfedb7969f 95 {
jack1930 0:08cfedb7969f 96 /*
jack1930 0:08cfedb7969f 97 RCC->APB2ENR|=(1<<9);
jack1930 0:08cfedb7969f 98 RCC->AHBENR|=0b111;
jack1930 0:08cfedb7969f 99 RCC->CR|=1; //HSI On
jack1930 0:08cfedb7969f 100 while ((RCC->CR&0b10)==0);
jack1930 0:08cfedb7969f 101 ADC1->CR1= (BDC_CR1_OVRIE<<26)+(BDC_CR1_RES<<24)+(BDC_CR1_AWDEN<<23)+(BDC_CR1_JAWDEN<<22)+(BDC_CR1_PDI<<17)+(BDC_CR1_PDD<<16)+(BDC_CR1_DISCNUM<<13)+(BDC_CR1_JDISCEN<<12)+(BDC_CR1_DISCEN<<11)+(BDC_CR1_JAUTO<<10)+(BDC_CR1_AWDSGL<<9)+(BDC_CR1_SCAN<<8)+(BDC_CR1_JEOCIE<<7)+(BDC_CR1_AWDIE<<6)+(BDC_CR1_EOCIE<<5)+(BDC_CR1_AWDCH);
jack1930 0:08cfedb7969f 102 ADC1->CR2=(BDC_CR2_SWSTART<<30)+(BDC_CR2_EXTEN<<28)+(BDC_CR2_EXTSEL<<24)+(BDC_CR2_JSWSTART<<22)+(BDC_CR2_JEXTEN<<20)+(BDC_CR2_JEXTSEL<<16)+(BDC_CR2_ALIGN<<11)+(BDC_CR2_EOCS<<10)+(BDC_CR2_DDS<<9)+(BDC_CR2_DMA<<8)+(BDC_CR2_DELS<<4)+(BDC_CR2_BDC_CFG<<2)+(BDC_CR2_CONT<<1)+(BDC_CR2_ADON);
jack1930 0:08cfedb7969f 103 switch ((int)myPin) //0-15 PA, 16-31 PB, 32-47 PC
jack1930 0:08cfedb7969f 104 {
jack1930 0:08cfedb7969f 105 case 0: BDCin=0; GPIOA->MODER|=0b11; break;//PA_0 .. PA_7
jack1930 0:08cfedb7969f 106 case 1: BDCin=1; GPIOA->MODER|=0b11<<2; break;
jack1930 0:08cfedb7969f 107 case 2: BDCin=2; GPIOA->MODER|=0b11<<4; break;
jack1930 0:08cfedb7969f 108 case 3: BDCin=3; GPIOA->MODER|=0b11<<6; break;
jack1930 0:08cfedb7969f 109 case 4: BDCin=4; GPIOA->MODER|=0b11<<8; break;
jack1930 0:08cfedb7969f 110 case 5: BDCin=5; GPIOA->MODER|=0b11<<10; break;
jack1930 0:08cfedb7969f 111 case 6: BDCin=6; GPIOA->MODER|=0b11<<12; break;
jack1930 0:08cfedb7969f 112 case 7: BDCin=7; GPIOA->MODER|=0b11<<14; break;
jack1930 0:08cfedb7969f 113 case 16: //PB_0
jack1930 0:08cfedb7969f 114 BDCin=8; GPIOB->MODER|=0b11; break;
jack1930 0:08cfedb7969f 115 case 17: //PB_1
jack1930 0:08cfedb7969f 116 BDCin=9; GPIOB->MODER|=0b11<<2; break;
jack1930 0:08cfedb7969f 117 case 18: //PB_2
jack1930 0:08cfedb7969f 118 BDCin=0; GPIOB->MODER|=0b11<<4; gruppe=1; break;
jack1930 0:08cfedb7969f 119 case 28: //PB_12
jack1930 0:08cfedb7969f 120 BDCin=18; GPIOB->MODER|=0b11<<24; break;
jack1930 0:08cfedb7969f 121 case 29: //PB_13
jack1930 0:08cfedb7969f 122 BDCin=19; GPIOB->MODER|=0b11<<26; break;
jack1930 0:08cfedb7969f 123 case 30: //PB_14
jack1930 0:08cfedb7969f 124 BDCin=20; GPIOB->MODER|=0b11<<28; break;
jack1930 0:08cfedb7969f 125 case 31: //PB_15
jack1930 0:08cfedb7969f 126 BDCin=21; GPIOB->MODER|=0b11<<30; break;
jack1930 0:08cfedb7969f 127 case 32: //PC_0
jack1930 0:08cfedb7969f 128 BDCin=10; GPIOC->MODER|=0b11; break;
jack1930 0:08cfedb7969f 129 case 33: //PC_1
jack1930 0:08cfedb7969f 130 BDCin=11; GPIOC->MODER|=0b11<<2; break;
jack1930 0:08cfedb7969f 131 case 34: //PC_2
jack1930 0:08cfedb7969f 132 BDCin=12; GPIOC->MODER|=0b11<<4; break;
jack1930 0:08cfedb7969f 133 case 35: //PC_3
jack1930 0:08cfedb7969f 134 BDCin=13; GPIOC->MODER|=0b11<<6; break;
jack1930 0:08cfedb7969f 135 case 36: //PC_4
jack1930 0:08cfedb7969f 136 BDCin=14; GPIOC->MODER|=0b11<<8; break;
jack1930 0:08cfedb7969f 137 case 37: //PC_5
jack1930 0:08cfedb7969f 138 BDCin=15; GPIOC->MODER|=0b11<<10; break;
jack1930 0:08cfedb7969f 139 };
jack1930 0:08cfedb7969f 140 */
jack1930 0:08cfedb7969f 141
jack1930 0:08cfedb7969f 142 ADC1->SQR5=BDCin;
jack1930 0:08cfedb7969f 143 if (gruppe==1) ADC1->CR2|= (1<<2); //gruppe
jack1930 0:08cfedb7969f 144 else ADC1->CR2&=~(1<<2);
jack1930 0:08cfedb7969f 145
jack1930 0:08cfedb7969f 146 ADC1->CR2|=(1<<30); //SWStart
jack1930 0:08cfedb7969f 147
jack1930 0:08cfedb7969f 148
jack1930 0:08cfedb7969f 149 while ((ADC1->SR & 0b10)==0);
jack1930 0:08cfedb7969f 150 //warte(1000);
jack1930 0:08cfedb7969f 151
jack1930 0:08cfedb7969f 152 return (float)ADC1->DR/65535;
jack1930 0:08cfedb7969f 153 };
jack1930 0:08cfedb7969f 154
jack1930 0:08cfedb7969f 155 /** Read the input voltage, represented as an unsigned short in the range [0x0, 0xFFFF]
jack1930 0:08cfedb7969f 156 *
jack1930 0:08cfedb7969f 157 * @returns
jack1930 0:08cfedb7969f 158 * 16-bit unsigned short representing the current input voltage, normalized to a 16-bit value
jack1930 0:08cfedb7969f 159 */
jack1930 0:08cfedb7969f 160
jack1930 0:08cfedb7969f 161 unsigned short HSAnalogIn::read_u16()
jack1930 0:08cfedb7969f 162 {
jack1930 0:08cfedb7969f 163
jack1930 0:08cfedb7969f 164 ADC1->SQR5=BDCin;
jack1930 0:08cfedb7969f 165 if (gruppe==1) ADC1->CR2|= (1<<2); //gruppe
jack1930 0:08cfedb7969f 166 else ADC1->CR2&=~(1<<2);
jack1930 0:08cfedb7969f 167
jack1930 0:08cfedb7969f 168 ADC1->CR2|=(1<<30); //SWStart
jack1930 0:08cfedb7969f 169
jack1930 0:08cfedb7969f 170
jack1930 0:08cfedb7969f 171 while ((ADC1->SR & 0b10)==0);
jack1930 0:08cfedb7969f 172 return (unsigned short)ADC1->DR;
jack1930 0:08cfedb7969f 173
jack1930 0:08cfedb7969f 174 };
jack1930 0:08cfedb7969f 175