Library for H3LIS331DL
H3LIS331DL.h@0:915a712ec85a, 2017-04-28 (annotated)
- Committer:
- j3
- Date:
- Fri Apr 28 00:07:39 2017 +0000
- Revision:
- 0:915a712ec85a
init commit
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
j3 | 0:915a712ec85a | 1 | /****************************************************************************** |
j3 | 0:915a712ec85a | 2 | * MIT License |
j3 | 0:915a712ec85a | 3 | * |
j3 | 0:915a712ec85a | 4 | * Copyright (c) 2017 Justin J. Jordan |
j3 | 0:915a712ec85a | 5 | * |
j3 | 0:915a712ec85a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
j3 | 0:915a712ec85a | 7 | * of this software and associated documentation files (the "Software"), to deal |
j3 | 0:915a712ec85a | 8 | * in the Software without restriction, including without limitation the rights |
j3 | 0:915a712ec85a | 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
j3 | 0:915a712ec85a | 10 | * copies of the Software, and to permit persons to whom the Software is |
j3 | 0:915a712ec85a | 11 | * furnished to do so, subject to the following conditions: |
j3 | 0:915a712ec85a | 12 | |
j3 | 0:915a712ec85a | 13 | * The above copyright notice and this permission notice shall be included in all |
j3 | 0:915a712ec85a | 14 | * copies or substantial portions of the Software. |
j3 | 0:915a712ec85a | 15 | |
j3 | 0:915a712ec85a | 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
j3 | 0:915a712ec85a | 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
j3 | 0:915a712ec85a | 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
j3 | 0:915a712ec85a | 19 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
j3 | 0:915a712ec85a | 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
j3 | 0:915a712ec85a | 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
j3 | 0:915a712ec85a | 22 | * SOFTWARE. |
j3 | 0:915a712ec85a | 23 | ******************************************************************************/ |
j3 | 0:915a712ec85a | 24 | |
j3 | 0:915a712ec85a | 25 | |
j3 | 0:915a712ec85a | 26 | #ifndef _H3LIS331DL_H_ |
j3 | 0:915a712ec85a | 27 | #define _H3LIS331DL_H_ |
j3 | 0:915a712ec85a | 28 | |
j3 | 0:915a712ec85a | 29 | |
j3 | 0:915a712ec85a | 30 | #include "mbed.h" |
j3 | 0:915a712ec85a | 31 | |
j3 | 0:915a712ec85a | 32 | |
j3 | 0:915a712ec85a | 33 | /** |
j3 | 0:915a712ec85a | 34 | @brief The H3LIS331DL is a low-power highperformance 3-axis linear accelerometer |
j3 | 0:915a712ec85a | 35 | belonging to the “nano” family, with digital I2C/SPI serial interface standard |
j3 | 0:915a712ec85a | 36 | output. |
j3 | 0:915a712ec85a | 37 | */ |
j3 | 0:915a712ec85a | 38 | class H3LIS331DL |
j3 | 0:915a712ec85a | 39 | { |
j3 | 0:915a712ec85a | 40 | |
j3 | 0:915a712ec85a | 41 | public: |
j3 | 0:915a712ec85a | 42 | |
j3 | 0:915a712ec85a | 43 | static const uint8_t DEVICE_ID = 0x32; |
j3 | 0:915a712ec85a | 44 | |
j3 | 0:915a712ec85a | 45 | ///H3LIS331DL Register map |
j3 | 0:915a712ec85a | 46 | enum Register_e |
j3 | 0:915a712ec85a | 47 | { |
j3 | 0:915a712ec85a | 48 | WHO_AM_I = 0x0F, |
j3 | 0:915a712ec85a | 49 | CTRL_REG1 = 0x20, |
j3 | 0:915a712ec85a | 50 | CTRL_REG2 = 0x21, |
j3 | 0:915a712ec85a | 51 | CTRL_REG3 = 0x22, |
j3 | 0:915a712ec85a | 52 | CTRL_REG4 = 0x23, |
j3 | 0:915a712ec85a | 53 | CTRL_REG5 = 0x24, |
j3 | 0:915a712ec85a | 54 | HP_FILTER_RESET = 0x25, |
j3 | 0:915a712ec85a | 55 | REFERENCE = 0x26, |
j3 | 0:915a712ec85a | 56 | STATUS_REG = 0x27, |
j3 | 0:915a712ec85a | 57 | OUT_X_L = 0x28, |
j3 | 0:915a712ec85a | 58 | OUT_X_H = 0x29, |
j3 | 0:915a712ec85a | 59 | OUT_Y_L = 0x2A, |
j3 | 0:915a712ec85a | 60 | OUT_Y_H = 0x2B, |
j3 | 0:915a712ec85a | 61 | OUT_Z_L = 0x2C, |
j3 | 0:915a712ec85a | 62 | OUT_Z_H = 0x2D, |
j3 | 0:915a712ec85a | 63 | INT1_CFG = 0x30, |
j3 | 0:915a712ec85a | 64 | INT1_SRC = 0x31, |
j3 | 0:915a712ec85a | 65 | INT1_THS = 0x32, |
j3 | 0:915a712ec85a | 66 | INT1_DURATION = 0x33, |
j3 | 0:915a712ec85a | 67 | INT2_CFG = 0x34, |
j3 | 0:915a712ec85a | 68 | INT2_SRC = 0x35, |
j3 | 0:915a712ec85a | 69 | INT2_THS = 0x36, |
j3 | 0:915a712ec85a | 70 | INT2_DURATION = 0x37 |
j3 | 0:915a712ec85a | 71 | }; |
j3 | 0:915a712ec85a | 72 | |
j3 | 0:915a712ec85a | 73 | union CTRL_REG1_u |
j3 | 0:915a712ec85a | 74 | { |
j3 | 0:915a712ec85a | 75 | uint8_t all; |
j3 | 0:915a712ec85a | 76 | |
j3 | 0:915a712ec85a | 77 | struct BitField_s |
j3 | 0:915a712ec85a | 78 | { |
j3 | 0:915a712ec85a | 79 | uint8_t xen : 1; |
j3 | 0:915a712ec85a | 80 | uint8_t yen : 1; |
j3 | 0:915a712ec85a | 81 | uint8_t zen : 1; |
j3 | 0:915a712ec85a | 82 | uint8_t dr0 : 1; |
j3 | 0:915a712ec85a | 83 | uint8_t dr1 : 1; |
j3 | 0:915a712ec85a | 84 | uint8_t pm0 : 1; |
j3 | 0:915a712ec85a | 85 | uint8_t pm1 : 1; |
j3 | 0:915a712ec85a | 86 | uint8_t pm2 : 1; |
j3 | 0:915a712ec85a | 87 | }bits; |
j3 | 0:915a712ec85a | 88 | }; |
j3 | 0:915a712ec85a | 89 | |
j3 | 0:915a712ec85a | 90 | union CTRL_REG2_u |
j3 | 0:915a712ec85a | 91 | { |
j3 | 0:915a712ec85a | 92 | uint8_t all; |
j3 | 0:915a712ec85a | 93 | |
j3 | 0:915a712ec85a | 94 | struct BitField_s |
j3 | 0:915a712ec85a | 95 | { |
j3 | 0:915a712ec85a | 96 | uint8_t hpcf0 : 1; |
j3 | 0:915a712ec85a | 97 | uint8_t hpcf1 : 1; |
j3 | 0:915a712ec85a | 98 | uint8_t hpen1 : 1; |
j3 | 0:915a712ec85a | 99 | uint8_t hpen2 : 1; |
j3 | 0:915a712ec85a | 100 | uint8_t fds : 1; |
j3 | 0:915a712ec85a | 101 | uint8_t hpm0 : 1; |
j3 | 0:915a712ec85a | 102 | uint8_t hpm1 : 1; |
j3 | 0:915a712ec85a | 103 | uint8_t boot : 1; |
j3 | 0:915a712ec85a | 104 | }bits; |
j3 | 0:915a712ec85a | 105 | }; |
j3 | 0:915a712ec85a | 106 | |
j3 | 0:915a712ec85a | 107 | union CTRL_REG3_u |
j3 | 0:915a712ec85a | 108 | { |
j3 | 0:915a712ec85a | 109 | uint8_t all; |
j3 | 0:915a712ec85a | 110 | |
j3 | 0:915a712ec85a | 111 | struct BitField_s |
j3 | 0:915a712ec85a | 112 | { |
j3 | 0:915a712ec85a | 113 | uint8_t i1_cfg0 : 1; |
j3 | 0:915a712ec85a | 114 | uint8_t i1_cfg1 : 1; |
j3 | 0:915a712ec85a | 115 | uint8_t lir1 : 1; |
j3 | 0:915a712ec85a | 116 | uint8_t i2_cfg0 : 1; |
j3 | 0:915a712ec85a | 117 | uint8_t i2_cfg1 : 1; |
j3 | 0:915a712ec85a | 118 | uint8_t lir2 : 1; |
j3 | 0:915a712ec85a | 119 | uint8_t pp_od : 1; |
j3 | 0:915a712ec85a | 120 | uint8_t ihl : 1; |
j3 | 0:915a712ec85a | 121 | }bits; |
j3 | 0:915a712ec85a | 122 | }; |
j3 | 0:915a712ec85a | 123 | |
j3 | 0:915a712ec85a | 124 | union CTRL_REG4_u |
j3 | 0:915a712ec85a | 125 | { |
j3 | 0:915a712ec85a | 126 | uint8_t all; |
j3 | 0:915a712ec85a | 127 | |
j3 | 0:915a712ec85a | 128 | struct BitField_s |
j3 | 0:915a712ec85a | 129 | { |
j3 | 0:915a712ec85a | 130 | uint8_t sim : 1; |
j3 | 0:915a712ec85a | 131 | uint8_t res1 : 1; |
j3 | 0:915a712ec85a | 132 | uint8_t res2 : 1; |
j3 | 0:915a712ec85a | 133 | uint8_t res3 : 1; |
j3 | 0:915a712ec85a | 134 | uint8_t fs0 : 1; |
j3 | 0:915a712ec85a | 135 | uint8_t fs1 : 1; |
j3 | 0:915a712ec85a | 136 | uint8_t ble : 1; |
j3 | 0:915a712ec85a | 137 | uint8_t bdu : 1; |
j3 | 0:915a712ec85a | 138 | }bits; |
j3 | 0:915a712ec85a | 139 | }; |
j3 | 0:915a712ec85a | 140 | |
j3 | 0:915a712ec85a | 141 | union CTRL_REG5_u |
j3 | 0:915a712ec85a | 142 | { |
j3 | 0:915a712ec85a | 143 | uint8_t all; |
j3 | 0:915a712ec85a | 144 | |
j3 | 0:915a712ec85a | 145 | struct BitField_s |
j3 | 0:915a712ec85a | 146 | { |
j3 | 0:915a712ec85a | 147 | uint8_t turnOn0 : 1; |
j3 | 0:915a712ec85a | 148 | uint8_t turnOn1 : 1; |
j3 | 0:915a712ec85a | 149 | uint8_t res2 : 1; |
j3 | 0:915a712ec85a | 150 | uint8_t res3 : 1; |
j3 | 0:915a712ec85a | 151 | uint8_t res4 : 1; |
j3 | 0:915a712ec85a | 152 | uint8_t res5 : 1; |
j3 | 0:915a712ec85a | 153 | uint8_t res6 : 1; |
j3 | 0:915a712ec85a | 154 | uint8_t res7 : 1; |
j3 | 0:915a712ec85a | 155 | }bits; |
j3 | 0:915a712ec85a | 156 | }; |
j3 | 0:915a712ec85a | 157 | |
j3 | 0:915a712ec85a | 158 | union STATUS_REG_u |
j3 | 0:915a712ec85a | 159 | { |
j3 | 0:915a712ec85a | 160 | uint8_t all; |
j3 | 0:915a712ec85a | 161 | |
j3 | 0:915a712ec85a | 162 | struct BitField_s |
j3 | 0:915a712ec85a | 163 | { |
j3 | 0:915a712ec85a | 164 | uint8_t xda : 1; |
j3 | 0:915a712ec85a | 165 | uint8_t yda : 1; |
j3 | 0:915a712ec85a | 166 | uint8_t zda : 1; |
j3 | 0:915a712ec85a | 167 | uint8_t zyxda : 1; |
j3 | 0:915a712ec85a | 168 | uint8_t xor_ : 1; |
j3 | 0:915a712ec85a | 169 | uint8_t yor : 1; |
j3 | 0:915a712ec85a | 170 | uint8_t zor : 1; |
j3 | 0:915a712ec85a | 171 | uint8_t zyxor : 1; |
j3 | 0:915a712ec85a | 172 | }bits; |
j3 | 0:915a712ec85a | 173 | }; |
j3 | 0:915a712ec85a | 174 | |
j3 | 0:915a712ec85a | 175 | union INT_CFG_u |
j3 | 0:915a712ec85a | 176 | { |
j3 | 0:915a712ec85a | 177 | uint8_t all; |
j3 | 0:915a712ec85a | 178 | |
j3 | 0:915a712ec85a | 179 | struct BitField_s |
j3 | 0:915a712ec85a | 180 | { |
j3 | 0:915a712ec85a | 181 | uint8_t xlie : 1; |
j3 | 0:915a712ec85a | 182 | uint8_t xhie : 1; |
j3 | 0:915a712ec85a | 183 | uint8_t ylie : 1; |
j3 | 0:915a712ec85a | 184 | uint8_t yhie : 1; |
j3 | 0:915a712ec85a | 185 | uint8_t zlie : 1; |
j3 | 0:915a712ec85a | 186 | uint8_t zhie : 1; |
j3 | 0:915a712ec85a | 187 | uint8_t res6 : 1; |
j3 | 0:915a712ec85a | 188 | uint8_t aoi : 1; |
j3 | 0:915a712ec85a | 189 | }bits; |
j3 | 0:915a712ec85a | 190 | }; |
j3 | 0:915a712ec85a | 191 | |
j3 | 0:915a712ec85a | 192 | union INT_SRC_u |
j3 | 0:915a712ec85a | 193 | { |
j3 | 0:915a712ec85a | 194 | uint8_t all; |
j3 | 0:915a712ec85a | 195 | |
j3 | 0:915a712ec85a | 196 | struct BitField_s |
j3 | 0:915a712ec85a | 197 | { |
j3 | 0:915a712ec85a | 198 | uint8_t xl : 1; |
j3 | 0:915a712ec85a | 199 | uint8_t xh : 1; |
j3 | 0:915a712ec85a | 200 | uint8_t yl : 1; |
j3 | 0:915a712ec85a | 201 | uint8_t yh : 1; |
j3 | 0:915a712ec85a | 202 | uint8_t zl : 1; |
j3 | 0:915a712ec85a | 203 | uint8_t zh : 1; |
j3 | 0:915a712ec85a | 204 | uint8_t ia : 1; |
j3 | 0:915a712ec85a | 205 | uint8_t res7 : 1; |
j3 | 0:915a712ec85a | 206 | }bits; |
j3 | 0:915a712ec85a | 207 | }; |
j3 | 0:915a712ec85a | 208 | |
j3 | 0:915a712ec85a | 209 | struct ControlRegisters_s |
j3 | 0:915a712ec85a | 210 | { |
j3 | 0:915a712ec85a | 211 | CTRL_REG1_u reg1; |
j3 | 0:915a712ec85a | 212 | CTRL_REG2_u reg2; |
j3 | 0:915a712ec85a | 213 | CTRL_REG3_u reg3; |
j3 | 0:915a712ec85a | 214 | CTRL_REG4_u reg4; |
j3 | 0:915a712ec85a | 215 | CTRL_REG5_u reg5; |
j3 | 0:915a712ec85a | 216 | }; |
j3 | 0:915a712ec85a | 217 | |
j3 | 0:915a712ec85a | 218 | struct Axis_s |
j3 | 0:915a712ec85a | 219 | { |
j3 | 0:915a712ec85a | 220 | uint16_t x_axis; |
j3 | 0:915a712ec85a | 221 | uint16_t y_axis; |
j3 | 0:915a712ec85a | 222 | uint16_t z_axis; |
j3 | 0:915a712ec85a | 223 | }; |
j3 | 0:915a712ec85a | 224 | |
j3 | 0:915a712ec85a | 225 | struct InterruptConfig_s |
j3 | 0:915a712ec85a | 226 | { |
j3 | 0:915a712ec85a | 227 | INT_CFG_u cfg; |
j3 | 0:915a712ec85a | 228 | INT_SRC_u src; |
j3 | 0:915a712ec85a | 229 | uint8_t threshold; |
j3 | 0:915a712ec85a | 230 | uint8_t duration; |
j3 | 0:915a712ec85a | 231 | }; |
j3 | 0:915a712ec85a | 232 | |
j3 | 0:915a712ec85a | 233 | ///@brief Get the device id of the accelerometer. |
j3 | 0:915a712ec85a | 234 | /// |
j3 | 0:915a712ec85a | 235 | ///On Entry: |
j3 | 0:915a712ec85a | 236 | ///@param[in] data - Place holder for data |
j3 | 0:915a712ec85a | 237 | /// |
j3 | 0:915a712ec85a | 238 | ///On Exit: |
j3 | 0:915a712ec85a | 239 | ///@param[out] data - Device ID on success |
j3 | 0:915a712ec85a | 240 | /// |
j3 | 0:915a712ec85a | 241 | ///@returns 0 on success, non-0 otherwise |
j3 | 0:915a712ec85a | 242 | int32_t getDeviceId(uint8_t &data); |
j3 | 0:915a712ec85a | 243 | |
j3 | 0:915a712ec85a | 244 | ///@brief Read all 5 control registers. |
j3 | 0:915a712ec85a | 245 | /// |
j3 | 0:915a712ec85a | 246 | ///On Entry: |
j3 | 0:915a712ec85a | 247 | ///@param[in] controlRegisters - Reference to ControlRegisters_s object |
j3 | 0:915a712ec85a | 248 | /// |
j3 | 0:915a712ec85a | 249 | ///On Exit: |
j3 | 0:915a712ec85a | 250 | ///@param[out] controlRegisters - contents of control registers on success |
j3 | 0:915a712ec85a | 251 | /// |
j3 | 0:915a712ec85a | 252 | ///@returns 0 on success, non-0 otherwise |
j3 | 0:915a712ec85a | 253 | int32_t readControlRegisters(ControlRegisters_s &controlRegisters); |
j3 | 0:915a712ec85a | 254 | |
j3 | 0:915a712ec85a | 255 | ///@brief Write all 5 control registers. |
j3 | 0:915a712ec85a | 256 | /// |
j3 | 0:915a712ec85a | 257 | ///On Entry: |
j3 | 0:915a712ec85a | 258 | ///@param[in] controlRegisters - Reference to ControlRegisters_s object |
j3 | 0:915a712ec85a | 259 | /// containing configuration to write |
j3 | 0:915a712ec85a | 260 | /// |
j3 | 0:915a712ec85a | 261 | ///On Exit: |
j3 | 0:915a712ec85a | 262 | ///@param[out] none |
j3 | 0:915a712ec85a | 263 | /// |
j3 | 0:915a712ec85a | 264 | ///@returns 0 on success, non-0 otherwise |
j3 | 0:915a712ec85a | 265 | int32_t writeControlRegisters(const ControlRegisters_s &controlRegisters); |
j3 | 0:915a712ec85a | 266 | |
j3 | 0:915a712ec85a | 267 | ///@brief Resets High Pass Filter, if HPF is enabled, will 0 axis |
j3 | 0:915a712ec85a | 268 | /// |
j3 | 0:915a712ec85a | 269 | ///On Entry: |
j3 | 0:915a712ec85a | 270 | ///@param[in] none |
j3 | 0:915a712ec85a | 271 | /// |
j3 | 0:915a712ec85a | 272 | ///On Exit: |
j3 | 0:915a712ec85a | 273 | ///@param[out] none |
j3 | 0:915a712ec85a | 274 | /// |
j3 | 0:915a712ec85a | 275 | ///@returns 0 on success, non-0 otherwise |
j3 | 0:915a712ec85a | 276 | int32_t resetHPF(); |
j3 | 0:915a712ec85a | 277 | |
j3 | 0:915a712ec85a | 278 | ///@brief Read reference register |
j3 | 0:915a712ec85a | 279 | /// |
j3 | 0:915a712ec85a | 280 | ///On Entry: |
j3 | 0:915a712ec85a | 281 | ///@param[in] ref - byte for data |
j3 | 0:915a712ec85a | 282 | /// |
j3 | 0:915a712ec85a | 283 | ///On Exit: |
j3 | 0:915a712ec85a | 284 | ///@param[out] ref - contents of reference register on success |
j3 | 0:915a712ec85a | 285 | /// |
j3 | 0:915a712ec85a | 286 | ///@returns 0 on success, non-0 otherwise |
j3 | 0:915a712ec85a | 287 | int32_t readReferenceRegister(uint8_t &ref); |
j3 | 0:915a712ec85a | 288 | |
j3 | 0:915a712ec85a | 289 | ///@brief Writes reference register |
j3 | 0:915a712ec85a | 290 | /// |
j3 | 0:915a712ec85a | 291 | ///On Entry: |
j3 | 0:915a712ec85a | 292 | ///@param[in] ref - reference value to be writen |
j3 | 0:915a712ec85a | 293 | /// |
j3 | 0:915a712ec85a | 294 | ///On Exit: |
j3 | 0:915a712ec85a | 295 | ///@param[out] none |
j3 | 0:915a712ec85a | 296 | /// |
j3 | 0:915a712ec85a | 297 | ///@returns 0 on success, non-0 otherwise |
j3 | 0:915a712ec85a | 298 | int32_t writeReferenceRegister(const uint8_t ref); |
j3 | 0:915a712ec85a | 299 | |
j3 | 0:915a712ec85a | 300 | ///@brief Read status register |
j3 | 0:915a712ec85a | 301 | /// |
j3 | 0:915a712ec85a | 302 | ///On Entry: |
j3 | 0:915a712ec85a | 303 | ///@param[in] status - Object for holding status data |
j3 | 0:915a712ec85a | 304 | /// |
j3 | 0:915a712ec85a | 305 | ///On Exit: |
j3 | 0:915a712ec85a | 306 | ///@param[out] status - contents of status register on success |
j3 | 0:915a712ec85a | 307 | /// |
j3 | 0:915a712ec85a | 308 | ///@returns 0 on success, non-0 otherwise |
j3 | 0:915a712ec85a | 309 | int32_t readStatusRegister(STATUS_REG_u &status); |
j3 | 0:915a712ec85a | 310 | |
j3 | 0:915a712ec85a | 311 | ///@brief Writes status register |
j3 | 0:915a712ec85a | 312 | /// |
j3 | 0:915a712ec85a | 313 | ///On Entry: |
j3 | 0:915a712ec85a | 314 | ///@param[in] status - Object holding data to write |
j3 | 0:915a712ec85a | 315 | /// |
j3 | 0:915a712ec85a | 316 | ///On Exit: |
j3 | 0:915a712ec85a | 317 | ///@param[out] none |
j3 | 0:915a712ec85a | 318 | /// |
j3 | 0:915a712ec85a | 319 | ///@returns 0 on success, non-0 otherwise |
j3 | 0:915a712ec85a | 320 | int32_t writeStatusRegister(const STATUS_REG_u &status); |
j3 | 0:915a712ec85a | 321 | |
j3 | 0:915a712ec85a | 322 | ///@brief Reads all three axis |
j3 | 0:915a712ec85a | 323 | /// |
j3 | 0:915a712ec85a | 324 | ///On Entry: |
j3 | 0:915a712ec85a | 325 | ///@param[in] axis - object for holding data |
j3 | 0:915a712ec85a | 326 | /// |
j3 | 0:915a712ec85a | 327 | ///On Exit: |
j3 | 0:915a712ec85a | 328 | ///@param[out] axis - contents of registers on success |
j3 | 0:915a712ec85a | 329 | /// |
j3 | 0:915a712ec85a | 330 | ///@returns 0 on success, non-0 otherwise |
j3 | 0:915a712ec85a | 331 | int32_t readAxis(Axis_s &axis); |
j3 | 0:915a712ec85a | 332 | |
j3 | 0:915a712ec85a | 333 | ///@brief Reads interrupt one or two's config, src, threshold and duration |
j3 | 0:915a712ec85a | 334 | /// data. |
j3 | 0:915a712ec85a | 335 | /// |
j3 | 0:915a712ec85a | 336 | ///On Entry: |
j3 | 0:915a712ec85a | 337 | ///@param[in] cfg - Object to hold data |
j3 | 0:915a712ec85a | 338 | ///@param[in] oneOrTwo - Boolean representing which interrupt's data to read |
j3 | 0:915a712ec85a | 339 | /// |
j3 | 0:915a712ec85a | 340 | ///On Exit: |
j3 | 0:915a712ec85a | 341 | ///@param[out] cfg - Chosen interrupt's data on success |
j3 | 0:915a712ec85a | 342 | /// |
j3 | 0:915a712ec85a | 343 | ///@returns 0 on success, non-0 otherwise |
j3 | 0:915a712ec85a | 344 | int32_t readInterruptConfig(InterruptConfig_s &cfg, bool oneOrTwo); |
j3 | 0:915a712ec85a | 345 | |
j3 | 0:915a712ec85a | 346 | ///@brief Writes interrupt one or two's config, src, threshold and duration |
j3 | 0:915a712ec85a | 347 | /// data. |
j3 | 0:915a712ec85a | 348 | ///On Entry: |
j3 | 0:915a712ec85a | 349 | ///@param[in] cfg - Data to write |
j3 | 0:915a712ec85a | 350 | ///@param[in] oneOrTwo - Boolean representing which interrupt's data to |
j3 | 0:915a712ec85a | 351 | /// write |
j3 | 0:915a712ec85a | 352 | /// |
j3 | 0:915a712ec85a | 353 | ///On Exit: |
j3 | 0:915a712ec85a | 354 | ///@param[out] none |
j3 | 0:915a712ec85a | 355 | /// |
j3 | 0:915a712ec85a | 356 | ///@returns 0 on success, non-0 otherwise |
j3 | 0:915a712ec85a | 357 | int32_t writeInterruptConfig(const InterruptConfig_s &cfg, bool oneOrTwo); |
j3 | 0:915a712ec85a | 358 | |
j3 | 0:915a712ec85a | 359 | protected: |
j3 | 0:915a712ec85a | 360 | |
j3 | 0:915a712ec85a | 361 | ///@brief Read given register. |
j3 | 0:915a712ec85a | 362 | /// |
j3 | 0:915a712ec85a | 363 | ///On Entry: |
j3 | 0:915a712ec85a | 364 | ///@param[in] reg - Register to read. |
j3 | 0:915a712ec85a | 365 | /// |
j3 | 0:915a712ec85a | 366 | ///On Exit: |
j3 | 0:915a712ec85a | 367 | ///@param[out] data - Contents of register on success. |
j3 | 0:915a712ec85a | 368 | /// |
j3 | 0:915a712ec85a | 369 | ///@returns 0 on success, non-0 otherwise |
j3 | 0:915a712ec85a | 370 | virtual int32_t readRegister(Register_e reg, uint8_t &data) = 0; |
j3 | 0:915a712ec85a | 371 | |
j3 | 0:915a712ec85a | 372 | ///@brief Write given register. |
j3 | 0:915a712ec85a | 373 | /// |
j3 | 0:915a712ec85a | 374 | ///On Entry: |
j3 | 0:915a712ec85a | 375 | ///@param[in] reg - Register to write. |
j3 | 0:915a712ec85a | 376 | ///@param[in] data - Data to write. |
j3 | 0:915a712ec85a | 377 | /// |
j3 | 0:915a712ec85a | 378 | ///On Exit: |
j3 | 0:915a712ec85a | 379 | /// |
j3 | 0:915a712ec85a | 380 | ///@returns 0 on success, non-0 otherwise |
j3 | 0:915a712ec85a | 381 | virtual int32_t writeRegister(Register_e reg, const uint8_t data) = 0; |
j3 | 0:915a712ec85a | 382 | |
j3 | 0:915a712ec85a | 383 | ///@brief Read number of bytes starting at startReg |
j3 | 0:915a712ec85a | 384 | /// |
j3 | 0:915a712ec85a | 385 | ///On Entry: |
j3 | 0:915a712ec85a | 386 | ///@param[in] startReg - Register to start reading from. |
j3 | 0:915a712ec85a | 387 | ///@param[in] readLength - Number of bytes to read. |
j3 | 0:915a712ec85a | 388 | ///@param[in] data - Pointer to buffer for storing data |
j3 | 0:915a712ec85a | 389 | /// |
j3 | 0:915a712ec85a | 390 | ///On Exit: |
j3 | 0:915a712ec85a | 391 | ///@param[out] data - Contents of read registers on success. |
j3 | 0:915a712ec85a | 392 | /// |
j3 | 0:915a712ec85a | 393 | ///@returns 0 on success, non-0 otherwise |
j3 | 0:915a712ec85a | 394 | virtual int32_t readBlock(Register_e startReg, const uint8_t readLength, |
j3 | 0:915a712ec85a | 395 | uint8_t *data) = 0; |
j3 | 0:915a712ec85a | 396 | |
j3 | 0:915a712ec85a | 397 | ///@brief Write number of bytes starting at startReg |
j3 | 0:915a712ec85a | 398 | /// |
j3 | 0:915a712ec85a | 399 | ///On Entry: |
j3 | 0:915a712ec85a | 400 | ///@param[in] startReg - Register to start writing to. |
j3 | 0:915a712ec85a | 401 | ///@param[in] writeLength - Number of bytes to write. |
j3 | 0:915a712ec85a | 402 | ///@param[in] data - Pointer to write data buffer |
j3 | 0:915a712ec85a | 403 | /// |
j3 | 0:915a712ec85a | 404 | ///On Exit: |
j3 | 0:915a712ec85a | 405 | /// |
j3 | 0:915a712ec85a | 406 | ///@returns 0 on success, non-0 otherwise |
j3 | 0:915a712ec85a | 407 | virtual int32_t writeBlock(Register_e startReg, const uint8_t writeLength, |
j3 | 0:915a712ec85a | 408 | const uint8_t *data) = 0; |
j3 | 0:915a712ec85a | 409 | }; |
j3 | 0:915a712ec85a | 410 | |
j3 | 0:915a712ec85a | 411 | |
j3 | 0:915a712ec85a | 412 | /** |
j3 | 0:915a712ec85a | 413 | @brief H3LIS331DL type for I2C interface |
j3 | 0:915a712ec85a | 414 | */ |
j3 | 0:915a712ec85a | 415 | class H3LIS331DL_I2C: public H3LIS331DL |
j3 | 0:915a712ec85a | 416 | { |
j3 | 0:915a712ec85a | 417 | |
j3 | 0:915a712ec85a | 418 | public: |
j3 | 0:915a712ec85a | 419 | |
j3 | 0:915a712ec85a | 420 | H3LIS331DL_I2C(I2C &i2cBus, uint8_t slvAdrs); |
j3 | 0:915a712ec85a | 421 | |
j3 | 0:915a712ec85a | 422 | ~H3LIS331DL_I2C(){} |
j3 | 0:915a712ec85a | 423 | |
j3 | 0:915a712ec85a | 424 | private: |
j3 | 0:915a712ec85a | 425 | |
j3 | 0:915a712ec85a | 426 | virtual int32_t readRegister(Register_e reg, uint8_t &data); |
j3 | 0:915a712ec85a | 427 | |
j3 | 0:915a712ec85a | 428 | virtual int32_t writeRegister(Register_e reg, const uint8_t data); |
j3 | 0:915a712ec85a | 429 | |
j3 | 0:915a712ec85a | 430 | virtual int32_t readBlock(Register_e startReg, const uint8_t readLength, |
j3 | 0:915a712ec85a | 431 | uint8_t *data); |
j3 | 0:915a712ec85a | 432 | |
j3 | 0:915a712ec85a | 433 | virtual int32_t writeBlock(Register_e startReg, const uint8_t writeLength, |
j3 | 0:915a712ec85a | 434 | const uint8_t *data); |
j3 | 0:915a712ec85a | 435 | |
j3 | 0:915a712ec85a | 436 | I2C m_i2cBus; |
j3 | 0:915a712ec85a | 437 | uint8_t m_w_adrs, m_r_adrs; |
j3 | 0:915a712ec85a | 438 | }; |
j3 | 0:915a712ec85a | 439 | |
j3 | 0:915a712ec85a | 440 | |
j3 | 0:915a712ec85a | 441 | /** |
j3 | 0:915a712ec85a | 442 | @brief H3LIS331DL type for SPI interface |
j3 | 0:915a712ec85a | 443 | */ |
j3 | 0:915a712ec85a | 444 | class H3LIS331DL_SPI: public H3LIS331DL |
j3 | 0:915a712ec85a | 445 | { |
j3 | 0:915a712ec85a | 446 | |
j3 | 0:915a712ec85a | 447 | public: |
j3 | 0:915a712ec85a | 448 | |
j3 | 0:915a712ec85a | 449 | static const uint8_t R_BIT = 0x80; |
j3 | 0:915a712ec85a | 450 | static const uint8_t AUTO_INC_BIT = 0x40; |
j3 | 0:915a712ec85a | 451 | |
j3 | 0:915a712ec85a | 452 | H3LIS331DL_SPI(SPI &spiBus, PinName cs); |
j3 | 0:915a712ec85a | 453 | |
j3 | 0:915a712ec85a | 454 | ~H3LIS331DL_SPI(){} |
j3 | 0:915a712ec85a | 455 | |
j3 | 0:915a712ec85a | 456 | private: |
j3 | 0:915a712ec85a | 457 | |
j3 | 0:915a712ec85a | 458 | virtual int32_t readRegister(Register_e reg, uint8_t &data); |
j3 | 0:915a712ec85a | 459 | |
j3 | 0:915a712ec85a | 460 | virtual int32_t writeRegister(Register_e reg, const uint8_t data); |
j3 | 0:915a712ec85a | 461 | |
j3 | 0:915a712ec85a | 462 | virtual int32_t readBlock(Register_e startReg, const uint8_t readLength, |
j3 | 0:915a712ec85a | 463 | uint8_t *data); |
j3 | 0:915a712ec85a | 464 | |
j3 | 0:915a712ec85a | 465 | virtual int32_t writeBlock(Register_e startReg, const uint8_t writeLength, |
j3 | 0:915a712ec85a | 466 | const uint8_t *data); |
j3 | 0:915a712ec85a | 467 | |
j3 | 0:915a712ec85a | 468 | SPI m_spiBus; |
j3 | 0:915a712ec85a | 469 | DigitalOut m_cs; |
j3 | 0:915a712ec85a | 470 | }; |
j3 | 0:915a712ec85a | 471 | |
j3 | 0:915a712ec85a | 472 | #endif /*_H3LIS331DL_H_*/ |
j3 | 0:915a712ec85a | 473 | |
j3 | 0:915a712ec85a | 474 | ///@brief fx documentation template.\n |
j3 | 0:915a712ec85a | 475 | /// |
j3 | 0:915a712ec85a | 476 | ///On Entry: |
j3 | 0:915a712ec85a | 477 | ///@param[in] none |
j3 | 0:915a712ec85a | 478 | /// |
j3 | 0:915a712ec85a | 479 | ///On Exit: |
j3 | 0:915a712ec85a | 480 | ///@param[out] none |
j3 | 0:915a712ec85a | 481 | /// |
j3 | 0:915a712ec85a | 482 | ///@returns none |