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utility/enc28j60.h@1:01c2344f98a3, 2014-11-20 (annotated)

Committer:
hudakz
Date:
Thu Nov 20 21:26:54 2014 +0000
Revision:
1:01c2344f98a3
Parent:
uitility/enc28j60.h@0:5350a66d5279 
rev. 01

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UserRevisionLine numberNew contents of line
hudakz 0:5350a66d5279 1 /*****************************************************************************
hudakz 0:5350a66d5279 2 *
hudakz 0:5350a66d5279 3 * Title : Microchip ENC28J60 Ethernet Interface Driver
hudakz 0:5350a66d5279 4 * Author : Pascal Stang (c)2005
hudakz 0:5350a66d5279 5 * Modified by Norbert Truchsess
hudakz 0:5350a66d5279 6 * Copyright: GPL V2
hudakz 0:5350a66d5279 7 *
hudakz 0:5350a66d5279 8 *This driver provides initialization and transmit/receive
hudakz 0:5350a66d5279 9 *functions for the Microchip ENC28J60 10Mb Ethernet Controller and PHY.
hudakz 0:5350a66d5279 10 *This chip is novel in that it is a full MAC+PHY interface all in a 28-pin
hudakz 0:5350a66d5279 11 *chip, using an SPI interface to the host processor.
hudakz 0:5350a66d5279 12 *
hudakz 0:5350a66d5279 13 *
hudakz 0:5350a66d5279 14 *****************************************************************************/
hudakz 0:5350a66d5279 15 #ifndef ENC28J60_H
hudakz 0:5350a66d5279 16 #define ENC28J60_H
hudakz 0:5350a66d5279 17 #include <inttypes.h>
hudakz 0:5350a66d5279 18
hudakz 0:5350a66d5279 19 // ENC28J60 Control Registers
hudakz 0:5350a66d5279 20
hudakz 0:5350a66d5279 21 // Control register definitions are a combination of address,
hudakz 0:5350a66d5279 22 // bank number, and Ethernet/MAC/PHY indicator bits.
hudakz 0:5350a66d5279 23 // - Register address (bits 0-4)
hudakz 0:5350a66d5279 24 // - Bank number (bits 5-6)
hudakz 0:5350a66d5279 25 // - MAC/PHY indicator (bit 7)
hudakz 0:5350a66d5279 26 #define ADDR_MASK 0x1F
hudakz 0:5350a66d5279 27 #define BANK_MASK 0x60
hudakz 0:5350a66d5279 28 #define SPRD_MASK 0x80
hudakz 0:5350a66d5279 29 // All-bank registers
hudakz 0:5350a66d5279 30
hudakz 0:5350a66d5279 31 #define EIE 0x1B
hudakz 0:5350a66d5279 32 #define EIR 0x1C
hudakz 0:5350a66d5279 33 #define ESTAT 0x1D
hudakz 0:5350a66d5279 34 #define ECON2 0x1E
hudakz 0:5350a66d5279 35 #define ECON1 0x1F
hudakz 0:5350a66d5279 36 // Bank 0 registers
hudakz 0:5350a66d5279 37
hudakz 0:5350a66d5279 38 #define ERDPTL (0x00 | 0x00)
hudakz 0:5350a66d5279 39 #define ERDPTH (0x01 | 0x00)
hudakz 0:5350a66d5279 40 #define EWRPTL (0x02 | 0x00)
hudakz 0:5350a66d5279 41 #define EWRPTH (0x03 | 0x00)
hudakz 0:5350a66d5279 42 #define ETXSTL (0x04 | 0x00)
hudakz 0:5350a66d5279 43 #define ETXSTH (0x05 | 0x00)
hudakz 0:5350a66d5279 44 #define ETXNDL (0x06 | 0x00)
hudakz 0:5350a66d5279 45 #define ETXNDH (0x07 | 0x00)
hudakz 0:5350a66d5279 46 #define ERXSTL (0x08 | 0x00)
hudakz 0:5350a66d5279 47 #define ERXSTH (0x09 | 0x00)
hudakz 0:5350a66d5279 48 #define ERXNDL (0x0A | 0x00)
hudakz 0:5350a66d5279 49 #define ERXNDH (0x0B | 0x00)
hudakz 0:5350a66d5279 50 #define ERXRDPTL (0x0C | 0x00)
hudakz 0:5350a66d5279 51 #define ERXRDPTH (0x0D | 0x00)
hudakz 0:5350a66d5279 52 #define ERXWRPTL (0x0E | 0x00)
hudakz 0:5350a66d5279 53 #define ERXWRPTH (0x0F | 0x00)
hudakz 0:5350a66d5279 54 #define EDMASTL (0x10 | 0x00)
hudakz 0:5350a66d5279 55 #define EDMASTH (0x11 | 0x00)
hudakz 0:5350a66d5279 56 #define EDMANDL (0x12 | 0x00)
hudakz 0:5350a66d5279 57 #define EDMANDH (0x13 | 0x00)
hudakz 0:5350a66d5279 58 #define EDMADSTL (0x14 | 0x00)
hudakz 0:5350a66d5279 59 #define EDMADSTH (0x15 | 0x00)
hudakz 0:5350a66d5279 60 #define EDMACSL (0x16 | 0x00)
hudakz 0:5350a66d5279 61 #define EDMACSH (0x17 | 0x00)
hudakz 0:5350a66d5279 62 // Bank 1 registers
hudakz 0:5350a66d5279 63
hudakz 0:5350a66d5279 64 #define EHT0 (0x00 | 0x20)
hudakz 0:5350a66d5279 65 #define EHT1 (0x01 | 0x20)
hudakz 0:5350a66d5279 66 #define EHT2 (0x02 | 0x20)
hudakz 0:5350a66d5279 67 #define EHT3 (0x03 | 0x20)
hudakz 0:5350a66d5279 68 #define EHT4 (0x04 | 0x20)
hudakz 0:5350a66d5279 69 #define EHT5 (0x05 | 0x20)
hudakz 0:5350a66d5279 70 #define EHT6 (0x06 | 0x20)
hudakz 0:5350a66d5279 71 #define EHT7 (0x07 | 0x20)
hudakz 0:5350a66d5279 72 #define EPMM0 (0x08 | 0x20)
hudakz 0:5350a66d5279 73 #define EPMM1 (0x09 | 0x20)
hudakz 0:5350a66d5279 74 #define EPMM2 (0x0A | 0x20)
hudakz 0:5350a66d5279 75 #define EPMM3 (0x0B | 0x20)
hudakz 0:5350a66d5279 76 #define EPMM4 (0x0C | 0x20)
hudakz 0:5350a66d5279 77 #define EPMM5 (0x0D | 0x20)
hudakz 0:5350a66d5279 78 #define EPMM6 (0x0E | 0x20)
hudakz 0:5350a66d5279 79 #define EPMM7 (0x0F | 0x20)
hudakz 0:5350a66d5279 80 #define EPMCSL (0x10 | 0x20)
hudakz 0:5350a66d5279 81 #define EPMCSH (0x11 | 0x20)
hudakz 0:5350a66d5279 82 #define EPMOL (0x14 | 0x20)
hudakz 0:5350a66d5279 83 #define EPMOH (0x15 | 0x20)
hudakz 0:5350a66d5279 84 #define EWOLIE (0x16 | 0x20)
hudakz 0:5350a66d5279 85 #define EWOLIR (0x17 | 0x20)
hudakz 0:5350a66d5279 86 #define ERXFCON (0x18 | 0x20)
hudakz 0:5350a66d5279 87 #define EPKTCNT (0x19 | 0x20)
hudakz 0:5350a66d5279 88 // Bank 2 registers
hudakz 0:5350a66d5279 89
hudakz 0:5350a66d5279 90 #define MACON1 (0x00 | 0x40 | 0x80)
hudakz 0:5350a66d5279 91 #define MACON2 (0x01 | 0x40 | 0x80)
hudakz 0:5350a66d5279 92 #define MACON3 (0x02 | 0x40 | 0x80)
hudakz 0:5350a66d5279 93 #define MACON4 (0x03 | 0x40 | 0x80)
hudakz 0:5350a66d5279 94 #define MABBIPG (0x04 | 0x40 | 0x80)
hudakz 0:5350a66d5279 95 #define MAIPGL (0x06 | 0x40 | 0x80)
hudakz 0:5350a66d5279 96 #define MAIPGH (0x07 | 0x40 | 0x80)
hudakz 0:5350a66d5279 97 #define MACLCON1 (0x08 | 0x40 | 0x80)
hudakz 0:5350a66d5279 98 #define MACLCON2 (0x09 | 0x40 | 0x80)
hudakz 0:5350a66d5279 99 #define MAMXFLL (0x0A | 0x40 | 0x80)
hudakz 0:5350a66d5279 100 #define MAMXFLH (0x0B | 0x40 | 0x80)
hudakz 0:5350a66d5279 101 #define MAPHSUP (0x0D | 0x40 | 0x80)
hudakz 0:5350a66d5279 102 #define MICON (0x11 | 0x40 | 0x80)
hudakz 0:5350a66d5279 103 #define MICMD (0x12 | 0x40 | 0x80)
hudakz 0:5350a66d5279 104 #define MIREGADR (0x14 | 0x40 | 0x80)
hudakz 0:5350a66d5279 105 #define MIWRL (0x16 | 0x40 | 0x80)
hudakz 0:5350a66d5279 106 #define MIWRH (0x17 | 0x40 | 0x80)
hudakz 0:5350a66d5279 107 #define MIRDL (0x18 | 0x40 | 0x80)
hudakz 0:5350a66d5279 108 #define MIRDH (0x19 | 0x40 | 0x80)
hudakz 0:5350a66d5279 109 // Bank 3 registers
hudakz 0:5350a66d5279 110
hudakz 0:5350a66d5279 111 #define MAADR1 (0x00 | 0x60 | 0x80)
hudakz 0:5350a66d5279 112 #define MAADR0 (0x01 | 0x60 | 0x80)
hudakz 0:5350a66d5279 113 #define MAADR3 (0x02 | 0x60 | 0x80)
hudakz 0:5350a66d5279 114 #define MAADR2 (0x03 | 0x60 | 0x80)
hudakz 0:5350a66d5279 115 #define MAADR5 (0x04 | 0x60 | 0x80)
hudakz 0:5350a66d5279 116 #define MAADR4 (0x05 | 0x60 | 0x80)
hudakz 0:5350a66d5279 117 #define EBSTSD (0x06 | 0x60)
hudakz 0:5350a66d5279 118 #define EBSTCON (0x07 | 0x60)
hudakz 0:5350a66d5279 119 #define EBSTCSL (0x08 | 0x60)
hudakz 0:5350a66d5279 120 #define EBSTCSH (0x09 | 0x60)
hudakz 0:5350a66d5279 121 #define MISTAT (0x0A | 0x60 | 0x80)
hudakz 0:5350a66d5279 122 #define EREVID (0x12 | 0x60)
hudakz 0:5350a66d5279 123 #define ECOCON (0x15 | 0x60)
hudakz 0:5350a66d5279 124 #define EFLOCON (0x17 | 0x60)
hudakz 0:5350a66d5279 125 #define EPAUSL (0x18 | 0x60)
hudakz 0:5350a66d5279 126 #define EPAUSH (0x19 | 0x60)
hudakz 0:5350a66d5279 127 // PHY registers
hudakz 0:5350a66d5279 128
hudakz 0:5350a66d5279 129 #define PHCON1 0x00
hudakz 0:5350a66d5279 130 #define PHSTAT1 0x01
hudakz 0:5350a66d5279 131 #define PHHID1 0x02
hudakz 0:5350a66d5279 132 #define PHHID2 0x03
hudakz 0:5350a66d5279 133 #define PHCON2 0x10
hudakz 0:5350a66d5279 134 #define PHSTAT2 0x11
hudakz 0:5350a66d5279 135 #define PHIE 0x12
hudakz 0:5350a66d5279 136 #define PHIR 0x13
hudakz 0:5350a66d5279 137 #define PHLCON 0x14
hudakz 0:5350a66d5279 138
hudakz 0:5350a66d5279 139 // ENC28J60 ERXFCON Register Bit Definitions
hudakz 0:5350a66d5279 140
hudakz 0:5350a66d5279 141 #define ERXFCON_UCEN 0x80
hudakz 0:5350a66d5279 142 #define ERXFCON_ANDOR 0x40
hudakz 0:5350a66d5279 143 #define ERXFCON_CRCEN 0x20
hudakz 0:5350a66d5279 144 #define ERXFCON_PMEN 0x10
hudakz 0:5350a66d5279 145 #define ERXFCON_MPEN 0x08
hudakz 0:5350a66d5279 146 #define ERXFCON_HTEN 0x04
hudakz 0:5350a66d5279 147 #define ERXFCON_MCEN 0x02
hudakz 0:5350a66d5279 148 #define ERXFCON_BCEN 0x01
hudakz 0:5350a66d5279 149 // ENC28J60 EIE Register Bit Definitions
hudakz 0:5350a66d5279 150
hudakz 0:5350a66d5279 151 #define EIE_INTIE 0x80
hudakz 0:5350a66d5279 152 #define EIE_PKTIE 0x40
hudakz 0:5350a66d5279 153 #define EIE_DMAIE 0x20
hudakz 0:5350a66d5279 154 #define EIE_LINKIE 0x10
hudakz 0:5350a66d5279 155 #define EIE_TXIE 0x08
hudakz 0:5350a66d5279 156 #define EIE_WOLIE 0x04
hudakz 0:5350a66d5279 157 #define EIE_TXERIE 0x02
hudakz 0:5350a66d5279 158 #define EIE_RXERIE 0x01
hudakz 0:5350a66d5279 159 // ENC28J60 EIR Register Bit Definitions
hudakz 0:5350a66d5279 160
hudakz 0:5350a66d5279 161 #define EIR_PKTIF 0x40
hudakz 0:5350a66d5279 162 #define EIR_DMAIF 0x20
hudakz 0:5350a66d5279 163 #define EIR_LINKIF 0x10
hudakz 0:5350a66d5279 164 #define EIR_TXIF 0x08
hudakz 0:5350a66d5279 165 #define EIR_WOLIF 0x04
hudakz 0:5350a66d5279 166 #define EIR_TXERIF 0x02
hudakz 0:5350a66d5279 167 #define EIR_RXERIF 0x01
hudakz 0:5350a66d5279 168 // ENC28J60 ESTAT Register Bit Definitions
hudakz 0:5350a66d5279 169
hudakz 0:5350a66d5279 170 #define ESTAT_INT 0x80
hudakz 0:5350a66d5279 171 #define ESTAT_LATECOL 0x10
hudakz 0:5350a66d5279 172 #define ESTAT_RXBUSY 0x04
hudakz 0:5350a66d5279 173 #define ESTAT_TXABRT 0x02
hudakz 0:5350a66d5279 174 #define ESTAT_CLKRDY 0x01
hudakz 0:5350a66d5279 175 // ENC28J60 ECON2 Register Bit Definitions
hudakz 0:5350a66d5279 176
hudakz 0:5350a66d5279 177 #define ECON2_AUTOINC 0x80
hudakz 0:5350a66d5279 178 #define ECON2_PKTDEC 0x40
hudakz 0:5350a66d5279 179 #define ECON2_PWRSV 0x20
hudakz 0:5350a66d5279 180 #define ECON2_VRPS 0x08
hudakz 0:5350a66d5279 181 // ENC28J60 ECON1 Register Bit Definitions
hudakz 0:5350a66d5279 182
hudakz 0:5350a66d5279 183 #define ECON1_TXRST 0x80
hudakz 0:5350a66d5279 184 #define ECON1_RXRST 0x40
hudakz 0:5350a66d5279 185 #define ECON1_DMAST 0x20
hudakz 0:5350a66d5279 186 #define ECON1_CSUMEN 0x10
hudakz 0:5350a66d5279 187 #define ECON1_TXRTS 0x08
hudakz 0:5350a66d5279 188 #define ECON1_RXEN 0x04
hudakz 0:5350a66d5279 189 #define ECON1_BSEL1 0x02
hudakz 0:5350a66d5279 190 #define ECON1_BSEL0 0x01
hudakz 0:5350a66d5279 191 // ENC28J60 MACON1 Register Bit Definitions
hudakz 0:5350a66d5279 192
hudakz 0:5350a66d5279 193 #define MACON1_LOOPBK 0x10
hudakz 0:5350a66d5279 194 #define MACON1_TXPAUS 0x08
hudakz 0:5350a66d5279 195 #define MACON1_RXPAUS 0x04
hudakz 0:5350a66d5279 196 #define MACON1_PASSALL 0x02
hudakz 0:5350a66d5279 197 #define MACON1_MARXEN 0x01
hudakz 0:5350a66d5279 198 // ENC28J60 MACON2 Register Bit Definitions
hudakz 0:5350a66d5279 199
hudakz 0:5350a66d5279 200 #define MACON2_MARST 0x80
hudakz 0:5350a66d5279 201 #define MACON2_RNDRST 0x40
hudakz 0:5350a66d5279 202 #define MACON2_MARXRST 0x08
hudakz 0:5350a66d5279 203 #define MACON2_RFUNRST 0x04
hudakz 0:5350a66d5279 204 #define MACON2_MATXRST 0x02
hudakz 0:5350a66d5279 205 #define MACON2_TFUNRST 0x01
hudakz 0:5350a66d5279 206 // ENC28J60 MACON3 Register Bit Definitions
hudakz 0:5350a66d5279 207
hudakz 0:5350a66d5279 208 #define MACON3_PADCFG2 0x80
hudakz 0:5350a66d5279 209 #define MACON3_PADCFG1 0x40
hudakz 0:5350a66d5279 210 #define MACON3_PADCFG0 0x20
hudakz 0:5350a66d5279 211 #define MACON3_TXCRCEN 0x10
hudakz 0:5350a66d5279 212 #define MACON3_PHDRLEN 0x08
hudakz 0:5350a66d5279 213 #define MACON3_HFRMLEN 0x04
hudakz 0:5350a66d5279 214 #define MACON3_FRMLNEN 0x02
hudakz 0:5350a66d5279 215 #define MACON3_FULDPX 0x01
hudakz 0:5350a66d5279 216 // ENC28J60 MICMD Register Bit Definitions
hudakz 0:5350a66d5279 217
hudakz 0:5350a66d5279 218 #define MICMD_MIISCAN 0x02
hudakz 0:5350a66d5279 219 #define MICMD_MIIRD 0x01
hudakz 0:5350a66d5279 220 // ENC28J60 MISTAT Register Bit Definitions
hudakz 0:5350a66d5279 221
hudakz 0:5350a66d5279 222 #define MISTAT_NVALID 0x04
hudakz 0:5350a66d5279 223 #define MISTAT_SCAN 0x02
hudakz 0:5350a66d5279 224 #define MISTAT_BUSY 0x01
hudakz 0:5350a66d5279 225 // ENC28J60 PHY PHCON1 Register Bit Definitions
hudakz 0:5350a66d5279 226
hudakz 0:5350a66d5279 227 #define PHCON1_PRST 0x8000
hudakz 0:5350a66d5279 228 #define PHCON1_PLOOPBK 0x4000
hudakz 0:5350a66d5279 229 #define PHCON1_PPWRSV 0x0800
hudakz 0:5350a66d5279 230 #define PHCON1_PDPXMD 0x0100
hudakz 0:5350a66d5279 231 // ENC28J60 PHY PHSTAT1 Register Bit Definitions
hudakz 0:5350a66d5279 232
hudakz 0:5350a66d5279 233 #define PHSTAT1_PFDPX 0x1000
hudakz 0:5350a66d5279 234 #define PHSTAT1_PHDPX 0x0800
hudakz 0:5350a66d5279 235 #define PHSTAT1_LLSTAT 0x0004
hudakz 0:5350a66d5279 236 #define PHSTAT1_JBSTAT 0x0002
hudakz 0:5350a66d5279 237 // ENC28J60 PHY PHCON2 Register Bit Definitions
hudakz 0:5350a66d5279 238
hudakz 0:5350a66d5279 239 #define PHCON2_FRCLINK 0x4000
hudakz 0:5350a66d5279 240 #define PHCON2_TXDIS 0x2000
hudakz 0:5350a66d5279 241 #define PHCON2_JABBER 0x0400
hudakz 0:5350a66d5279 242 #define PHCON2_HDLDIS 0x0100
hudakz 0:5350a66d5279 243
hudakz 0:5350a66d5279 244 // ENC28J60 Packet Control Byte Bit Definitions
hudakz 0:5350a66d5279 245
hudakz 0:5350a66d5279 246 #define PKTCTRL_PHUGEEN 0x08
hudakz 0:5350a66d5279 247 #define PKTCTRL_PPADEN 0x04
hudakz 0:5350a66d5279 248 #define PKTCTRL_PCRCEN 0x02
hudakz 0:5350a66d5279 249 #define PKTCTRL_POVERRIDE 0x01
hudakz 0:5350a66d5279 250
hudakz 0:5350a66d5279 251 // SPI operation codes
hudakz 0:5350a66d5279 252
hudakz 0:5350a66d5279 253 #define ENC28J60_READ_CTRL_REG 0x00
hudakz 0:5350a66d5279 254 #define ENC28J60_READ_BUF_MEM 0x3A
hudakz 0:5350a66d5279 255 #define ENC28J60_WRITE_CTRL_REG 0x40
hudakz 0:5350a66d5279 256 #define ENC28J60_WRITE_BUF_MEM 0x7A
hudakz 0:5350a66d5279 257 #define ENC28J60_BIT_FIELD_SET 0x80
hudakz 0:5350a66d5279 258 #define ENC28J60_BIT_FIELD_CLR 0xA0
hudakz 0:5350a66d5279 259 #define ENC28J60_SOFT_RESET 0xFF
hudakz 0:5350a66d5279 260
hudakz 0:5350a66d5279 261 // The RXSTART_INIT should be zero. See Rev. B4 Silicon Errata
hudakz 0:5350a66d5279 262
hudakz 0:5350a66d5279 263 // buffer boundaries applied to internal 8K ram
hudakz 0:5350a66d5279 264 // the entire available packet buffer space is allocated
hudakz 0:5350a66d5279 265 //
hudakz 0:5350a66d5279 266 // start with recbuf at 0/
hudakz 0:5350a66d5279 267 #define RXSTART_INIT 0x0
hudakz 0:5350a66d5279 268 // receive buffer end. make sure this is an odd value ( See Rev. B1,B4,B5,B7 Silicon Errata 'Memory (Ethernet Buffer)')
hudakz 0:5350a66d5279 269
hudakz 0:5350a66d5279 270 #define RXSTOP_INIT (0x1FFF - 0x1800)
hudakz 0:5350a66d5279 271 // start TX buffer RXSTOP_INIT+1
hudakz 0:5350a66d5279 272
hudakz 0:5350a66d5279 273 #define TXSTART_INIT (RXSTOP_INIT + 1)
hudakz 0:5350a66d5279 274 // stp TX buffer at end of mem
hudakz 0:5350a66d5279 275
hudakz 0:5350a66d5279 276 #define TXSTOP_INIT 0x1FFF
hudakz 0:5350a66d5279 277 //
hudakz 0:5350a66d5279 278
hudakz 0:5350a66d5279 279 // max frame length which the conroller will accept:
hudakz 0:5350a66d5279 280 #define MAX_FRAMELEN 1500 // (note: maximum ethernet frame length would be 1518)
hudakz 0:5350a66d5279 281
hudakz 0:5350a66d5279 282 //#define MAX_FRAMELEN 600
hudakz 0:5350a66d5279 283 #endif