David Lakata / Mbed 2 deprecated QuadTrio

ESE350 project, Spring 2016, University of Pennsylvania

Dependencies:   Adafruit9-DOf Receiver mbed-rtos mbed

MRF24J40/MRF24J40.cpp@51:b6d76a4dfae8, 2016-05-07 (annotated)

Committer:
ivo_david_michelle
Date:
Sat May 07 17:47:22 2016 +0000
Revision:
51:b6d76a4dfae8
Parent:
14:64b06476d943 
publishing

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ivo_david_michelle 14:64b06476d943 1 /* mbed MRF24J40 (IEEE 802.15.4 tranceiver) Library
ivo_david_michelle 14:64b06476d943 2 * Copyright (c) 2011 Jeroen Hilgers
ivo_david_michelle 14:64b06476d943 3 *
ivo_david_michelle 14:64b06476d943 4 * Permission is hereby granted, free of charge, to any person obtaining a copy
ivo_david_michelle 14:64b06476d943 5 * of this software and associated documentation files (the "Software"), to deal
ivo_david_michelle 14:64b06476d943 6 * in the Software without restriction, including without limitation the rights
ivo_david_michelle 14:64b06476d943 7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
ivo_david_michelle 14:64b06476d943 8 * copies of the Software, and to permit persons to whom the Software is
ivo_david_michelle 14:64b06476d943 9 * furnished to do so, subject to the following conditions:
ivo_david_michelle 14:64b06476d943 10 *
ivo_david_michelle 14:64b06476d943 11 * The above copyright notice and this permission notice shall be included in
ivo_david_michelle 14:64b06476d943 12 * all copies or substantial portions of the Software.
ivo_david_michelle 14:64b06476d943 13 *
ivo_david_michelle 14:64b06476d943 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
ivo_david_michelle 14:64b06476d943 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
ivo_david_michelle 14:64b06476d943 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
ivo_david_michelle 14:64b06476d943 17 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
ivo_david_michelle 14:64b06476d943 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
ivo_david_michelle 14:64b06476d943 19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
ivo_david_michelle 14:64b06476d943 20 * THE SOFTWARE.
ivo_david_michelle 14:64b06476d943 21 */
ivo_david_michelle 14:64b06476d943 22
ivo_david_michelle 14:64b06476d943 23 #include "MRF24J40.h"
ivo_david_michelle 14:64b06476d943 24
ivo_david_michelle 14:64b06476d943 25 // MRF20J40 Short address control register mapping.
ivo_david_michelle 14:64b06476d943 26 #define RXMCR 0x00
ivo_david_michelle 14:64b06476d943 27 #define PANIDL 0x01
ivo_david_michelle 14:64b06476d943 28 #define PANIDH 0x02
ivo_david_michelle 14:64b06476d943 29 #define SADRL 0x03
ivo_david_michelle 14:64b06476d943 30 #define SADRH 0x04
ivo_david_michelle 14:64b06476d943 31 #define EADR0 0x05
ivo_david_michelle 14:64b06476d943 32 #define EADR1 0x06
ivo_david_michelle 14:64b06476d943 33 #define EADR2 0x07
ivo_david_michelle 14:64b06476d943 34 #define EADR3 0x08
ivo_david_michelle 14:64b06476d943 35 #define EADR4 0x09
ivo_david_michelle 14:64b06476d943 36 #define EADR5 0x0a
ivo_david_michelle 14:64b06476d943 37 #define EADR6 0x0b
ivo_david_michelle 14:64b06476d943 38 #define EADR7 0x0c
ivo_david_michelle 14:64b06476d943 39 #define RXFLUSH 0x0d
ivo_david_michelle 14:64b06476d943 40
ivo_david_michelle 14:64b06476d943 41 #define TXNMTRIG 0x1b
ivo_david_michelle 14:64b06476d943 42 #define TXSR 0x24
ivo_david_michelle 14:64b06476d943 43
ivo_david_michelle 14:64b06476d943 44 #define ISRSTS 0x31
ivo_david_michelle 14:64b06476d943 45 #define INTMSK 0x32
ivo_david_michelle 14:64b06476d943 46 #define GPIO 0x33
ivo_david_michelle 14:64b06476d943 47 #define TRISGPIO 0x34
ivo_david_michelle 14:64b06476d943 48
ivo_david_michelle 14:64b06476d943 49 #define RFCTL 0x36
ivo_david_michelle 14:64b06476d943 50
ivo_david_michelle 14:64b06476d943 51 #define BBREG2 0x3A
ivo_david_michelle 14:64b06476d943 52
ivo_david_michelle 14:64b06476d943 53 #define BBREG6 0x3E
ivo_david_michelle 14:64b06476d943 54 #define RSSITHCCA 0x3F
ivo_david_michelle 14:64b06476d943 55
ivo_david_michelle 14:64b06476d943 56 // MRF20J40 Long address control register mapping.
ivo_david_michelle 14:64b06476d943 57 #define RFCTRL0 0x200
ivo_david_michelle 14:64b06476d943 58
ivo_david_michelle 14:64b06476d943 59 #define RFCTRL2 0x202
ivo_david_michelle 14:64b06476d943 60 #define RFCTRL3 0x203
ivo_david_michelle 14:64b06476d943 61
ivo_david_michelle 14:64b06476d943 62 #define RFCTRL6 0x206
ivo_david_michelle 14:64b06476d943 63 #define RFCTRL7 0x207
ivo_david_michelle 14:64b06476d943 64 #define RFCTRL8 0x208
ivo_david_michelle 14:64b06476d943 65
ivo_david_michelle 14:64b06476d943 66 #define CLKINTCR 0x211
ivo_david_michelle 14:64b06476d943 67 #define CLCCTRL 0x220
ivo_david_michelle 14:64b06476d943 68
ivo_david_michelle 14:64b06476d943 69 MRF24J40::MRF24J40(PinName mosi, PinName miso, PinName sck, PinName cs, PinName reset) ://, PinName irq, PinName wake) :
ivo_david_michelle 14:64b06476d943 70 mSpi(mosi, miso, sck), // mosi, miso, sclk
ivo_david_michelle 14:64b06476d943 71 mCs(cs),
ivo_david_michelle 14:64b06476d943 72 mReset(reset)
ivo_david_michelle 14:64b06476d943 73 // mIrq(irq),
ivo_david_michelle 14:64b06476d943 74 // mWake(wake)
ivo_david_michelle 14:64b06476d943 75 {
ivo_david_michelle 14:64b06476d943 76 mSpi.format(8, 0); // 8 bits, cpol=0; cpha=0
ivo_david_michelle 14:64b06476d943 77 mSpi.frequency(500000);
ivo_david_michelle 14:64b06476d943 78 Reset();
ivo_david_michelle 14:64b06476d943 79 }
ivo_david_michelle 14:64b06476d943 80
ivo_david_michelle 14:64b06476d943 81 /*
ivo_david_michelle 14:64b06476d943 82 void MRF24J40::DebugDump(Serial &ser)
ivo_david_michelle 14:64b06476d943 83 {
ivo_david_michelle 14:64b06476d943 84 ser.printf("MRF24J40 registers:\r");
ivo_david_michelle 14:64b06476d943 85 ser.printf("RXMCR=0x%X\r", MrfReadShort(RXMCR));
ivo_david_michelle 14:64b06476d943 86 ser.printf("RXFLUSH=0x%X\r", MrfReadShort(RXFLUSH));
ivo_david_michelle 14:64b06476d943 87 ser.printf("TXNMTRIG=0x%X\r", MrfReadShort(TXNMTRIG));
ivo_david_michelle 14:64b06476d943 88 ser.printf("TXSR=0x%X\r", MrfReadShort(TXSR));
ivo_david_michelle 14:64b06476d943 89 ser.printf("ISRSTS=0x%X\r", MrfReadShort(ISRSTS));
ivo_david_michelle 14:64b06476d943 90 ser.printf("INTMSK=0x%X\r", MrfReadShort(INTMSK));
ivo_david_michelle 14:64b06476d943 91 ser.printf("GPIO=0x%X\r", MrfReadShort(GPIO));
ivo_david_michelle 14:64b06476d943 92 ser.printf("TRISGPIO=0x%X\r", MrfReadShort(TRISGPIO));
ivo_david_michelle 14:64b06476d943 93 ser.printf("RFCTL=0x%X\r", MrfReadShort(RFCTL));
ivo_david_michelle 14:64b06476d943 94 ser.printf("BBREG2=0x%X\r", MrfReadShort(BBREG2));
ivo_david_michelle 14:64b06476d943 95 ser.printf("BBREG6=0x%X\r", MrfReadShort(BBREG6));
ivo_david_michelle 14:64b06476d943 96 ser.printf("RSSITHCCA=0x%X\r", MrfReadShort(RSSITHCCA));
ivo_david_michelle 14:64b06476d943 97
ivo_david_michelle 14:64b06476d943 98
ivo_david_michelle 14:64b06476d943 99 ser.printf("RFCTRL0=0x%X\r", MrfReadLong(RFCTRL0));
ivo_david_michelle 14:64b06476d943 100 ser.printf("RFCTRL2=0x%X\r", MrfReadLong(RFCTRL2));
ivo_david_michelle 14:64b06476d943 101 ser.printf("RFCTRL3=0x%X\r", MrfReadLong(RFCTRL3));
ivo_david_michelle 14:64b06476d943 102 ser.printf("RFCTRL6=0x%X\r", MrfReadLong(RFCTRL6));
ivo_david_michelle 14:64b06476d943 103 ser.printf("RFCTRL7=0x%X\r", MrfReadLong(RFCTRL7));
ivo_david_michelle 14:64b06476d943 104 ser.printf("RFCTRL8=0x%X\r", MrfReadLong(RFCTRL8));
ivo_david_michelle 14:64b06476d943 105 ser.printf("CLKINTCR=0x%X\r", MrfReadLong(CLKINTCR));
ivo_david_michelle 14:64b06476d943 106 ser.printf("CLCCTRL=0x%X\r", MrfReadLong(CLCCTRL));
ivo_david_michelle 14:64b06476d943 107 ser.printf("\r");
ivo_david_michelle 14:64b06476d943 108 }
ivo_david_michelle 14:64b06476d943 109 */
ivo_david_michelle 14:64b06476d943 110
ivo_david_michelle 14:64b06476d943 111 void MRF24J40::Reset(void)
ivo_david_michelle 14:64b06476d943 112 {
ivo_david_michelle 14:64b06476d943 113 mCs = 1;
ivo_david_michelle 14:64b06476d943 114 // Pulse hardware reset.
ivo_david_michelle 14:64b06476d943 115 mReset = 0;
ivo_david_michelle 14:64b06476d943 116 wait_us(100);
ivo_david_michelle 14:64b06476d943 117 mReset = 1;
ivo_david_michelle 14:64b06476d943 118 wait_us(100);
ivo_david_michelle 14:64b06476d943 119
ivo_david_michelle 14:64b06476d943 120 // Reset RF module.
ivo_david_michelle 14:64b06476d943 121 WriteShort(RFCTL, 0x04);
ivo_david_michelle 14:64b06476d943 122 WriteShort(RFCTL, 0x00);
ivo_david_michelle 14:64b06476d943 123
ivo_david_michelle 14:64b06476d943 124 WriteShort(RFCTL, 0x00);
ivo_david_michelle 14:64b06476d943 125
ivo_david_michelle 14:64b06476d943 126 WriteShort(PANIDL, 0xAA);
ivo_david_michelle 14:64b06476d943 127 WriteShort(PANIDH, 0xAA);
ivo_david_michelle 14:64b06476d943 128 WriteShort(SADRL, 0xAA);
ivo_david_michelle 14:64b06476d943 129 WriteShort(SADRH, 0xAA);
ivo_david_michelle 14:64b06476d943 130
ivo_david_michelle 14:64b06476d943 131 // Flush RX fifo.
ivo_david_michelle 14:64b06476d943 132 WriteShort(RXFLUSH, 0x01);
ivo_david_michelle 14:64b06476d943 133
ivo_david_michelle 14:64b06476d943 134 // Write MAC addresses here. We don't care.
ivo_david_michelle 14:64b06476d943 135
ivo_david_michelle 14:64b06476d943 136 WriteLong(RFCTRL2, 0x80); // Enable RF PLL.
ivo_david_michelle 14:64b06476d943 137
ivo_david_michelle 14:64b06476d943 138 WriteLong(RFCTRL3, 0x00); // Full power.
ivo_david_michelle 14:64b06476d943 139 WriteLong(RFCTRL6, 0x80); // Enable TX filter (recommended)
ivo_david_michelle 14:64b06476d943 140 WriteLong(RFCTRL8, 0x10); // Enhanced VCO (recommended)
ivo_david_michelle 14:64b06476d943 141
ivo_david_michelle 14:64b06476d943 142 WriteShort(BBREG2,0x78); // Clear Channel Assesment use carrier sense.
ivo_david_michelle 14:64b06476d943 143 WriteShort(BBREG6,0x40); // Calculate RSSI for Rx packet.
ivo_david_michelle 14:64b06476d943 144 WriteShort(RSSITHCCA,0x00);// RSSI threshold for CCA.
ivo_david_michelle 14:64b06476d943 145
ivo_david_michelle 14:64b06476d943 146 WriteLong(RFCTRL0, 0x00); // Channel 11.
ivo_david_michelle 14:64b06476d943 147
ivo_david_michelle 14:64b06476d943 148 WriteShort(RXMCR, 0x01); // Don't check address upon reception.
ivo_david_michelle 14:64b06476d943 149 // MrfWriteShort(RXMCR, 0x00); // Check address upon reception.
ivo_david_michelle 14:64b06476d943 150
ivo_david_michelle 14:64b06476d943 151 // Reset RF module with new settings.
ivo_david_michelle 14:64b06476d943 152 WriteShort(RFCTL, 0x04);
ivo_david_michelle 14:64b06476d943 153 WriteShort(RFCTL, 0x00);
ivo_david_michelle 14:64b06476d943 154 }
ivo_david_michelle 14:64b06476d943 155
ivo_david_michelle 14:64b06476d943 156 void MRF24J40::Send(uint8_t *data, uint8_t length)
ivo_david_michelle 14:64b06476d943 157 {
ivo_david_michelle 14:64b06476d943 158 uint8_t i;
ivo_david_michelle 14:64b06476d943 159
ivo_david_michelle 14:64b06476d943 160 WriteLong(0x000, 0); // No addresses in header.
ivo_david_michelle 14:64b06476d943 161 WriteLong(0x001, length); // 11 bytes
ivo_david_michelle 14:64b06476d943 162 for(i=0; i<length; i++)
ivo_david_michelle 14:64b06476d943 163 WriteLong(0x002+i, data[i]);
ivo_david_michelle 14:64b06476d943 164
ivo_david_michelle 14:64b06476d943 165 WriteShort(TXNMTRIG, 0x01);
ivo_david_michelle 14:64b06476d943 166 }
ivo_david_michelle 14:64b06476d943 167
ivo_david_michelle 14:64b06476d943 168 uint8_t MRF24J40::Receive_RSSI(uint8_t *data, uint8_t *rssi, uint8_t maxLength)
ivo_david_michelle 14:64b06476d943 169 {
ivo_david_michelle 14:64b06476d943 170 uint8_t i, length;
ivo_david_michelle 14:64b06476d943 171
ivo_david_michelle 14:64b06476d943 172 if(ReadShort(ISRSTS)& 0x08)
ivo_david_michelle 14:64b06476d943 173 {
ivo_david_michelle 14:64b06476d943 174 length = ReadLong(0x300);
ivo_david_michelle 14:64b06476d943 175 *rssi = ReadLong(0x302 + length);
ivo_david_michelle 14:64b06476d943 176 for(i=0; i<length; i++)
ivo_david_michelle 14:64b06476d943 177 if(i<maxLength)
ivo_david_michelle 14:64b06476d943 178 *data++ = ReadLong(0x301 + (uint16_t)i);
ivo_david_michelle 14:64b06476d943 179 else
ivo_david_michelle 14:64b06476d943 180 ReadLong(0x301 + (uint16_t)i);
ivo_david_michelle 14:64b06476d943 181 if(length < maxLength)
ivo_david_michelle 14:64b06476d943 182 return length;
ivo_david_michelle 14:64b06476d943 183 }
ivo_david_michelle 14:64b06476d943 184 return 0;
ivo_david_michelle 14:64b06476d943 185 }
ivo_david_michelle 14:64b06476d943 186
ivo_david_michelle 14:64b06476d943 187 uint8_t MRF24J40::ReadShort (uint8_t address)
ivo_david_michelle 14:64b06476d943 188 {
ivo_david_michelle 14:64b06476d943 189 uint8_t value;
ivo_david_michelle 14:64b06476d943 190 mCs = 0;
ivo_david_michelle 14:64b06476d943 191 wait_us(1);
ivo_david_michelle 14:64b06476d943 192 mSpi.write((address<<1) & 0x7E);
ivo_david_michelle 14:64b06476d943 193 wait_us(1);
ivo_david_michelle 14:64b06476d943 194 value = mSpi.write(0xFF);
ivo_david_michelle 14:64b06476d943 195 wait_us(1);
ivo_david_michelle 14:64b06476d943 196 mCs = 1;
ivo_david_michelle 14:64b06476d943 197 wait_us(1);
ivo_david_michelle 14:64b06476d943 198 return value;
ivo_david_michelle 14:64b06476d943 199 }
ivo_david_michelle 14:64b06476d943 200
ivo_david_michelle 14:64b06476d943 201 void MRF24J40::WriteShort (uint8_t address, uint8_t data)
ivo_david_michelle 14:64b06476d943 202 {
ivo_david_michelle 14:64b06476d943 203 mCs = 0;
ivo_david_michelle 14:64b06476d943 204 wait_us(1);
ivo_david_michelle 14:64b06476d943 205 mSpi.write(((address<<1) & 0x7E) | 0x01);
ivo_david_michelle 14:64b06476d943 206 wait_us(1);
ivo_david_michelle 14:64b06476d943 207 mSpi.write(data);
ivo_david_michelle 14:64b06476d943 208 wait_us(1);
ivo_david_michelle 14:64b06476d943 209 mCs = 1;
ivo_david_michelle 14:64b06476d943 210 wait_us(1);
ivo_david_michelle 14:64b06476d943 211 }
ivo_david_michelle 14:64b06476d943 212
ivo_david_michelle 14:64b06476d943 213 uint8_t MRF24J40::ReadLong (uint16_t address)
ivo_david_michelle 14:64b06476d943 214 {
ivo_david_michelle 14:64b06476d943 215 uint8_t value;
ivo_david_michelle 14:64b06476d943 216 mCs = 0;
ivo_david_michelle 14:64b06476d943 217 wait_us(1);
ivo_david_michelle 14:64b06476d943 218 mSpi.write((address>>3) | 0x80);
ivo_david_michelle 14:64b06476d943 219 wait_us(1);
ivo_david_michelle 14:64b06476d943 220 mSpi.write((address<<5) & 0xE0);
ivo_david_michelle 14:64b06476d943 221 wait_us(1);
ivo_david_michelle 14:64b06476d943 222 value = mSpi.write(0xFF);
ivo_david_michelle 14:64b06476d943 223 wait_us(1);
ivo_david_michelle 14:64b06476d943 224 mCs = 1;
ivo_david_michelle 14:64b06476d943 225 wait_us(1);
ivo_david_michelle 14:64b06476d943 226 return value;
ivo_david_michelle 14:64b06476d943 227 }
ivo_david_michelle 14:64b06476d943 228
ivo_david_michelle 14:64b06476d943 229 void MRF24J40::WriteLong (uint16_t address, uint8_t data)
ivo_david_michelle 14:64b06476d943 230 {
ivo_david_michelle 14:64b06476d943 231 mCs = 0;
ivo_david_michelle 14:64b06476d943 232 wait_us(1);
ivo_david_michelle 14:64b06476d943 233 mSpi.write((address>>3) | 0x80);
ivo_david_michelle 14:64b06476d943 234 wait_us(1);
ivo_david_michelle 14:64b06476d943 235 mSpi.write(((address<<5) & 0xE0) | 0x10);
ivo_david_michelle 14:64b06476d943 236 wait_us(1);
ivo_david_michelle 14:64b06476d943 237 mSpi.write(data);
ivo_david_michelle 14:64b06476d943 238 wait_us(1);
ivo_david_michelle 14:64b06476d943 239 mCs = 1;
ivo_david_michelle 14:64b06476d943 240 wait_us(1);
ivo_david_michelle 14:64b06476d943 241 }
ivo_david_michelle 14:64b06476d943 242
ivo_david_michelle 14:64b06476d943 243 void MRF24J40::SetChannel(uint8_t channel)
ivo_david_michelle 14:64b06476d943 244 {
ivo_david_michelle 14:64b06476d943 245 WriteLong(RFCTRL0, (channel & 0x0F)<<4 | 0x03); // Set channel, leave RFOPT bits at recommended
ivo_david_michelle 14:64b06476d943 246
ivo_david_michelle 14:64b06476d943 247 //Reset the board by first writing a 4 to RFCTL, then writing a 0
ivo_david_michelle 14:64b06476d943 248 WriteShort(RFCTL, 0x04);
ivo_david_michelle 14:64b06476d943 249 WriteShort(RFCTL, 0x00);
ivo_david_michelle 14:64b06476d943 250 wait(0.5);
ivo_david_michelle 14:64b06476d943 251 }