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LPC1768/core_cm3.h@1:b749145a7bb1, 2013-10-04 (annotated)

Committer:: itotaka
Date:: Fri Oct 04 12:17:02 2013 +0000
Revision:: 1:b749145a7bb1
Parent:: 0:a8fa94490a0a

changed Max_Arg to 80

Who changed what in which revision?

User	Revision	Line number	New contents of line
gokmenascioglu	0:a8fa94490a0a	1	/************************************************************************//
gokmenascioglu	0:a8fa94490a0a	2	* @file core_cm3.h
gokmenascioglu	0:a8fa94490a0a	3	* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
gokmenascioglu	0:a8fa94490a0a	4	* @version V3.01
gokmenascioglu	0:a8fa94490a0a	5	* @date 06. March 2012
gokmenascioglu	0:a8fa94490a0a	6	*
gokmenascioglu	0:a8fa94490a0a	7	* @note
gokmenascioglu	0:a8fa94490a0a	8	* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
gokmenascioglu	0:a8fa94490a0a	9	*
gokmenascioglu	0:a8fa94490a0a	10	* @par
gokmenascioglu	0:a8fa94490a0a	11	* ARM Limited (ARM) is supplying this software for use with Cortex-M
gokmenascioglu	0:a8fa94490a0a	12	* processor based microcontrollers. This file can be freely distributed
gokmenascioglu	0:a8fa94490a0a	13	* within development tools that are supporting such ARM based processors.
gokmenascioglu	0:a8fa94490a0a	14	*
gokmenascioglu	0:a8fa94490a0a	15	* @par
gokmenascioglu	0:a8fa94490a0a	16	* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
gokmenascioglu	0:a8fa94490a0a	17	* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
gokmenascioglu	0:a8fa94490a0a	18	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
gokmenascioglu	0:a8fa94490a0a	19	* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
gokmenascioglu	0:a8fa94490a0a	20	* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
gokmenascioglu	0:a8fa94490a0a	21	*
gokmenascioglu	0:a8fa94490a0a	22	******************************************************************************/
gokmenascioglu	0:a8fa94490a0a	23	#if defined ( __ICCARM__ )
gokmenascioglu	0:a8fa94490a0a	24	#pragma system_include /* treat file as system include file for MISRA check */
gokmenascioglu	0:a8fa94490a0a	25	#endif
gokmenascioglu	0:a8fa94490a0a	26
gokmenascioglu	0:a8fa94490a0a	27	#ifdef __cplusplus
gokmenascioglu	0:a8fa94490a0a	28	extern "C" {
gokmenascioglu	0:a8fa94490a0a	29	#endif
gokmenascioglu	0:a8fa94490a0a	30
gokmenascioglu	0:a8fa94490a0a	31	#ifndef __CORE_CM3_H_GENERIC
gokmenascioglu	0:a8fa94490a0a	32	#define __CORE_CM3_H_GENERIC
gokmenascioglu	0:a8fa94490a0a	33
gokmenascioglu	0:a8fa94490a0a	34	/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
gokmenascioglu	0:a8fa94490a0a	35	CMSIS violates the following MISRA-C:2004 rules:
gokmenascioglu	0:a8fa94490a0a	36
gokmenascioglu	0:a8fa94490a0a	37	\li Required Rule 8.5, object/function definition in header file.<br>
gokmenascioglu	0:a8fa94490a0a	38	Function definitions in header files are used to allow 'inlining'.
gokmenascioglu	0:a8fa94490a0a	39
gokmenascioglu	0:a8fa94490a0a	40	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
gokmenascioglu	0:a8fa94490a0a	41	Unions are used for effective representation of core registers.
gokmenascioglu	0:a8fa94490a0a	42
gokmenascioglu	0:a8fa94490a0a	43	\li Advisory Rule 19.7, Function-like macro defined.<br>
gokmenascioglu	0:a8fa94490a0a	44	Function-like macros are used to allow more efficient code.
gokmenascioglu	0:a8fa94490a0a	45	*/
gokmenascioglu	0:a8fa94490a0a	46
gokmenascioglu	0:a8fa94490a0a	47
gokmenascioglu	0:a8fa94490a0a	48	/*******************************************************************************
gokmenascioglu	0:a8fa94490a0a	49	* CMSIS definitions
gokmenascioglu	0:a8fa94490a0a	50	******************************************************************************/
gokmenascioglu	0:a8fa94490a0a	51	/** \ingroup Cortex_M3
gokmenascioglu	0:a8fa94490a0a	52	@{
gokmenascioglu	0:a8fa94490a0a	53	*/
gokmenascioglu	0:a8fa94490a0a	54
gokmenascioglu	0:a8fa94490a0a	55	/* CMSIS CM3 definitions */
gokmenascioglu	0:a8fa94490a0a	56	#define __CM3_CMSIS_VERSION_MAIN (0x03) /!< [31:16] CMSIS HAL main version /
gokmenascioglu	0:a8fa94490a0a	57	#define __CM3_CMSIS_VERSION_SUB (0x01) /!< [15:0] CMSIS HAL sub version /
gokmenascioglu	0:a8fa94490a0a	58	#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) \| \
gokmenascioglu	0:a8fa94490a0a	59	__CM3_CMSIS_VERSION_SUB ) /!< CMSIS HAL version number /
gokmenascioglu	0:a8fa94490a0a	60
gokmenascioglu	0:a8fa94490a0a	61	#define __CORTEX_M (0x03) /!< Cortex-M Core /
gokmenascioglu	0:a8fa94490a0a	62
gokmenascioglu	0:a8fa94490a0a	63
gokmenascioglu	0:a8fa94490a0a	64	#if defined ( __CC_ARM )
gokmenascioglu	0:a8fa94490a0a	65	#define __ASM __asm /!< asm keyword for ARM Compiler /
gokmenascioglu	0:a8fa94490a0a	66	#define __INLINE __inline /!< inline keyword for ARM Compiler /
gokmenascioglu	0:a8fa94490a0a	67	#define __STATIC_INLINE static __inline
gokmenascioglu	0:a8fa94490a0a	68
gokmenascioglu	0:a8fa94490a0a	69	#elif defined ( __ICCARM__ )
gokmenascioglu	0:a8fa94490a0a	70	#define __ASM __asm /!< asm keyword for IAR Compiler /
gokmenascioglu	0:a8fa94490a0a	71	#define __INLINE inline /!< inline keyword for IAR Compiler. Only available in High optimization mode! /
gokmenascioglu	0:a8fa94490a0a	72	#define __STATIC_INLINE static inline
gokmenascioglu	0:a8fa94490a0a	73
gokmenascioglu	0:a8fa94490a0a	74	#elif defined ( __TMS470__ )
gokmenascioglu	0:a8fa94490a0a	75	#define __ASM __asm /!< asm keyword for TI CCS Compiler /
gokmenascioglu	0:a8fa94490a0a	76	#define __STATIC_INLINE static inline
gokmenascioglu	0:a8fa94490a0a	77
gokmenascioglu	0:a8fa94490a0a	78	#elif defined ( __GNUC__ )
gokmenascioglu	0:a8fa94490a0a	79	#define __ASM __asm /!< asm keyword for GNU Compiler /
gokmenascioglu	0:a8fa94490a0a	80	#define __INLINE inline /!< inline keyword for GNU Compiler /
gokmenascioglu	0:a8fa94490a0a	81	#define __STATIC_INLINE static inline
gokmenascioglu	0:a8fa94490a0a	82
gokmenascioglu	0:a8fa94490a0a	83	#elif defined ( __TASKING__ )
gokmenascioglu	0:a8fa94490a0a	84	#define __ASM __asm /!< asm keyword for TASKING Compiler /
gokmenascioglu	0:a8fa94490a0a	85	#define __INLINE inline /!< inline keyword for TASKING Compiler /
gokmenascioglu	0:a8fa94490a0a	86	#define __STATIC_INLINE static inline
gokmenascioglu	0:a8fa94490a0a	87
gokmenascioglu	0:a8fa94490a0a	88	#endif
gokmenascioglu	0:a8fa94490a0a	89
gokmenascioglu	0:a8fa94490a0a	90	/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
gokmenascioglu	0:a8fa94490a0a	91	*/
gokmenascioglu	0:a8fa94490a0a	92	#define __FPU_USED 0
gokmenascioglu	0:a8fa94490a0a	93
gokmenascioglu	0:a8fa94490a0a	94	#if defined ( __CC_ARM )
gokmenascioglu	0:a8fa94490a0a	95	#if defined __TARGET_FPU_VFP
gokmenascioglu	0:a8fa94490a0a	96	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
gokmenascioglu	0:a8fa94490a0a	97	#endif
gokmenascioglu	0:a8fa94490a0a	98
gokmenascioglu	0:a8fa94490a0a	99	#elif defined ( __ICCARM__ )
gokmenascioglu	0:a8fa94490a0a	100	#if defined __ARMVFP__
gokmenascioglu	0:a8fa94490a0a	101	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
gokmenascioglu	0:a8fa94490a0a	102	#endif
gokmenascioglu	0:a8fa94490a0a	103
gokmenascioglu	0:a8fa94490a0a	104	#elif defined ( __TMS470__ )
gokmenascioglu	0:a8fa94490a0a	105	#if defined __TI__VFP_SUPPORT____
gokmenascioglu	0:a8fa94490a0a	106	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
gokmenascioglu	0:a8fa94490a0a	107	#endif
gokmenascioglu	0:a8fa94490a0a	108
gokmenascioglu	0:a8fa94490a0a	109	#elif defined ( __GNUC__ )
gokmenascioglu	0:a8fa94490a0a	110	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
gokmenascioglu	0:a8fa94490a0a	111	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
gokmenascioglu	0:a8fa94490a0a	112	#endif
gokmenascioglu	0:a8fa94490a0a	113
gokmenascioglu	0:a8fa94490a0a	114	#elif defined ( __TASKING__ )
gokmenascioglu	0:a8fa94490a0a	115	/* add preprocessor checks */
gokmenascioglu	0:a8fa94490a0a	116	#endif
gokmenascioglu	0:a8fa94490a0a	117
gokmenascioglu	0:a8fa94490a0a	118	#include <stdint.h> /* standard types definitions */
gokmenascioglu	0:a8fa94490a0a	119	#include <core_cmInstr.h> /* Core Instruction Access */
gokmenascioglu	0:a8fa94490a0a	120	#include <core_cmFunc.h> /* Core Function Access */
gokmenascioglu	0:a8fa94490a0a	121
gokmenascioglu	0:a8fa94490a0a	122	#endif /* __CORE_CM3_H_GENERIC */
gokmenascioglu	0:a8fa94490a0a	123
gokmenascioglu	0:a8fa94490a0a	124	#ifndef __CMSIS_GENERIC
gokmenascioglu	0:a8fa94490a0a	125
gokmenascioglu	0:a8fa94490a0a	126	#ifndef __CORE_CM3_H_DEPENDANT
gokmenascioglu	0:a8fa94490a0a	127	#define __CORE_CM3_H_DEPENDANT
gokmenascioglu	0:a8fa94490a0a	128
gokmenascioglu	0:a8fa94490a0a	129	/* check device defines and use defaults */
gokmenascioglu	0:a8fa94490a0a	130	#if defined __CHECK_DEVICE_DEFINES
gokmenascioglu	0:a8fa94490a0a	131	#ifndef __CM3_REV
gokmenascioglu	0:a8fa94490a0a	132	#define __CM3_REV 0x0200
gokmenascioglu	0:a8fa94490a0a	133	#warning "__CM3_REV not defined in device header file; using default!"
gokmenascioglu	0:a8fa94490a0a	134	#endif
gokmenascioglu	0:a8fa94490a0a	135
gokmenascioglu	0:a8fa94490a0a	136	#ifndef __MPU_PRESENT
gokmenascioglu	0:a8fa94490a0a	137	#define __MPU_PRESENT 0
gokmenascioglu	0:a8fa94490a0a	138	#warning "__MPU_PRESENT not defined in device header file; using default!"
gokmenascioglu	0:a8fa94490a0a	139	#endif
gokmenascioglu	0:a8fa94490a0a	140
gokmenascioglu	0:a8fa94490a0a	141	#ifndef __NVIC_PRIO_BITS
gokmenascioglu	0:a8fa94490a0a	142	#define __NVIC_PRIO_BITS 4
gokmenascioglu	0:a8fa94490a0a	143	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
gokmenascioglu	0:a8fa94490a0a	144	#endif
gokmenascioglu	0:a8fa94490a0a	145
gokmenascioglu	0:a8fa94490a0a	146	#ifndef __Vendor_SysTickConfig
gokmenascioglu	0:a8fa94490a0a	147	#define __Vendor_SysTickConfig 0
gokmenascioglu	0:a8fa94490a0a	148	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
gokmenascioglu	0:a8fa94490a0a	149	#endif
gokmenascioglu	0:a8fa94490a0a	150	#endif
gokmenascioglu	0:a8fa94490a0a	151
gokmenascioglu	0:a8fa94490a0a	152	/* IO definitions (access restrictions to peripheral registers) */
gokmenascioglu	0:a8fa94490a0a	153	/**
gokmenascioglu	0:a8fa94490a0a	154	\defgroup CMSIS_glob_defs CMSIS Global Defines
gokmenascioglu	0:a8fa94490a0a	155
gokmenascioglu	0:a8fa94490a0a	156	<strong>IO Type Qualifiers</strong> are used
gokmenascioglu	0:a8fa94490a0a	157	\li to specify the access to peripheral variables.
gokmenascioglu	0:a8fa94490a0a	158	\li for automatic generation of peripheral register debug information.
gokmenascioglu	0:a8fa94490a0a	159	*/
gokmenascioglu	0:a8fa94490a0a	160	#ifdef __cplusplus
gokmenascioglu	0:a8fa94490a0a	161	#define __I volatile /!< Defines 'read only' permissions /
gokmenascioglu	0:a8fa94490a0a	162	#else
gokmenascioglu	0:a8fa94490a0a	163	#define __I volatile const /!< Defines 'read only' permissions /
gokmenascioglu	0:a8fa94490a0a	164	#endif
gokmenascioglu	0:a8fa94490a0a	165	#define __O volatile /!< Defines 'write only' permissions /
gokmenascioglu	0:a8fa94490a0a	166	#define __IO volatile /!< Defines 'read / write' permissions /
gokmenascioglu	0:a8fa94490a0a	167
gokmenascioglu	0:a8fa94490a0a	168	/@} end of group Cortex_M3 /
gokmenascioglu	0:a8fa94490a0a	169
gokmenascioglu	0:a8fa94490a0a	170
gokmenascioglu	0:a8fa94490a0a	171
gokmenascioglu	0:a8fa94490a0a	172	/*******************************************************************************
gokmenascioglu	0:a8fa94490a0a	173	* Register Abstraction
gokmenascioglu	0:a8fa94490a0a	174	Core Register contain:
gokmenascioglu	0:a8fa94490a0a	175	- Core Register
gokmenascioglu	0:a8fa94490a0a	176	- Core NVIC Register
gokmenascioglu	0:a8fa94490a0a	177	- Core SCB Register
gokmenascioglu	0:a8fa94490a0a	178	- Core SysTick Register
gokmenascioglu	0:a8fa94490a0a	179	- Core Debug Register
gokmenascioglu	0:a8fa94490a0a	180	- Core MPU Register
gokmenascioglu	0:a8fa94490a0a	181	******************************************************************************/
gokmenascioglu	0:a8fa94490a0a	182	/** \defgroup CMSIS_core_register Defines and Type Definitions
gokmenascioglu	0:a8fa94490a0a	183	\brief Type definitions and defines for Cortex-M processor based devices.
gokmenascioglu	0:a8fa94490a0a	184	*/
gokmenascioglu	0:a8fa94490a0a	185
gokmenascioglu	0:a8fa94490a0a	186	/** \ingroup CMSIS_core_register
gokmenascioglu	0:a8fa94490a0a	187	\defgroup CMSIS_CORE Status and Control Registers
gokmenascioglu	0:a8fa94490a0a	188	\brief Core Register type definitions.
gokmenascioglu	0:a8fa94490a0a	189	@{
gokmenascioglu	0:a8fa94490a0a	190	*/
gokmenascioglu	0:a8fa94490a0a	191
gokmenascioglu	0:a8fa94490a0a	192	/** \brief Union type to access the Application Program Status Register (APSR).
gokmenascioglu	0:a8fa94490a0a	193	*/
gokmenascioglu	0:a8fa94490a0a	194	typedef union
gokmenascioglu	0:a8fa94490a0a	195	{
gokmenascioglu	0:a8fa94490a0a	196	struct
gokmenascioglu	0:a8fa94490a0a	197	{
gokmenascioglu	0:a8fa94490a0a	198	#if (__CORTEX_M != 0x04)
gokmenascioglu	0:a8fa94490a0a	199	uint32_t _reserved0:27; /!< bit: 0..26 Reserved /
gokmenascioglu	0:a8fa94490a0a	200	#else
gokmenascioglu	0:a8fa94490a0a	201	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
gokmenascioglu	0:a8fa94490a0a	202	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
gokmenascioglu	0:a8fa94490a0a	203	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
gokmenascioglu	0:a8fa94490a0a	204	#endif
gokmenascioglu	0:a8fa94490a0a	205	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
gokmenascioglu	0:a8fa94490a0a	206	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
gokmenascioglu	0:a8fa94490a0a	207	uint32_t C:1; /!< bit: 29 Carry condition code flag /
gokmenascioglu	0:a8fa94490a0a	208	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
gokmenascioglu	0:a8fa94490a0a	209	uint32_t N:1; /!< bit: 31 Negative condition code flag /
gokmenascioglu	0:a8fa94490a0a	210	} b; /!< Structure used for bit access /
gokmenascioglu	0:a8fa94490a0a	211	uint32_t w; /!< Type used for word access /
gokmenascioglu	0:a8fa94490a0a	212	} APSR_Type;
gokmenascioglu	0:a8fa94490a0a	213
gokmenascioglu	0:a8fa94490a0a	214
gokmenascioglu	0:a8fa94490a0a	215	/** \brief Union type to access the Interrupt Program Status Register (IPSR).
gokmenascioglu	0:a8fa94490a0a	216	*/
gokmenascioglu	0:a8fa94490a0a	217	typedef union
gokmenascioglu	0:a8fa94490a0a	218	{
gokmenascioglu	0:a8fa94490a0a	219	struct
gokmenascioglu	0:a8fa94490a0a	220	{
gokmenascioglu	0:a8fa94490a0a	221	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
gokmenascioglu	0:a8fa94490a0a	222	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
gokmenascioglu	0:a8fa94490a0a	223	} b; /!< Structure used for bit access /
gokmenascioglu	0:a8fa94490a0a	224	uint32_t w; /!< Type used for word access /
gokmenascioglu	0:a8fa94490a0a	225	} IPSR_Type;
gokmenascioglu	0:a8fa94490a0a	226
gokmenascioglu	0:a8fa94490a0a	227
gokmenascioglu	0:a8fa94490a0a	228	/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
gokmenascioglu	0:a8fa94490a0a	229	*/
gokmenascioglu	0:a8fa94490a0a	230	typedef union
gokmenascioglu	0:a8fa94490a0a	231	{
gokmenascioglu	0:a8fa94490a0a	232	struct
gokmenascioglu	0:a8fa94490a0a	233	{
gokmenascioglu	0:a8fa94490a0a	234	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
gokmenascioglu	0:a8fa94490a0a	235	#if (__CORTEX_M != 0x04)
gokmenascioglu	0:a8fa94490a0a	236	uint32_t _reserved0:15; /!< bit: 9..23 Reserved /
gokmenascioglu	0:a8fa94490a0a	237	#else
gokmenascioglu	0:a8fa94490a0a	238	uint32_t _reserved0:7; /!< bit: 9..15 Reserved /
gokmenascioglu	0:a8fa94490a0a	239	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
gokmenascioglu	0:a8fa94490a0a	240	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
gokmenascioglu	0:a8fa94490a0a	241	#endif
gokmenascioglu	0:a8fa94490a0a	242	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
gokmenascioglu	0:a8fa94490a0a	243	uint32_t IT:2; /!< bit: 25..26 saved IT state (read 0) /
gokmenascioglu	0:a8fa94490a0a	244	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
gokmenascioglu	0:a8fa94490a0a	245	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
gokmenascioglu	0:a8fa94490a0a	246	uint32_t C:1; /!< bit: 29 Carry condition code flag /
gokmenascioglu	0:a8fa94490a0a	247	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
gokmenascioglu	0:a8fa94490a0a	248	uint32_t N:1; /!< bit: 31 Negative condition code flag /
gokmenascioglu	0:a8fa94490a0a	249	} b; /!< Structure used for bit access /
gokmenascioglu	0:a8fa94490a0a	250	uint32_t w; /!< Type used for word access /
gokmenascioglu	0:a8fa94490a0a	251	} xPSR_Type;
gokmenascioglu	0:a8fa94490a0a	252
gokmenascioglu	0:a8fa94490a0a	253
gokmenascioglu	0:a8fa94490a0a	254	/** \brief Union type to access the Control Registers (CONTROL).
gokmenascioglu	0:a8fa94490a0a	255	*/
gokmenascioglu	0:a8fa94490a0a	256	typedef union
gokmenascioglu	0:a8fa94490a0a	257	{
gokmenascioglu	0:a8fa94490a0a	258	struct
gokmenascioglu	0:a8fa94490a0a	259	{
gokmenascioglu	0:a8fa94490a0a	260	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
gokmenascioglu	0:a8fa94490a0a	261	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
gokmenascioglu	0:a8fa94490a0a	262	uint32_t FPCA:1; /!< bit: 2 FP extension active flag /
gokmenascioglu	0:a8fa94490a0a	263	uint32_t _reserved0:29; /!< bit: 3..31 Reserved /
gokmenascioglu	0:a8fa94490a0a	264	} b; /!< Structure used for bit access /
gokmenascioglu	0:a8fa94490a0a	265	uint32_t w; /!< Type used for word access /
gokmenascioglu	0:a8fa94490a0a	266	} CONTROL_Type;
gokmenascioglu	0:a8fa94490a0a	267
gokmenascioglu	0:a8fa94490a0a	268	/@} end of group CMSIS_CORE /
gokmenascioglu	0:a8fa94490a0a	269
gokmenascioglu	0:a8fa94490a0a	270
gokmenascioglu	0:a8fa94490a0a	271	/** \ingroup CMSIS_core_register
gokmenascioglu	0:a8fa94490a0a	272	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
gokmenascioglu	0:a8fa94490a0a	273	\brief Type definitions for the NVIC Registers
gokmenascioglu	0:a8fa94490a0a	274	@{
gokmenascioglu	0:a8fa94490a0a	275	*/
gokmenascioglu	0:a8fa94490a0a	276
gokmenascioglu	0:a8fa94490a0a	277	/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
gokmenascioglu	0:a8fa94490a0a	278	*/
gokmenascioglu	0:a8fa94490a0a	279	typedef struct
gokmenascioglu	0:a8fa94490a0a	280	{
gokmenascioglu	0:a8fa94490a0a	281	__IO uint32_t ISER[8]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
gokmenascioglu	0:a8fa94490a0a	282	uint32_t RESERVED0[24];
gokmenascioglu	0:a8fa94490a0a	283	__IO uint32_t ICER[8]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
gokmenascioglu	0:a8fa94490a0a	284	uint32_t RSERVED1[24];
gokmenascioglu	0:a8fa94490a0a	285	__IO uint32_t ISPR[8]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
gokmenascioglu	0:a8fa94490a0a	286	uint32_t RESERVED2[24];
gokmenascioglu	0:a8fa94490a0a	287	__IO uint32_t ICPR[8]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
gokmenascioglu	0:a8fa94490a0a	288	uint32_t RESERVED3[24];
gokmenascioglu	0:a8fa94490a0a	289	__IO uint32_t IABR[8]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
gokmenascioglu	0:a8fa94490a0a	290	uint32_t RESERVED4[56];
gokmenascioglu	0:a8fa94490a0a	291	__IO uint8_t IP[240]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
gokmenascioglu	0:a8fa94490a0a	292	uint32_t RESERVED5[644];
gokmenascioglu	0:a8fa94490a0a	293	__O uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
gokmenascioglu	0:a8fa94490a0a	294	} NVIC_Type;
gokmenascioglu	0:a8fa94490a0a	295
gokmenascioglu	0:a8fa94490a0a	296	/* Software Triggered Interrupt Register Definitions */
gokmenascioglu	0:a8fa94490a0a	297	#define NVIC_STIR_INTID_Pos 0 /!< STIR: INTLINESNUM Position /
gokmenascioglu	0:a8fa94490a0a	298	#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /!< STIR: INTLINESNUM Mask /
gokmenascioglu	0:a8fa94490a0a	299
gokmenascioglu	0:a8fa94490a0a	300	/@} end of group CMSIS_NVIC /
gokmenascioglu	0:a8fa94490a0a	301
gokmenascioglu	0:a8fa94490a0a	302
gokmenascioglu	0:a8fa94490a0a	303	/** \ingroup CMSIS_core_register
gokmenascioglu	0:a8fa94490a0a	304	\defgroup CMSIS_SCB System Control Block (SCB)
gokmenascioglu	0:a8fa94490a0a	305	\brief Type definitions for the System Control Block Registers
gokmenascioglu	0:a8fa94490a0a	306	@{
gokmenascioglu	0:a8fa94490a0a	307	*/
gokmenascioglu	0:a8fa94490a0a	308
gokmenascioglu	0:a8fa94490a0a	309	/** \brief Structure type to access the System Control Block (SCB).
gokmenascioglu	0:a8fa94490a0a	310	*/
gokmenascioglu	0:a8fa94490a0a	311	typedef struct
gokmenascioglu	0:a8fa94490a0a	312	{
gokmenascioglu	0:a8fa94490a0a	313	__I uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
gokmenascioglu	0:a8fa94490a0a	314	__IO uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
gokmenascioglu	0:a8fa94490a0a	315	__IO uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
gokmenascioglu	0:a8fa94490a0a	316	__IO uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
gokmenascioglu	0:a8fa94490a0a	317	__IO uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
gokmenascioglu	0:a8fa94490a0a	318	__IO uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
gokmenascioglu	0:a8fa94490a0a	319	__IO uint8_t SHP[12]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
gokmenascioglu	0:a8fa94490a0a	320	__IO uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
gokmenascioglu	0:a8fa94490a0a	321	__IO uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
gokmenascioglu	0:a8fa94490a0a	322	__IO uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
gokmenascioglu	0:a8fa94490a0a	323	__IO uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
gokmenascioglu	0:a8fa94490a0a	324	__IO uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
gokmenascioglu	0:a8fa94490a0a	325	__IO uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
gokmenascioglu	0:a8fa94490a0a	326	__IO uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
gokmenascioglu	0:a8fa94490a0a	327	__I uint32_t PFR[2]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
gokmenascioglu	0:a8fa94490a0a	328	__I uint32_t DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
gokmenascioglu	0:a8fa94490a0a	329	__I uint32_t ADR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
gokmenascioglu	0:a8fa94490a0a	330	__I uint32_t MMFR[4]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
gokmenascioglu	0:a8fa94490a0a	331	__I uint32_t ISAR[5]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
gokmenascioglu	0:a8fa94490a0a	332	uint32_t RESERVED0[5];
gokmenascioglu	0:a8fa94490a0a	333	__IO uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
gokmenascioglu	0:a8fa94490a0a	334	} SCB_Type;
gokmenascioglu	0:a8fa94490a0a	335
gokmenascioglu	0:a8fa94490a0a	336	/* SCB CPUID Register Definitions */
gokmenascioglu	0:a8fa94490a0a	337	#define SCB_CPUID_IMPLEMENTER_Pos 24 /!< SCB CPUID: IMPLEMENTER Position /
gokmenascioglu	0:a8fa94490a0a	338	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
gokmenascioglu	0:a8fa94490a0a	339
gokmenascioglu	0:a8fa94490a0a	340	#define SCB_CPUID_VARIANT_Pos 20 /!< SCB CPUID: VARIANT Position /
gokmenascioglu	0:a8fa94490a0a	341	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
gokmenascioglu	0:a8fa94490a0a	342
gokmenascioglu	0:a8fa94490a0a	343	#define SCB_CPUID_ARCHITECTURE_Pos 16 /!< SCB CPUID: ARCHITECTURE Position /
gokmenascioglu	0:a8fa94490a0a	344	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
gokmenascioglu	0:a8fa94490a0a	345
gokmenascioglu	0:a8fa94490a0a	346	#define SCB_CPUID_PARTNO_Pos 4 /!< SCB CPUID: PARTNO Position /
gokmenascioglu	0:a8fa94490a0a	347	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
gokmenascioglu	0:a8fa94490a0a	348
gokmenascioglu	0:a8fa94490a0a	349	#define SCB_CPUID_REVISION_Pos 0 /!< SCB CPUID: REVISION Position /
gokmenascioglu	0:a8fa94490a0a	350	#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /!< SCB CPUID: REVISION Mask /
gokmenascioglu	0:a8fa94490a0a	351
gokmenascioglu	0:a8fa94490a0a	352	/* SCB Interrupt Control State Register Definitions */
gokmenascioglu	0:a8fa94490a0a	353	#define SCB_ICSR_NMIPENDSET_Pos 31 /!< SCB ICSR: NMIPENDSET Position /
gokmenascioglu	0:a8fa94490a0a	354	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
gokmenascioglu	0:a8fa94490a0a	355
gokmenascioglu	0:a8fa94490a0a	356	#define SCB_ICSR_PENDSVSET_Pos 28 /!< SCB ICSR: PENDSVSET Position /
gokmenascioglu	0:a8fa94490a0a	357	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
gokmenascioglu	0:a8fa94490a0a	358
gokmenascioglu	0:a8fa94490a0a	359	#define SCB_ICSR_PENDSVCLR_Pos 27 /!< SCB ICSR: PENDSVCLR Position /
gokmenascioglu	0:a8fa94490a0a	360	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
gokmenascioglu	0:a8fa94490a0a	361
gokmenascioglu	0:a8fa94490a0a	362	#define SCB_ICSR_PENDSTSET_Pos 26 /!< SCB ICSR: PENDSTSET Position /
gokmenascioglu	0:a8fa94490a0a	363	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
gokmenascioglu	0:a8fa94490a0a	364
gokmenascioglu	0:a8fa94490a0a	365	#define SCB_ICSR_PENDSTCLR_Pos 25 /!< SCB ICSR: PENDSTCLR Position /
gokmenascioglu	0:a8fa94490a0a	366	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
gokmenascioglu	0:a8fa94490a0a	367
gokmenascioglu	0:a8fa94490a0a	368	#define SCB_ICSR_ISRPREEMPT_Pos 23 /!< SCB ICSR: ISRPREEMPT Position /
gokmenascioglu	0:a8fa94490a0a	369	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
gokmenascioglu	0:a8fa94490a0a	370
gokmenascioglu	0:a8fa94490a0a	371	#define SCB_ICSR_ISRPENDING_Pos 22 /!< SCB ICSR: ISRPENDING Position /
gokmenascioglu	0:a8fa94490a0a	372	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
gokmenascioglu	0:a8fa94490a0a	373
gokmenascioglu	0:a8fa94490a0a	374	#define SCB_ICSR_VECTPENDING_Pos 12 /!< SCB ICSR: VECTPENDING Position /
gokmenascioglu	0:a8fa94490a0a	375	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
gokmenascioglu	0:a8fa94490a0a	376
gokmenascioglu	0:a8fa94490a0a	377	#define SCB_ICSR_RETTOBASE_Pos 11 /!< SCB ICSR: RETTOBASE Position /
gokmenascioglu	0:a8fa94490a0a	378	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
gokmenascioglu	0:a8fa94490a0a	379
gokmenascioglu	0:a8fa94490a0a	380	#define SCB_ICSR_VECTACTIVE_Pos 0 /!< SCB ICSR: VECTACTIVE Position /
gokmenascioglu	0:a8fa94490a0a	381	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /!< SCB ICSR: VECTACTIVE Mask /
gokmenascioglu	0:a8fa94490a0a	382
gokmenascioglu	0:a8fa94490a0a	383	/* SCB Vector Table Offset Register Definitions */
gokmenascioglu	0:a8fa94490a0a	384	#if (__CM3_REV < 0x0201) /* core r2p1 */
gokmenascioglu	0:a8fa94490a0a	385	#define SCB_VTOR_TBLBASE_Pos 29 /!< SCB VTOR: TBLBASE Position /
gokmenascioglu	0:a8fa94490a0a	386	#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /!< SCB VTOR: TBLBASE Mask /
gokmenascioglu	0:a8fa94490a0a	387
gokmenascioglu	0:a8fa94490a0a	388	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
gokmenascioglu	0:a8fa94490a0a	389	#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
gokmenascioglu	0:a8fa94490a0a	390	#else
gokmenascioglu	0:a8fa94490a0a	391	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
gokmenascioglu	0:a8fa94490a0a	392	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
gokmenascioglu	0:a8fa94490a0a	393	#endif
gokmenascioglu	0:a8fa94490a0a	394
gokmenascioglu	0:a8fa94490a0a	395	/* SCB Application Interrupt and Reset Control Register Definitions */
gokmenascioglu	0:a8fa94490a0a	396	#define SCB_AIRCR_VECTKEY_Pos 16 /!< SCB AIRCR: VECTKEY Position /
gokmenascioglu	0:a8fa94490a0a	397	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
gokmenascioglu	0:a8fa94490a0a	398
gokmenascioglu	0:a8fa94490a0a	399	#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /!< SCB AIRCR: VECTKEYSTAT Position /
gokmenascioglu	0:a8fa94490a0a	400	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
gokmenascioglu	0:a8fa94490a0a	401
gokmenascioglu	0:a8fa94490a0a	402	#define SCB_AIRCR_ENDIANESS_Pos 15 /!< SCB AIRCR: ENDIANESS Position /
gokmenascioglu	0:a8fa94490a0a	403	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
gokmenascioglu	0:a8fa94490a0a	404
gokmenascioglu	0:a8fa94490a0a	405	#define SCB_AIRCR_PRIGROUP_Pos 8 /!< SCB AIRCR: PRIGROUP Position /
gokmenascioglu	0:a8fa94490a0a	406	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
gokmenascioglu	0:a8fa94490a0a	407
gokmenascioglu	0:a8fa94490a0a	408	#define SCB_AIRCR_SYSRESETREQ_Pos 2 /!< SCB AIRCR: SYSRESETREQ Position /
gokmenascioglu	0:a8fa94490a0a	409	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
gokmenascioglu	0:a8fa94490a0a	410
gokmenascioglu	0:a8fa94490a0a	411	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /!< SCB AIRCR: VECTCLRACTIVE Position /
gokmenascioglu	0:a8fa94490a0a	412	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
gokmenascioglu	0:a8fa94490a0a	413
gokmenascioglu	0:a8fa94490a0a	414	#define SCB_AIRCR_VECTRESET_Pos 0 /!< SCB AIRCR: VECTRESET Position /
gokmenascioglu	0:a8fa94490a0a	415	#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /!< SCB AIRCR: VECTRESET Mask /
gokmenascioglu	0:a8fa94490a0a	416
gokmenascioglu	0:a8fa94490a0a	417	/* SCB System Control Register Definitions */
gokmenascioglu	0:a8fa94490a0a	418	#define SCB_SCR_SEVONPEND_Pos 4 /!< SCB SCR: SEVONPEND Position /
gokmenascioglu	0:a8fa94490a0a	419	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
gokmenascioglu	0:a8fa94490a0a	420
gokmenascioglu	0:a8fa94490a0a	421	#define SCB_SCR_SLEEPDEEP_Pos 2 /!< SCB SCR: SLEEPDEEP Position /
gokmenascioglu	0:a8fa94490a0a	422	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
gokmenascioglu	0:a8fa94490a0a	423
gokmenascioglu	0:a8fa94490a0a	424	#define SCB_SCR_SLEEPONEXIT_Pos 1 /!< SCB SCR: SLEEPONEXIT Position /
gokmenascioglu	0:a8fa94490a0a	425	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
gokmenascioglu	0:a8fa94490a0a	426
gokmenascioglu	0:a8fa94490a0a	427	/* SCB Configuration Control Register Definitions */
gokmenascioglu	0:a8fa94490a0a	428	#define SCB_CCR_STKALIGN_Pos 9 /!< SCB CCR: STKALIGN Position /
gokmenascioglu	0:a8fa94490a0a	429	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
gokmenascioglu	0:a8fa94490a0a	430
gokmenascioglu	0:a8fa94490a0a	431	#define SCB_CCR_BFHFNMIGN_Pos 8 /!< SCB CCR: BFHFNMIGN Position /
gokmenascioglu	0:a8fa94490a0a	432	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
gokmenascioglu	0:a8fa94490a0a	433
gokmenascioglu	0:a8fa94490a0a	434	#define SCB_CCR_DIV_0_TRP_Pos 4 /!< SCB CCR: DIV_0_TRP Position /
gokmenascioglu	0:a8fa94490a0a	435	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
gokmenascioglu	0:a8fa94490a0a	436
gokmenascioglu	0:a8fa94490a0a	437	#define SCB_CCR_UNALIGN_TRP_Pos 3 /!< SCB CCR: UNALIGN_TRP Position /
gokmenascioglu	0:a8fa94490a0a	438	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
gokmenascioglu	0:a8fa94490a0a	439
gokmenascioglu	0:a8fa94490a0a	440	#define SCB_CCR_USERSETMPEND_Pos 1 /!< SCB CCR: USERSETMPEND Position /
gokmenascioglu	0:a8fa94490a0a	441	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
gokmenascioglu	0:a8fa94490a0a	442
gokmenascioglu	0:a8fa94490a0a	443	#define SCB_CCR_NONBASETHRDENA_Pos 0 /!< SCB CCR: NONBASETHRDENA Position /
gokmenascioglu	0:a8fa94490a0a	444	#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /!< SCB CCR: NONBASETHRDENA Mask /
gokmenascioglu	0:a8fa94490a0a	445
gokmenascioglu	0:a8fa94490a0a	446	/* SCB System Handler Control and State Register Definitions */
gokmenascioglu	0:a8fa94490a0a	447	#define SCB_SHCSR_USGFAULTENA_Pos 18 /!< SCB SHCSR: USGFAULTENA Position /
gokmenascioglu	0:a8fa94490a0a	448	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
gokmenascioglu	0:a8fa94490a0a	449
gokmenascioglu	0:a8fa94490a0a	450	#define SCB_SHCSR_BUSFAULTENA_Pos 17 /!< SCB SHCSR: BUSFAULTENA Position /
gokmenascioglu	0:a8fa94490a0a	451	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
gokmenascioglu	0:a8fa94490a0a	452
gokmenascioglu	0:a8fa94490a0a	453	#define SCB_SHCSR_MEMFAULTENA_Pos 16 /!< SCB SHCSR: MEMFAULTENA Position /
gokmenascioglu	0:a8fa94490a0a	454	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
gokmenascioglu	0:a8fa94490a0a	455
gokmenascioglu	0:a8fa94490a0a	456	#define SCB_SHCSR_SVCALLPENDED_Pos 15 /!< SCB SHCSR: SVCALLPENDED Position /
gokmenascioglu	0:a8fa94490a0a	457	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
gokmenascioglu	0:a8fa94490a0a	458
gokmenascioglu	0:a8fa94490a0a	459	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /!< SCB SHCSR: BUSFAULTPENDED Position /
gokmenascioglu	0:a8fa94490a0a	460	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
gokmenascioglu	0:a8fa94490a0a	461
gokmenascioglu	0:a8fa94490a0a	462	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /!< SCB SHCSR: MEMFAULTPENDED Position /
gokmenascioglu	0:a8fa94490a0a	463	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
gokmenascioglu	0:a8fa94490a0a	464
gokmenascioglu	0:a8fa94490a0a	465	#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /!< SCB SHCSR: USGFAULTPENDED Position /
gokmenascioglu	0:a8fa94490a0a	466	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
gokmenascioglu	0:a8fa94490a0a	467
gokmenascioglu	0:a8fa94490a0a	468	#define SCB_SHCSR_SYSTICKACT_Pos 11 /!< SCB SHCSR: SYSTICKACT Position /
gokmenascioglu	0:a8fa94490a0a	469	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
gokmenascioglu	0:a8fa94490a0a	470
gokmenascioglu	0:a8fa94490a0a	471	#define SCB_SHCSR_PENDSVACT_Pos 10 /!< SCB SHCSR: PENDSVACT Position /
gokmenascioglu	0:a8fa94490a0a	472	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
gokmenascioglu	0:a8fa94490a0a	473
gokmenascioglu	0:a8fa94490a0a	474	#define SCB_SHCSR_MONITORACT_Pos 8 /!< SCB SHCSR: MONITORACT Position /
gokmenascioglu	0:a8fa94490a0a	475	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
gokmenascioglu	0:a8fa94490a0a	476
gokmenascioglu	0:a8fa94490a0a	477	#define SCB_SHCSR_SVCALLACT_Pos 7 /!< SCB SHCSR: SVCALLACT Position /
gokmenascioglu	0:a8fa94490a0a	478	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
gokmenascioglu	0:a8fa94490a0a	479
gokmenascioglu	0:a8fa94490a0a	480	#define SCB_SHCSR_USGFAULTACT_Pos 3 /!< SCB SHCSR: USGFAULTACT Position /
gokmenascioglu	0:a8fa94490a0a	481	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
gokmenascioglu	0:a8fa94490a0a	482
gokmenascioglu	0:a8fa94490a0a	483	#define SCB_SHCSR_BUSFAULTACT_Pos 1 /!< SCB SHCSR: BUSFAULTACT Position /
gokmenascioglu	0:a8fa94490a0a	484	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
gokmenascioglu	0:a8fa94490a0a	485
gokmenascioglu	0:a8fa94490a0a	486	#define SCB_SHCSR_MEMFAULTACT_Pos 0 /!< SCB SHCSR: MEMFAULTACT Position /
gokmenascioglu	0:a8fa94490a0a	487	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /!< SCB SHCSR: MEMFAULTACT Mask /
gokmenascioglu	0:a8fa94490a0a	488
gokmenascioglu	0:a8fa94490a0a	489	/* SCB Configurable Fault Status Registers Definitions */
gokmenascioglu	0:a8fa94490a0a	490	#define SCB_CFSR_USGFAULTSR_Pos 16 /!< SCB CFSR: Usage Fault Status Register Position /
gokmenascioglu	0:a8fa94490a0a	491	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
gokmenascioglu	0:a8fa94490a0a	492
gokmenascioglu	0:a8fa94490a0a	493	#define SCB_CFSR_BUSFAULTSR_Pos 8 /!< SCB CFSR: Bus Fault Status Register Position /
gokmenascioglu	0:a8fa94490a0a	494	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
gokmenascioglu	0:a8fa94490a0a	495
gokmenascioglu	0:a8fa94490a0a	496	#define SCB_CFSR_MEMFAULTSR_Pos 0 /!< SCB CFSR: Memory Manage Fault Status Register Position /
gokmenascioglu	0:a8fa94490a0a	497	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
gokmenascioglu	0:a8fa94490a0a	498
gokmenascioglu	0:a8fa94490a0a	499	/* SCB Hard Fault Status Registers Definitions */
gokmenascioglu	0:a8fa94490a0a	500	#define SCB_HFSR_DEBUGEVT_Pos 31 /!< SCB HFSR: DEBUGEVT Position /
gokmenascioglu	0:a8fa94490a0a	501	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
gokmenascioglu	0:a8fa94490a0a	502
gokmenascioglu	0:a8fa94490a0a	503	#define SCB_HFSR_FORCED_Pos 30 /!< SCB HFSR: FORCED Position /
gokmenascioglu	0:a8fa94490a0a	504	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
gokmenascioglu	0:a8fa94490a0a	505
gokmenascioglu	0:a8fa94490a0a	506	#define SCB_HFSR_VECTTBL_Pos 1 /!< SCB HFSR: VECTTBL Position /
gokmenascioglu	0:a8fa94490a0a	507	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
gokmenascioglu	0:a8fa94490a0a	508
gokmenascioglu	0:a8fa94490a0a	509	/* SCB Debug Fault Status Register Definitions */
gokmenascioglu	0:a8fa94490a0a	510	#define SCB_DFSR_EXTERNAL_Pos 4 /!< SCB DFSR: EXTERNAL Position /
gokmenascioglu	0:a8fa94490a0a	511	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
gokmenascioglu	0:a8fa94490a0a	512
gokmenascioglu	0:a8fa94490a0a	513	#define SCB_DFSR_VCATCH_Pos 3 /!< SCB DFSR: VCATCH Position /
gokmenascioglu	0:a8fa94490a0a	514	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
gokmenascioglu	0:a8fa94490a0a	515
gokmenascioglu	0:a8fa94490a0a	516	#define SCB_DFSR_DWTTRAP_Pos 2 /!< SCB DFSR: DWTTRAP Position /
gokmenascioglu	0:a8fa94490a0a	517	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
gokmenascioglu	0:a8fa94490a0a	518
gokmenascioglu	0:a8fa94490a0a	519	#define SCB_DFSR_BKPT_Pos 1 /!< SCB DFSR: BKPT Position /
gokmenascioglu	0:a8fa94490a0a	520	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
gokmenascioglu	0:a8fa94490a0a	521
gokmenascioglu	0:a8fa94490a0a	522	#define SCB_DFSR_HALTED_Pos 0 /!< SCB DFSR: HALTED Position /
gokmenascioglu	0:a8fa94490a0a	523	#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /!< SCB DFSR: HALTED Mask /
gokmenascioglu	0:a8fa94490a0a	524
gokmenascioglu	0:a8fa94490a0a	525	/@} end of group CMSIS_SCB /
gokmenascioglu	0:a8fa94490a0a	526
gokmenascioglu	0:a8fa94490a0a	527
gokmenascioglu	0:a8fa94490a0a	528	/** \ingroup CMSIS_core_register
gokmenascioglu	0:a8fa94490a0a	529	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
gokmenascioglu	0:a8fa94490a0a	530	\brief Type definitions for the System Control and ID Register not in the SCB
gokmenascioglu	0:a8fa94490a0a	531	@{
gokmenascioglu	0:a8fa94490a0a	532	*/
gokmenascioglu	0:a8fa94490a0a	533
gokmenascioglu	0:a8fa94490a0a	534	/** \brief Structure type to access the System Control and ID Register not in the SCB.
gokmenascioglu	0:a8fa94490a0a	535	*/
gokmenascioglu	0:a8fa94490a0a	536	typedef struct
gokmenascioglu	0:a8fa94490a0a	537	{
gokmenascioglu	0:a8fa94490a0a	538	uint32_t RESERVED0[1];
gokmenascioglu	0:a8fa94490a0a	539	__I uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
gokmenascioglu	0:a8fa94490a0a	540	#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
gokmenascioglu	0:a8fa94490a0a	541	__IO uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
gokmenascioglu	0:a8fa94490a0a	542	#else
gokmenascioglu	0:a8fa94490a0a	543	uint32_t RESERVED1[1];
gokmenascioglu	0:a8fa94490a0a	544	#endif
gokmenascioglu	0:a8fa94490a0a	545	} SCnSCB_Type;
gokmenascioglu	0:a8fa94490a0a	546
gokmenascioglu	0:a8fa94490a0a	547	/* Interrupt Controller Type Register Definitions */
gokmenascioglu	0:a8fa94490a0a	548	#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /!< ICTR: INTLINESNUM Position /
gokmenascioglu	0:a8fa94490a0a	549	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /!< ICTR: INTLINESNUM Mask /
gokmenascioglu	0:a8fa94490a0a	550
gokmenascioglu	0:a8fa94490a0a	551	/* Auxiliary Control Register Definitions */
gokmenascioglu	0:a8fa94490a0a	552
gokmenascioglu	0:a8fa94490a0a	553	#define SCnSCB_ACTLR_DISFOLD_Pos 2 /!< ACTLR: DISFOLD Position /
gokmenascioglu	0:a8fa94490a0a	554	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
gokmenascioglu	0:a8fa94490a0a	555
gokmenascioglu	0:a8fa94490a0a	556	#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /!< ACTLR: DISDEFWBUF Position /
gokmenascioglu	0:a8fa94490a0a	557	#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /!< ACTLR: DISDEFWBUF Mask /
gokmenascioglu	0:a8fa94490a0a	558
gokmenascioglu	0:a8fa94490a0a	559	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /!< ACTLR: DISMCYCINT Position /
gokmenascioglu	0:a8fa94490a0a	560	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /!< ACTLR: DISMCYCINT Mask /
gokmenascioglu	0:a8fa94490a0a	561
gokmenascioglu	0:a8fa94490a0a	562	/@} end of group CMSIS_SCnotSCB /
gokmenascioglu	0:a8fa94490a0a	563
gokmenascioglu	0:a8fa94490a0a	564
gokmenascioglu	0:a8fa94490a0a	565	/** \ingroup CMSIS_core_register
gokmenascioglu	0:a8fa94490a0a	566	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
gokmenascioglu	0:a8fa94490a0a	567	\brief Type definitions for the System Timer Registers.
gokmenascioglu	0:a8fa94490a0a	568	@{
gokmenascioglu	0:a8fa94490a0a	569	*/
gokmenascioglu	0:a8fa94490a0a	570
gokmenascioglu	0:a8fa94490a0a	571	/** \brief Structure type to access the System Timer (SysTick).
gokmenascioglu	0:a8fa94490a0a	572	*/
gokmenascioglu	0:a8fa94490a0a	573	typedef struct
gokmenascioglu	0:a8fa94490a0a	574	{
gokmenascioglu	0:a8fa94490a0a	575	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
gokmenascioglu	0:a8fa94490a0a	576	__IO uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
gokmenascioglu	0:a8fa94490a0a	577	__IO uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
gokmenascioglu	0:a8fa94490a0a	578	__I uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
gokmenascioglu	0:a8fa94490a0a	579	} SysTick_Type;
gokmenascioglu	0:a8fa94490a0a	580
gokmenascioglu	0:a8fa94490a0a	581	/* SysTick Control / Status Register Definitions */
gokmenascioglu	0:a8fa94490a0a	582	#define SysTick_CTRL_COUNTFLAG_Pos 16 /!< SysTick CTRL: COUNTFLAG Position /
gokmenascioglu	0:a8fa94490a0a	583	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
gokmenascioglu	0:a8fa94490a0a	584
gokmenascioglu	0:a8fa94490a0a	585	#define SysTick_CTRL_CLKSOURCE_Pos 2 /!< SysTick CTRL: CLKSOURCE Position /
gokmenascioglu	0:a8fa94490a0a	586	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
gokmenascioglu	0:a8fa94490a0a	587
gokmenascioglu	0:a8fa94490a0a	588	#define SysTick_CTRL_TICKINT_Pos 1 /!< SysTick CTRL: TICKINT Position /
gokmenascioglu	0:a8fa94490a0a	589	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
gokmenascioglu	0:a8fa94490a0a	590
gokmenascioglu	0:a8fa94490a0a	591	#define SysTick_CTRL_ENABLE_Pos 0 /!< SysTick CTRL: ENABLE Position /
gokmenascioglu	0:a8fa94490a0a	592	#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /!< SysTick CTRL: ENABLE Mask /
gokmenascioglu	0:a8fa94490a0a	593
gokmenascioglu	0:a8fa94490a0a	594	/* SysTick Reload Register Definitions */
gokmenascioglu	0:a8fa94490a0a	595	#define SysTick_LOAD_RELOAD_Pos 0 /!< SysTick LOAD: RELOAD Position /
gokmenascioglu	0:a8fa94490a0a	596	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /!< SysTick LOAD: RELOAD Mask /
gokmenascioglu	0:a8fa94490a0a	597
gokmenascioglu	0:a8fa94490a0a	598	/* SysTick Current Register Definitions */
gokmenascioglu	0:a8fa94490a0a	599	#define SysTick_VAL_CURRENT_Pos 0 /!< SysTick VAL: CURRENT Position /
gokmenascioglu	0:a8fa94490a0a	600	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /!< SysTick VAL: CURRENT Mask /
gokmenascioglu	0:a8fa94490a0a	601
gokmenascioglu	0:a8fa94490a0a	602	/* SysTick Calibration Register Definitions */
gokmenascioglu	0:a8fa94490a0a	603	#define SysTick_CALIB_NOREF_Pos 31 /!< SysTick CALIB: NOREF Position /
gokmenascioglu	0:a8fa94490a0a	604	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
gokmenascioglu	0:a8fa94490a0a	605
gokmenascioglu	0:a8fa94490a0a	606	#define SysTick_CALIB_SKEW_Pos 30 /!< SysTick CALIB: SKEW Position /
gokmenascioglu	0:a8fa94490a0a	607	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
gokmenascioglu	0:a8fa94490a0a	608
gokmenascioglu	0:a8fa94490a0a	609	#define SysTick_CALIB_TENMS_Pos 0 /!< SysTick CALIB: TENMS Position /
gokmenascioglu	0:a8fa94490a0a	610	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /!< SysTick CALIB: TENMS Mask /
gokmenascioglu	0:a8fa94490a0a	611
gokmenascioglu	0:a8fa94490a0a	612	/@} end of group CMSIS_SysTick /
gokmenascioglu	0:a8fa94490a0a	613
gokmenascioglu	0:a8fa94490a0a	614
gokmenascioglu	0:a8fa94490a0a	615	/** \ingroup CMSIS_core_register
gokmenascioglu	0:a8fa94490a0a	616	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
gokmenascioglu	0:a8fa94490a0a	617	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
gokmenascioglu	0:a8fa94490a0a	618	@{
gokmenascioglu	0:a8fa94490a0a	619	*/
gokmenascioglu	0:a8fa94490a0a	620
gokmenascioglu	0:a8fa94490a0a	621	/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
gokmenascioglu	0:a8fa94490a0a	622	*/
gokmenascioglu	0:a8fa94490a0a	623	typedef struct
gokmenascioglu	0:a8fa94490a0a	624	{
gokmenascioglu	0:a8fa94490a0a	625	__O union
gokmenascioglu	0:a8fa94490a0a	626	{
gokmenascioglu	0:a8fa94490a0a	627	__O uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
gokmenascioglu	0:a8fa94490a0a	628	__O uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
gokmenascioglu	0:a8fa94490a0a	629	__O uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
gokmenascioglu	0:a8fa94490a0a	630	} PORT [32]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
gokmenascioglu	0:a8fa94490a0a	631	uint32_t RESERVED0[864];
gokmenascioglu	0:a8fa94490a0a	632	__IO uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
gokmenascioglu	0:a8fa94490a0a	633	uint32_t RESERVED1[15];
gokmenascioglu	0:a8fa94490a0a	634	__IO uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
gokmenascioglu	0:a8fa94490a0a	635	uint32_t RESERVED2[15];
gokmenascioglu	0:a8fa94490a0a	636	__IO uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
gokmenascioglu	0:a8fa94490a0a	637	} ITM_Type;
gokmenascioglu	0:a8fa94490a0a	638
gokmenascioglu	0:a8fa94490a0a	639	/* ITM Trace Privilege Register Definitions */
gokmenascioglu	0:a8fa94490a0a	640	#define ITM_TPR_PRIVMASK_Pos 0 /!< ITM TPR: PRIVMASK Position /
gokmenascioglu	0:a8fa94490a0a	641	#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /!< ITM TPR: PRIVMASK Mask /
gokmenascioglu	0:a8fa94490a0a	642
gokmenascioglu	0:a8fa94490a0a	643	/* ITM Trace Control Register Definitions */
gokmenascioglu	0:a8fa94490a0a	644	#define ITM_TCR_BUSY_Pos 23 /!< ITM TCR: BUSY Position /
gokmenascioglu	0:a8fa94490a0a	645	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
gokmenascioglu	0:a8fa94490a0a	646
gokmenascioglu	0:a8fa94490a0a	647	#define ITM_TCR_TraceBusID_Pos 16 /!< ITM TCR: ATBID Position /
gokmenascioglu	0:a8fa94490a0a	648	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
gokmenascioglu	0:a8fa94490a0a	649
gokmenascioglu	0:a8fa94490a0a	650	#define ITM_TCR_GTSFREQ_Pos 10 /!< ITM TCR: Global timestamp frequency Position /
gokmenascioglu	0:a8fa94490a0a	651	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
gokmenascioglu	0:a8fa94490a0a	652
gokmenascioglu	0:a8fa94490a0a	653	#define ITM_TCR_TSPrescale_Pos 8 /!< ITM TCR: TSPrescale Position /
gokmenascioglu	0:a8fa94490a0a	654	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
gokmenascioglu	0:a8fa94490a0a	655
gokmenascioglu	0:a8fa94490a0a	656	#define ITM_TCR_SWOENA_Pos 4 /!< ITM TCR: SWOENA Position /
gokmenascioglu	0:a8fa94490a0a	657	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
gokmenascioglu	0:a8fa94490a0a	658
gokmenascioglu	0:a8fa94490a0a	659	#define ITM_TCR_TXENA_Pos 3 /!< ITM TCR: TXENA Position /
gokmenascioglu	0:a8fa94490a0a	660	#define ITM_TCR_TXENA_Msk (1UL << ITM_TCR_TXENA_Pos) /!< ITM TCR: TXENA Mask /
gokmenascioglu	0:a8fa94490a0a	661
gokmenascioglu	0:a8fa94490a0a	662	#define ITM_TCR_SYNCENA_Pos 2 /!< ITM TCR: SYNCENA Position /
gokmenascioglu	0:a8fa94490a0a	663	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
gokmenascioglu	0:a8fa94490a0a	664
gokmenascioglu	0:a8fa94490a0a	665	#define ITM_TCR_TSENA_Pos 1 /!< ITM TCR: TSENA Position /
gokmenascioglu	0:a8fa94490a0a	666	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
gokmenascioglu	0:a8fa94490a0a	667
gokmenascioglu	0:a8fa94490a0a	668	#define ITM_TCR_ITMENA_Pos 0 /!< ITM TCR: ITM Enable bit Position /
gokmenascioglu	0:a8fa94490a0a	669	#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /!< ITM TCR: ITM Enable bit Mask /
gokmenascioglu	0:a8fa94490a0a	670
gokmenascioglu	0:a8fa94490a0a	671	/@}/ /* end of group CMSIS_ITM */
gokmenascioglu	0:a8fa94490a0a	672
gokmenascioglu	0:a8fa94490a0a	673
gokmenascioglu	0:a8fa94490a0a	674	/** \ingroup CMSIS_core_register
gokmenascioglu	0:a8fa94490a0a	675	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
gokmenascioglu	0:a8fa94490a0a	676	\brief Type definitions for the Data Watchpoint and Trace (DWT)
gokmenascioglu	0:a8fa94490a0a	677	@{
gokmenascioglu	0:a8fa94490a0a	678	*/
gokmenascioglu	0:a8fa94490a0a	679
gokmenascioglu	0:a8fa94490a0a	680	/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
gokmenascioglu	0:a8fa94490a0a	681	*/
gokmenascioglu	0:a8fa94490a0a	682	typedef struct
gokmenascioglu	0:a8fa94490a0a	683	{
gokmenascioglu	0:a8fa94490a0a	684	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
gokmenascioglu	0:a8fa94490a0a	685	__IO uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
gokmenascioglu	0:a8fa94490a0a	686	__IO uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
gokmenascioglu	0:a8fa94490a0a	687	__IO uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
gokmenascioglu	0:a8fa94490a0a	688	__IO uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
gokmenascioglu	0:a8fa94490a0a	689	__IO uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
gokmenascioglu	0:a8fa94490a0a	690	__IO uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
gokmenascioglu	0:a8fa94490a0a	691	__I uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
gokmenascioglu	0:a8fa94490a0a	692	__IO uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
gokmenascioglu	0:a8fa94490a0a	693	__IO uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
gokmenascioglu	0:a8fa94490a0a	694	__IO uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
gokmenascioglu	0:a8fa94490a0a	695	uint32_t RESERVED0[1];
gokmenascioglu	0:a8fa94490a0a	696	__IO uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
gokmenascioglu	0:a8fa94490a0a	697	__IO uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
gokmenascioglu	0:a8fa94490a0a	698	__IO uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
gokmenascioglu	0:a8fa94490a0a	699	uint32_t RESERVED1[1];
gokmenascioglu	0:a8fa94490a0a	700	__IO uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
gokmenascioglu	0:a8fa94490a0a	701	__IO uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
gokmenascioglu	0:a8fa94490a0a	702	__IO uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
gokmenascioglu	0:a8fa94490a0a	703	uint32_t RESERVED2[1];
gokmenascioglu	0:a8fa94490a0a	704	__IO uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
gokmenascioglu	0:a8fa94490a0a	705	__IO uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
gokmenascioglu	0:a8fa94490a0a	706	__IO uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
gokmenascioglu	0:a8fa94490a0a	707	} DWT_Type;
gokmenascioglu	0:a8fa94490a0a	708
gokmenascioglu	0:a8fa94490a0a	709	/* DWT Control Register Definitions */
gokmenascioglu	0:a8fa94490a0a	710	#define DWT_CTRL_NUMCOMP_Pos 28 /!< DWT CTRL: NUMCOMP Position /
gokmenascioglu	0:a8fa94490a0a	711	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
gokmenascioglu	0:a8fa94490a0a	712
gokmenascioglu	0:a8fa94490a0a	713	#define DWT_CTRL_NOTRCPKT_Pos 27 /!< DWT CTRL: NOTRCPKT Position /
gokmenascioglu	0:a8fa94490a0a	714	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
gokmenascioglu	0:a8fa94490a0a	715
gokmenascioglu	0:a8fa94490a0a	716	#define DWT_CTRL_NOEXTTRIG_Pos 26 /!< DWT CTRL: NOEXTTRIG Position /
gokmenascioglu	0:a8fa94490a0a	717	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
gokmenascioglu	0:a8fa94490a0a	718
gokmenascioglu	0:a8fa94490a0a	719	#define DWT_CTRL_NOCYCCNT_Pos 25 /!< DWT CTRL: NOCYCCNT Position /
gokmenascioglu	0:a8fa94490a0a	720	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
gokmenascioglu	0:a8fa94490a0a	721
gokmenascioglu	0:a8fa94490a0a	722	#define DWT_CTRL_NOPRFCNT_Pos 24 /!< DWT CTRL: NOPRFCNT Position /
gokmenascioglu	0:a8fa94490a0a	723	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
gokmenascioglu	0:a8fa94490a0a	724
gokmenascioglu	0:a8fa94490a0a	725	#define DWT_CTRL_CYCEVTENA_Pos 22 /!< DWT CTRL: CYCEVTENA Position /
gokmenascioglu	0:a8fa94490a0a	726	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
gokmenascioglu	0:a8fa94490a0a	727
gokmenascioglu	0:a8fa94490a0a	728	#define DWT_CTRL_FOLDEVTENA_Pos 21 /!< DWT CTRL: FOLDEVTENA Position /
gokmenascioglu	0:a8fa94490a0a	729	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
gokmenascioglu	0:a8fa94490a0a	730
gokmenascioglu	0:a8fa94490a0a	731	#define DWT_CTRL_LSUEVTENA_Pos 20 /!< DWT CTRL: LSUEVTENA Position /
gokmenascioglu	0:a8fa94490a0a	732	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
gokmenascioglu	0:a8fa94490a0a	733
gokmenascioglu	0:a8fa94490a0a	734	#define DWT_CTRL_SLEEPEVTENA_Pos 19 /!< DWT CTRL: SLEEPEVTENA Position /
gokmenascioglu	0:a8fa94490a0a	735	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
gokmenascioglu	0:a8fa94490a0a	736
gokmenascioglu	0:a8fa94490a0a	737	#define DWT_CTRL_EXCEVTENA_Pos 18 /!< DWT CTRL: EXCEVTENA Position /
gokmenascioglu	0:a8fa94490a0a	738	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
gokmenascioglu	0:a8fa94490a0a	739
gokmenascioglu	0:a8fa94490a0a	740	#define DWT_CTRL_CPIEVTENA_Pos 17 /!< DWT CTRL: CPIEVTENA Position /
gokmenascioglu	0:a8fa94490a0a	741	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
gokmenascioglu	0:a8fa94490a0a	742
gokmenascioglu	0:a8fa94490a0a	743	#define DWT_CTRL_EXCTRCENA_Pos 16 /!< DWT CTRL: EXCTRCENA Position /
gokmenascioglu	0:a8fa94490a0a	744	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
gokmenascioglu	0:a8fa94490a0a	745
gokmenascioglu	0:a8fa94490a0a	746	#define DWT_CTRL_PCSAMPLENA_Pos 12 /!< DWT CTRL: PCSAMPLENA Position /
gokmenascioglu	0:a8fa94490a0a	747	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
gokmenascioglu	0:a8fa94490a0a	748
gokmenascioglu	0:a8fa94490a0a	749	#define DWT_CTRL_SYNCTAP_Pos 10 /!< DWT CTRL: SYNCTAP Position /
gokmenascioglu	0:a8fa94490a0a	750	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
gokmenascioglu	0:a8fa94490a0a	751
gokmenascioglu	0:a8fa94490a0a	752	#define DWT_CTRL_CYCTAP_Pos 9 /!< DWT CTRL: CYCTAP Position /
gokmenascioglu	0:a8fa94490a0a	753	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
gokmenascioglu	0:a8fa94490a0a	754
gokmenascioglu	0:a8fa94490a0a	755	#define DWT_CTRL_POSTINIT_Pos 5 /!< DWT CTRL: POSTINIT Position /
gokmenascioglu	0:a8fa94490a0a	756	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
gokmenascioglu	0:a8fa94490a0a	757
gokmenascioglu	0:a8fa94490a0a	758	#define DWT_CTRL_POSTPRESET_Pos 1 /!< DWT CTRL: POSTPRESET Position /
gokmenascioglu	0:a8fa94490a0a	759	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
gokmenascioglu	0:a8fa94490a0a	760
gokmenascioglu	0:a8fa94490a0a	761	#define DWT_CTRL_CYCCNTENA_Pos 0 /!< DWT CTRL: CYCCNTENA Position /
gokmenascioglu	0:a8fa94490a0a	762	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /!< DWT CTRL: CYCCNTENA Mask /
gokmenascioglu	0:a8fa94490a0a	763
gokmenascioglu	0:a8fa94490a0a	764	/* DWT CPI Count Register Definitions */
gokmenascioglu	0:a8fa94490a0a	765	#define DWT_CPICNT_CPICNT_Pos 0 /!< DWT CPICNT: CPICNT Position /
gokmenascioglu	0:a8fa94490a0a	766	#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /!< DWT CPICNT: CPICNT Mask /
gokmenascioglu	0:a8fa94490a0a	767
gokmenascioglu	0:a8fa94490a0a	768	/* DWT Exception Overhead Count Register Definitions */
gokmenascioglu	0:a8fa94490a0a	769	#define DWT_EXCCNT_EXCCNT_Pos 0 /!< DWT EXCCNT: EXCCNT Position /
gokmenascioglu	0:a8fa94490a0a	770	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /!< DWT EXCCNT: EXCCNT Mask /
gokmenascioglu	0:a8fa94490a0a	771
gokmenascioglu	0:a8fa94490a0a	772	/* DWT Sleep Count Register Definitions */
gokmenascioglu	0:a8fa94490a0a	773	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /!< DWT SLEEPCNT: SLEEPCNT Position /
gokmenascioglu	0:a8fa94490a0a	774	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /!< DWT SLEEPCNT: SLEEPCNT Mask /
gokmenascioglu	0:a8fa94490a0a	775
gokmenascioglu	0:a8fa94490a0a	776	/* DWT LSU Count Register Definitions */
gokmenascioglu	0:a8fa94490a0a	777	#define DWT_LSUCNT_LSUCNT_Pos 0 /!< DWT LSUCNT: LSUCNT Position /
gokmenascioglu	0:a8fa94490a0a	778	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /!< DWT LSUCNT: LSUCNT Mask /
gokmenascioglu	0:a8fa94490a0a	779
gokmenascioglu	0:a8fa94490a0a	780	/* DWT Folded-instruction Count Register Definitions */
gokmenascioglu	0:a8fa94490a0a	781	#define DWT_FOLDCNT_FOLDCNT_Pos 0 /!< DWT FOLDCNT: FOLDCNT Position /
gokmenascioglu	0:a8fa94490a0a	782	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /!< DWT FOLDCNT: FOLDCNT Mask /
gokmenascioglu	0:a8fa94490a0a	783
gokmenascioglu	0:a8fa94490a0a	784	/* DWT Comparator Mask Register Definitions */
gokmenascioglu	0:a8fa94490a0a	785	#define DWT_MASK_MASK_Pos 0 /!< DWT MASK: MASK Position /
gokmenascioglu	0:a8fa94490a0a	786	#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /!< DWT MASK: MASK Mask /
gokmenascioglu	0:a8fa94490a0a	787
gokmenascioglu	0:a8fa94490a0a	788	/* DWT Comparator Function Register Definitions */
gokmenascioglu	0:a8fa94490a0a	789	#define DWT_FUNCTION_MATCHED_Pos 24 /!< DWT FUNCTION: MATCHED Position /
gokmenascioglu	0:a8fa94490a0a	790	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
gokmenascioglu	0:a8fa94490a0a	791
gokmenascioglu	0:a8fa94490a0a	792	#define DWT_FUNCTION_DATAVADDR1_Pos 16 /!< DWT FUNCTION: DATAVADDR1 Position /
gokmenascioglu	0:a8fa94490a0a	793	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
gokmenascioglu	0:a8fa94490a0a	794
gokmenascioglu	0:a8fa94490a0a	795	#define DWT_FUNCTION_DATAVADDR0_Pos 12 /!< DWT FUNCTION: DATAVADDR0 Position /
gokmenascioglu	0:a8fa94490a0a	796	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
gokmenascioglu	0:a8fa94490a0a	797
gokmenascioglu	0:a8fa94490a0a	798	#define DWT_FUNCTION_DATAVSIZE_Pos 10 /!< DWT FUNCTION: DATAVSIZE Position /
gokmenascioglu	0:a8fa94490a0a	799	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
gokmenascioglu	0:a8fa94490a0a	800
gokmenascioglu	0:a8fa94490a0a	801	#define DWT_FUNCTION_LNK1ENA_Pos 9 /!< DWT FUNCTION: LNK1ENA Position /
gokmenascioglu	0:a8fa94490a0a	802	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
gokmenascioglu	0:a8fa94490a0a	803
gokmenascioglu	0:a8fa94490a0a	804	#define DWT_FUNCTION_DATAVMATCH_Pos 8 /!< DWT FUNCTION: DATAVMATCH Position /
gokmenascioglu	0:a8fa94490a0a	805	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
gokmenascioglu	0:a8fa94490a0a	806
gokmenascioglu	0:a8fa94490a0a	807	#define DWT_FUNCTION_CYCMATCH_Pos 7 /!< DWT FUNCTION: CYCMATCH Position /
gokmenascioglu	0:a8fa94490a0a	808	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
gokmenascioglu	0:a8fa94490a0a	809
gokmenascioglu	0:a8fa94490a0a	810	#define DWT_FUNCTION_EMITRANGE_Pos 5 /!< DWT FUNCTION: EMITRANGE Position /
gokmenascioglu	0:a8fa94490a0a	811	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
gokmenascioglu	0:a8fa94490a0a	812
gokmenascioglu	0:a8fa94490a0a	813	#define DWT_FUNCTION_FUNCTION_Pos 0 /!< DWT FUNCTION: FUNCTION Position /
gokmenascioglu	0:a8fa94490a0a	814	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /!< DWT FUNCTION: FUNCTION Mask /
gokmenascioglu	0:a8fa94490a0a	815
gokmenascioglu	0:a8fa94490a0a	816	/@}/ /* end of group CMSIS_DWT */
gokmenascioglu	0:a8fa94490a0a	817
gokmenascioglu	0:a8fa94490a0a	818
gokmenascioglu	0:a8fa94490a0a	819	/** \ingroup CMSIS_core_register
gokmenascioglu	0:a8fa94490a0a	820	\defgroup CMSIS_TPI Trace Port Interface (TPI)
gokmenascioglu	0:a8fa94490a0a	821	\brief Type definitions for the Trace Port Interface (TPI)
gokmenascioglu	0:a8fa94490a0a	822	@{
gokmenascioglu	0:a8fa94490a0a	823	*/
gokmenascioglu	0:a8fa94490a0a	824
gokmenascioglu	0:a8fa94490a0a	825	/** \brief Structure type to access the Trace Port Interface Register (TPI).
gokmenascioglu	0:a8fa94490a0a	826	*/
gokmenascioglu	0:a8fa94490a0a	827	typedef struct
gokmenascioglu	0:a8fa94490a0a	828	{
gokmenascioglu	0:a8fa94490a0a	829	__IO uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
gokmenascioglu	0:a8fa94490a0a	830	__IO uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
gokmenascioglu	0:a8fa94490a0a	831	uint32_t RESERVED0[2];
gokmenascioglu	0:a8fa94490a0a	832	__IO uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
gokmenascioglu	0:a8fa94490a0a	833	uint32_t RESERVED1[55];
gokmenascioglu	0:a8fa94490a0a	834	__IO uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
gokmenascioglu	0:a8fa94490a0a	835	uint32_t RESERVED2[131];
gokmenascioglu	0:a8fa94490a0a	836	__I uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
gokmenascioglu	0:a8fa94490a0a	837	__IO uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
gokmenascioglu	0:a8fa94490a0a	838	__I uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
gokmenascioglu	0:a8fa94490a0a	839	uint32_t RESERVED3[759];
gokmenascioglu	0:a8fa94490a0a	840	__I uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
gokmenascioglu	0:a8fa94490a0a	841	__I uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
gokmenascioglu	0:a8fa94490a0a	842	__I uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
gokmenascioglu	0:a8fa94490a0a	843	uint32_t RESERVED4[1];
gokmenascioglu	0:a8fa94490a0a	844	__I uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
gokmenascioglu	0:a8fa94490a0a	845	__I uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
gokmenascioglu	0:a8fa94490a0a	846	__IO uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
gokmenascioglu	0:a8fa94490a0a	847	uint32_t RESERVED5[39];
gokmenascioglu	0:a8fa94490a0a	848	__IO uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
gokmenascioglu	0:a8fa94490a0a	849	__IO uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
gokmenascioglu	0:a8fa94490a0a	850	uint32_t RESERVED7[8];
gokmenascioglu	0:a8fa94490a0a	851	__I uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
gokmenascioglu	0:a8fa94490a0a	852	__I uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
gokmenascioglu	0:a8fa94490a0a	853	} TPI_Type;
gokmenascioglu	0:a8fa94490a0a	854
gokmenascioglu	0:a8fa94490a0a	855	/* TPI Asynchronous Clock Prescaler Register Definitions */
gokmenascioglu	0:a8fa94490a0a	856	#define TPI_ACPR_PRESCALER_Pos 0 /!< TPI ACPR: PRESCALER Position /
gokmenascioglu	0:a8fa94490a0a	857	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /!< TPI ACPR: PRESCALER Mask /
gokmenascioglu	0:a8fa94490a0a	858
gokmenascioglu	0:a8fa94490a0a	859	/* TPI Selected Pin Protocol Register Definitions */
gokmenascioglu	0:a8fa94490a0a	860	#define TPI_SPPR_TXMODE_Pos 0 /!< TPI SPPR: TXMODE Position /
gokmenascioglu	0:a8fa94490a0a	861	#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /!< TPI SPPR: TXMODE Mask /
gokmenascioglu	0:a8fa94490a0a	862
gokmenascioglu	0:a8fa94490a0a	863	/* TPI Formatter and Flush Status Register Definitions */
gokmenascioglu	0:a8fa94490a0a	864	#define TPI_FFSR_FtNonStop_Pos 3 /!< TPI FFSR: FtNonStop Position /
gokmenascioglu	0:a8fa94490a0a	865	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
gokmenascioglu	0:a8fa94490a0a	866
gokmenascioglu	0:a8fa94490a0a	867	#define TPI_FFSR_TCPresent_Pos 2 /!< TPI FFSR: TCPresent Position /
gokmenascioglu	0:a8fa94490a0a	868	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
gokmenascioglu	0:a8fa94490a0a	869
gokmenascioglu	0:a8fa94490a0a	870	#define TPI_FFSR_FtStopped_Pos 1 /!< TPI FFSR: FtStopped Position /
gokmenascioglu	0:a8fa94490a0a	871	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
gokmenascioglu	0:a8fa94490a0a	872
gokmenascioglu	0:a8fa94490a0a	873	#define TPI_FFSR_FlInProg_Pos 0 /!< TPI FFSR: FlInProg Position /
gokmenascioglu	0:a8fa94490a0a	874	#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /!< TPI FFSR: FlInProg Mask /
gokmenascioglu	0:a8fa94490a0a	875
gokmenascioglu	0:a8fa94490a0a	876	/* TPI Formatter and Flush Control Register Definitions */
gokmenascioglu	0:a8fa94490a0a	877	#define TPI_FFCR_TrigIn_Pos 8 /!< TPI FFCR: TrigIn Position /
gokmenascioglu	0:a8fa94490a0a	878	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
gokmenascioglu	0:a8fa94490a0a	879
gokmenascioglu	0:a8fa94490a0a	880	#define TPI_FFCR_EnFCont_Pos 1 /!< TPI FFCR: EnFCont Position /
gokmenascioglu	0:a8fa94490a0a	881	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
gokmenascioglu	0:a8fa94490a0a	882
gokmenascioglu	0:a8fa94490a0a	883	/* TPI TRIGGER Register Definitions */
gokmenascioglu	0:a8fa94490a0a	884	#define TPI_TRIGGER_TRIGGER_Pos 0 /!< TPI TRIGGER: TRIGGER Position /
gokmenascioglu	0:a8fa94490a0a	885	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /!< TPI TRIGGER: TRIGGER Mask /
gokmenascioglu	0:a8fa94490a0a	886
gokmenascioglu	0:a8fa94490a0a	887	/* TPI Integration ETM Data Register Definitions (FIFO0) */
gokmenascioglu	0:a8fa94490a0a	888	#define TPI_FIFO0_ITM_ATVALID_Pos 29 /!< TPI FIFO0: ITM_ATVALID Position /
gokmenascioglu	0:a8fa94490a0a	889	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
gokmenascioglu	0:a8fa94490a0a	890
gokmenascioglu	0:a8fa94490a0a	891	#define TPI_FIFO0_ITM_bytecount_Pos 27 /!< TPI FIFO0: ITM_bytecount Position /
gokmenascioglu	0:a8fa94490a0a	892	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
gokmenascioglu	0:a8fa94490a0a	893
gokmenascioglu	0:a8fa94490a0a	894	#define TPI_FIFO0_ETM_ATVALID_Pos 26 /!< TPI FIFO0: ETM_ATVALID Position /
gokmenascioglu	0:a8fa94490a0a	895	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
gokmenascioglu	0:a8fa94490a0a	896
gokmenascioglu	0:a8fa94490a0a	897	#define TPI_FIFO0_ETM_bytecount_Pos 24 /!< TPI FIFO0: ETM_bytecount Position /
gokmenascioglu	0:a8fa94490a0a	898	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
gokmenascioglu	0:a8fa94490a0a	899
gokmenascioglu	0:a8fa94490a0a	900	#define TPI_FIFO0_ETM2_Pos 16 /!< TPI FIFO0: ETM2 Position /
gokmenascioglu	0:a8fa94490a0a	901	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
gokmenascioglu	0:a8fa94490a0a	902
gokmenascioglu	0:a8fa94490a0a	903	#define TPI_FIFO0_ETM1_Pos 8 /!< TPI FIFO0: ETM1 Position /
gokmenascioglu	0:a8fa94490a0a	904	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
gokmenascioglu	0:a8fa94490a0a	905
gokmenascioglu	0:a8fa94490a0a	906	#define TPI_FIFO0_ETM0_Pos 0 /!< TPI FIFO0: ETM0 Position /
gokmenascioglu	0:a8fa94490a0a	907	#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /!< TPI FIFO0: ETM0 Mask /
gokmenascioglu	0:a8fa94490a0a	908
gokmenascioglu	0:a8fa94490a0a	909	/* TPI ITATBCTR2 Register Definitions */
gokmenascioglu	0:a8fa94490a0a	910	#define TPI_ITATBCTR2_ATREADY_Pos 0 /!< TPI ITATBCTR2: ATREADY Position /
gokmenascioglu	0:a8fa94490a0a	911	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /!< TPI ITATBCTR2: ATREADY Mask /
gokmenascioglu	0:a8fa94490a0a	912
gokmenascioglu	0:a8fa94490a0a	913	/* TPI Integration ITM Data Register Definitions (FIFO1) */
gokmenascioglu	0:a8fa94490a0a	914	#define TPI_FIFO1_ITM_ATVALID_Pos 29 /!< TPI FIFO1: ITM_ATVALID Position /
gokmenascioglu	0:a8fa94490a0a	915	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
gokmenascioglu	0:a8fa94490a0a	916
gokmenascioglu	0:a8fa94490a0a	917	#define TPI_FIFO1_ITM_bytecount_Pos 27 /!< TPI FIFO1: ITM_bytecount Position /
gokmenascioglu	0:a8fa94490a0a	918	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
gokmenascioglu	0:a8fa94490a0a	919
gokmenascioglu	0:a8fa94490a0a	920	#define TPI_FIFO1_ETM_ATVALID_Pos 26 /!< TPI FIFO1: ETM_ATVALID Position /
gokmenascioglu	0:a8fa94490a0a	921	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
gokmenascioglu	0:a8fa94490a0a	922
gokmenascioglu	0:a8fa94490a0a	923	#define TPI_FIFO1_ETM_bytecount_Pos 24 /!< TPI FIFO1: ETM_bytecount Position /
gokmenascioglu	0:a8fa94490a0a	924	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
gokmenascioglu	0:a8fa94490a0a	925
gokmenascioglu	0:a8fa94490a0a	926	#define TPI_FIFO1_ITM2_Pos 16 /!< TPI FIFO1: ITM2 Position /
gokmenascioglu	0:a8fa94490a0a	927	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
gokmenascioglu	0:a8fa94490a0a	928
gokmenascioglu	0:a8fa94490a0a	929	#define TPI_FIFO1_ITM1_Pos 8 /!< TPI FIFO1: ITM1 Position /
gokmenascioglu	0:a8fa94490a0a	930	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
gokmenascioglu	0:a8fa94490a0a	931
gokmenascioglu	0:a8fa94490a0a	932	#define TPI_FIFO1_ITM0_Pos 0 /!< TPI FIFO1: ITM0 Position /
gokmenascioglu	0:a8fa94490a0a	933	#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /!< TPI FIFO1: ITM0 Mask /
gokmenascioglu	0:a8fa94490a0a	934
gokmenascioglu	0:a8fa94490a0a	935	/* TPI ITATBCTR0 Register Definitions */
gokmenascioglu	0:a8fa94490a0a	936	#define TPI_ITATBCTR0_ATREADY_Pos 0 /!< TPI ITATBCTR0: ATREADY Position /
gokmenascioglu	0:a8fa94490a0a	937	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /!< TPI ITATBCTR0: ATREADY Mask /
gokmenascioglu	0:a8fa94490a0a	938
gokmenascioglu	0:a8fa94490a0a	939	/* TPI Integration Mode Control Register Definitions */
gokmenascioglu	0:a8fa94490a0a	940	#define TPI_ITCTRL_Mode_Pos 0 /!< TPI ITCTRL: Mode Position /
gokmenascioglu	0:a8fa94490a0a	941	#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /!< TPI ITCTRL: Mode Mask /
gokmenascioglu	0:a8fa94490a0a	942
gokmenascioglu	0:a8fa94490a0a	943	/* TPI DEVID Register Definitions */
gokmenascioglu	0:a8fa94490a0a	944	#define TPI_DEVID_NRZVALID_Pos 11 /!< TPI DEVID: NRZVALID Position /
gokmenascioglu	0:a8fa94490a0a	945	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
gokmenascioglu	0:a8fa94490a0a	946
gokmenascioglu	0:a8fa94490a0a	947	#define TPI_DEVID_MANCVALID_Pos 10 /!< TPI DEVID: MANCVALID Position /
gokmenascioglu	0:a8fa94490a0a	948	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
gokmenascioglu	0:a8fa94490a0a	949
gokmenascioglu	0:a8fa94490a0a	950	#define TPI_DEVID_PTINVALID_Pos 9 /!< TPI DEVID: PTINVALID Position /
gokmenascioglu	0:a8fa94490a0a	951	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
gokmenascioglu	0:a8fa94490a0a	952
gokmenascioglu	0:a8fa94490a0a	953	#define TPI_DEVID_MinBufSz_Pos 6 /!< TPI DEVID: MinBufSz Position /
gokmenascioglu	0:a8fa94490a0a	954	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
gokmenascioglu	0:a8fa94490a0a	955
gokmenascioglu	0:a8fa94490a0a	956	#define TPI_DEVID_AsynClkIn_Pos 5 /!< TPI DEVID: AsynClkIn Position /
gokmenascioglu	0:a8fa94490a0a	957	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
gokmenascioglu	0:a8fa94490a0a	958
gokmenascioglu	0:a8fa94490a0a	959	#define TPI_DEVID_NrTraceInput_Pos 0 /!< TPI DEVID: NrTraceInput Position /
gokmenascioglu	0:a8fa94490a0a	960	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /!< TPI DEVID: NrTraceInput Mask /
gokmenascioglu	0:a8fa94490a0a	961
gokmenascioglu	0:a8fa94490a0a	962	/* TPI DEVTYPE Register Definitions */
gokmenascioglu	0:a8fa94490a0a	963	#define TPI_DEVTYPE_SubType_Pos 0 /!< TPI DEVTYPE: SubType Position /
gokmenascioglu	0:a8fa94490a0a	964	#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /!< TPI DEVTYPE: SubType Mask /
gokmenascioglu	0:a8fa94490a0a	965
gokmenascioglu	0:a8fa94490a0a	966	#define TPI_DEVTYPE_MajorType_Pos 4 /!< TPI DEVTYPE: MajorType Position /
gokmenascioglu	0:a8fa94490a0a	967	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
gokmenascioglu	0:a8fa94490a0a	968
gokmenascioglu	0:a8fa94490a0a	969	/@}/ /* end of group CMSIS_TPI */
gokmenascioglu	0:a8fa94490a0a	970
gokmenascioglu	0:a8fa94490a0a	971
gokmenascioglu	0:a8fa94490a0a	972	#if (__MPU_PRESENT == 1)
gokmenascioglu	0:a8fa94490a0a	973	/** \ingroup CMSIS_core_register
gokmenascioglu	0:a8fa94490a0a	974	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
gokmenascioglu	0:a8fa94490a0a	975	\brief Type definitions for the Memory Protection Unit (MPU)
gokmenascioglu	0:a8fa94490a0a	976	@{
gokmenascioglu	0:a8fa94490a0a	977	*/
gokmenascioglu	0:a8fa94490a0a	978
gokmenascioglu	0:a8fa94490a0a	979	/** \brief Structure type to access the Memory Protection Unit (MPU).
gokmenascioglu	0:a8fa94490a0a	980	*/
gokmenascioglu	0:a8fa94490a0a	981	typedef struct
gokmenascioglu	0:a8fa94490a0a	982	{
gokmenascioglu	0:a8fa94490a0a	983	__I uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
gokmenascioglu	0:a8fa94490a0a	984	__IO uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
gokmenascioglu	0:a8fa94490a0a	985	__IO uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
gokmenascioglu	0:a8fa94490a0a	986	__IO uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
gokmenascioglu	0:a8fa94490a0a	987	__IO uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
gokmenascioglu	0:a8fa94490a0a	988	__IO uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
gokmenascioglu	0:a8fa94490a0a	989	__IO uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
gokmenascioglu	0:a8fa94490a0a	990	__IO uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
gokmenascioglu	0:a8fa94490a0a	991	__IO uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
gokmenascioglu	0:a8fa94490a0a	992	__IO uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
gokmenascioglu	0:a8fa94490a0a	993	__IO uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
gokmenascioglu	0:a8fa94490a0a	994	} MPU_Type;
gokmenascioglu	0:a8fa94490a0a	995
gokmenascioglu	0:a8fa94490a0a	996	/* MPU Type Register */
gokmenascioglu	0:a8fa94490a0a	997	#define MPU_TYPE_IREGION_Pos 16 /!< MPU TYPE: IREGION Position /
gokmenascioglu	0:a8fa94490a0a	998	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
gokmenascioglu	0:a8fa94490a0a	999
gokmenascioglu	0:a8fa94490a0a	1000	#define MPU_TYPE_DREGION_Pos 8 /!< MPU TYPE: DREGION Position /
gokmenascioglu	0:a8fa94490a0a	1001	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
gokmenascioglu	0:a8fa94490a0a	1002
gokmenascioglu	0:a8fa94490a0a	1003	#define MPU_TYPE_SEPARATE_Pos 0 /!< MPU TYPE: SEPARATE Position /
gokmenascioglu	0:a8fa94490a0a	1004	#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /!< MPU TYPE: SEPARATE Mask /
gokmenascioglu	0:a8fa94490a0a	1005
gokmenascioglu	0:a8fa94490a0a	1006	/* MPU Control Register */
gokmenascioglu	0:a8fa94490a0a	1007	#define MPU_CTRL_PRIVDEFENA_Pos 2 /!< MPU CTRL: PRIVDEFENA Position /
gokmenascioglu	0:a8fa94490a0a	1008	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
gokmenascioglu	0:a8fa94490a0a	1009
gokmenascioglu	0:a8fa94490a0a	1010	#define MPU_CTRL_HFNMIENA_Pos 1 /!< MPU CTRL: HFNMIENA Position /
gokmenascioglu	0:a8fa94490a0a	1011	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
gokmenascioglu	0:a8fa94490a0a	1012
gokmenascioglu	0:a8fa94490a0a	1013	#define MPU_CTRL_ENABLE_Pos 0 /!< MPU CTRL: ENABLE Position /
gokmenascioglu	0:a8fa94490a0a	1014	#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /!< MPU CTRL: ENABLE Mask /
gokmenascioglu	0:a8fa94490a0a	1015
gokmenascioglu	0:a8fa94490a0a	1016	/* MPU Region Number Register */
gokmenascioglu	0:a8fa94490a0a	1017	#define MPU_RNR_REGION_Pos 0 /!< MPU RNR: REGION Position /
gokmenascioglu	0:a8fa94490a0a	1018	#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /!< MPU RNR: REGION Mask /
gokmenascioglu	0:a8fa94490a0a	1019
gokmenascioglu	0:a8fa94490a0a	1020	/* MPU Region Base Address Register */
gokmenascioglu	0:a8fa94490a0a	1021	#define MPU_RBAR_ADDR_Pos 5 /!< MPU RBAR: ADDR Position /
gokmenascioglu	0:a8fa94490a0a	1022	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
gokmenascioglu	0:a8fa94490a0a	1023
gokmenascioglu	0:a8fa94490a0a	1024	#define MPU_RBAR_VALID_Pos 4 /!< MPU RBAR: VALID Position /
gokmenascioglu	0:a8fa94490a0a	1025	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
gokmenascioglu	0:a8fa94490a0a	1026
gokmenascioglu	0:a8fa94490a0a	1027	#define MPU_RBAR_REGION_Pos 0 /!< MPU RBAR: REGION Position /
gokmenascioglu	0:a8fa94490a0a	1028	#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /!< MPU RBAR: REGION Mask /
gokmenascioglu	0:a8fa94490a0a	1029
gokmenascioglu	0:a8fa94490a0a	1030	/* MPU Region Attribute and Size Register */
gokmenascioglu	0:a8fa94490a0a	1031	#define MPU_RASR_ATTRS_Pos 16 /!< MPU RASR: MPU Region Attribute field Position /
gokmenascioglu	0:a8fa94490a0a	1032	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
gokmenascioglu	0:a8fa94490a0a	1033
gokmenascioglu	0:a8fa94490a0a	1034	#define MPU_RASR_SRD_Pos 8 /!< MPU RASR: Sub-Region Disable Position /
gokmenascioglu	0:a8fa94490a0a	1035	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
gokmenascioglu	0:a8fa94490a0a	1036
gokmenascioglu	0:a8fa94490a0a	1037	#define MPU_RASR_SIZE_Pos 1 /!< MPU RASR: Region Size Field Position /
gokmenascioglu	0:a8fa94490a0a	1038	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
gokmenascioglu	0:a8fa94490a0a	1039
gokmenascioglu	0:a8fa94490a0a	1040	#define MPU_RASR_ENABLE_Pos 0 /!< MPU RASR: Region enable bit Position /
gokmenascioglu	0:a8fa94490a0a	1041	#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /!< MPU RASR: Region enable bit Disable Mask /
gokmenascioglu	0:a8fa94490a0a	1042
gokmenascioglu	0:a8fa94490a0a	1043	/@} end of group CMSIS_MPU /
gokmenascioglu	0:a8fa94490a0a	1044	#endif
gokmenascioglu	0:a8fa94490a0a	1045
gokmenascioglu	0:a8fa94490a0a	1046
gokmenascioglu	0:a8fa94490a0a	1047	/** \ingroup CMSIS_core_register
gokmenascioglu	0:a8fa94490a0a	1048	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
gokmenascioglu	0:a8fa94490a0a	1049	\brief Type definitions for the Core Debug Registers
gokmenascioglu	0:a8fa94490a0a	1050	@{
gokmenascioglu	0:a8fa94490a0a	1051	*/
gokmenascioglu	0:a8fa94490a0a	1052
gokmenascioglu	0:a8fa94490a0a	1053	/** \brief Structure type to access the Core Debug Register (CoreDebug).
gokmenascioglu	0:a8fa94490a0a	1054	*/
gokmenascioglu	0:a8fa94490a0a	1055	typedef struct
gokmenascioglu	0:a8fa94490a0a	1056	{
gokmenascioglu	0:a8fa94490a0a	1057	__IO uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
gokmenascioglu	0:a8fa94490a0a	1058	__O uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
gokmenascioglu	0:a8fa94490a0a	1059	__IO uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
gokmenascioglu	0:a8fa94490a0a	1060	__IO uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
gokmenascioglu	0:a8fa94490a0a	1061	} CoreDebug_Type;
gokmenascioglu	0:a8fa94490a0a	1062
gokmenascioglu	0:a8fa94490a0a	1063	/* Debug Halting Control and Status Register */
gokmenascioglu	0:a8fa94490a0a	1064	#define CoreDebug_DHCSR_DBGKEY_Pos 16 /!< CoreDebug DHCSR: DBGKEY Position /
gokmenascioglu	0:a8fa94490a0a	1065	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
gokmenascioglu	0:a8fa94490a0a	1066
gokmenascioglu	0:a8fa94490a0a	1067	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /!< CoreDebug DHCSR: S_RESET_ST Position /
gokmenascioglu	0:a8fa94490a0a	1068	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
gokmenascioglu	0:a8fa94490a0a	1069
gokmenascioglu	0:a8fa94490a0a	1070	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /!< CoreDebug DHCSR: S_RETIRE_ST Position /
gokmenascioglu	0:a8fa94490a0a	1071	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
gokmenascioglu	0:a8fa94490a0a	1072
gokmenascioglu	0:a8fa94490a0a	1073	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /!< CoreDebug DHCSR: S_LOCKUP Position /
gokmenascioglu	0:a8fa94490a0a	1074	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
gokmenascioglu	0:a8fa94490a0a	1075
gokmenascioglu	0:a8fa94490a0a	1076	#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /!< CoreDebug DHCSR: S_SLEEP Position /
gokmenascioglu	0:a8fa94490a0a	1077	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
gokmenascioglu	0:a8fa94490a0a	1078
gokmenascioglu	0:a8fa94490a0a	1079	#define CoreDebug_DHCSR_S_HALT_Pos 17 /!< CoreDebug DHCSR: S_HALT Position /
gokmenascioglu	0:a8fa94490a0a	1080	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
gokmenascioglu	0:a8fa94490a0a	1081
gokmenascioglu	0:a8fa94490a0a	1082	#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /!< CoreDebug DHCSR: S_REGRDY Position /
gokmenascioglu	0:a8fa94490a0a	1083	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
gokmenascioglu	0:a8fa94490a0a	1084
gokmenascioglu	0:a8fa94490a0a	1085	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /!< CoreDebug DHCSR: C_SNAPSTALL Position /
gokmenascioglu	0:a8fa94490a0a	1086	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
gokmenascioglu	0:a8fa94490a0a	1087
gokmenascioglu	0:a8fa94490a0a	1088	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /!< CoreDebug DHCSR: C_MASKINTS Position /
gokmenascioglu	0:a8fa94490a0a	1089	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
gokmenascioglu	0:a8fa94490a0a	1090
gokmenascioglu	0:a8fa94490a0a	1091	#define CoreDebug_DHCSR_C_STEP_Pos 2 /!< CoreDebug DHCSR: C_STEP Position /
gokmenascioglu	0:a8fa94490a0a	1092	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
gokmenascioglu	0:a8fa94490a0a	1093
gokmenascioglu	0:a8fa94490a0a	1094	#define CoreDebug_DHCSR_C_HALT_Pos 1 /!< CoreDebug DHCSR: C_HALT Position /
gokmenascioglu	0:a8fa94490a0a	1095	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
gokmenascioglu	0:a8fa94490a0a	1096
gokmenascioglu	0:a8fa94490a0a	1097	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /!< CoreDebug DHCSR: C_DEBUGEN Position /
gokmenascioglu	0:a8fa94490a0a	1098	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
gokmenascioglu	0:a8fa94490a0a	1099
gokmenascioglu	0:a8fa94490a0a	1100	/* Debug Core Register Selector Register */
gokmenascioglu	0:a8fa94490a0a	1101	#define CoreDebug_DCRSR_REGWnR_Pos 16 /!< CoreDebug DCRSR: REGWnR Position /
gokmenascioglu	0:a8fa94490a0a	1102	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
gokmenascioglu	0:a8fa94490a0a	1103
gokmenascioglu	0:a8fa94490a0a	1104	#define CoreDebug_DCRSR_REGSEL_Pos 0 /!< CoreDebug DCRSR: REGSEL Position /
gokmenascioglu	0:a8fa94490a0a	1105	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /!< CoreDebug DCRSR: REGSEL Mask /
gokmenascioglu	0:a8fa94490a0a	1106
gokmenascioglu	0:a8fa94490a0a	1107	/* Debug Exception and Monitor Control Register */
gokmenascioglu	0:a8fa94490a0a	1108	#define CoreDebug_DEMCR_TRCENA_Pos 24 /!< CoreDebug DEMCR: TRCENA Position /
gokmenascioglu	0:a8fa94490a0a	1109	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
gokmenascioglu	0:a8fa94490a0a	1110
gokmenascioglu	0:a8fa94490a0a	1111	#define CoreDebug_DEMCR_MON_REQ_Pos 19 /!< CoreDebug DEMCR: MON_REQ Position /
gokmenascioglu	0:a8fa94490a0a	1112	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
gokmenascioglu	0:a8fa94490a0a	1113
gokmenascioglu	0:a8fa94490a0a	1114	#define CoreDebug_DEMCR_MON_STEP_Pos 18 /!< CoreDebug DEMCR: MON_STEP Position /
gokmenascioglu	0:a8fa94490a0a	1115	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
gokmenascioglu	0:a8fa94490a0a	1116
gokmenascioglu	0:a8fa94490a0a	1117	#define CoreDebug_DEMCR_MON_PEND_Pos 17 /!< CoreDebug DEMCR: MON_PEND Position /
gokmenascioglu	0:a8fa94490a0a	1118	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
gokmenascioglu	0:a8fa94490a0a	1119
gokmenascioglu	0:a8fa94490a0a	1120	#define CoreDebug_DEMCR_MON_EN_Pos 16 /!< CoreDebug DEMCR: MON_EN Position /
gokmenascioglu	0:a8fa94490a0a	1121	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
gokmenascioglu	0:a8fa94490a0a	1122
gokmenascioglu	0:a8fa94490a0a	1123	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /!< CoreDebug DEMCR: VC_HARDERR Position /
gokmenascioglu	0:a8fa94490a0a	1124	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
gokmenascioglu	0:a8fa94490a0a	1125
gokmenascioglu	0:a8fa94490a0a	1126	#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /!< CoreDebug DEMCR: VC_INTERR Position /
gokmenascioglu	0:a8fa94490a0a	1127	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
gokmenascioglu	0:a8fa94490a0a	1128
gokmenascioglu	0:a8fa94490a0a	1129	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /!< CoreDebug DEMCR: VC_BUSERR Position /
gokmenascioglu	0:a8fa94490a0a	1130	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
gokmenascioglu	0:a8fa94490a0a	1131
gokmenascioglu	0:a8fa94490a0a	1132	#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /!< CoreDebug DEMCR: VC_STATERR Position /
gokmenascioglu	0:a8fa94490a0a	1133	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
gokmenascioglu	0:a8fa94490a0a	1134
gokmenascioglu	0:a8fa94490a0a	1135	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /!< CoreDebug DEMCR: VC_CHKERR Position /
gokmenascioglu	0:a8fa94490a0a	1136	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
gokmenascioglu	0:a8fa94490a0a	1137
gokmenascioglu	0:a8fa94490a0a	1138	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /!< CoreDebug DEMCR: VC_NOCPERR Position /
gokmenascioglu	0:a8fa94490a0a	1139	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
gokmenascioglu	0:a8fa94490a0a	1140
gokmenascioglu	0:a8fa94490a0a	1141	#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /!< CoreDebug DEMCR: VC_MMERR Position /
gokmenascioglu	0:a8fa94490a0a	1142	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
gokmenascioglu	0:a8fa94490a0a	1143
gokmenascioglu	0:a8fa94490a0a	1144	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /!< CoreDebug DEMCR: VC_CORERESET Position /
gokmenascioglu	0:a8fa94490a0a	1145	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /!< CoreDebug DEMCR: VC_CORERESET Mask /
gokmenascioglu	0:a8fa94490a0a	1146
gokmenascioglu	0:a8fa94490a0a	1147	/@} end of group CMSIS_CoreDebug /
gokmenascioglu	0:a8fa94490a0a	1148
gokmenascioglu	0:a8fa94490a0a	1149
gokmenascioglu	0:a8fa94490a0a	1150	/** \ingroup CMSIS_core_register
gokmenascioglu	0:a8fa94490a0a	1151	\defgroup CMSIS_core_base Core Definitions
gokmenascioglu	0:a8fa94490a0a	1152	\brief Definitions for base addresses, unions, and structures.
gokmenascioglu	0:a8fa94490a0a	1153	@{
gokmenascioglu	0:a8fa94490a0a	1154	*/
gokmenascioglu	0:a8fa94490a0a	1155
gokmenascioglu	0:a8fa94490a0a	1156	/* Memory mapping of Cortex-M3 Hardware */
gokmenascioglu	0:a8fa94490a0a	1157	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
gokmenascioglu	0:a8fa94490a0a	1158	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
gokmenascioglu	0:a8fa94490a0a	1159	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
gokmenascioglu	0:a8fa94490a0a	1160	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
gokmenascioglu	0:a8fa94490a0a	1161	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
gokmenascioglu	0:a8fa94490a0a	1162	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
gokmenascioglu	0:a8fa94490a0a	1163	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
gokmenascioglu	0:a8fa94490a0a	1164	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
gokmenascioglu	0:a8fa94490a0a	1165
gokmenascioglu	0:a8fa94490a0a	1166	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
gokmenascioglu	0:a8fa94490a0a	1167	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
gokmenascioglu	0:a8fa94490a0a	1168	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
gokmenascioglu	0:a8fa94490a0a	1169	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
gokmenascioglu	0:a8fa94490a0a	1170	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
gokmenascioglu	0:a8fa94490a0a	1171	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
gokmenascioglu	0:a8fa94490a0a	1172	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
gokmenascioglu	0:a8fa94490a0a	1173	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
gokmenascioglu	0:a8fa94490a0a	1174
gokmenascioglu	0:a8fa94490a0a	1175	#if (__MPU_PRESENT == 1)
gokmenascioglu	0:a8fa94490a0a	1176	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
gokmenascioglu	0:a8fa94490a0a	1177	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
gokmenascioglu	0:a8fa94490a0a	1178	#endif
gokmenascioglu	0:a8fa94490a0a	1179
gokmenascioglu	0:a8fa94490a0a	1180	/@} /
gokmenascioglu	0:a8fa94490a0a	1181
gokmenascioglu	0:a8fa94490a0a	1182
gokmenascioglu	0:a8fa94490a0a	1183
gokmenascioglu	0:a8fa94490a0a	1184	/*******************************************************************************
gokmenascioglu	0:a8fa94490a0a	1185	* Hardware Abstraction Layer
gokmenascioglu	0:a8fa94490a0a	1186	Core Function Interface contains:
gokmenascioglu	0:a8fa94490a0a	1187	- Core NVIC Functions
gokmenascioglu	0:a8fa94490a0a	1188	- Core SysTick Functions
gokmenascioglu	0:a8fa94490a0a	1189	- Core Debug Functions
gokmenascioglu	0:a8fa94490a0a	1190	- Core Register Access Functions
gokmenascioglu	0:a8fa94490a0a	1191	******************************************************************************/
gokmenascioglu	0:a8fa94490a0a	1192	/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
gokmenascioglu	0:a8fa94490a0a	1193	*/
gokmenascioglu	0:a8fa94490a0a	1194
gokmenascioglu	0:a8fa94490a0a	1195
gokmenascioglu	0:a8fa94490a0a	1196
gokmenascioglu	0:a8fa94490a0a	1197	/* ########################## NVIC functions #################################### */
gokmenascioglu	0:a8fa94490a0a	1198	/** \ingroup CMSIS_Core_FunctionInterface
gokmenascioglu	0:a8fa94490a0a	1199	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
gokmenascioglu	0:a8fa94490a0a	1200	\brief Functions that manage interrupts and exceptions via the NVIC.
gokmenascioglu	0:a8fa94490a0a	1201	@{
gokmenascioglu	0:a8fa94490a0a	1202	*/
gokmenascioglu	0:a8fa94490a0a	1203
gokmenascioglu	0:a8fa94490a0a	1204	/** \brief Set Priority Grouping
gokmenascioglu	0:a8fa94490a0a	1205
gokmenascioglu	0:a8fa94490a0a	1206	The function sets the priority grouping field using the required unlock sequence.
gokmenascioglu	0:a8fa94490a0a	1207	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
gokmenascioglu	0:a8fa94490a0a	1208	Only values from 0..7 are used.
gokmenascioglu	0:a8fa94490a0a	1209	In case of a conflict between priority grouping and available
gokmenascioglu	0:a8fa94490a0a	1210	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
gokmenascioglu	0:a8fa94490a0a	1211
gokmenascioglu	0:a8fa94490a0a	1212	\param [in] PriorityGroup Priority grouping field.
gokmenascioglu	0:a8fa94490a0a	1213	*/
gokmenascioglu	0:a8fa94490a0a	1214	__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
gokmenascioglu	0:a8fa94490a0a	1215	{
gokmenascioglu	0:a8fa94490a0a	1216	uint32_t reg_value;
gokmenascioglu	0:a8fa94490a0a	1217	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
gokmenascioglu	0:a8fa94490a0a	1218
gokmenascioglu	0:a8fa94490a0a	1219	reg_value = SCB->AIRCR; /* read old register configuration */
gokmenascioglu	0:a8fa94490a0a	1220	reg_value &= ~(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
gokmenascioglu	0:a8fa94490a0a	1221	reg_value = (reg_value \|
gokmenascioglu	0:a8fa94490a0a	1222	((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) \|
gokmenascioglu	0:a8fa94490a0a	1223	(PriorityGroupTmp << 8)); /* Insert write key and priorty group */
gokmenascioglu	0:a8fa94490a0a	1224	SCB->AIRCR = reg_value;
gokmenascioglu	0:a8fa94490a0a	1225	}
gokmenascioglu	0:a8fa94490a0a	1226
gokmenascioglu	0:a8fa94490a0a	1227
gokmenascioglu	0:a8fa94490a0a	1228	/** \brief Get Priority Grouping
gokmenascioglu	0:a8fa94490a0a	1229
gokmenascioglu	0:a8fa94490a0a	1230	The function reads the priority grouping field from the NVIC Interrupt Controller.
gokmenascioglu	0:a8fa94490a0a	1231
gokmenascioglu	0:a8fa94490a0a	1232	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
gokmenascioglu	0:a8fa94490a0a	1233	*/
gokmenascioglu	0:a8fa94490a0a	1234	__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
gokmenascioglu	0:a8fa94490a0a	1235	{
gokmenascioglu	0:a8fa94490a0a	1236	return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
gokmenascioglu	0:a8fa94490a0a	1237	}
gokmenascioglu	0:a8fa94490a0a	1238
gokmenascioglu	0:a8fa94490a0a	1239
gokmenascioglu	0:a8fa94490a0a	1240	/** \brief Enable External Interrupt
gokmenascioglu	0:a8fa94490a0a	1241
gokmenascioglu	0:a8fa94490a0a	1242	The function enables a device-specific interrupt in the NVIC interrupt controller.
gokmenascioglu	0:a8fa94490a0a	1243
gokmenascioglu	0:a8fa94490a0a	1244	\param [in] IRQn External interrupt number. Value cannot be negative.
gokmenascioglu	0:a8fa94490a0a	1245	*/
gokmenascioglu	0:a8fa94490a0a	1246	__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
gokmenascioglu	0:a8fa94490a0a	1247	{
gokmenascioglu	0:a8fa94490a0a	1248	NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
gokmenascioglu	0:a8fa94490a0a	1249	}
gokmenascioglu	0:a8fa94490a0a	1250
gokmenascioglu	0:a8fa94490a0a	1251
gokmenascioglu	0:a8fa94490a0a	1252	/** \brief Disable External Interrupt
gokmenascioglu	0:a8fa94490a0a	1253
gokmenascioglu	0:a8fa94490a0a	1254	The function disables a device-specific interrupt in the NVIC interrupt controller.
gokmenascioglu	0:a8fa94490a0a	1255
gokmenascioglu	0:a8fa94490a0a	1256	\param [in] IRQn External interrupt number. Value cannot be negative.
gokmenascioglu	0:a8fa94490a0a	1257	*/
gokmenascioglu	0:a8fa94490a0a	1258	__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
gokmenascioglu	0:a8fa94490a0a	1259	{
gokmenascioglu	0:a8fa94490a0a	1260	NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
gokmenascioglu	0:a8fa94490a0a	1261	}
gokmenascioglu	0:a8fa94490a0a	1262
gokmenascioglu	0:a8fa94490a0a	1263
gokmenascioglu	0:a8fa94490a0a	1264	/** \brief Get Pending Interrupt
gokmenascioglu	0:a8fa94490a0a	1265
gokmenascioglu	0:a8fa94490a0a	1266	The function reads the pending register in the NVIC and returns the pending bit
gokmenascioglu	0:a8fa94490a0a	1267	for the specified interrupt.
gokmenascioglu	0:a8fa94490a0a	1268
gokmenascioglu	0:a8fa94490a0a	1269	\param [in] IRQn Interrupt number.
gokmenascioglu	0:a8fa94490a0a	1270
gokmenascioglu	0:a8fa94490a0a	1271	\return 0 Interrupt status is not pending.
gokmenascioglu	0:a8fa94490a0a	1272	\return 1 Interrupt status is pending.
gokmenascioglu	0:a8fa94490a0a	1273	*/
gokmenascioglu	0:a8fa94490a0a	1274	__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
gokmenascioglu	0:a8fa94490a0a	1275	{
gokmenascioglu	0:a8fa94490a0a	1276	return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
gokmenascioglu	0:a8fa94490a0a	1277	}
gokmenascioglu	0:a8fa94490a0a	1278
gokmenascioglu	0:a8fa94490a0a	1279
gokmenascioglu	0:a8fa94490a0a	1280	/** \brief Set Pending Interrupt
gokmenascioglu	0:a8fa94490a0a	1281
gokmenascioglu	0:a8fa94490a0a	1282	The function sets the pending bit of an external interrupt.
gokmenascioglu	0:a8fa94490a0a	1283
gokmenascioglu	0:a8fa94490a0a	1284	\param [in] IRQn Interrupt number. Value cannot be negative.
gokmenascioglu	0:a8fa94490a0a	1285	*/
gokmenascioglu	0:a8fa94490a0a	1286	__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
gokmenascioglu	0:a8fa94490a0a	1287	{
gokmenascioglu	0:a8fa94490a0a	1288	NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
gokmenascioglu	0:a8fa94490a0a	1289	}
gokmenascioglu	0:a8fa94490a0a	1290
gokmenascioglu	0:a8fa94490a0a	1291
gokmenascioglu	0:a8fa94490a0a	1292	/** \brief Clear Pending Interrupt
gokmenascioglu	0:a8fa94490a0a	1293
gokmenascioglu	0:a8fa94490a0a	1294	The function clears the pending bit of an external interrupt.
gokmenascioglu	0:a8fa94490a0a	1295
gokmenascioglu	0:a8fa94490a0a	1296	\param [in] IRQn External interrupt number. Value cannot be negative.
gokmenascioglu	0:a8fa94490a0a	1297	*/
gokmenascioglu	0:a8fa94490a0a	1298	__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
gokmenascioglu	0:a8fa94490a0a	1299	{
gokmenascioglu	0:a8fa94490a0a	1300	NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
gokmenascioglu	0:a8fa94490a0a	1301	}
gokmenascioglu	0:a8fa94490a0a	1302
gokmenascioglu	0:a8fa94490a0a	1303
gokmenascioglu	0:a8fa94490a0a	1304	/** \brief Get Active Interrupt
gokmenascioglu	0:a8fa94490a0a	1305
gokmenascioglu	0:a8fa94490a0a	1306	The function reads the active register in NVIC and returns the active bit.
gokmenascioglu	0:a8fa94490a0a	1307
gokmenascioglu	0:a8fa94490a0a	1308	\param [in] IRQn Interrupt number.
gokmenascioglu	0:a8fa94490a0a	1309
gokmenascioglu	0:a8fa94490a0a	1310	\return 0 Interrupt status is not active.
gokmenascioglu	0:a8fa94490a0a	1311	\return 1 Interrupt status is active.
gokmenascioglu	0:a8fa94490a0a	1312	*/
gokmenascioglu	0:a8fa94490a0a	1313	__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
gokmenascioglu	0:a8fa94490a0a	1314	{
gokmenascioglu	0:a8fa94490a0a	1315	return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
gokmenascioglu	0:a8fa94490a0a	1316	}
gokmenascioglu	0:a8fa94490a0a	1317
gokmenascioglu	0:a8fa94490a0a	1318
gokmenascioglu	0:a8fa94490a0a	1319	/** \brief Set Interrupt Priority
gokmenascioglu	0:a8fa94490a0a	1320
gokmenascioglu	0:a8fa94490a0a	1321	The function sets the priority of an interrupt.
gokmenascioglu	0:a8fa94490a0a	1322
gokmenascioglu	0:a8fa94490a0a	1323	\note The priority cannot be set for every core interrupt.
gokmenascioglu	0:a8fa94490a0a	1324
gokmenascioglu	0:a8fa94490a0a	1325	\param [in] IRQn Interrupt number.
gokmenascioglu	0:a8fa94490a0a	1326	\param [in] priority Priority to set.
gokmenascioglu	0:a8fa94490a0a	1327	*/
gokmenascioglu	0:a8fa94490a0a	1328	__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
gokmenascioglu	0:a8fa94490a0a	1329	{
gokmenascioglu	0:a8fa94490a0a	1330	if(IRQn < 0) {
gokmenascioglu	0:a8fa94490a0a	1331	SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
gokmenascioglu	0:a8fa94490a0a	1332	else {
gokmenascioglu	0:a8fa94490a0a	1333	NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
gokmenascioglu	0:a8fa94490a0a	1334	}
gokmenascioglu	0:a8fa94490a0a	1335
gokmenascioglu	0:a8fa94490a0a	1336
gokmenascioglu	0:a8fa94490a0a	1337	/** \brief Get Interrupt Priority
gokmenascioglu	0:a8fa94490a0a	1338
gokmenascioglu	0:a8fa94490a0a	1339	The function reads the priority of an interrupt. The interrupt
gokmenascioglu	0:a8fa94490a0a	1340	number can be positive to specify an external (device specific)
gokmenascioglu	0:a8fa94490a0a	1341	interrupt, or negative to specify an internal (core) interrupt.
gokmenascioglu	0:a8fa94490a0a	1342
gokmenascioglu	0:a8fa94490a0a	1343
gokmenascioglu	0:a8fa94490a0a	1344	\param [in] IRQn Interrupt number.
gokmenascioglu	0:a8fa94490a0a	1345	\return Interrupt Priority. Value is aligned automatically to the implemented
gokmenascioglu	0:a8fa94490a0a	1346	priority bits of the microcontroller.
gokmenascioglu	0:a8fa94490a0a	1347	*/
gokmenascioglu	0:a8fa94490a0a	1348	__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
gokmenascioglu	0:a8fa94490a0a	1349	{
gokmenascioglu	0:a8fa94490a0a	1350
gokmenascioglu	0:a8fa94490a0a	1351	if(IRQn < 0) {
gokmenascioglu	0:a8fa94490a0a	1352	return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
gokmenascioglu	0:a8fa94490a0a	1353	else {
gokmenascioglu	0:a8fa94490a0a	1354	return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
gokmenascioglu	0:a8fa94490a0a	1355	}
gokmenascioglu	0:a8fa94490a0a	1356
gokmenascioglu	0:a8fa94490a0a	1357
gokmenascioglu	0:a8fa94490a0a	1358	/** \brief Encode Priority
gokmenascioglu	0:a8fa94490a0a	1359
gokmenascioglu	0:a8fa94490a0a	1360	The function encodes the priority for an interrupt with the given priority group,
gokmenascioglu	0:a8fa94490a0a	1361	preemptive priority value, and subpriority value.
gokmenascioglu	0:a8fa94490a0a	1362	In case of a conflict between priority grouping and available
gokmenascioglu	0:a8fa94490a0a	1363	priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
gokmenascioglu	0:a8fa94490a0a	1364
gokmenascioglu	0:a8fa94490a0a	1365	\param [in] PriorityGroup Used priority group.
gokmenascioglu	0:a8fa94490a0a	1366	\param [in] PreemptPriority Preemptive priority value (starting from 0).
gokmenascioglu	0:a8fa94490a0a	1367	\param [in] SubPriority Subpriority value (starting from 0).
gokmenascioglu	0:a8fa94490a0a	1368	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
gokmenascioglu	0:a8fa94490a0a	1369	*/
gokmenascioglu	0:a8fa94490a0a	1370	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
gokmenascioglu	0:a8fa94490a0a	1371	{
gokmenascioglu	0:a8fa94490a0a	1372	uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
gokmenascioglu	0:a8fa94490a0a	1373	uint32_t PreemptPriorityBits;
gokmenascioglu	0:a8fa94490a0a	1374	uint32_t SubPriorityBits;
gokmenascioglu	0:a8fa94490a0a	1375
gokmenascioglu	0:a8fa94490a0a	1376	PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
gokmenascioglu	0:a8fa94490a0a	1377	SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
gokmenascioglu	0:a8fa94490a0a	1378
gokmenascioglu	0:a8fa94490a0a	1379	return (
gokmenascioglu	0:a8fa94490a0a	1380	((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) \|
gokmenascioglu	0:a8fa94490a0a	1381	((SubPriority & ((1 << (SubPriorityBits )) - 1)))
gokmenascioglu	0:a8fa94490a0a	1382	);
gokmenascioglu	0:a8fa94490a0a	1383	}
gokmenascioglu	0:a8fa94490a0a	1384
gokmenascioglu	0:a8fa94490a0a	1385
gokmenascioglu	0:a8fa94490a0a	1386	/** \brief Decode Priority
gokmenascioglu	0:a8fa94490a0a	1387
gokmenascioglu	0:a8fa94490a0a	1388	The function decodes an interrupt priority value with a given priority group to
gokmenascioglu	0:a8fa94490a0a	1389	preemptive priority value and subpriority value.
gokmenascioglu	0:a8fa94490a0a	1390	In case of a conflict between priority grouping and available
gokmenascioglu	0:a8fa94490a0a	1391	priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
gokmenascioglu	0:a8fa94490a0a	1392
gokmenascioglu	0:a8fa94490a0a	1393	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
gokmenascioglu	0:a8fa94490a0a	1394	\param [in] PriorityGroup Used priority group.
gokmenascioglu	0:a8fa94490a0a	1395	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
gokmenascioglu	0:a8fa94490a0a	1396	\param [out] pSubPriority Subpriority value (starting from 0).
gokmenascioglu	0:a8fa94490a0a	1397	*/
gokmenascioglu	0:a8fa94490a0a	1398	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
gokmenascioglu	0:a8fa94490a0a	1399	{
gokmenascioglu	0:a8fa94490a0a	1400	uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
gokmenascioglu	0:a8fa94490a0a	1401	uint32_t PreemptPriorityBits;
gokmenascioglu	0:a8fa94490a0a	1402	uint32_t SubPriorityBits;
gokmenascioglu	0:a8fa94490a0a	1403
gokmenascioglu	0:a8fa94490a0a	1404	PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
gokmenascioglu	0:a8fa94490a0a	1405	SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
gokmenascioglu	0:a8fa94490a0a	1406
gokmenascioglu	0:a8fa94490a0a	1407	*pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
gokmenascioglu	0:a8fa94490a0a	1408	*pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
gokmenascioglu	0:a8fa94490a0a	1409	}
gokmenascioglu	0:a8fa94490a0a	1410
gokmenascioglu	0:a8fa94490a0a	1411
gokmenascioglu	0:a8fa94490a0a	1412	/** \brief System Reset
gokmenascioglu	0:a8fa94490a0a	1413
gokmenascioglu	0:a8fa94490a0a	1414	The function initiates a system reset request to reset the MCU.
gokmenascioglu	0:a8fa94490a0a	1415	*/
gokmenascioglu	0:a8fa94490a0a	1416	__STATIC_INLINE void NVIC_SystemReset(void)
gokmenascioglu	0:a8fa94490a0a	1417	{
gokmenascioglu	0:a8fa94490a0a	1418	__DSB(); /* Ensure all outstanding memory accesses included
gokmenascioglu	0:a8fa94490a0a	1419	buffered write are completed before reset */
gokmenascioglu	0:a8fa94490a0a	1420	SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) \|
gokmenascioglu	0:a8fa94490a0a	1421	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
gokmenascioglu	0:a8fa94490a0a	1422	SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
gokmenascioglu	0:a8fa94490a0a	1423	__DSB(); /* Ensure completion of memory access */
gokmenascioglu	0:a8fa94490a0a	1424	while(1); /* wait until reset */
gokmenascioglu	0:a8fa94490a0a	1425	}
gokmenascioglu	0:a8fa94490a0a	1426
gokmenascioglu	0:a8fa94490a0a	1427	/@} end of CMSIS_Core_NVICFunctions /
gokmenascioglu	0:a8fa94490a0a	1428
gokmenascioglu	0:a8fa94490a0a	1429
gokmenascioglu	0:a8fa94490a0a	1430
gokmenascioglu	0:a8fa94490a0a	1431	/* ################################## SysTick function ############################################ */
gokmenascioglu	0:a8fa94490a0a	1432	/** \ingroup CMSIS_Core_FunctionInterface
gokmenascioglu	0:a8fa94490a0a	1433	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
gokmenascioglu	0:a8fa94490a0a	1434	\brief Functions that configure the System.
gokmenascioglu	0:a8fa94490a0a	1435	@{
gokmenascioglu	0:a8fa94490a0a	1436	*/
gokmenascioglu	0:a8fa94490a0a	1437
gokmenascioglu	0:a8fa94490a0a	1438	#if (__Vendor_SysTickConfig == 0)
gokmenascioglu	0:a8fa94490a0a	1439
gokmenascioglu	0:a8fa94490a0a	1440	/** \brief System Tick Configuration
gokmenascioglu	0:a8fa94490a0a	1441
gokmenascioglu	0:a8fa94490a0a	1442	The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
gokmenascioglu	0:a8fa94490a0a	1443	Counter is in free running mode to generate periodic interrupts.
gokmenascioglu	0:a8fa94490a0a	1444
gokmenascioglu	0:a8fa94490a0a	1445	\param [in] ticks Number of ticks between two interrupts.
gokmenascioglu	0:a8fa94490a0a	1446
gokmenascioglu	0:a8fa94490a0a	1447	\return 0 Function succeeded.
gokmenascioglu	0:a8fa94490a0a	1448	\return 1 Function failed.
gokmenascioglu	0:a8fa94490a0a	1449
gokmenascioglu	0:a8fa94490a0a	1450	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
gokmenascioglu	0:a8fa94490a0a	1451	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
gokmenascioglu	0:a8fa94490a0a	1452	must contain a vendor-specific implementation of this function.
gokmenascioglu	0:a8fa94490a0a	1453
gokmenascioglu	0:a8fa94490a0a	1454	*/
gokmenascioglu	0:a8fa94490a0a	1455	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
gokmenascioglu	0:a8fa94490a0a	1456	{
gokmenascioglu	0:a8fa94490a0a	1457	if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
gokmenascioglu	0:a8fa94490a0a	1458
gokmenascioglu	0:a8fa94490a0a	1459	SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
gokmenascioglu	0:a8fa94490a0a	1460	NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
gokmenascioglu	0:a8fa94490a0a	1461	SysTick->VAL = 0; /* Load the SysTick Counter Value */
gokmenascioglu	0:a8fa94490a0a	1462	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
gokmenascioglu	0:a8fa94490a0a	1463	SysTick_CTRL_TICKINT_Msk \|
gokmenascioglu	0:a8fa94490a0a	1464	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
gokmenascioglu	0:a8fa94490a0a	1465	return (0); /* Function successful */
gokmenascioglu	0:a8fa94490a0a	1466	}
gokmenascioglu	0:a8fa94490a0a	1467
gokmenascioglu	0:a8fa94490a0a	1468	#endif
gokmenascioglu	0:a8fa94490a0a	1469
gokmenascioglu	0:a8fa94490a0a	1470	/@} end of CMSIS_Core_SysTickFunctions /
gokmenascioglu	0:a8fa94490a0a	1471
gokmenascioglu	0:a8fa94490a0a	1472
gokmenascioglu	0:a8fa94490a0a	1473
gokmenascioglu	0:a8fa94490a0a	1474	/* ##################################### Debug In/Output function ########################################### */
gokmenascioglu	0:a8fa94490a0a	1475	/** \ingroup CMSIS_Core_FunctionInterface
gokmenascioglu	0:a8fa94490a0a	1476	\defgroup CMSIS_core_DebugFunctions ITM Functions
gokmenascioglu	0:a8fa94490a0a	1477	\brief Functions that access the ITM debug interface.
gokmenascioglu	0:a8fa94490a0a	1478	@{
gokmenascioglu	0:a8fa94490a0a	1479	*/
gokmenascioglu	0:a8fa94490a0a	1480
gokmenascioglu	0:a8fa94490a0a	1481	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
gokmenascioglu	0:a8fa94490a0a	1482	#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
gokmenascioglu	0:a8fa94490a0a	1483
gokmenascioglu	0:a8fa94490a0a	1484
gokmenascioglu	0:a8fa94490a0a	1485	/** \brief ITM Send Character
gokmenascioglu	0:a8fa94490a0a	1486
gokmenascioglu	0:a8fa94490a0a	1487	The function transmits a character via the ITM channel 0, and
gokmenascioglu	0:a8fa94490a0a	1488	\li Just returns when no debugger is connected that has booked the output.
gokmenascioglu	0:a8fa94490a0a	1489	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
gokmenascioglu	0:a8fa94490a0a	1490
gokmenascioglu	0:a8fa94490a0a	1491	\param [in] ch Character to transmit.
gokmenascioglu	0:a8fa94490a0a	1492
gokmenascioglu	0:a8fa94490a0a	1493	\returns Character to transmit.
gokmenascioglu	0:a8fa94490a0a	1494	*/
gokmenascioglu	0:a8fa94490a0a	1495	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
gokmenascioglu	0:a8fa94490a0a	1496	{
gokmenascioglu	0:a8fa94490a0a	1497	if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
gokmenascioglu	0:a8fa94490a0a	1498	(ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
gokmenascioglu	0:a8fa94490a0a	1499	{
gokmenascioglu	0:a8fa94490a0a	1500	while (ITM->PORT[0].u32 == 0);
gokmenascioglu	0:a8fa94490a0a	1501	ITM->PORT[0].u8 = (uint8_t) ch;
gokmenascioglu	0:a8fa94490a0a	1502	}
gokmenascioglu	0:a8fa94490a0a	1503	return (ch);
gokmenascioglu	0:a8fa94490a0a	1504	}
gokmenascioglu	0:a8fa94490a0a	1505
gokmenascioglu	0:a8fa94490a0a	1506
gokmenascioglu	0:a8fa94490a0a	1507	/** \brief ITM Receive Character
gokmenascioglu	0:a8fa94490a0a	1508
gokmenascioglu	0:a8fa94490a0a	1509	The function inputs a character via the external variable \ref ITM_RxBuffer.
gokmenascioglu	0:a8fa94490a0a	1510
gokmenascioglu	0:a8fa94490a0a	1511	\return Received character.
gokmenascioglu	0:a8fa94490a0a	1512	\return -1 No character pending.
gokmenascioglu	0:a8fa94490a0a	1513	*/
gokmenascioglu	0:a8fa94490a0a	1514	__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
gokmenascioglu	0:a8fa94490a0a	1515	int32_t ch = -1; /* no character available */
gokmenascioglu	0:a8fa94490a0a	1516
gokmenascioglu	0:a8fa94490a0a	1517	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
gokmenascioglu	0:a8fa94490a0a	1518	ch = ITM_RxBuffer;
gokmenascioglu	0:a8fa94490a0a	1519	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
gokmenascioglu	0:a8fa94490a0a	1520	}
gokmenascioglu	0:a8fa94490a0a	1521
gokmenascioglu	0:a8fa94490a0a	1522	return (ch);
gokmenascioglu	0:a8fa94490a0a	1523	}
gokmenascioglu	0:a8fa94490a0a	1524
gokmenascioglu	0:a8fa94490a0a	1525
gokmenascioglu	0:a8fa94490a0a	1526	/** \brief ITM Check Character
gokmenascioglu	0:a8fa94490a0a	1527
gokmenascioglu	0:a8fa94490a0a	1528	The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
gokmenascioglu	0:a8fa94490a0a	1529
gokmenascioglu	0:a8fa94490a0a	1530	\return 0 No character available.
gokmenascioglu	0:a8fa94490a0a	1531	\return 1 Character available.
gokmenascioglu	0:a8fa94490a0a	1532	*/
gokmenascioglu	0:a8fa94490a0a	1533	__STATIC_INLINE int32_t ITM_CheckChar (void) {
gokmenascioglu	0:a8fa94490a0a	1534
gokmenascioglu	0:a8fa94490a0a	1535	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
gokmenascioglu	0:a8fa94490a0a	1536	return (0); /* no character available */
gokmenascioglu	0:a8fa94490a0a	1537	} else {
gokmenascioglu	0:a8fa94490a0a	1538	return (1); /* character available */
gokmenascioglu	0:a8fa94490a0a	1539	}
gokmenascioglu	0:a8fa94490a0a	1540	}
gokmenascioglu	0:a8fa94490a0a	1541
gokmenascioglu	0:a8fa94490a0a	1542	/@} end of CMSIS_core_DebugFunctions /
gokmenascioglu	0:a8fa94490a0a	1543
gokmenascioglu	0:a8fa94490a0a	1544	#endif /* __CORE_CM3_H_DEPENDANT */
gokmenascioglu	0:a8fa94490a0a	1545
gokmenascioglu	0:a8fa94490a0a	1546	#endif /* __CMSIS_GENERIC */
gokmenascioglu	0:a8fa94490a0a	1547
gokmenascioglu	0:a8fa94490a0a	1548	#ifdef __cplusplus
gokmenascioglu	0:a8fa94490a0a	1549	}
gokmenascioglu	0:a8fa94490a0a	1550	#endif

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Type:	Library
Created:	04 Oct 2013
Imports:	265
Forks:	0
Commits:	2
Dependents:	1
Dependencies:	0
Followers:	5

The code in this repository is Apache licensed.

LPC1768/core_cm3.h@1:b749145a7bb1, 2013-10-04 (annotated)

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