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Fork of mbed by gokmen ascioglu

LPC1768/LPC17xx.h@1:b749145a7bb1, 2013-10-04 (annotated)

Committer:
itotaka
Date:
Fri Oct 04 12:17:02 2013 +0000
Revision:
1:b749145a7bb1
Parent:
0:a8fa94490a0a 
changed Max_Arg to 80

Who changed what in which revision?

UserRevisionLine numberNew contents of line
gokmenascioglu 0:a8fa94490a0a 1 /**************************************************************************//**
gokmenascioglu 0:a8fa94490a0a 2 * @file LPC17xx.h
gokmenascioglu 0:a8fa94490a0a 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
gokmenascioglu 0:a8fa94490a0a 4 * NXP LPC17xx Device Series
gokmenascioglu 0:a8fa94490a0a 5 * @version: V1.09
gokmenascioglu 0:a8fa94490a0a 6 * @date: 17. March 2010
gokmenascioglu 0:a8fa94490a0a 7
gokmenascioglu 0:a8fa94490a0a 8 *
gokmenascioglu 0:a8fa94490a0a 9 * @note
gokmenascioglu 0:a8fa94490a0a 10 * Copyright (C) 2009 ARM Limited. All rights reserved.
gokmenascioglu 0:a8fa94490a0a 11 *
gokmenascioglu 0:a8fa94490a0a 12 * @par
gokmenascioglu 0:a8fa94490a0a 13 * ARM Limited (ARM) is supplying this software for use with Cortex-M
gokmenascioglu 0:a8fa94490a0a 14 * processor based microcontrollers. This file can be freely distributed
gokmenascioglu 0:a8fa94490a0a 15 * within development tools that are supporting such ARM based processors.
gokmenascioglu 0:a8fa94490a0a 16 *
gokmenascioglu 0:a8fa94490a0a 17 * @par
gokmenascioglu 0:a8fa94490a0a 18 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
gokmenascioglu 0:a8fa94490a0a 19 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
gokmenascioglu 0:a8fa94490a0a 20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
gokmenascioglu 0:a8fa94490a0a 21 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
gokmenascioglu 0:a8fa94490a0a 22 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
gokmenascioglu 0:a8fa94490a0a 23 *
gokmenascioglu 0:a8fa94490a0a 24 ******************************************************************************/
gokmenascioglu 0:a8fa94490a0a 25
gokmenascioglu 0:a8fa94490a0a 26
gokmenascioglu 0:a8fa94490a0a 27 #ifndef __LPC17xx_H__
gokmenascioglu 0:a8fa94490a0a 28 #define __LPC17xx_H__
gokmenascioglu 0:a8fa94490a0a 29
gokmenascioglu 0:a8fa94490a0a 30 /*
gokmenascioglu 0:a8fa94490a0a 31 * ==========================================================================
gokmenascioglu 0:a8fa94490a0a 32 * ---------- Interrupt Number Definition -----------------------------------
gokmenascioglu 0:a8fa94490a0a 33 * ==========================================================================
gokmenascioglu 0:a8fa94490a0a 34 */
gokmenascioglu 0:a8fa94490a0a 35
gokmenascioglu 0:a8fa94490a0a 36 typedef enum IRQn
gokmenascioglu 0:a8fa94490a0a 37 {
gokmenascioglu 0:a8fa94490a0a 38 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
gokmenascioglu 0:a8fa94490a0a 39 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
gokmenascioglu 0:a8fa94490a0a 40 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
gokmenascioglu 0:a8fa94490a0a 41 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
gokmenascioglu 0:a8fa94490a0a 42 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
gokmenascioglu 0:a8fa94490a0a 43 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
gokmenascioglu 0:a8fa94490a0a 44 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
gokmenascioglu 0:a8fa94490a0a 45 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
gokmenascioglu 0:a8fa94490a0a 46 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
gokmenascioglu 0:a8fa94490a0a 47
gokmenascioglu 0:a8fa94490a0a 48 /****** LPC17xx Specific Interrupt Numbers *******************************************************/
gokmenascioglu 0:a8fa94490a0a 49 WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
gokmenascioglu 0:a8fa94490a0a 50 TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
gokmenascioglu 0:a8fa94490a0a 51 TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
gokmenascioglu 0:a8fa94490a0a 52 TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
gokmenascioglu 0:a8fa94490a0a 53 TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
gokmenascioglu 0:a8fa94490a0a 54 UART0_IRQn = 5, /*!< UART0 Interrupt */
gokmenascioglu 0:a8fa94490a0a 55 UART1_IRQn = 6, /*!< UART1 Interrupt */
gokmenascioglu 0:a8fa94490a0a 56 UART2_IRQn = 7, /*!< UART2 Interrupt */
gokmenascioglu 0:a8fa94490a0a 57 UART3_IRQn = 8, /*!< UART3 Interrupt */
gokmenascioglu 0:a8fa94490a0a 58 PWM1_IRQn = 9, /*!< PWM1 Interrupt */
gokmenascioglu 0:a8fa94490a0a 59 I2C0_IRQn = 10, /*!< I2C0 Interrupt */
gokmenascioglu 0:a8fa94490a0a 60 I2C1_IRQn = 11, /*!< I2C1 Interrupt */
gokmenascioglu 0:a8fa94490a0a 61 I2C2_IRQn = 12, /*!< I2C2 Interrupt */
gokmenascioglu 0:a8fa94490a0a 62 SPI_IRQn = 13, /*!< SPI Interrupt */
gokmenascioglu 0:a8fa94490a0a 63 SSP0_IRQn = 14, /*!< SSP0 Interrupt */
gokmenascioglu 0:a8fa94490a0a 64 SSP1_IRQn = 15, /*!< SSP1 Interrupt */
gokmenascioglu 0:a8fa94490a0a 65 PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
gokmenascioglu 0:a8fa94490a0a 66 RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
gokmenascioglu 0:a8fa94490a0a 67 EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
gokmenascioglu 0:a8fa94490a0a 68 EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
gokmenascioglu 0:a8fa94490a0a 69 EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
gokmenascioglu 0:a8fa94490a0a 70 EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
gokmenascioglu 0:a8fa94490a0a 71 ADC_IRQn = 22, /*!< A/D Converter Interrupt */
gokmenascioglu 0:a8fa94490a0a 72 BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
gokmenascioglu 0:a8fa94490a0a 73 USB_IRQn = 24, /*!< USB Interrupt */
gokmenascioglu 0:a8fa94490a0a 74 CAN_IRQn = 25, /*!< CAN Interrupt */
gokmenascioglu 0:a8fa94490a0a 75 DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
gokmenascioglu 0:a8fa94490a0a 76 I2S_IRQn = 27, /*!< I2S Interrupt */
gokmenascioglu 0:a8fa94490a0a 77 ENET_IRQn = 28, /*!< Ethernet Interrupt */
gokmenascioglu 0:a8fa94490a0a 78 RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */
gokmenascioglu 0:a8fa94490a0a 79 MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
gokmenascioglu 0:a8fa94490a0a 80 QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
gokmenascioglu 0:a8fa94490a0a 81 PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
gokmenascioglu 0:a8fa94490a0a 82 USBActivity_IRQn = 33, /* USB Activity interrupt */
gokmenascioglu 0:a8fa94490a0a 83 CANActivity_IRQn = 34, /* CAN Activity interrupt */
gokmenascioglu 0:a8fa94490a0a 84 } IRQn_Type;
gokmenascioglu 0:a8fa94490a0a 85
gokmenascioglu 0:a8fa94490a0a 86
gokmenascioglu 0:a8fa94490a0a 87 /*
gokmenascioglu 0:a8fa94490a0a 88 * ==========================================================================
gokmenascioglu 0:a8fa94490a0a 89 * ----------- Processor and Core Peripheral Section ------------------------
gokmenascioglu 0:a8fa94490a0a 90 * ==========================================================================
gokmenascioglu 0:a8fa94490a0a 91 */
gokmenascioglu 0:a8fa94490a0a 92
gokmenascioglu 0:a8fa94490a0a 93 /* Configuration of the Cortex-M3 Processor and Core Peripherals */
gokmenascioglu 0:a8fa94490a0a 94 #define __MPU_PRESENT 1 /*!< MPU present or not */
gokmenascioglu 0:a8fa94490a0a 95 #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
gokmenascioglu 0:a8fa94490a0a 96 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
gokmenascioglu 0:a8fa94490a0a 97
gokmenascioglu 0:a8fa94490a0a 98
gokmenascioglu 0:a8fa94490a0a 99 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
gokmenascioglu 0:a8fa94490a0a 100 #include "system_LPC17xx.h" /* System Header */
gokmenascioglu 0:a8fa94490a0a 101
gokmenascioglu 0:a8fa94490a0a 102
gokmenascioglu 0:a8fa94490a0a 103 /******************************************************************************/
gokmenascioglu 0:a8fa94490a0a 104 /* Device Specific Peripheral registers structures */
gokmenascioglu 0:a8fa94490a0a 105 /******************************************************************************/
gokmenascioglu 0:a8fa94490a0a 106
gokmenascioglu 0:a8fa94490a0a 107 #if defined ( __CC_ARM )
gokmenascioglu 0:a8fa94490a0a 108 #pragma anon_unions
gokmenascioglu 0:a8fa94490a0a 109 #endif
gokmenascioglu 0:a8fa94490a0a 110
gokmenascioglu 0:a8fa94490a0a 111 /*------------- System Control (SC) ------------------------------------------*/
gokmenascioglu 0:a8fa94490a0a 112 typedef struct
gokmenascioglu 0:a8fa94490a0a 113 {
gokmenascioglu 0:a8fa94490a0a 114 __IO uint32_t FLASHCFG; /* Flash Accelerator Module */
gokmenascioglu 0:a8fa94490a0a 115 uint32_t RESERVED0[31];
gokmenascioglu 0:a8fa94490a0a 116 __IO uint32_t PLL0CON; /* Clocking and Power Control */
gokmenascioglu 0:a8fa94490a0a 117 __IO uint32_t PLL0CFG;
gokmenascioglu 0:a8fa94490a0a 118 __I uint32_t PLL0STAT;
gokmenascioglu 0:a8fa94490a0a 119 __O uint32_t PLL0FEED;
gokmenascioglu 0:a8fa94490a0a 120 uint32_t RESERVED1[4];
gokmenascioglu 0:a8fa94490a0a 121 __IO uint32_t PLL1CON;
gokmenascioglu 0:a8fa94490a0a 122 __IO uint32_t PLL1CFG;
gokmenascioglu 0:a8fa94490a0a 123 __I uint32_t PLL1STAT;
gokmenascioglu 0:a8fa94490a0a 124 __O uint32_t PLL1FEED;
gokmenascioglu 0:a8fa94490a0a 125 uint32_t RESERVED2[4];
gokmenascioglu 0:a8fa94490a0a 126 __IO uint32_t PCON;
gokmenascioglu 0:a8fa94490a0a 127 __IO uint32_t PCONP;
gokmenascioglu 0:a8fa94490a0a 128 uint32_t RESERVED3[15];
gokmenascioglu 0:a8fa94490a0a 129 __IO uint32_t CCLKCFG;
gokmenascioglu 0:a8fa94490a0a 130 __IO uint32_t USBCLKCFG;
gokmenascioglu 0:a8fa94490a0a 131 __IO uint32_t CLKSRCSEL;
gokmenascioglu 0:a8fa94490a0a 132 __IO uint32_t CANSLEEPCLR;
gokmenascioglu 0:a8fa94490a0a 133 __IO uint32_t CANWAKEFLAGS;
gokmenascioglu 0:a8fa94490a0a 134 uint32_t RESERVED4[10];
gokmenascioglu 0:a8fa94490a0a 135 __IO uint32_t EXTINT; /* External Interrupts */
gokmenascioglu 0:a8fa94490a0a 136 uint32_t RESERVED5;
gokmenascioglu 0:a8fa94490a0a 137 __IO uint32_t EXTMODE;
gokmenascioglu 0:a8fa94490a0a 138 __IO uint32_t EXTPOLAR;
gokmenascioglu 0:a8fa94490a0a 139 uint32_t RESERVED6[12];
gokmenascioglu 0:a8fa94490a0a 140 __IO uint32_t RSID; /* Reset */
gokmenascioglu 0:a8fa94490a0a 141 uint32_t RESERVED7[7];
gokmenascioglu 0:a8fa94490a0a 142 __IO uint32_t SCS; /* Syscon Miscellaneous Registers */
gokmenascioglu 0:a8fa94490a0a 143 __IO uint32_t IRCTRIM; /* Clock Dividers */
gokmenascioglu 0:a8fa94490a0a 144 __IO uint32_t PCLKSEL0;
gokmenascioglu 0:a8fa94490a0a 145 __IO uint32_t PCLKSEL1;
gokmenascioglu 0:a8fa94490a0a 146 uint32_t RESERVED8[4];
gokmenascioglu 0:a8fa94490a0a 147 __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
gokmenascioglu 0:a8fa94490a0a 148 __IO uint32_t DMAREQSEL;
gokmenascioglu 0:a8fa94490a0a 149 __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
gokmenascioglu 0:a8fa94490a0a 150 } LPC_SC_TypeDef;
gokmenascioglu 0:a8fa94490a0a 151
gokmenascioglu 0:a8fa94490a0a 152 /*------------- Pin Connect Block (PINCON) -----------------------------------*/
gokmenascioglu 0:a8fa94490a0a 153 typedef struct
gokmenascioglu 0:a8fa94490a0a 154 {
gokmenascioglu 0:a8fa94490a0a 155 __IO uint32_t PINSEL0;
gokmenascioglu 0:a8fa94490a0a 156 __IO uint32_t PINSEL1;
gokmenascioglu 0:a8fa94490a0a 157 __IO uint32_t PINSEL2;
gokmenascioglu 0:a8fa94490a0a 158 __IO uint32_t PINSEL3;
gokmenascioglu 0:a8fa94490a0a 159 __IO uint32_t PINSEL4;
gokmenascioglu 0:a8fa94490a0a 160 __IO uint32_t PINSEL5;
gokmenascioglu 0:a8fa94490a0a 161 __IO uint32_t PINSEL6;
gokmenascioglu 0:a8fa94490a0a 162 __IO uint32_t PINSEL7;
gokmenascioglu 0:a8fa94490a0a 163 __IO uint32_t PINSEL8;
gokmenascioglu 0:a8fa94490a0a 164 __IO uint32_t PINSEL9;
gokmenascioglu 0:a8fa94490a0a 165 __IO uint32_t PINSEL10;
gokmenascioglu 0:a8fa94490a0a 166 uint32_t RESERVED0[5];
gokmenascioglu 0:a8fa94490a0a 167 __IO uint32_t PINMODE0;
gokmenascioglu 0:a8fa94490a0a 168 __IO uint32_t PINMODE1;
gokmenascioglu 0:a8fa94490a0a 169 __IO uint32_t PINMODE2;
gokmenascioglu 0:a8fa94490a0a 170 __IO uint32_t PINMODE3;
gokmenascioglu 0:a8fa94490a0a 171 __IO uint32_t PINMODE4;
gokmenascioglu 0:a8fa94490a0a 172 __IO uint32_t PINMODE5;
gokmenascioglu 0:a8fa94490a0a 173 __IO uint32_t PINMODE6;
gokmenascioglu 0:a8fa94490a0a 174 __IO uint32_t PINMODE7;
gokmenascioglu 0:a8fa94490a0a 175 __IO uint32_t PINMODE8;
gokmenascioglu 0:a8fa94490a0a 176 __IO uint32_t PINMODE9;
gokmenascioglu 0:a8fa94490a0a 177 __IO uint32_t PINMODE_OD0;
gokmenascioglu 0:a8fa94490a0a 178 __IO uint32_t PINMODE_OD1;
gokmenascioglu 0:a8fa94490a0a 179 __IO uint32_t PINMODE_OD2;
gokmenascioglu 0:a8fa94490a0a 180 __IO uint32_t PINMODE_OD3;
gokmenascioglu 0:a8fa94490a0a 181 __IO uint32_t PINMODE_OD4;
gokmenascioglu 0:a8fa94490a0a 182 __IO uint32_t I2CPADCFG;
gokmenascioglu 0:a8fa94490a0a 183 } LPC_PINCON_TypeDef;
gokmenascioglu 0:a8fa94490a0a 184
gokmenascioglu 0:a8fa94490a0a 185 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
gokmenascioglu 0:a8fa94490a0a 186 typedef struct
gokmenascioglu 0:a8fa94490a0a 187 {
gokmenascioglu 0:a8fa94490a0a 188 union {
gokmenascioglu 0:a8fa94490a0a 189 __IO uint32_t FIODIR;
gokmenascioglu 0:a8fa94490a0a 190 struct {
gokmenascioglu 0:a8fa94490a0a 191 __IO uint16_t FIODIRL;
gokmenascioglu 0:a8fa94490a0a 192 __IO uint16_t FIODIRH;
gokmenascioglu 0:a8fa94490a0a 193 };
gokmenascioglu 0:a8fa94490a0a 194 struct {
gokmenascioglu 0:a8fa94490a0a 195 __IO uint8_t FIODIR0;
gokmenascioglu 0:a8fa94490a0a 196 __IO uint8_t FIODIR1;
gokmenascioglu 0:a8fa94490a0a 197 __IO uint8_t FIODIR2;
gokmenascioglu 0:a8fa94490a0a 198 __IO uint8_t FIODIR3;
gokmenascioglu 0:a8fa94490a0a 199 };
gokmenascioglu 0:a8fa94490a0a 200 };
gokmenascioglu 0:a8fa94490a0a 201 uint32_t RESERVED0[3];
gokmenascioglu 0:a8fa94490a0a 202 union {
gokmenascioglu 0:a8fa94490a0a 203 __IO uint32_t FIOMASK;
gokmenascioglu 0:a8fa94490a0a 204 struct {
gokmenascioglu 0:a8fa94490a0a 205 __IO uint16_t FIOMASKL;
gokmenascioglu 0:a8fa94490a0a 206 __IO uint16_t FIOMASKH;
gokmenascioglu 0:a8fa94490a0a 207 };
gokmenascioglu 0:a8fa94490a0a 208 struct {
gokmenascioglu 0:a8fa94490a0a 209 __IO uint8_t FIOMASK0;
gokmenascioglu 0:a8fa94490a0a 210 __IO uint8_t FIOMASK1;
gokmenascioglu 0:a8fa94490a0a 211 __IO uint8_t FIOMASK2;
gokmenascioglu 0:a8fa94490a0a 212 __IO uint8_t FIOMASK3;
gokmenascioglu 0:a8fa94490a0a 213 };
gokmenascioglu 0:a8fa94490a0a 214 };
gokmenascioglu 0:a8fa94490a0a 215 union {
gokmenascioglu 0:a8fa94490a0a 216 __IO uint32_t FIOPIN;
gokmenascioglu 0:a8fa94490a0a 217 struct {
gokmenascioglu 0:a8fa94490a0a 218 __IO uint16_t FIOPINL;
gokmenascioglu 0:a8fa94490a0a 219 __IO uint16_t FIOPINH;
gokmenascioglu 0:a8fa94490a0a 220 };
gokmenascioglu 0:a8fa94490a0a 221 struct {
gokmenascioglu 0:a8fa94490a0a 222 __IO uint8_t FIOPIN0;
gokmenascioglu 0:a8fa94490a0a 223 __IO uint8_t FIOPIN1;
gokmenascioglu 0:a8fa94490a0a 224 __IO uint8_t FIOPIN2;
gokmenascioglu 0:a8fa94490a0a 225 __IO uint8_t FIOPIN3;
gokmenascioglu 0:a8fa94490a0a 226 };
gokmenascioglu 0:a8fa94490a0a 227 };
gokmenascioglu 0:a8fa94490a0a 228 union {
gokmenascioglu 0:a8fa94490a0a 229 __IO uint32_t FIOSET;
gokmenascioglu 0:a8fa94490a0a 230 struct {
gokmenascioglu 0:a8fa94490a0a 231 __IO uint16_t FIOSETL;
gokmenascioglu 0:a8fa94490a0a 232 __IO uint16_t FIOSETH;
gokmenascioglu 0:a8fa94490a0a 233 };
gokmenascioglu 0:a8fa94490a0a 234 struct {
gokmenascioglu 0:a8fa94490a0a 235 __IO uint8_t FIOSET0;
gokmenascioglu 0:a8fa94490a0a 236 __IO uint8_t FIOSET1;
gokmenascioglu 0:a8fa94490a0a 237 __IO uint8_t FIOSET2;
gokmenascioglu 0:a8fa94490a0a 238 __IO uint8_t FIOSET3;
gokmenascioglu 0:a8fa94490a0a 239 };
gokmenascioglu 0:a8fa94490a0a 240 };
gokmenascioglu 0:a8fa94490a0a 241 union {
gokmenascioglu 0:a8fa94490a0a 242 __O uint32_t FIOCLR;
gokmenascioglu 0:a8fa94490a0a 243 struct {
gokmenascioglu 0:a8fa94490a0a 244 __O uint16_t FIOCLRL;
gokmenascioglu 0:a8fa94490a0a 245 __O uint16_t FIOCLRH;
gokmenascioglu 0:a8fa94490a0a 246 };
gokmenascioglu 0:a8fa94490a0a 247 struct {
gokmenascioglu 0:a8fa94490a0a 248 __O uint8_t FIOCLR0;
gokmenascioglu 0:a8fa94490a0a 249 __O uint8_t FIOCLR1;
gokmenascioglu 0:a8fa94490a0a 250 __O uint8_t FIOCLR2;
gokmenascioglu 0:a8fa94490a0a 251 __O uint8_t FIOCLR3;
gokmenascioglu 0:a8fa94490a0a 252 };
gokmenascioglu 0:a8fa94490a0a 253 };
gokmenascioglu 0:a8fa94490a0a 254 } LPC_GPIO_TypeDef;
gokmenascioglu 0:a8fa94490a0a 255
gokmenascioglu 0:a8fa94490a0a 256 typedef struct
gokmenascioglu 0:a8fa94490a0a 257 {
gokmenascioglu 0:a8fa94490a0a 258 __I uint32_t IntStatus;
gokmenascioglu 0:a8fa94490a0a 259 __I uint32_t IO0IntStatR;
gokmenascioglu 0:a8fa94490a0a 260 __I uint32_t IO0IntStatF;
gokmenascioglu 0:a8fa94490a0a 261 __O uint32_t IO0IntClr;
gokmenascioglu 0:a8fa94490a0a 262 __IO uint32_t IO0IntEnR;
gokmenascioglu 0:a8fa94490a0a 263 __IO uint32_t IO0IntEnF;
gokmenascioglu 0:a8fa94490a0a 264 uint32_t RESERVED0[3];
gokmenascioglu 0:a8fa94490a0a 265 __I uint32_t IO2IntStatR;
gokmenascioglu 0:a8fa94490a0a 266 __I uint32_t IO2IntStatF;
gokmenascioglu 0:a8fa94490a0a 267 __O uint32_t IO2IntClr;
gokmenascioglu 0:a8fa94490a0a 268 __IO uint32_t IO2IntEnR;
gokmenascioglu 0:a8fa94490a0a 269 __IO uint32_t IO2IntEnF;
gokmenascioglu 0:a8fa94490a0a 270 } LPC_GPIOINT_TypeDef;
gokmenascioglu 0:a8fa94490a0a 271
gokmenascioglu 0:a8fa94490a0a 272 /*------------- Timer (TIM) --------------------------------------------------*/
gokmenascioglu 0:a8fa94490a0a 273 typedef struct
gokmenascioglu 0:a8fa94490a0a 274 {
gokmenascioglu 0:a8fa94490a0a 275 __IO uint32_t IR;
gokmenascioglu 0:a8fa94490a0a 276 __IO uint32_t TCR;
gokmenascioglu 0:a8fa94490a0a 277 __IO uint32_t TC;
gokmenascioglu 0:a8fa94490a0a 278 __IO uint32_t PR;
gokmenascioglu 0:a8fa94490a0a 279 __IO uint32_t PC;
gokmenascioglu 0:a8fa94490a0a 280 __IO uint32_t MCR;
gokmenascioglu 0:a8fa94490a0a 281 __IO uint32_t MR0;
gokmenascioglu 0:a8fa94490a0a 282 __IO uint32_t MR1;
gokmenascioglu 0:a8fa94490a0a 283 __IO uint32_t MR2;
gokmenascioglu 0:a8fa94490a0a 284 __IO uint32_t MR3;
gokmenascioglu 0:a8fa94490a0a 285 __IO uint32_t CCR;
gokmenascioglu 0:a8fa94490a0a 286 __I uint32_t CR0;
gokmenascioglu 0:a8fa94490a0a 287 __I uint32_t CR1;
gokmenascioglu 0:a8fa94490a0a 288 uint32_t RESERVED0[2];
gokmenascioglu 0:a8fa94490a0a 289 __IO uint32_t EMR;
gokmenascioglu 0:a8fa94490a0a 290 uint32_t RESERVED1[12];
gokmenascioglu 0:a8fa94490a0a 291 __IO uint32_t CTCR;
gokmenascioglu 0:a8fa94490a0a 292 } LPC_TIM_TypeDef;
gokmenascioglu 0:a8fa94490a0a 293
gokmenascioglu 0:a8fa94490a0a 294 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
gokmenascioglu 0:a8fa94490a0a 295 typedef struct
gokmenascioglu 0:a8fa94490a0a 296 {
gokmenascioglu 0:a8fa94490a0a 297 __IO uint32_t IR;
gokmenascioglu 0:a8fa94490a0a 298 __IO uint32_t TCR;
gokmenascioglu 0:a8fa94490a0a 299 __IO uint32_t TC;
gokmenascioglu 0:a8fa94490a0a 300 __IO uint32_t PR;
gokmenascioglu 0:a8fa94490a0a 301 __IO uint32_t PC;
gokmenascioglu 0:a8fa94490a0a 302 __IO uint32_t MCR;
gokmenascioglu 0:a8fa94490a0a 303 __IO uint32_t MR0;
gokmenascioglu 0:a8fa94490a0a 304 __IO uint32_t MR1;
gokmenascioglu 0:a8fa94490a0a 305 __IO uint32_t MR2;
gokmenascioglu 0:a8fa94490a0a 306 __IO uint32_t MR3;
gokmenascioglu 0:a8fa94490a0a 307 __IO uint32_t CCR;
gokmenascioglu 0:a8fa94490a0a 308 __I uint32_t CR0;
gokmenascioglu 0:a8fa94490a0a 309 __I uint32_t CR1;
gokmenascioglu 0:a8fa94490a0a 310 __I uint32_t CR2;
gokmenascioglu 0:a8fa94490a0a 311 __I uint32_t CR3;
gokmenascioglu 0:a8fa94490a0a 312 uint32_t RESERVED0;
gokmenascioglu 0:a8fa94490a0a 313 __IO uint32_t MR4;
gokmenascioglu 0:a8fa94490a0a 314 __IO uint32_t MR5;
gokmenascioglu 0:a8fa94490a0a 315 __IO uint32_t MR6;
gokmenascioglu 0:a8fa94490a0a 316 __IO uint32_t PCR;
gokmenascioglu 0:a8fa94490a0a 317 __IO uint32_t LER;
gokmenascioglu 0:a8fa94490a0a 318 uint32_t RESERVED1[7];
gokmenascioglu 0:a8fa94490a0a 319 __IO uint32_t CTCR;
gokmenascioglu 0:a8fa94490a0a 320 } LPC_PWM_TypeDef;
gokmenascioglu 0:a8fa94490a0a 321
gokmenascioglu 0:a8fa94490a0a 322 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
gokmenascioglu 0:a8fa94490a0a 323 typedef struct
gokmenascioglu 0:a8fa94490a0a 324 {
gokmenascioglu 0:a8fa94490a0a 325 union {
gokmenascioglu 0:a8fa94490a0a 326 __I uint8_t RBR;
gokmenascioglu 0:a8fa94490a0a 327 __O uint8_t THR;
gokmenascioglu 0:a8fa94490a0a 328 __IO uint8_t DLL;
gokmenascioglu 0:a8fa94490a0a 329 uint32_t RESERVED0;
gokmenascioglu 0:a8fa94490a0a 330 };
gokmenascioglu 0:a8fa94490a0a 331 union {
gokmenascioglu 0:a8fa94490a0a 332 __IO uint8_t DLM;
gokmenascioglu 0:a8fa94490a0a 333 __IO uint32_t IER;
gokmenascioglu 0:a8fa94490a0a 334 };
gokmenascioglu 0:a8fa94490a0a 335 union {
gokmenascioglu 0:a8fa94490a0a 336 __I uint32_t IIR;
gokmenascioglu 0:a8fa94490a0a 337 __O uint8_t FCR;
gokmenascioglu 0:a8fa94490a0a 338 };
gokmenascioglu 0:a8fa94490a0a 339 __IO uint8_t LCR;
gokmenascioglu 0:a8fa94490a0a 340 uint8_t RESERVED1[7];
gokmenascioglu 0:a8fa94490a0a 341 __I uint8_t LSR;
gokmenascioglu 0:a8fa94490a0a 342 uint8_t RESERVED2[7];
gokmenascioglu 0:a8fa94490a0a 343 __IO uint8_t SCR;
gokmenascioglu 0:a8fa94490a0a 344 uint8_t RESERVED3[3];
gokmenascioglu 0:a8fa94490a0a 345 __IO uint32_t ACR;
gokmenascioglu 0:a8fa94490a0a 346 __IO uint8_t ICR;
gokmenascioglu 0:a8fa94490a0a 347 uint8_t RESERVED4[3];
gokmenascioglu 0:a8fa94490a0a 348 __IO uint8_t FDR;
gokmenascioglu 0:a8fa94490a0a 349 uint8_t RESERVED5[7];
gokmenascioglu 0:a8fa94490a0a 350 __IO uint8_t TER;
gokmenascioglu 0:a8fa94490a0a 351 uint8_t RESERVED6[39];
gokmenascioglu 0:a8fa94490a0a 352 __IO uint32_t FIFOLVL;
gokmenascioglu 0:a8fa94490a0a 353 } LPC_UART_TypeDef;
gokmenascioglu 0:a8fa94490a0a 354
gokmenascioglu 0:a8fa94490a0a 355 typedef struct
gokmenascioglu 0:a8fa94490a0a 356 {
gokmenascioglu 0:a8fa94490a0a 357 union {
gokmenascioglu 0:a8fa94490a0a 358 __I uint8_t RBR;
gokmenascioglu 0:a8fa94490a0a 359 __O uint8_t THR;
gokmenascioglu 0:a8fa94490a0a 360 __IO uint8_t DLL;
gokmenascioglu 0:a8fa94490a0a 361 uint32_t RESERVED0;
gokmenascioglu 0:a8fa94490a0a 362 };
gokmenascioglu 0:a8fa94490a0a 363 union {
gokmenascioglu 0:a8fa94490a0a 364 __IO uint8_t DLM;
gokmenascioglu 0:a8fa94490a0a 365 __IO uint32_t IER;
gokmenascioglu 0:a8fa94490a0a 366 };
gokmenascioglu 0:a8fa94490a0a 367 union {
gokmenascioglu 0:a8fa94490a0a 368 __I uint32_t IIR;
gokmenascioglu 0:a8fa94490a0a 369 __O uint8_t FCR;
gokmenascioglu 0:a8fa94490a0a 370 };
gokmenascioglu 0:a8fa94490a0a 371 __IO uint8_t LCR;
gokmenascioglu 0:a8fa94490a0a 372 uint8_t RESERVED1[7];
gokmenascioglu 0:a8fa94490a0a 373 __I uint8_t LSR;
gokmenascioglu 0:a8fa94490a0a 374 uint8_t RESERVED2[7];
gokmenascioglu 0:a8fa94490a0a 375 __IO uint8_t SCR;
gokmenascioglu 0:a8fa94490a0a 376 uint8_t RESERVED3[3];
gokmenascioglu 0:a8fa94490a0a 377 __IO uint32_t ACR;
gokmenascioglu 0:a8fa94490a0a 378 __IO uint8_t ICR;
gokmenascioglu 0:a8fa94490a0a 379 uint8_t RESERVED4[3];
gokmenascioglu 0:a8fa94490a0a 380 __IO uint8_t FDR;
gokmenascioglu 0:a8fa94490a0a 381 uint8_t RESERVED5[7];
gokmenascioglu 0:a8fa94490a0a 382 __IO uint8_t TER;
gokmenascioglu 0:a8fa94490a0a 383 uint8_t RESERVED6[39];
gokmenascioglu 0:a8fa94490a0a 384 __IO uint32_t FIFOLVL;
gokmenascioglu 0:a8fa94490a0a 385 } LPC_UART0_TypeDef;
gokmenascioglu 0:a8fa94490a0a 386
gokmenascioglu 0:a8fa94490a0a 387 typedef struct
gokmenascioglu 0:a8fa94490a0a 388 {
gokmenascioglu 0:a8fa94490a0a 389 union {
gokmenascioglu 0:a8fa94490a0a 390 __I uint8_t RBR;
gokmenascioglu 0:a8fa94490a0a 391 __O uint8_t THR;
gokmenascioglu 0:a8fa94490a0a 392 __IO uint8_t DLL;
gokmenascioglu 0:a8fa94490a0a 393 uint32_t RESERVED0;
gokmenascioglu 0:a8fa94490a0a 394 };
gokmenascioglu 0:a8fa94490a0a 395 union {
gokmenascioglu 0:a8fa94490a0a 396 __IO uint8_t DLM;
gokmenascioglu 0:a8fa94490a0a 397 __IO uint32_t IER;
gokmenascioglu 0:a8fa94490a0a 398 };
gokmenascioglu 0:a8fa94490a0a 399 union {
gokmenascioglu 0:a8fa94490a0a 400 __I uint32_t IIR;
gokmenascioglu 0:a8fa94490a0a 401 __O uint8_t FCR;
gokmenascioglu 0:a8fa94490a0a 402 };
gokmenascioglu 0:a8fa94490a0a 403 __IO uint8_t LCR;
gokmenascioglu 0:a8fa94490a0a 404 uint8_t RESERVED1[3];
gokmenascioglu 0:a8fa94490a0a 405 __IO uint8_t MCR;
gokmenascioglu 0:a8fa94490a0a 406 uint8_t RESERVED2[3];
gokmenascioglu 0:a8fa94490a0a 407 __I uint8_t LSR;
gokmenascioglu 0:a8fa94490a0a 408 uint8_t RESERVED3[3];
gokmenascioglu 0:a8fa94490a0a 409 __I uint8_t MSR;
gokmenascioglu 0:a8fa94490a0a 410 uint8_t RESERVED4[3];
gokmenascioglu 0:a8fa94490a0a 411 __IO uint8_t SCR;
gokmenascioglu 0:a8fa94490a0a 412 uint8_t RESERVED5[3];
gokmenascioglu 0:a8fa94490a0a 413 __IO uint32_t ACR;
gokmenascioglu 0:a8fa94490a0a 414 uint32_t RESERVED6;
gokmenascioglu 0:a8fa94490a0a 415 __IO uint32_t FDR;
gokmenascioglu 0:a8fa94490a0a 416 uint32_t RESERVED7;
gokmenascioglu 0:a8fa94490a0a 417 __IO uint8_t TER;
gokmenascioglu 0:a8fa94490a0a 418 uint8_t RESERVED8[27];
gokmenascioglu 0:a8fa94490a0a 419 __IO uint8_t RS485CTRL;
gokmenascioglu 0:a8fa94490a0a 420 uint8_t RESERVED9[3];
gokmenascioglu 0:a8fa94490a0a 421 __IO uint8_t ADRMATCH;
gokmenascioglu 0:a8fa94490a0a 422 uint8_t RESERVED10[3];
gokmenascioglu 0:a8fa94490a0a 423 __IO uint8_t RS485DLY;
gokmenascioglu 0:a8fa94490a0a 424 uint8_t RESERVED11[3];
gokmenascioglu 0:a8fa94490a0a 425 __IO uint32_t FIFOLVL;
gokmenascioglu 0:a8fa94490a0a 426 } LPC_UART1_TypeDef;
gokmenascioglu 0:a8fa94490a0a 427
gokmenascioglu 0:a8fa94490a0a 428 /*------------- Serial Peripheral Interface (SPI) ----------------------------*/
gokmenascioglu 0:a8fa94490a0a 429 typedef struct
gokmenascioglu 0:a8fa94490a0a 430 {
gokmenascioglu 0:a8fa94490a0a 431 __IO uint32_t SPCR;
gokmenascioglu 0:a8fa94490a0a 432 __I uint32_t SPSR;
gokmenascioglu 0:a8fa94490a0a 433 __IO uint32_t SPDR;
gokmenascioglu 0:a8fa94490a0a 434 __IO uint32_t SPCCR;
gokmenascioglu 0:a8fa94490a0a 435 uint32_t RESERVED0[3];
gokmenascioglu 0:a8fa94490a0a 436 __IO uint32_t SPINT;
gokmenascioglu 0:a8fa94490a0a 437 } LPC_SPI_TypeDef;
gokmenascioglu 0:a8fa94490a0a 438
gokmenascioglu 0:a8fa94490a0a 439 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
gokmenascioglu 0:a8fa94490a0a 440 typedef struct
gokmenascioglu 0:a8fa94490a0a 441 {
gokmenascioglu 0:a8fa94490a0a 442 __IO uint32_t CR0;
gokmenascioglu 0:a8fa94490a0a 443 __IO uint32_t CR1;
gokmenascioglu 0:a8fa94490a0a 444 __IO uint32_t DR;
gokmenascioglu 0:a8fa94490a0a 445 __I uint32_t SR;
gokmenascioglu 0:a8fa94490a0a 446 __IO uint32_t CPSR;
gokmenascioglu 0:a8fa94490a0a 447 __IO uint32_t IMSC;
gokmenascioglu 0:a8fa94490a0a 448 __IO uint32_t RIS;
gokmenascioglu 0:a8fa94490a0a 449 __IO uint32_t MIS;
gokmenascioglu 0:a8fa94490a0a 450 __IO uint32_t ICR;
gokmenascioglu 0:a8fa94490a0a 451 __IO uint32_t DMACR;
gokmenascioglu 0:a8fa94490a0a 452 } LPC_SSP_TypeDef;
gokmenascioglu 0:a8fa94490a0a 453
gokmenascioglu 0:a8fa94490a0a 454 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
gokmenascioglu 0:a8fa94490a0a 455 typedef struct
gokmenascioglu 0:a8fa94490a0a 456 {
gokmenascioglu 0:a8fa94490a0a 457 __IO uint32_t I2CONSET;
gokmenascioglu 0:a8fa94490a0a 458 __I uint32_t I2STAT;
gokmenascioglu 0:a8fa94490a0a 459 __IO uint32_t I2DAT;
gokmenascioglu 0:a8fa94490a0a 460 __IO uint32_t I2ADR0;
gokmenascioglu 0:a8fa94490a0a 461 __IO uint32_t I2SCLH;
gokmenascioglu 0:a8fa94490a0a 462 __IO uint32_t I2SCLL;
gokmenascioglu 0:a8fa94490a0a 463 __O uint32_t I2CONCLR;
gokmenascioglu 0:a8fa94490a0a 464 __IO uint32_t MMCTRL;
gokmenascioglu 0:a8fa94490a0a 465 __IO uint32_t I2ADR1;
gokmenascioglu 0:a8fa94490a0a 466 __IO uint32_t I2ADR2;
gokmenascioglu 0:a8fa94490a0a 467 __IO uint32_t I2ADR3;
gokmenascioglu 0:a8fa94490a0a 468 __I uint32_t I2DATA_BUFFER;
gokmenascioglu 0:a8fa94490a0a 469 __IO uint32_t I2MASK0;
gokmenascioglu 0:a8fa94490a0a 470 __IO uint32_t I2MASK1;
gokmenascioglu 0:a8fa94490a0a 471 __IO uint32_t I2MASK2;
gokmenascioglu 0:a8fa94490a0a 472 __IO uint32_t I2MASK3;
gokmenascioglu 0:a8fa94490a0a 473 } LPC_I2C_TypeDef;
gokmenascioglu 0:a8fa94490a0a 474
gokmenascioglu 0:a8fa94490a0a 475 /*------------- Inter IC Sound (I2S) -----------------------------------------*/
gokmenascioglu 0:a8fa94490a0a 476 typedef struct
gokmenascioglu 0:a8fa94490a0a 477 {
gokmenascioglu 0:a8fa94490a0a 478 __IO uint32_t I2SDAO;
gokmenascioglu 0:a8fa94490a0a 479 __IO uint32_t I2SDAI;
gokmenascioglu 0:a8fa94490a0a 480 __O uint32_t I2STXFIFO;
gokmenascioglu 0:a8fa94490a0a 481 __I uint32_t I2SRXFIFO;
gokmenascioglu 0:a8fa94490a0a 482 __I uint32_t I2SSTATE;
gokmenascioglu 0:a8fa94490a0a 483 __IO uint32_t I2SDMA1;
gokmenascioglu 0:a8fa94490a0a 484 __IO uint32_t I2SDMA2;
gokmenascioglu 0:a8fa94490a0a 485 __IO uint32_t I2SIRQ;
gokmenascioglu 0:a8fa94490a0a 486 __IO uint32_t I2STXRATE;
gokmenascioglu 0:a8fa94490a0a 487 __IO uint32_t I2SRXRATE;
gokmenascioglu 0:a8fa94490a0a 488 __IO uint32_t I2STXBITRATE;
gokmenascioglu 0:a8fa94490a0a 489 __IO uint32_t I2SRXBITRATE;
gokmenascioglu 0:a8fa94490a0a 490 __IO uint32_t I2STXMODE;
gokmenascioglu 0:a8fa94490a0a 491 __IO uint32_t I2SRXMODE;
gokmenascioglu 0:a8fa94490a0a 492 } LPC_I2S_TypeDef;
gokmenascioglu 0:a8fa94490a0a 493
gokmenascioglu 0:a8fa94490a0a 494 /*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/
gokmenascioglu 0:a8fa94490a0a 495 typedef struct
gokmenascioglu 0:a8fa94490a0a 496 {
gokmenascioglu 0:a8fa94490a0a 497 __IO uint32_t RICOMPVAL;
gokmenascioglu 0:a8fa94490a0a 498 __IO uint32_t RIMASK;
gokmenascioglu 0:a8fa94490a0a 499 __IO uint8_t RICTRL;
gokmenascioglu 0:a8fa94490a0a 500 uint8_t RESERVED0[3];
gokmenascioglu 0:a8fa94490a0a 501 __IO uint32_t RICOUNTER;
gokmenascioglu 0:a8fa94490a0a 502 } LPC_RIT_TypeDef;
gokmenascioglu 0:a8fa94490a0a 503
gokmenascioglu 0:a8fa94490a0a 504 /*------------- Real-Time Clock (RTC) ----------------------------------------*/
gokmenascioglu 0:a8fa94490a0a 505 typedef struct
gokmenascioglu 0:a8fa94490a0a 506 {
gokmenascioglu 0:a8fa94490a0a 507 __IO uint8_t ILR;
gokmenascioglu 0:a8fa94490a0a 508 uint8_t RESERVED0[7];
gokmenascioglu 0:a8fa94490a0a 509 __IO uint8_t CCR;
gokmenascioglu 0:a8fa94490a0a 510 uint8_t RESERVED1[3];
gokmenascioglu 0:a8fa94490a0a 511 __IO uint8_t CIIR;
gokmenascioglu 0:a8fa94490a0a 512 uint8_t RESERVED2[3];
gokmenascioglu 0:a8fa94490a0a 513 __IO uint8_t AMR;
gokmenascioglu 0:a8fa94490a0a 514 uint8_t RESERVED3[3];
gokmenascioglu 0:a8fa94490a0a 515 __I uint32_t CTIME0;
gokmenascioglu 0:a8fa94490a0a 516 __I uint32_t CTIME1;
gokmenascioglu 0:a8fa94490a0a 517 __I uint32_t CTIME2;
gokmenascioglu 0:a8fa94490a0a 518 __IO uint8_t SEC;
gokmenascioglu 0:a8fa94490a0a 519 uint8_t RESERVED4[3];
gokmenascioglu 0:a8fa94490a0a 520 __IO uint8_t MIN;
gokmenascioglu 0:a8fa94490a0a 521 uint8_t RESERVED5[3];
gokmenascioglu 0:a8fa94490a0a 522 __IO uint8_t HOUR;
gokmenascioglu 0:a8fa94490a0a 523 uint8_t RESERVED6[3];
gokmenascioglu 0:a8fa94490a0a 524 __IO uint8_t DOM;
gokmenascioglu 0:a8fa94490a0a 525 uint8_t RESERVED7[3];
gokmenascioglu 0:a8fa94490a0a 526 __IO uint8_t DOW;
gokmenascioglu 0:a8fa94490a0a 527 uint8_t RESERVED8[3];
gokmenascioglu 0:a8fa94490a0a 528 __IO uint16_t DOY;
gokmenascioglu 0:a8fa94490a0a 529 uint16_t RESERVED9;
gokmenascioglu 0:a8fa94490a0a 530 __IO uint8_t MONTH;
gokmenascioglu 0:a8fa94490a0a 531 uint8_t RESERVED10[3];
gokmenascioglu 0:a8fa94490a0a 532 __IO uint16_t YEAR;
gokmenascioglu 0:a8fa94490a0a 533 uint16_t RESERVED11;
gokmenascioglu 0:a8fa94490a0a 534 __IO uint32_t CALIBRATION;
gokmenascioglu 0:a8fa94490a0a 535 __IO uint32_t GPREG0;
gokmenascioglu 0:a8fa94490a0a 536 __IO uint32_t GPREG1;
gokmenascioglu 0:a8fa94490a0a 537 __IO uint32_t GPREG2;
gokmenascioglu 0:a8fa94490a0a 538 __IO uint32_t GPREG3;
gokmenascioglu 0:a8fa94490a0a 539 __IO uint32_t GPREG4;
gokmenascioglu 0:a8fa94490a0a 540 __IO uint8_t RTC_AUXEN;
gokmenascioglu 0:a8fa94490a0a 541 uint8_t RESERVED12[3];
gokmenascioglu 0:a8fa94490a0a 542 __IO uint8_t RTC_AUX;
gokmenascioglu 0:a8fa94490a0a 543 uint8_t RESERVED13[3];
gokmenascioglu 0:a8fa94490a0a 544 __IO uint8_t ALSEC;
gokmenascioglu 0:a8fa94490a0a 545 uint8_t RESERVED14[3];
gokmenascioglu 0:a8fa94490a0a 546 __IO uint8_t ALMIN;
gokmenascioglu 0:a8fa94490a0a 547 uint8_t RESERVED15[3];
gokmenascioglu 0:a8fa94490a0a 548 __IO uint8_t ALHOUR;
gokmenascioglu 0:a8fa94490a0a 549 uint8_t RESERVED16[3];
gokmenascioglu 0:a8fa94490a0a 550 __IO uint8_t ALDOM;
gokmenascioglu 0:a8fa94490a0a 551 uint8_t RESERVED17[3];
gokmenascioglu 0:a8fa94490a0a 552 __IO uint8_t ALDOW;
gokmenascioglu 0:a8fa94490a0a 553 uint8_t RESERVED18[3];
gokmenascioglu 0:a8fa94490a0a 554 __IO uint16_t ALDOY;
gokmenascioglu 0:a8fa94490a0a 555 uint16_t RESERVED19;
gokmenascioglu 0:a8fa94490a0a 556 __IO uint8_t ALMON;
gokmenascioglu 0:a8fa94490a0a 557 uint8_t RESERVED20[3];
gokmenascioglu 0:a8fa94490a0a 558 __IO uint16_t ALYEAR;
gokmenascioglu 0:a8fa94490a0a 559 uint16_t RESERVED21;
gokmenascioglu 0:a8fa94490a0a 560 } LPC_RTC_TypeDef;
gokmenascioglu 0:a8fa94490a0a 561
gokmenascioglu 0:a8fa94490a0a 562 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
gokmenascioglu 0:a8fa94490a0a 563 typedef struct
gokmenascioglu 0:a8fa94490a0a 564 {
gokmenascioglu 0:a8fa94490a0a 565 __IO uint8_t WDMOD;
gokmenascioglu 0:a8fa94490a0a 566 uint8_t RESERVED0[3];
gokmenascioglu 0:a8fa94490a0a 567 __IO uint32_t WDTC;
gokmenascioglu 0:a8fa94490a0a 568 __O uint8_t WDFEED;
gokmenascioglu 0:a8fa94490a0a 569 uint8_t RESERVED1[3];
gokmenascioglu 0:a8fa94490a0a 570 __I uint32_t WDTV;
gokmenascioglu 0:a8fa94490a0a 571 __IO uint32_t WDCLKSEL;
gokmenascioglu 0:a8fa94490a0a 572 } LPC_WDT_TypeDef;
gokmenascioglu 0:a8fa94490a0a 573
gokmenascioglu 0:a8fa94490a0a 574 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
gokmenascioglu 0:a8fa94490a0a 575 typedef struct
gokmenascioglu 0:a8fa94490a0a 576 {
gokmenascioglu 0:a8fa94490a0a 577 __IO uint32_t ADCR;
gokmenascioglu 0:a8fa94490a0a 578 __IO uint32_t ADGDR;
gokmenascioglu 0:a8fa94490a0a 579 uint32_t RESERVED0;
gokmenascioglu 0:a8fa94490a0a 580 __IO uint32_t ADINTEN;
gokmenascioglu 0:a8fa94490a0a 581 __I uint32_t ADDR0;
gokmenascioglu 0:a8fa94490a0a 582 __I uint32_t ADDR1;
gokmenascioglu 0:a8fa94490a0a 583 __I uint32_t ADDR2;
gokmenascioglu 0:a8fa94490a0a 584 __I uint32_t ADDR3;
gokmenascioglu 0:a8fa94490a0a 585 __I uint32_t ADDR4;
gokmenascioglu 0:a8fa94490a0a 586 __I uint32_t ADDR5;
gokmenascioglu 0:a8fa94490a0a 587 __I uint32_t ADDR6;
gokmenascioglu 0:a8fa94490a0a 588 __I uint32_t ADDR7;
gokmenascioglu 0:a8fa94490a0a 589 __I uint32_t ADSTAT;
gokmenascioglu 0:a8fa94490a0a 590 __IO uint32_t ADTRM;
gokmenascioglu 0:a8fa94490a0a 591 } LPC_ADC_TypeDef;
gokmenascioglu 0:a8fa94490a0a 592
gokmenascioglu 0:a8fa94490a0a 593 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
gokmenascioglu 0:a8fa94490a0a 594 typedef struct
gokmenascioglu 0:a8fa94490a0a 595 {
gokmenascioglu 0:a8fa94490a0a 596 __IO uint32_t DACR;
gokmenascioglu 0:a8fa94490a0a 597 __IO uint32_t DACCTRL;
gokmenascioglu 0:a8fa94490a0a 598 __IO uint16_t DACCNTVAL;
gokmenascioglu 0:a8fa94490a0a 599 } LPC_DAC_TypeDef;
gokmenascioglu 0:a8fa94490a0a 600
gokmenascioglu 0:a8fa94490a0a 601 /*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
gokmenascioglu 0:a8fa94490a0a 602 typedef struct
gokmenascioglu 0:a8fa94490a0a 603 {
gokmenascioglu 0:a8fa94490a0a 604 __I uint32_t MCCON;
gokmenascioglu 0:a8fa94490a0a 605 __O uint32_t MCCON_SET;
gokmenascioglu 0:a8fa94490a0a 606 __O uint32_t MCCON_CLR;
gokmenascioglu 0:a8fa94490a0a 607 __I uint32_t MCCAPCON;
gokmenascioglu 0:a8fa94490a0a 608 __O uint32_t MCCAPCON_SET;
gokmenascioglu 0:a8fa94490a0a 609 __O uint32_t MCCAPCON_CLR;
gokmenascioglu 0:a8fa94490a0a 610 __IO uint32_t MCTIM0;
gokmenascioglu 0:a8fa94490a0a 611 __IO uint32_t MCTIM1;
gokmenascioglu 0:a8fa94490a0a 612 __IO uint32_t MCTIM2;
gokmenascioglu 0:a8fa94490a0a 613 __IO uint32_t MCPER0;
gokmenascioglu 0:a8fa94490a0a 614 __IO uint32_t MCPER1;
gokmenascioglu 0:a8fa94490a0a 615 __IO uint32_t MCPER2;
gokmenascioglu 0:a8fa94490a0a 616 __IO uint32_t MCPW0;
gokmenascioglu 0:a8fa94490a0a 617 __IO uint32_t MCPW1;
gokmenascioglu 0:a8fa94490a0a 618 __IO uint32_t MCPW2;
gokmenascioglu 0:a8fa94490a0a 619 __IO uint32_t MCDEADTIME;
gokmenascioglu 0:a8fa94490a0a 620 __IO uint32_t MCCCP;
gokmenascioglu 0:a8fa94490a0a 621 __IO uint32_t MCCR0;
gokmenascioglu 0:a8fa94490a0a 622 __IO uint32_t MCCR1;
gokmenascioglu 0:a8fa94490a0a 623 __IO uint32_t MCCR2;
gokmenascioglu 0:a8fa94490a0a 624 __I uint32_t MCINTEN;
gokmenascioglu 0:a8fa94490a0a 625 __O uint32_t MCINTEN_SET;
gokmenascioglu 0:a8fa94490a0a 626 __O uint32_t MCINTEN_CLR;
gokmenascioglu 0:a8fa94490a0a 627 __I uint32_t MCCNTCON;
gokmenascioglu 0:a8fa94490a0a 628 __O uint32_t MCCNTCON_SET;
gokmenascioglu 0:a8fa94490a0a 629 __O uint32_t MCCNTCON_CLR;
gokmenascioglu 0:a8fa94490a0a 630 __I uint32_t MCINTFLAG;
gokmenascioglu 0:a8fa94490a0a 631 __O uint32_t MCINTFLAG_SET;
gokmenascioglu 0:a8fa94490a0a 632 __O uint32_t MCINTFLAG_CLR;
gokmenascioglu 0:a8fa94490a0a 633 __O uint32_t MCCAP_CLR;
gokmenascioglu 0:a8fa94490a0a 634 } LPC_MCPWM_TypeDef;
gokmenascioglu 0:a8fa94490a0a 635
gokmenascioglu 0:a8fa94490a0a 636 /*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
gokmenascioglu 0:a8fa94490a0a 637 typedef struct
gokmenascioglu 0:a8fa94490a0a 638 {
gokmenascioglu 0:a8fa94490a0a 639 __O uint32_t QEICON;
gokmenascioglu 0:a8fa94490a0a 640 __I uint32_t QEISTAT;
gokmenascioglu 0:a8fa94490a0a 641 __IO uint32_t QEICONF;
gokmenascioglu 0:a8fa94490a0a 642 __I uint32_t QEIPOS;
gokmenascioglu 0:a8fa94490a0a 643 __IO uint32_t QEIMAXPOS;
gokmenascioglu 0:a8fa94490a0a 644 __IO uint32_t CMPOS0;
gokmenascioglu 0:a8fa94490a0a 645 __IO uint32_t CMPOS1;
gokmenascioglu 0:a8fa94490a0a 646 __IO uint32_t CMPOS2;
gokmenascioglu 0:a8fa94490a0a 647 __I uint32_t INXCNT;
gokmenascioglu 0:a8fa94490a0a 648 __IO uint32_t INXCMP;
gokmenascioglu 0:a8fa94490a0a 649 __IO uint32_t QEILOAD;
gokmenascioglu 0:a8fa94490a0a 650 __I uint32_t QEITIME;
gokmenascioglu 0:a8fa94490a0a 651 __I uint32_t QEIVEL;
gokmenascioglu 0:a8fa94490a0a 652 __I uint32_t QEICAP;
gokmenascioglu 0:a8fa94490a0a 653 __IO uint32_t VELCOMP;
gokmenascioglu 0:a8fa94490a0a 654 __IO uint32_t FILTER;
gokmenascioglu 0:a8fa94490a0a 655 uint32_t RESERVED0[998];
gokmenascioglu 0:a8fa94490a0a 656 __O uint32_t QEIIEC;
gokmenascioglu 0:a8fa94490a0a 657 __O uint32_t QEIIES;
gokmenascioglu 0:a8fa94490a0a 658 __I uint32_t QEIINTSTAT;
gokmenascioglu 0:a8fa94490a0a 659 __I uint32_t QEIIE;
gokmenascioglu 0:a8fa94490a0a 660 __O uint32_t QEICLR;
gokmenascioglu 0:a8fa94490a0a 661 __O uint32_t QEISET;
gokmenascioglu 0:a8fa94490a0a 662 } LPC_QEI_TypeDef;
gokmenascioglu 0:a8fa94490a0a 663
gokmenascioglu 0:a8fa94490a0a 664 /*------------- Controller Area Network (CAN) --------------------------------*/
gokmenascioglu 0:a8fa94490a0a 665 typedef struct
gokmenascioglu 0:a8fa94490a0a 666 {
gokmenascioglu 0:a8fa94490a0a 667 __IO uint32_t mask[512]; /* ID Masks */
gokmenascioglu 0:a8fa94490a0a 668 } LPC_CANAF_RAM_TypeDef;
gokmenascioglu 0:a8fa94490a0a 669
gokmenascioglu 0:a8fa94490a0a 670 typedef struct /* Acceptance Filter Registers */
gokmenascioglu 0:a8fa94490a0a 671 {
gokmenascioglu 0:a8fa94490a0a 672 __IO uint32_t AFMR;
gokmenascioglu 0:a8fa94490a0a 673 __IO uint32_t SFF_sa;
gokmenascioglu 0:a8fa94490a0a 674 __IO uint32_t SFF_GRP_sa;
gokmenascioglu 0:a8fa94490a0a 675 __IO uint32_t EFF_sa;
gokmenascioglu 0:a8fa94490a0a 676 __IO uint32_t EFF_GRP_sa;
gokmenascioglu 0:a8fa94490a0a 677 __IO uint32_t ENDofTable;
gokmenascioglu 0:a8fa94490a0a 678 __I uint32_t LUTerrAd;
gokmenascioglu 0:a8fa94490a0a 679 __I uint32_t LUTerr;
gokmenascioglu 0:a8fa94490a0a 680 __IO uint32_t FCANIE;
gokmenascioglu 0:a8fa94490a0a 681 __IO uint32_t FCANIC0;
gokmenascioglu 0:a8fa94490a0a 682 __IO uint32_t FCANIC1;
gokmenascioglu 0:a8fa94490a0a 683 } LPC_CANAF_TypeDef;
gokmenascioglu 0:a8fa94490a0a 684
gokmenascioglu 0:a8fa94490a0a 685 typedef struct /* Central Registers */
gokmenascioglu 0:a8fa94490a0a 686 {
gokmenascioglu 0:a8fa94490a0a 687 __I uint32_t CANTxSR;
gokmenascioglu 0:a8fa94490a0a 688 __I uint32_t CANRxSR;
gokmenascioglu 0:a8fa94490a0a 689 __I uint32_t CANMSR;
gokmenascioglu 0:a8fa94490a0a 690 } LPC_CANCR_TypeDef;
gokmenascioglu 0:a8fa94490a0a 691
gokmenascioglu 0:a8fa94490a0a 692 typedef struct /* Controller Registers */
gokmenascioglu 0:a8fa94490a0a 693 {
gokmenascioglu 0:a8fa94490a0a 694 __IO uint32_t MOD;
gokmenascioglu 0:a8fa94490a0a 695 __O uint32_t CMR;
gokmenascioglu 0:a8fa94490a0a 696 __IO uint32_t GSR;
gokmenascioglu 0:a8fa94490a0a 697 __I uint32_t ICR;
gokmenascioglu 0:a8fa94490a0a 698 __IO uint32_t IER;
gokmenascioglu 0:a8fa94490a0a 699 __IO uint32_t BTR;
gokmenascioglu 0:a8fa94490a0a 700 __IO uint32_t EWL;
gokmenascioglu 0:a8fa94490a0a 701 __I uint32_t SR;
gokmenascioglu 0:a8fa94490a0a 702 __IO uint32_t RFS;
gokmenascioglu 0:a8fa94490a0a 703 __IO uint32_t RID;
gokmenascioglu 0:a8fa94490a0a 704 __IO uint32_t RDA;
gokmenascioglu 0:a8fa94490a0a 705 __IO uint32_t RDB;
gokmenascioglu 0:a8fa94490a0a 706 __IO uint32_t TFI1;
gokmenascioglu 0:a8fa94490a0a 707 __IO uint32_t TID1;
gokmenascioglu 0:a8fa94490a0a 708 __IO uint32_t TDA1;
gokmenascioglu 0:a8fa94490a0a 709 __IO uint32_t TDB1;
gokmenascioglu 0:a8fa94490a0a 710 __IO uint32_t TFI2;
gokmenascioglu 0:a8fa94490a0a 711 __IO uint32_t TID2;
gokmenascioglu 0:a8fa94490a0a 712 __IO uint32_t TDA2;
gokmenascioglu 0:a8fa94490a0a 713 __IO uint32_t TDB2;
gokmenascioglu 0:a8fa94490a0a 714 __IO uint32_t TFI3;
gokmenascioglu 0:a8fa94490a0a 715 __IO uint32_t TID3;
gokmenascioglu 0:a8fa94490a0a 716 __IO uint32_t TDA3;
gokmenascioglu 0:a8fa94490a0a 717 __IO uint32_t TDB3;
gokmenascioglu 0:a8fa94490a0a 718 } LPC_CAN_TypeDef;
gokmenascioglu 0:a8fa94490a0a 719
gokmenascioglu 0:a8fa94490a0a 720 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
gokmenascioglu 0:a8fa94490a0a 721 typedef struct /* Common Registers */
gokmenascioglu 0:a8fa94490a0a 722 {
gokmenascioglu 0:a8fa94490a0a 723 __I uint32_t DMACIntStat;
gokmenascioglu 0:a8fa94490a0a 724 __I uint32_t DMACIntTCStat;
gokmenascioglu 0:a8fa94490a0a 725 __O uint32_t DMACIntTCClear;
gokmenascioglu 0:a8fa94490a0a 726 __I uint32_t DMACIntErrStat;
gokmenascioglu 0:a8fa94490a0a 727 __O uint32_t DMACIntErrClr;
gokmenascioglu 0:a8fa94490a0a 728 __I uint32_t DMACRawIntTCStat;
gokmenascioglu 0:a8fa94490a0a 729 __I uint32_t DMACRawIntErrStat;
gokmenascioglu 0:a8fa94490a0a 730 __I uint32_t DMACEnbldChns;
gokmenascioglu 0:a8fa94490a0a 731 __IO uint32_t DMACSoftBReq;
gokmenascioglu 0:a8fa94490a0a 732 __IO uint32_t DMACSoftSReq;
gokmenascioglu 0:a8fa94490a0a 733 __IO uint32_t DMACSoftLBReq;
gokmenascioglu 0:a8fa94490a0a 734 __IO uint32_t DMACSoftLSReq;
gokmenascioglu 0:a8fa94490a0a 735 __IO uint32_t DMACConfig;
gokmenascioglu 0:a8fa94490a0a 736 __IO uint32_t DMACSync;
gokmenascioglu 0:a8fa94490a0a 737 } LPC_GPDMA_TypeDef;
gokmenascioglu 0:a8fa94490a0a 738
gokmenascioglu 0:a8fa94490a0a 739 typedef struct /* Channel Registers */
gokmenascioglu 0:a8fa94490a0a 740 {
gokmenascioglu 0:a8fa94490a0a 741 __IO uint32_t DMACCSrcAddr;
gokmenascioglu 0:a8fa94490a0a 742 __IO uint32_t DMACCDestAddr;
gokmenascioglu 0:a8fa94490a0a 743 __IO uint32_t DMACCLLI;
gokmenascioglu 0:a8fa94490a0a 744 __IO uint32_t DMACCControl;
gokmenascioglu 0:a8fa94490a0a 745 __IO uint32_t DMACCConfig;
gokmenascioglu 0:a8fa94490a0a 746 } LPC_GPDMACH_TypeDef;
gokmenascioglu 0:a8fa94490a0a 747
gokmenascioglu 0:a8fa94490a0a 748 /*------------- Universal Serial Bus (USB) -----------------------------------*/
gokmenascioglu 0:a8fa94490a0a 749 typedef struct
gokmenascioglu 0:a8fa94490a0a 750 {
gokmenascioglu 0:a8fa94490a0a 751 __I uint32_t HcRevision; /* USB Host Registers */
gokmenascioglu 0:a8fa94490a0a 752 __IO uint32_t HcControl;
gokmenascioglu 0:a8fa94490a0a 753 __IO uint32_t HcCommandStatus;
gokmenascioglu 0:a8fa94490a0a 754 __IO uint32_t HcInterruptStatus;
gokmenascioglu 0:a8fa94490a0a 755 __IO uint32_t HcInterruptEnable;
gokmenascioglu 0:a8fa94490a0a 756 __IO uint32_t HcInterruptDisable;
gokmenascioglu 0:a8fa94490a0a 757 __IO uint32_t HcHCCA;
gokmenascioglu 0:a8fa94490a0a 758 __I uint32_t HcPeriodCurrentED;
gokmenascioglu 0:a8fa94490a0a 759 __IO uint32_t HcControlHeadED;
gokmenascioglu 0:a8fa94490a0a 760 __IO uint32_t HcControlCurrentED;
gokmenascioglu 0:a8fa94490a0a 761 __IO uint32_t HcBulkHeadED;
gokmenascioglu 0:a8fa94490a0a 762 __IO uint32_t HcBulkCurrentED;
gokmenascioglu 0:a8fa94490a0a 763 __I uint32_t HcDoneHead;
gokmenascioglu 0:a8fa94490a0a 764 __IO uint32_t HcFmInterval;
gokmenascioglu 0:a8fa94490a0a 765 __I uint32_t HcFmRemaining;
gokmenascioglu 0:a8fa94490a0a 766 __I uint32_t HcFmNumber;
gokmenascioglu 0:a8fa94490a0a 767 __IO uint32_t HcPeriodicStart;
gokmenascioglu 0:a8fa94490a0a 768 __IO uint32_t HcLSTreshold;
gokmenascioglu 0:a8fa94490a0a 769 __IO uint32_t HcRhDescriptorA;
gokmenascioglu 0:a8fa94490a0a 770 __IO uint32_t HcRhDescriptorB;
gokmenascioglu 0:a8fa94490a0a 771 __IO uint32_t HcRhStatus;
gokmenascioglu 0:a8fa94490a0a 772 __IO uint32_t HcRhPortStatus1;
gokmenascioglu 0:a8fa94490a0a 773 __IO uint32_t HcRhPortStatus2;
gokmenascioglu 0:a8fa94490a0a 774 uint32_t RESERVED0[40];
gokmenascioglu 0:a8fa94490a0a 775 __I uint32_t Module_ID;
gokmenascioglu 0:a8fa94490a0a 776
gokmenascioglu 0:a8fa94490a0a 777 __I uint32_t OTGIntSt; /* USB On-The-Go Registers */
gokmenascioglu 0:a8fa94490a0a 778 __IO uint32_t OTGIntEn;
gokmenascioglu 0:a8fa94490a0a 779 __O uint32_t OTGIntSet;
gokmenascioglu 0:a8fa94490a0a 780 __O uint32_t OTGIntClr;
gokmenascioglu 0:a8fa94490a0a 781 __IO uint32_t OTGStCtrl;
gokmenascioglu 0:a8fa94490a0a 782 __IO uint32_t OTGTmr;
gokmenascioglu 0:a8fa94490a0a 783 uint32_t RESERVED1[58];
gokmenascioglu 0:a8fa94490a0a 784
gokmenascioglu 0:a8fa94490a0a 785 __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
gokmenascioglu 0:a8fa94490a0a 786 __IO uint32_t USBDevIntEn;
gokmenascioglu 0:a8fa94490a0a 787 __O uint32_t USBDevIntClr;
gokmenascioglu 0:a8fa94490a0a 788 __O uint32_t USBDevIntSet;
gokmenascioglu 0:a8fa94490a0a 789
gokmenascioglu 0:a8fa94490a0a 790 __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
gokmenascioglu 0:a8fa94490a0a 791 __I uint32_t USBCmdData;
gokmenascioglu 0:a8fa94490a0a 792
gokmenascioglu 0:a8fa94490a0a 793 __I uint32_t USBRxData; /* USB Device Transfer Registers */
gokmenascioglu 0:a8fa94490a0a 794 __O uint32_t USBTxData;
gokmenascioglu 0:a8fa94490a0a 795 __I uint32_t USBRxPLen;
gokmenascioglu 0:a8fa94490a0a 796 __O uint32_t USBTxPLen;
gokmenascioglu 0:a8fa94490a0a 797 __IO uint32_t USBCtrl;
gokmenascioglu 0:a8fa94490a0a 798 __O uint32_t USBDevIntPri;
gokmenascioglu 0:a8fa94490a0a 799
gokmenascioglu 0:a8fa94490a0a 800 __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
gokmenascioglu 0:a8fa94490a0a 801 __IO uint32_t USBEpIntEn;
gokmenascioglu 0:a8fa94490a0a 802 __O uint32_t USBEpIntClr;
gokmenascioglu 0:a8fa94490a0a 803 __O uint32_t USBEpIntSet;
gokmenascioglu 0:a8fa94490a0a 804 __O uint32_t USBEpIntPri;
gokmenascioglu 0:a8fa94490a0a 805
gokmenascioglu 0:a8fa94490a0a 806 __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
gokmenascioglu 0:a8fa94490a0a 807 __O uint32_t USBEpInd;
gokmenascioglu 0:a8fa94490a0a 808 __IO uint32_t USBMaxPSize;
gokmenascioglu 0:a8fa94490a0a 809
gokmenascioglu 0:a8fa94490a0a 810 __I uint32_t USBDMARSt; /* USB Device DMA Registers */
gokmenascioglu 0:a8fa94490a0a 811 __O uint32_t USBDMARClr;
gokmenascioglu 0:a8fa94490a0a 812 __O uint32_t USBDMARSet;
gokmenascioglu 0:a8fa94490a0a 813 uint32_t RESERVED2[9];
gokmenascioglu 0:a8fa94490a0a 814 __IO uint32_t USBUDCAH;
gokmenascioglu 0:a8fa94490a0a 815 __I uint32_t USBEpDMASt;
gokmenascioglu 0:a8fa94490a0a 816 __O uint32_t USBEpDMAEn;
gokmenascioglu 0:a8fa94490a0a 817 __O uint32_t USBEpDMADis;
gokmenascioglu 0:a8fa94490a0a 818 __I uint32_t USBDMAIntSt;
gokmenascioglu 0:a8fa94490a0a 819 __IO uint32_t USBDMAIntEn;
gokmenascioglu 0:a8fa94490a0a 820 uint32_t RESERVED3[2];
gokmenascioglu 0:a8fa94490a0a 821 __I uint32_t USBEoTIntSt;
gokmenascioglu 0:a8fa94490a0a 822 __O uint32_t USBEoTIntClr;
gokmenascioglu 0:a8fa94490a0a 823 __O uint32_t USBEoTIntSet;
gokmenascioglu 0:a8fa94490a0a 824 __I uint32_t USBNDDRIntSt;
gokmenascioglu 0:a8fa94490a0a 825 __O uint32_t USBNDDRIntClr;
gokmenascioglu 0:a8fa94490a0a 826 __O uint32_t USBNDDRIntSet;
gokmenascioglu 0:a8fa94490a0a 827 __I uint32_t USBSysErrIntSt;
gokmenascioglu 0:a8fa94490a0a 828 __O uint32_t USBSysErrIntClr;
gokmenascioglu 0:a8fa94490a0a 829 __O uint32_t USBSysErrIntSet;
gokmenascioglu 0:a8fa94490a0a 830 uint32_t RESERVED4[15];
gokmenascioglu 0:a8fa94490a0a 831
gokmenascioglu 0:a8fa94490a0a 832 union {
gokmenascioglu 0:a8fa94490a0a 833 __I uint32_t I2C_RX; /* USB OTG I2C Registers */
gokmenascioglu 0:a8fa94490a0a 834 __O uint32_t I2C_TX;
gokmenascioglu 0:a8fa94490a0a 835 };
gokmenascioglu 0:a8fa94490a0a 836 __I uint32_t I2C_STS;
gokmenascioglu 0:a8fa94490a0a 837 __IO uint32_t I2C_CTL;
gokmenascioglu 0:a8fa94490a0a 838 __IO uint32_t I2C_CLKHI;
gokmenascioglu 0:a8fa94490a0a 839 __O uint32_t I2C_CLKLO;
gokmenascioglu 0:a8fa94490a0a 840 uint32_t RESERVED5[824];
gokmenascioglu 0:a8fa94490a0a 841
gokmenascioglu 0:a8fa94490a0a 842 union {
gokmenascioglu 0:a8fa94490a0a 843 __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
gokmenascioglu 0:a8fa94490a0a 844 __IO uint32_t OTGClkCtrl;
gokmenascioglu 0:a8fa94490a0a 845 };
gokmenascioglu 0:a8fa94490a0a 846 union {
gokmenascioglu 0:a8fa94490a0a 847 __I uint32_t USBClkSt;
gokmenascioglu 0:a8fa94490a0a 848 __I uint32_t OTGClkSt;
gokmenascioglu 0:a8fa94490a0a 849 };
gokmenascioglu 0:a8fa94490a0a 850 } LPC_USB_TypeDef;
gokmenascioglu 0:a8fa94490a0a 851
gokmenascioglu 0:a8fa94490a0a 852 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
gokmenascioglu 0:a8fa94490a0a 853 typedef struct
gokmenascioglu 0:a8fa94490a0a 854 {
gokmenascioglu 0:a8fa94490a0a 855 __IO uint32_t MAC1; /* MAC Registers */
gokmenascioglu 0:a8fa94490a0a 856 __IO uint32_t MAC2;
gokmenascioglu 0:a8fa94490a0a 857 __IO uint32_t IPGT;
gokmenascioglu 0:a8fa94490a0a 858 __IO uint32_t IPGR;
gokmenascioglu 0:a8fa94490a0a 859 __IO uint32_t CLRT;
gokmenascioglu 0:a8fa94490a0a 860 __IO uint32_t MAXF;
gokmenascioglu 0:a8fa94490a0a 861 __IO uint32_t SUPP;
gokmenascioglu 0:a8fa94490a0a 862 __IO uint32_t TEST;
gokmenascioglu 0:a8fa94490a0a 863 __IO uint32_t MCFG;
gokmenascioglu 0:a8fa94490a0a 864 __IO uint32_t MCMD;
gokmenascioglu 0:a8fa94490a0a 865 __IO uint32_t MADR;
gokmenascioglu 0:a8fa94490a0a 866 __O uint32_t MWTD;
gokmenascioglu 0:a8fa94490a0a 867 __I uint32_t MRDD;
gokmenascioglu 0:a8fa94490a0a 868 __I uint32_t MIND;
gokmenascioglu 0:a8fa94490a0a 869 uint32_t RESERVED0[2];
gokmenascioglu 0:a8fa94490a0a 870 __IO uint32_t SA0;
gokmenascioglu 0:a8fa94490a0a 871 __IO uint32_t SA1;
gokmenascioglu 0:a8fa94490a0a 872 __IO uint32_t SA2;
gokmenascioglu 0:a8fa94490a0a 873 uint32_t RESERVED1[45];
gokmenascioglu 0:a8fa94490a0a 874 __IO uint32_t Command; /* Control Registers */
gokmenascioglu 0:a8fa94490a0a 875 __I uint32_t Status;
gokmenascioglu 0:a8fa94490a0a 876 __IO uint32_t RxDescriptor;
gokmenascioglu 0:a8fa94490a0a 877 __IO uint32_t RxStatus;
gokmenascioglu 0:a8fa94490a0a 878 __IO uint32_t RxDescriptorNumber;
gokmenascioglu 0:a8fa94490a0a 879 __I uint32_t RxProduceIndex;
gokmenascioglu 0:a8fa94490a0a 880 __IO uint32_t RxConsumeIndex;
gokmenascioglu 0:a8fa94490a0a 881 __IO uint32_t TxDescriptor;
gokmenascioglu 0:a8fa94490a0a 882 __IO uint32_t TxStatus;
gokmenascioglu 0:a8fa94490a0a 883 __IO uint32_t TxDescriptorNumber;
gokmenascioglu 0:a8fa94490a0a 884 __IO uint32_t TxProduceIndex;
gokmenascioglu 0:a8fa94490a0a 885 __I uint32_t TxConsumeIndex;
gokmenascioglu 0:a8fa94490a0a 886 uint32_t RESERVED2[10];
gokmenascioglu 0:a8fa94490a0a 887 __I uint32_t TSV0;
gokmenascioglu 0:a8fa94490a0a 888 __I uint32_t TSV1;
gokmenascioglu 0:a8fa94490a0a 889 __I uint32_t RSV;
gokmenascioglu 0:a8fa94490a0a 890 uint32_t RESERVED3[3];
gokmenascioglu 0:a8fa94490a0a 891 __IO uint32_t FlowControlCounter;
gokmenascioglu 0:a8fa94490a0a 892 __I uint32_t FlowControlStatus;
gokmenascioglu 0:a8fa94490a0a 893 uint32_t RESERVED4[34];
gokmenascioglu 0:a8fa94490a0a 894 __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
gokmenascioglu 0:a8fa94490a0a 895 __IO uint32_t RxFilterWoLStatus;
gokmenascioglu 0:a8fa94490a0a 896 __IO uint32_t RxFilterWoLClear;
gokmenascioglu 0:a8fa94490a0a 897 uint32_t RESERVED5;
gokmenascioglu 0:a8fa94490a0a 898 __IO uint32_t HashFilterL;
gokmenascioglu 0:a8fa94490a0a 899 __IO uint32_t HashFilterH;
gokmenascioglu 0:a8fa94490a0a 900 uint32_t RESERVED6[882];
gokmenascioglu 0:a8fa94490a0a 901 __I uint32_t IntStatus; /* Module Control Registers */
gokmenascioglu 0:a8fa94490a0a 902 __IO uint32_t IntEnable;
gokmenascioglu 0:a8fa94490a0a 903 __O uint32_t IntClear;
gokmenascioglu 0:a8fa94490a0a 904 __O uint32_t IntSet;
gokmenascioglu 0:a8fa94490a0a 905 uint32_t RESERVED7;
gokmenascioglu 0:a8fa94490a0a 906 __IO uint32_t PowerDown;
gokmenascioglu 0:a8fa94490a0a 907 uint32_t RESERVED8;
gokmenascioglu 0:a8fa94490a0a 908 __IO uint32_t Module_ID;
gokmenascioglu 0:a8fa94490a0a 909 } LPC_EMAC_TypeDef;
gokmenascioglu 0:a8fa94490a0a 910
gokmenascioglu 0:a8fa94490a0a 911 #if defined ( __CC_ARM )
gokmenascioglu 0:a8fa94490a0a 912 #pragma no_anon_unions
gokmenascioglu 0:a8fa94490a0a 913 #endif
gokmenascioglu 0:a8fa94490a0a 914
gokmenascioglu 0:a8fa94490a0a 915
gokmenascioglu 0:a8fa94490a0a 916 /******************************************************************************/
gokmenascioglu 0:a8fa94490a0a 917 /* Peripheral memory map */
gokmenascioglu 0:a8fa94490a0a 918 /******************************************************************************/
gokmenascioglu 0:a8fa94490a0a 919 /* Base addresses */
gokmenascioglu 0:a8fa94490a0a 920 #define LPC_FLASH_BASE (0x00000000UL)
gokmenascioglu 0:a8fa94490a0a 921 #define LPC_RAM_BASE (0x10000000UL)
gokmenascioglu 0:a8fa94490a0a 922 #define LPC_GPIO_BASE (0x2009C000UL)
gokmenascioglu 0:a8fa94490a0a 923 #define LPC_APB0_BASE (0x40000000UL)
gokmenascioglu 0:a8fa94490a0a 924 #define LPC_APB1_BASE (0x40080000UL)
gokmenascioglu 0:a8fa94490a0a 925 #define LPC_AHB_BASE (0x50000000UL)
gokmenascioglu 0:a8fa94490a0a 926 #define LPC_CM3_BASE (0xE0000000UL)
gokmenascioglu 0:a8fa94490a0a 927
gokmenascioglu 0:a8fa94490a0a 928 /* APB0 peripherals */
gokmenascioglu 0:a8fa94490a0a 929 #define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)
gokmenascioglu 0:a8fa94490a0a 930 #define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)
gokmenascioglu 0:a8fa94490a0a 931 #define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)
gokmenascioglu 0:a8fa94490a0a 932 #define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)
gokmenascioglu 0:a8fa94490a0a 933 #define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)
gokmenascioglu 0:a8fa94490a0a 934 #define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)
gokmenascioglu 0:a8fa94490a0a 935 #define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)
gokmenascioglu 0:a8fa94490a0a 936 #define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000)
gokmenascioglu 0:a8fa94490a0a 937 #define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)
gokmenascioglu 0:a8fa94490a0a 938 #define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)
gokmenascioglu 0:a8fa94490a0a 939 #define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000)
gokmenascioglu 0:a8fa94490a0a 940 #define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)
gokmenascioglu 0:a8fa94490a0a 941 #define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)
gokmenascioglu 0:a8fa94490a0a 942 #define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)
gokmenascioglu 0:a8fa94490a0a 943 #define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)
gokmenascioglu 0:a8fa94490a0a 944 #define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)
gokmenascioglu 0:a8fa94490a0a 945 #define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)
gokmenascioglu 0:a8fa94490a0a 946 #define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)
gokmenascioglu 0:a8fa94490a0a 947 #define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)
gokmenascioglu 0:a8fa94490a0a 948
gokmenascioglu 0:a8fa94490a0a 949 /* APB1 peripherals */
gokmenascioglu 0:a8fa94490a0a 950 #define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)
gokmenascioglu 0:a8fa94490a0a 951 #define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)
gokmenascioglu 0:a8fa94490a0a 952 #define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)
gokmenascioglu 0:a8fa94490a0a 953 #define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)
gokmenascioglu 0:a8fa94490a0a 954 #define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)
gokmenascioglu 0:a8fa94490a0a 955 #define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)
gokmenascioglu 0:a8fa94490a0a 956 #define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)
gokmenascioglu 0:a8fa94490a0a 957 #define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)
gokmenascioglu 0:a8fa94490a0a 958 #define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000)
gokmenascioglu 0:a8fa94490a0a 959 #define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)
gokmenascioglu 0:a8fa94490a0a 960 #define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)
gokmenascioglu 0:a8fa94490a0a 961 #define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)
gokmenascioglu 0:a8fa94490a0a 962
gokmenascioglu 0:a8fa94490a0a 963 /* AHB peripherals */
gokmenascioglu 0:a8fa94490a0a 964 #define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000)
gokmenascioglu 0:a8fa94490a0a 965 #define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000)
gokmenascioglu 0:a8fa94490a0a 966 #define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100)
gokmenascioglu 0:a8fa94490a0a 967 #define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120)
gokmenascioglu 0:a8fa94490a0a 968 #define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140)
gokmenascioglu 0:a8fa94490a0a 969 #define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160)
gokmenascioglu 0:a8fa94490a0a 970 #define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180)
gokmenascioglu 0:a8fa94490a0a 971 #define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0)
gokmenascioglu 0:a8fa94490a0a 972 #define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0)
gokmenascioglu 0:a8fa94490a0a 973 #define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0)
gokmenascioglu 0:a8fa94490a0a 974 #define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)
gokmenascioglu 0:a8fa94490a0a 975
gokmenascioglu 0:a8fa94490a0a 976 /* GPIOs */
gokmenascioglu 0:a8fa94490a0a 977 #define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000)
gokmenascioglu 0:a8fa94490a0a 978 #define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020)
gokmenascioglu 0:a8fa94490a0a 979 #define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040)
gokmenascioglu 0:a8fa94490a0a 980 #define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060)
gokmenascioglu 0:a8fa94490a0a 981 #define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080)
gokmenascioglu 0:a8fa94490a0a 982
gokmenascioglu 0:a8fa94490a0a 983
gokmenascioglu 0:a8fa94490a0a 984 /******************************************************************************/
gokmenascioglu 0:a8fa94490a0a 985 /* Peripheral declaration */
gokmenascioglu 0:a8fa94490a0a 986 /******************************************************************************/
gokmenascioglu 0:a8fa94490a0a 987 #define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
gokmenascioglu 0:a8fa94490a0a 988 #define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
gokmenascioglu 0:a8fa94490a0a 989 #define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
gokmenascioglu 0:a8fa94490a0a 990 #define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
gokmenascioglu 0:a8fa94490a0a 991 #define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
gokmenascioglu 0:a8fa94490a0a 992 #define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
gokmenascioglu 0:a8fa94490a0a 993 #define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
gokmenascioglu 0:a8fa94490a0a 994 #define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
gokmenascioglu 0:a8fa94490a0a 995 #define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
gokmenascioglu 0:a8fa94490a0a 996 #define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
gokmenascioglu 0:a8fa94490a0a 997 #define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
gokmenascioglu 0:a8fa94490a0a 998 #define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE )
gokmenascioglu 0:a8fa94490a0a 999 #define LPC_UART0 ((LPC_UART0_TypeDef *) LPC_UART0_BASE )
gokmenascioglu 0:a8fa94490a0a 1000 #define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
gokmenascioglu 0:a8fa94490a0a 1001 #define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
gokmenascioglu 0:a8fa94490a0a 1002 #define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
gokmenascioglu 0:a8fa94490a0a 1003 #define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
gokmenascioglu 0:a8fa94490a0a 1004 #define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
gokmenascioglu 0:a8fa94490a0a 1005 #define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
gokmenascioglu 0:a8fa94490a0a 1006 #define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
gokmenascioglu 0:a8fa94490a0a 1007 #define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
gokmenascioglu 0:a8fa94490a0a 1008 #define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE )
gokmenascioglu 0:a8fa94490a0a 1009 #define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
gokmenascioglu 0:a8fa94490a0a 1010 #define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
gokmenascioglu 0:a8fa94490a0a 1011 #define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE )
gokmenascioglu 0:a8fa94490a0a 1012 #define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
gokmenascioglu 0:a8fa94490a0a 1013 #define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
gokmenascioglu 0:a8fa94490a0a 1014 #define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
gokmenascioglu 0:a8fa94490a0a 1015 #define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
gokmenascioglu 0:a8fa94490a0a 1016 #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
gokmenascioglu 0:a8fa94490a0a 1017 #define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
gokmenascioglu 0:a8fa94490a0a 1018 #define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
gokmenascioglu 0:a8fa94490a0a 1019 #define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
gokmenascioglu 0:a8fa94490a0a 1020 #define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
gokmenascioglu 0:a8fa94490a0a 1021 #define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
gokmenascioglu 0:a8fa94490a0a 1022 #define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
gokmenascioglu 0:a8fa94490a0a 1023 #define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
gokmenascioglu 0:a8fa94490a0a 1024 #define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
gokmenascioglu 0:a8fa94490a0a 1025 #define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
gokmenascioglu 0:a8fa94490a0a 1026 #define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
gokmenascioglu 0:a8fa94490a0a 1027 #define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
gokmenascioglu 0:a8fa94490a0a 1028 #define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
gokmenascioglu 0:a8fa94490a0a 1029 #define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
gokmenascioglu 0:a8fa94490a0a 1030 #define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
gokmenascioglu 0:a8fa94490a0a 1031 #define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
gokmenascioglu 0:a8fa94490a0a 1032 #define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
gokmenascioglu 0:a8fa94490a0a 1033 #define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
gokmenascioglu 0:a8fa94490a0a 1034
gokmenascioglu 0:a8fa94490a0a 1035 #endif // __LPC17xx_H__