Franco Patane
/
Si5351A_Clock_generator
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Check_Si5351A_Clock_generator
by 
Kenji Arai
main.cpp@6:c99750606e25, 2018-03-27 (annotated)
- Committer:
- it9jru
- Date:
- Tue Mar 27 06:37:32 2018 +0000
- Revision:
- 6:c99750606e25
Clock generator @ 145 MHz and 7 MHz
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| it9jru | 6:c99750606e25 | 1 | #include "mbed.h" |
| it9jru | 6:c99750606e25 | 2 | #include "si5351a.h" |
| it9jru | 6:c99750606e25 | 3 | |
| it9jru | 6:c99750606e25 | 4 | Serial pc(USBTX, USBRX); |
| it9jru | 6:c99750606e25 | 5 | |
| it9jru | 6:c99750606e25 | 6 | I2C i2c(I2C_SDA, I2C_SCL); // communication with Si5351A |
| it9jru | 6:c99750606e25 | 7 | SI5351A clk(i2c, 24998410UL); // Base clock = 25MHz |
| it9jru | 6:c99750606e25 | 8 | |
| it9jru | 6:c99750606e25 | 9 | int main() { |
| it9jru | 6:c99750606e25 | 10 | uint32_t num=145000000; |
| it9jru | 6:c99750606e25 | 11 | |
| it9jru | 6:c99750606e25 | 12 | clk.set_frequency(SI5351_CLK0, 7000000); // CLK0=7MHz |
| it9jru | 6:c99750606e25 | 13 | |
| it9jru | 6:c99750606e25 | 14 | clk.set_frequency(SI5351_CLK1,num); // CLK0=145MHz |
| it9jru | 6:c99750606e25 | 15 | |
| it9jru | 6:c99750606e25 | 16 | while(true) { |
| it9jru | 6:c99750606e25 | 17 | |
| it9jru | 6:c99750606e25 | 18 | //wait(1); |
| it9jru | 6:c99750606e25 | 19 | num = num + 10000; |
| it9jru | 6:c99750606e25 | 20 | |
| it9jru | 6:c99750606e25 | 21 | pc.printf("%d scrivo -\r\n", num); |
| it9jru | 6:c99750606e25 | 22 | |
| it9jru | 6:c99750606e25 | 23 | /* clk.set_frequency(SI5351_CLK1,num); |
| it9jru | 6:c99750606e25 | 24 | if (num>146000000) |
| it9jru | 6:c99750606e25 | 25 | { |
| it9jru | 6:c99750606e25 | 26 | num=145000000; |
| it9jru | 6:c99750606e25 | 27 | }*/ |
| it9jru | 6:c99750606e25 | 28 | } |
| it9jru | 6:c99750606e25 | 29 | } |
| it9jru | 6:c99750606e25 | 30 | |
| it9jru | 6:c99750606e25 | 31 | // --------- CAUTION & RESTRICTION ----------------------------------------- |
| it9jru | 6:c99750606e25 | 32 | // 1) SETTING METHOD |
| it9jru | 6:c99750606e25 | 33 | // 2.6KHz~100MHz: fixed PLL(around 900 or around 600MHz), fractional divider |
| it9jru | 6:c99750606e25 | 34 | // 100~150MHz: fractional PLL 600-900MHz, fixed divider 6 |
| it9jru | 6:c99750606e25 | 35 | // 150~200MHz: fractional PLL 600-900MHz, fixed divider 4 |
| it9jru | 6:c99750606e25 | 36 | // |
| it9jru | 6:c99750606e25 | 37 | // 2) RESOURCE USAGE |
| it9jru | 6:c99750606e25 | 38 | // PLLA -> only for CLK0 (You can change freqency any time to any value.) |
| it9jru | 6:c99750606e25 | 39 | // PLLB -> use for bothe CLK1 & CLK2 |
| it9jru | 6:c99750606e25 | 40 | // If you set a freq. less than 100MHz, |
| it9jru | 6:c99750606e25 | 41 | // You can change both CLK1 & CLK2 independently. |
| it9jru | 6:c99750606e25 | 42 | // Over 100MHz, you may have a trouble becase need to change PLLB freq. |
| it9jru | 6:c99750606e25 | 43 | // |
| it9jru | 6:c99750606e25 | 44 | // 3) DISCONTINUITY |
| it9jru | 6:c99750606e25 | 45 | // If you use multiple output, you will lose output signal when you change |
| it9jru | 6:c99750606e25 | 46 | // the output frequency even not specific CLKn during I2C acccess. |
| it9jru | 6:c99750606e25 | 47 | // -------------------------------------------------------------------------- |
| it9jru | 6:c99750606e25 | 48 |