Igor Skochinsky
NXP's driver library for LPC17xx, ported to mbed's online compiler. Not tested! I had to fix a lot of warings and found a couple of pretty obvious bugs, so the chances are there are more. Original: http://ics.nxp.com/support/documents/microcontrollers/zip/lpc17xx.cmsis.driver.library.zip
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lpc17xx_gpdma.c
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00001 /** 00002 * @file : lpc17xx_gpdma.c 00003 * @brief : Contains all functions support for GPDMA firmware library on LPC17xx 00004 * @version : 1.0 00005 * @date : 20. Apr. 2009 00006 * @author : HieuNguyen 00007 ************************************************************************** 00008 * Software that is described herein is for illustrative purposes only 00009 * which provides customers with programming information regarding the 00010 * products. This software is supplied "AS IS" without any warranties. 00011 * NXP Semiconductors assumes no responsibility or liability for the 00012 * use of the software, conveys no license or title under any patent, 00013 * copyright, or mask work right to the product. NXP Semiconductors 00014 * reserves the right to make changes in the software without 00015 * notification. NXP Semiconductors also make no representation or 00016 * warranty that such application will be suitable for the specified 00017 * use without further testing or modification. 00018 **********************************************************************/ 00019 00020 /* Peripheral group ----------------------------------------------------------- */ 00021 /** @addtogroup GPDMA 00022 * @{ 00023 */ 00024 00025 /* Includes ------------------------------------------------------------------- */ 00026 #include "lpc17xx_gpdma.h" 00027 #include "lpc17xx_clkpwr.h" 00028 00029 /* If this source file built with example, the LPC17xx FW library configuration 00030 * file in each example directory ("lpc17xx_libcfg.h") must be included, 00031 * otherwise the default FW library configuration file must be included instead 00032 */ 00033 #ifdef __BUILD_WITH_EXAMPLE__ 00034 #include "lpc17xx_libcfg.h" 00035 #else 00036 #include "lpc17xx_libcfg_default.h" 00037 #endif /* __BUILD_WITH_EXAMPLE__ */ 00038 00039 #ifdef _GPDMA 00040 00041 00042 /* Private Variables ---------------------------------------------------------- */ 00043 /** @defgroup GPDMA_Private_Variables 00044 * @{ 00045 */ 00046 00047 /** 00048 * @brief Lookup Table of Connection Type matched with 00049 * Peripheral Data (FIFO) register base address 00050 */ 00051 #ifdef __IAR_SYSTEMS_ICC__ 00052 volatile const void *GPDMA_LUTPerAddr[] = { 00053 (&LPC_SSP0->DR), // SSP0 Tx 00054 (&LPC_SSP0->DR), // SSP0 Rx 00055 (&LPC_SSP1->DR), // SSP1 Tx 00056 (&LPC_SSP1->DR), // SSP1 Rx 00057 (&LPC_ADC->ADGDR), // ADC 00058 (&LPC_I2S->I2STXFIFO), // I2S Tx 00059 (&LPC_I2S->I2SRXFIFO), // I2S Rx 00060 (&LPC_DAC->DACR), // DAC 00061 (&LPC_UART0->/*RBTHDLR.*/THR), // UART0 Tx 00062 (&LPC_UART0->/*RBTHDLR.*/RBR), // UART0 Rx 00063 (&LPC_UART1->/*RBTHDLR.*/THR), // UART1 Tx 00064 (&LPC_UART1->/*RBTHDLR.*/RBR), // UART1 Rx 00065 (&LPC_UART2->/*RBTHDLR.*/THR), // UART2 Tx 00066 (&LPC_UART2->/*RBTHDLR.*/RBR), // UART2 Rx 00067 (&LPC_UART3->/*RBTHDLR.*/THR), // UART3 Tx 00068 (&LPC_UART3->/*RBTHDLR.*/RBR), // UART3 Rx 00069 (&LPC_TIM0->MR0), // MAT0.0 00070 (&LPC_TIM0->MR1), // MAT0.1 00071 (&LPC_TIM1->MR0), // MAT1.0 00072 (&LPC_TIM1->MR1), // MAT1.1 00073 (&LPC_TIM2->MR0), // MAT2.0 00074 (&LPC_TIM2->MR1), // MAT2.1 00075 (&LPC_TIM3->MR0), // MAT3.0 00076 (&LPC_TIM3->MR1), // MAT3.1 00077 }; 00078 #else 00079 const uint32_t GPDMA_LUTPerAddr[] = { 00080 ((uint32_t)&LPC_SSP0->DR), // SSP0 Tx 00081 ((uint32_t)&LPC_SSP0->DR), // SSP0 Rx 00082 ((uint32_t)&LPC_SSP1->DR), // SSP1 Tx 00083 ((uint32_t)&LPC_SSP1->DR), // SSP1 Rx 00084 ((uint32_t)&LPC_ADC->ADGDR), // ADC 00085 ((uint32_t)&LPC_I2S->I2STXFIFO), // I2S Tx 00086 ((uint32_t)&LPC_I2S->I2SRXFIFO), // I2S Rx 00087 ((uint32_t)&LPC_DAC->DACR), // DAC 00088 ((uint32_t)&LPC_UART0->/*RBTHDLR.*/THR), // UART0 Tx 00089 ((uint32_t)&LPC_UART0->/*RBTHDLR.*/RBR), // UART0 Rx 00090 ((uint32_t)&LPC_UART1->/*RBTHDLR.*/THR), // UART1 Tx 00091 ((uint32_t)&LPC_UART1->/*RBTHDLR.*/RBR), // UART1 Rx 00092 ((uint32_t)&LPC_UART2->/*RBTHDLR.*/THR), // UART2 Tx 00093 ((uint32_t)&LPC_UART2->/*RBTHDLR.*/RBR), // UART2 Rx 00094 ((uint32_t)&LPC_UART3->/*RBTHDLR.*/THR), // UART3 Tx 00095 ((uint32_t)&LPC_UART3->/*RBTHDLR.*/RBR), // UART3 Rx 00096 ((uint32_t)&LPC_TIM0->MR0), // MAT0.0 00097 ((uint32_t)&LPC_TIM0->MR1), // MAT0.1 00098 ((uint32_t)&LPC_TIM1->MR0), // MAT1.0 00099 ((uint32_t)&LPC_TIM1->MR1), // MAT1.1 00100 ((uint32_t)&LPC_TIM2->MR0), // MAT2.0 00101 ((uint32_t)&LPC_TIM2->MR1), // MAT2.1 00102 ((uint32_t)&LPC_TIM3->MR0), // MAT3.0 00103 ((uint32_t)&LPC_TIM3->MR1), // MAT3.1 00104 }; 00105 #endif 00106 /** 00107 * @brief Lookup Table of GPDMA Channel Number matched with 00108 * GPDMA channel pointer 00109 */ 00110 const LPC_GPDMACH_TypeDef *pGPDMACh[8] = { 00111 LPC_GPDMACH0, // GPDMA Channel 0 00112 LPC_GPDMACH1, // GPDMA Channel 1 00113 LPC_GPDMACH2, // GPDMA Channel 2 00114 LPC_GPDMACH3, // GPDMA Channel 3 00115 LPC_GPDMACH4, // GPDMA Channel 4 00116 LPC_GPDMACH5, // GPDMA Channel 5 00117 LPC_GPDMACH6, // GPDMA Channel 6 00118 LPC_GPDMACH7, // GPDMA Channel 7 00119 }; 00120 /** 00121 * @brief Optimized Peripheral Source and Destination burst size 00122 */ 00123 const uint8_t GPDMA_LUTPerBurst[] = { 00124 GPDMA_BSIZE_4, // SSP0 Tx 00125 GPDMA_BSIZE_4, // SSP0 Rx 00126 GPDMA_BSIZE_4, // SSP1 Tx 00127 GPDMA_BSIZE_4, // SSP1 Rx 00128 GPDMA_BSIZE_4, // ADC 00129 GPDMA_BSIZE_32, // I2S channel 0 00130 GPDMA_BSIZE_32, // I2S channel 1 00131 GPDMA_BSIZE_1, // DAC 00132 GPDMA_BSIZE_1, // UART0 Tx 00133 GPDMA_BSIZE_1, // UART0 Rx 00134 GPDMA_BSIZE_1, // UART1 Tx 00135 GPDMA_BSIZE_1, // UART1 Rx 00136 GPDMA_BSIZE_1, // UART2 Tx 00137 GPDMA_BSIZE_1, // UART2 Rx 00138 GPDMA_BSIZE_1, // UART3 Tx 00139 GPDMA_BSIZE_1, // UART3 Rx 00140 GPDMA_BSIZE_1, // MAT0.0 00141 GPDMA_BSIZE_1, // MAT0.1 00142 GPDMA_BSIZE_1, // MAT1.0 00143 GPDMA_BSIZE_1, // MAT1.1 00144 GPDMA_BSIZE_1, // MAT2.0 00145 GPDMA_BSIZE_1, // MAT2.1 00146 GPDMA_BSIZE_1, // MAT3.0 00147 GPDMA_BSIZE_1, // MAT3.1 00148 }; 00149 /** 00150 * @brief Optimized Peripheral Source and Destination transfer width 00151 */ 00152 const uint8_t GPDMA_LUTPerWid[] = { 00153 GPDMA_WIDTH_BYTE, // SSP0 Tx 00154 GPDMA_WIDTH_BYTE, // SSP0 Rx 00155 GPDMA_WIDTH_BYTE, // SSP1 Tx 00156 GPDMA_WIDTH_BYTE, // SSP1 Rx 00157 GPDMA_WIDTH_WORD, // ADC 00158 GPDMA_WIDTH_WORD, // I2S channel 0 00159 GPDMA_WIDTH_WORD, // I2S channel 1 00160 GPDMA_WIDTH_BYTE, // DAC 00161 GPDMA_WIDTH_BYTE, // UART0 Tx 00162 GPDMA_WIDTH_BYTE, // UART0 Rx 00163 GPDMA_WIDTH_BYTE, // UART1 Tx 00164 GPDMA_WIDTH_BYTE, // UART1 Rx 00165 GPDMA_WIDTH_BYTE, // UART2 Tx 00166 GPDMA_WIDTH_BYTE, // UART2 Rx 00167 GPDMA_WIDTH_BYTE, // UART3 Tx 00168 GPDMA_WIDTH_BYTE, // UART3 Rx 00169 GPDMA_WIDTH_WORD, // MAT0.0 00170 GPDMA_WIDTH_WORD, // MAT0.1 00171 GPDMA_WIDTH_WORD, // MAT1.0 00172 GPDMA_WIDTH_WORD, // MAT1.1 00173 GPDMA_WIDTH_WORD, // MAT2.0 00174 GPDMA_WIDTH_WORD, // MAT2.1 00175 GPDMA_WIDTH_WORD, // MAT3.0 00176 GPDMA_WIDTH_WORD, // MAT3.1 00177 }; 00178 00179 /** Interrupt Call-back function pointer data for each GPDMA channel */ 00180 static fnGPDMACbs_Type *_apfnGPDMACbs[8] = { 00181 NULL, // GPDMA Call-back function pointer for Channel 0 00182 NULL, // GPDMA Call-back function pointer for Channel 1 00183 NULL, // GPDMA Call-back function pointer for Channel 2 00184 NULL, // GPDMA Call-back function pointer for Channel 3 00185 NULL, // GPDMA Call-back function pointer for Channel 4 00186 NULL, // GPDMA Call-back function pointer for Channel 5 00187 NULL, // GPDMA Call-back function pointer for Channel 6 00188 NULL, // GPDMA Call-back function pointer for Channel 7 00189 }; 00190 00191 /** 00192 * @} 00193 */ 00194 00195 /* Public Functions ----------------------------------------------------------- */ 00196 /** @addtogroup GPDMA_Public_Functions 00197 * @{ 00198 */ 00199 00200 /********************************************************************//** 00201 * @brief Initialize GPDMA controller 00202 * @param None 00203 * @return None 00204 *********************************************************************/ 00205 void GPDMA_Init(void) 00206 { 00207 /* Enable GPDMA clock */ 00208 CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCGPDMA, ENABLE); 00209 00210 // Reset all channel configuration register 00211 LPC_GPDMACH0->DMACCConfig = 0; 00212 LPC_GPDMACH1->DMACCConfig = 0; 00213 LPC_GPDMACH2->DMACCConfig = 0; 00214 LPC_GPDMACH3->DMACCConfig = 0; 00215 LPC_GPDMACH4->DMACCConfig = 0; 00216 LPC_GPDMACH5->DMACCConfig = 0; 00217 LPC_GPDMACH6->DMACCConfig = 0; 00218 LPC_GPDMACH7->DMACCConfig = 0; 00219 00220 /* Clear all DMA interrupt and error flag */ 00221 LPC_GPDMA->DMACIntTCClear = 0xFF; 00222 LPC_GPDMA->DMACIntErrClr = 0xFF; 00223 } 00224 00225 /********************************************************************//** 00226 * @brief Setup GPDMA channel peripheral according to the specified 00227 * parameters in the GPDMAChannelConfig. 00228 * @param[in] GPDMAChannelConfig Pointer to a GPDMA_CH_CFG_Type 00229 * structure that contains the configuration 00230 * information for the specified GPDMA channel peripheral. 00231 * @param[in] pfnGPDMACbs Pointer to a GPDMA interrupt call-back function 00232 * @return ERROR if selected channel is enabled before 00233 * or SUCCESS if channel is configured successfully 00234 *********************************************************************/ 00235 Status GPDMA_Setup(GPDMA_Channel_CFG_Type *GPDMAChannelConfig, fnGPDMACbs_Type *pfnGPDMACbs) 00236 { 00237 LPC_GPDMACH_TypeDef *pDMAch; 00238 uint32_t tmp1, tmp2; 00239 00240 if (LPC_GPDMA->DMACEnbldChns & (GPDMA_DMACEnbldChns_Ch(GPDMAChannelConfig->ChannelNum))) { 00241 // This channel is enabled, return ERROR, need to release this channel first 00242 return ERROR; 00243 } 00244 00245 // Get Channel pointer 00246 pDMAch = (LPC_GPDMACH_TypeDef *) pGPDMACh[GPDMAChannelConfig->ChannelNum]; 00247 00248 // Setup call back function for this channel 00249 _apfnGPDMACbs[GPDMAChannelConfig->ChannelNum] = pfnGPDMACbs; 00250 00251 // Reset the Interrupt status 00252 LPC_GPDMA->DMACIntTCClear = GPDMA_DMACIntTCClear_Ch(GPDMAChannelConfig->ChannelNum); 00253 LPC_GPDMA->DMACIntErrClr = GPDMA_DMACIntErrClr_Ch(GPDMAChannelConfig->ChannelNum); 00254 00255 // Clear DMA configure 00256 pDMAch->DMACCControl = 0x00; 00257 pDMAch->DMACCConfig = 0x00; 00258 00259 /* Assign Linker List Item value */ 00260 pDMAch->DMACCLLI = GPDMAChannelConfig->DMALLI; 00261 00262 /* Set value to Channel Control Registers */ 00263 switch (GPDMAChannelConfig->TransferType) 00264 { 00265 // Memory to memory 00266 case GPDMA_TRANSFERTYPE_M2M: 00267 // Assign physical source and destination address 00268 pDMAch->DMACCSrcAddr = GPDMAChannelConfig->SrcMemAddr; 00269 pDMAch->DMACCDestAddr = GPDMAChannelConfig->DstMemAddr; 00270 pDMAch->DMACCControl 00271 = GPDMA_DMACCxControl_TransferSize(GPDMAChannelConfig->TransferSize) \ 00272 | GPDMA_DMACCxControl_SBSize(GPDMA_BSIZE_32) \ 00273 | GPDMA_DMACCxControl_DBSize(GPDMA_BSIZE_32) \ 00274 | GPDMA_DMACCxControl_SWidth(GPDMAChannelConfig->TransferWidth) \ 00275 | GPDMA_DMACCxControl_DWidth(GPDMAChannelConfig->TransferWidth) \ 00276 | GPDMA_DMACCxControl_SI \ 00277 | GPDMA_DMACCxControl_DI \ 00278 | GPDMA_DMACCxControl_I; 00279 break; 00280 // Memory to peripheral 00281 case GPDMA_TRANSFERTYPE_M2P: 00282 // Assign physical source 00283 pDMAch->DMACCSrcAddr = GPDMAChannelConfig->SrcMemAddr; 00284 // Assign peripheral destination address 00285 pDMAch->DMACCDestAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->DstConn]; 00286 pDMAch->DMACCControl 00287 = GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \ 00288 | GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \ 00289 | GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \ 00290 | GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \ 00291 | GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \ 00292 | GPDMA_DMACCxControl_SI \ 00293 | GPDMA_DMACCxControl_I; 00294 break; 00295 // Peripheral to memory 00296 case GPDMA_TRANSFERTYPE_P2M: 00297 // Assign peripheral source address 00298 pDMAch->DMACCSrcAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->SrcConn]; 00299 // Assign memory destination address 00300 pDMAch->DMACCDestAddr = GPDMAChannelConfig->DstMemAddr; 00301 pDMAch->DMACCControl 00302 = GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \ 00303 | GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \ 00304 | GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \ 00305 | GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \ 00306 | GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \ 00307 | GPDMA_DMACCxControl_DI \ 00308 | GPDMA_DMACCxControl_I; 00309 break; 00310 // Peripheral to peripheral 00311 case GPDMA_TRANSFERTYPE_P2P: 00312 // Assign peripheral source address 00313 pDMAch->DMACCSrcAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->SrcConn]; 00314 // Assign peripheral destination address 00315 pDMAch->DMACCDestAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->DstConn]; 00316 pDMAch->DMACCControl 00317 = GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \ 00318 | GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \ 00319 | GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \ 00320 | GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \ 00321 | GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \ 00322 | GPDMA_DMACCxControl_I; 00323 break; 00324 // Do not support any more transfer type, return ERROR 00325 default: 00326 return ERROR; 00327 } 00328 00329 /* Re-Configure DMA Request Select for source peripheral */ 00330 if (GPDMAChannelConfig->SrcConn > 15) 00331 { 00332 LPC_SC->RESERVED9 |= (1<<(GPDMAChannelConfig->SrcConn - 16)); 00333 } else { 00334 LPC_SC->RESERVED9 &= ~(1<<(GPDMAChannelConfig->SrcConn - 8)); 00335 } 00336 00337 /* Re-Configure DMA Request Select for Destination peripheral */ 00338 if (GPDMAChannelConfig->DstConn > 15) 00339 { 00340 LPC_SC->RESERVED9 |= (1<<(GPDMAChannelConfig->DstConn - 16)); 00341 } else { 00342 LPC_SC->RESERVED9 &= ~(1<<(GPDMAChannelConfig->DstConn - 8)); 00343 } 00344 00345 /* Enable DMA channels, little endian */ 00346 LPC_GPDMA->DMACConfig = GPDMA_DMACConfig_E; 00347 while (!(LPC_GPDMA->DMACConfig & GPDMA_DMACConfig_E)); 00348 00349 // Calculate absolute value for Connection number 00350 tmp1 = GPDMAChannelConfig->SrcConn; 00351 tmp1 = ((tmp1 > 15) ? (tmp1 - 8) : tmp1); 00352 tmp2 = GPDMAChannelConfig->DstConn; 00353 tmp2 = ((tmp2 > 15) ? (tmp2 - 8) : tmp2); 00354 00355 // Configure DMA Channel, enable Error Counter and Terminate counter 00356 pDMAch->DMACCConfig = GPDMA_DMACCxConfig_IE | GPDMA_DMACCxConfig_ITC /*| GPDMA_DMACCxConfig_E*/ \ 00357 | GPDMA_DMACCxConfig_TransferType((uint32_t)GPDMAChannelConfig->TransferType) \ 00358 | GPDMA_DMACCxConfig_SrcPeripheral(tmp1) \ 00359 | GPDMA_DMACCxConfig_DestPeripheral(tmp2); 00360 00361 return SUCCESS; 00362 } 00363 00364 00365 /*********************************************************************//** 00366 * @brief Enable/Disable DMA channel 00367 * @param[in] channelNum GPDMA channel, should be in range from 0 to 7 00368 * @param[in] NewState New State of this command, should be: 00369 * - ENABLE. 00370 * - DISABLE. 00371 * @return None 00372 **********************************************************************/ 00373 void GPDMA_ChannelCmd(uint8_t channelNum, FunctionalState NewState) 00374 { 00375 LPC_GPDMACH_TypeDef *pDMAch; 00376 00377 // Get Channel pointer 00378 pDMAch = (LPC_GPDMACH_TypeDef *) pGPDMACh[channelNum]; 00379 00380 if (NewState == ENABLE) { 00381 pDMAch->DMACCConfig |= GPDMA_DMACCxConfig_E; 00382 } else { 00383 pDMAch->DMACCConfig &= ~GPDMA_DMACCxConfig_E; 00384 } 00385 } 00386 00387 /*********************************************************************//** 00388 * @brief Standard GPDMA interrupt handler, this function will check 00389 * all interrupt status of GPDMA channels, then execute the call 00390 * back function id they're already installed 00391 * @param[in] None 00392 * @return None 00393 **********************************************************************/ 00394 void GPDMA_IntHandler(void) 00395 { 00396 uint32_t tmp; 00397 // Scan interrupt pending 00398 for (tmp = 0; tmp <= 7; tmp++) { 00399 if (LPC_GPDMA->DMACIntStat & GPDMA_DMACIntStat_Ch(tmp)) { 00400 // Check counter terminal status 00401 if (LPC_GPDMA->DMACIntTCStat & GPDMA_DMACIntTCStat_Ch(tmp)) { 00402 // Clear terminate counter Interrupt pending 00403 LPC_GPDMA->DMACIntTCClear = GPDMA_DMACIntTCClear_Ch(tmp); 00404 // Execute call-back function if it is already installed 00405 if(_apfnGPDMACbs[tmp] != NULL) { 00406 _apfnGPDMACbs[tmp](GPDMA_STAT_INTTC); 00407 } 00408 } 00409 // Check error terminal status 00410 if (LPC_GPDMA->DMACIntErrStat & GPDMA_DMACIntErrStat_Ch(tmp)) { 00411 // Clear error counter Interrupt pending 00412 LPC_GPDMA->DMACIntErrClr = GPDMA_DMACIntErrClr_Ch(tmp); 00413 // Execute call-back function if it is already installed 00414 if(_apfnGPDMACbs[tmp] != NULL) { 00415 _apfnGPDMACbs[tmp](GPDMA_STAT_INTERR); 00416 } 00417 } 00418 } 00419 } 00420 } 00421 00422 00423 /** 00424 * @} 00425 */ 00426 00427 #endif /* _GPDMA */ 00428 00429 /** 00430 * @} 00431 */ 00432 00433 /* --------------------------------- End Of File ------------------------------ */ 00434
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