NXP's driver library for LPC17xx, ported to mbed's online compiler. Not tested! I had to fix a lot of warings and found a couple of pretty obvious bugs, so the chances are there are more. Original: http://ics.nxp.com/support/documents/microcontrollers/zip/lpc17xx.cmsis.driver.library.zip
lpc17xx_qei.h
00001 /***********************************************************************//** 00002 * @file : lpc17xx_qei.h 00003 * @brief : Contains all macro definitions and function prototypes 00004 * support for QEI firmware library on LPC17xx 00005 * @version : 1.0 00006 * @date : 26. May. 2009 00007 * @author : HieuNguyen 00008 ************************************************************************** 00009 * Software that is described herein is for illustrative purposes only 00010 * which provides customers with programming information regarding the 00011 * products. This software is supplied "AS IS" without any warranties. 00012 * NXP Semiconductors assumes no responsibility or liability for the 00013 * use of the software, conveys no license or title under any patent, 00014 * copyright, or mask work right to the product. NXP Semiconductors 00015 * reserves the right to make changes in the software without 00016 * notification. NXP Semiconductors also make no representation or 00017 * warranty that such application will be suitable for the specified 00018 * use without further testing or modification. 00019 **************************************************************************/ 00020 00021 /* Peripheral group ----------------------------------------------------------- */ 00022 /** @defgroup QEI 00023 * @ingroup LPC1700CMSIS_FwLib_Drivers 00024 * @{ 00025 */ 00026 00027 #ifndef LPC17XX_QEI_H_ 00028 #define LPC17XX_QEI_H_ 00029 00030 /* Includes ------------------------------------------------------------------- */ 00031 #include "cmsis.h" 00032 #include "lpc_types.h" 00033 00034 00035 #ifdef __cplusplus 00036 extern "C" 00037 { 00038 #endif 00039 00040 00041 /* Private Macros ------------------------------------------------------------- */ 00042 /** @defgroup QEI_Private_Macros 00043 * @{ 00044 */ 00045 00046 /** @defgroup QEI_REGISTER_BIT_DEFINITIONS 00047 * @{ 00048 */ 00049 00050 /* Quadrature Encoder Interface Control Register Definition --------------------- */ 00051 /* QEI Control register */ 00052 #define QEI_CON_RESP ((uint32_t)(1<<0)) /**< Reset position counter */ 00053 #define QEI_CON_RESPI ((uint32_t)(1<<1)) /**< Reset Posistion Counter on Index */ 00054 #define QEI_CON_RESV ((uint32_t)(1<<2)) /**< Reset Velocity */ 00055 #define QEI_CON_RESI ((uint32_t)(1<<3)) /**< Reset Index Counter */ 00056 #define QEI_CON_BITMASK ((uint32_t)(0x0F)) /**< QEI Control register bit-mask */ 00057 00058 /* QEI Configuration register */ 00059 #define QEI_CONF_DIRINV ((uint32_t)(1<<0)) /**< Direction Invert */ 00060 #define QEI_CONF_SIGMODE ((uint32_t)(1<<1)) /**< Signal mode */ 00061 #define QEI_CONF_CAPMODE ((uint32_t)(1<<2)) /**< Capture mode */ 00062 #define QEI_CONF_INVINX ((uint32_t)(1<<3)) /**< Invert index */ 00063 #define QEI_CONF_BITMASK ((uint32_t)(0x0F)) /**< QEI Configuration register bit-mask */ 00064 00065 /* QEI Status register */ 00066 #define QEI_STAT_DIR ((uint32_t)(1<<0)) /**< Direction bit */ 00067 #define QEI_STAT_BITMASK ((uint32_t)(1<<0)) /**< QEI status register bit-mask */ 00068 00069 /* Quadrature Encoder Interface Position, index and timer Register Definitions --- */ 00070 /* QEI Position register */ 00071 00072 /* QEI Maximum Position register */ 00073 00074 /* QEI Position Compare register 0 */ 00075 00076 /* QEI Position Compare register 1 */ 00077 00078 /* QEI Position Compare register 2 */ 00079 00080 /* QEI Index Count register */ 00081 00082 /* QEI Index Compare register */ 00083 00084 /* QEI Timer Reload register */ 00085 00086 /* QEI Timer register */ 00087 00088 /* QEI Velocity register */ 00089 00090 /* QEI Velocity Capture register */ 00091 00092 /* QEI Velocity Compare register */ 00093 00094 /* QEI Digital Filter register */ 00095 00096 /* Quadrature Encoder Interface Interrupt registers definitions --------------------- */ 00097 /* QEI Interrupt Status register */ 00098 #define QEI_INTSTAT_INX_Int ((uint32_t)(1<<0)) /**< Indicates that an index pulse was detected */ 00099 #define QEI_INTSTAT_TIM_Int ((uint32_t)(1<<1)) /**< Indicates that a velocity timer overflow occurred */ 00100 #define QEI_INTSTAT_VELC_Int ((uint32_t)(1<<2)) /**< Indicates that capture velocity is less than compare velocity */ 00101 #define QEI_INTSTAT_DIR_Int ((uint32_t)(1<<3)) /**< Indicates that a change of direction was detected */ 00102 #define QEI_INTSTAT_ERR_Int ((uint32_t)(1<<4)) /**< Indicates that an encoder phase error was detected */ 00103 #define QEI_INTSTAT_ENCLK_Int ((uint32_t)(1<<5)) /**< Indicates that and encoder clock pulse was detected */ 00104 #define QEI_INTSTAT_POS0_Int ((uint32_t)(1<<6)) /**< Indicates that the position 0 compare value is equal to the 00105 current position */ 00106 #define QEI_INTSTAT_POS1_Int ((uint32_t)(1<<7)) /**< Indicates that the position 1compare value is equal to the 00107 current position */ 00108 #define QEI_INTSTAT_POS2_Int ((uint32_t)(1<<8)) /**< Indicates that the position 2 compare value is equal to the 00109 current position */ 00110 #define QEI_INTSTAT_REV_Int ((uint32_t)(1<<9)) /**< Indicates that the index compare value is equal to the current 00111 index count */ 00112 #define QEI_INTSTAT_POS0REV_Int ((uint32_t)(1<<10)) /**< Combined position 0 and revolution count interrupt. Set when 00113 both the POS0_Int bit is set and the REV_Int is set */ 00114 #define QEI_INTSTAT_POS1REV_Int ((uint32_t)(1<<11)) /**< Combined position 1 and revolution count interrupt. Set when 00115 both the POS1_Int bit is set and the REV_Int is set */ 00116 #define QEI_INTSTAT_POS2REV_Int ((uint32_t)(1<<12)) /**< Combined position 2 and revolution count interrupt. Set when 00117 both the POS2_Int bit is set and the REV_Int is set */ 00118 #define QEI_INTSTAT_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Status register bit-mask */ 00119 00120 /* QEI Interrupt Set register */ 00121 #define QEI_INTSET_INX_Int ((uint32_t)(1<<0)) /**< Set Bit Indicates that an index pulse was detected */ 00122 #define QEI_INTSET_TIM_Int ((uint32_t)(1<<1)) /**< Set Bit Indicates that a velocity timer overflow occurred */ 00123 #define QEI_INTSET_VELC_Int ((uint32_t)(1<<2)) /**< Set Bit Indicates that capture velocity is less than compare velocity */ 00124 #define QEI_INTSET_DIR_Int ((uint32_t)(1<<3)) /**< Set Bit Indicates that a change of direction was detected */ 00125 #define QEI_INTSET_ERR_Int ((uint32_t)(1<<4)) /**< Set Bit Indicates that an encoder phase error was detected */ 00126 #define QEI_INTSET_ENCLK_Int ((uint32_t)(1<<5)) /**< Set Bit Indicates that and encoder clock pulse was detected */ 00127 #define QEI_INTSET_POS0_Int ((uint32_t)(1<<6)) /**< Set Bit Indicates that the position 0 compare value is equal to the 00128 current position */ 00129 #define QEI_INTSET_POS1_Int ((uint32_t)(1<<7)) /**< Set Bit Indicates that the position 1compare value is equal to the 00130 current position */ 00131 #define QEI_INTSET_POS2_Int ((uint32_t)(1<<8)) /**< Set Bit Indicates that the position 2 compare value is equal to the 00132 current position */ 00133 #define QEI_INTSET_REV_Int ((uint32_t)(1<<9)) /**< Set Bit Indicates that the index compare value is equal to the current 00134 index count */ 00135 #define QEI_INTSET_POS0REV_Int ((uint32_t)(1<<10)) /**< Set Bit that combined position 0 and revolution count interrupt */ 00136 #define QEI_INTSET_POS1REV_Int ((uint32_t)(1<<11)) /**< Set Bit that Combined position 1 and revolution count interrupt */ 00137 #define QEI_INTSET_POS2REV_Int ((uint32_t)(1<<12)) /**< Set Bit that Combined position 2 and revolution count interrupt */ 00138 #define QEI_INTSET_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Set register bit-mask */ 00139 00140 /* QEI Interrupt Clear register */ 00141 #define QEI_INTCLR_INX_Int ((uint32_t)(1<<0)) /**< Clear Bit Indicates that an index pulse was detected */ 00142 #define QEI_INTCLR_TIM_Int ((uint32_t)(1<<1)) /**< Clear Bit Indicates that a velocity timer overflow occurred */ 00143 #define QEI_INTCLR_VELC_Int ((uint32_t)(1<<2)) /**< Clear Bit Indicates that capture velocity is less than compare velocity */ 00144 #define QEI_INTCLR_DIR_Int ((uint32_t)(1<<3)) /**< Clear Bit Indicates that a change of direction was detected */ 00145 #define QEI_INTCLR_ERR_Int ((uint32_t)(1<<4)) /**< Clear Bit Indicates that an encoder phase error was detected */ 00146 #define QEI_INTCLR_ENCLK_Int ((uint32_t)(1<<5)) /**< Clear Bit Indicates that and encoder clock pulse was detected */ 00147 #define QEI_INTCLR_POS0_Int ((uint32_t)(1<<6)) /**< Clear Bit Indicates that the position 0 compare value is equal to the 00148 current position */ 00149 #define QEI_INTCLR_POS1_Int ((uint32_t)(1<<7)) /**< Clear Bit Indicates that the position 1compare value is equal to the 00150 current position */ 00151 #define QEI_INTCLR_POS2_Int ((uint32_t)(1<<8)) /**< Clear Bit Indicates that the position 2 compare value is equal to the 00152 current position */ 00153 #define QEI_INTCLR_REV_Int ((uint32_t)(1<<9)) /**< Clear Bit Indicates that the index compare value is equal to the current 00154 index count */ 00155 #define QEI_INTCLR_POS0REV_Int ((uint32_t)(1<<10)) /**< Clear Bit that combined position 0 and revolution count interrupt */ 00156 #define QEI_INTCLR_POS1REV_Int ((uint32_t)(1<<11)) /**< Clear Bit that Combined position 1 and revolution count interrupt */ 00157 #define QEI_INTCLR_POS2REV_Int ((uint32_t)(1<<12)) /**< Clear Bit that Combined position 2 and revolution count interrupt */ 00158 #define QEI_INTCLR_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Clear register bit-mask */ 00159 00160 /* QEI Interrupt Enable register */ 00161 #define QEI_INTEN_INX_Int ((uint32_t)(1<<0)) /**< Enabled Interrupt Bit Indicates that an index pulse was detected */ 00162 #define QEI_INTEN_TIM_Int ((uint32_t)(1<<1)) /**< Enabled Interrupt Bit Indicates that a velocity timer overflow occurred */ 00163 #define QEI_INTEN_VELC_Int ((uint32_t)(1<<2)) /**< Enabled Interrupt Bit Indicates that capture velocity is less than compare velocity */ 00164 #define QEI_INTEN_DIR_Int ((uint32_t)(1<<3)) /**< Enabled Interrupt Bit Indicates that a change of direction was detected */ 00165 #define QEI_INTEN_ERR_Int ((uint32_t)(1<<4)) /**< Enabled Interrupt Bit Indicates that an encoder phase error was detected */ 00166 #define QEI_INTEN_ENCLK_Int ((uint32_t)(1<<5)) /**< Enabled Interrupt Bit Indicates that and encoder clock pulse was detected */ 00167 #define QEI_INTEN_POS0_Int ((uint32_t)(1<<6)) /**< Enabled Interrupt Bit Indicates that the position 0 compare value is equal to the 00168 current position */ 00169 #define QEI_INTEN_POS1_Int ((uint32_t)(1<<7)) /**< Enabled Interrupt Bit Indicates that the position 1compare value is equal to the 00170 current position */ 00171 #define QEI_INTEN_POS2_Int ((uint32_t)(1<<8)) /**< Enabled Interrupt Bit Indicates that the position 2 compare value is equal to the 00172 current position */ 00173 #define QEI_INTEN_REV_Int ((uint32_t)(1<<9)) /**< Enabled Interrupt Bit Indicates that the index compare value is equal to the current 00174 index count */ 00175 #define QEI_INTEN_POS0REV_Int ((uint32_t)(1<<10)) /**< Enabled Interrupt Bit that combined position 0 and revolution count interrupt */ 00176 #define QEI_INTEN_POS1REV_Int ((uint32_t)(1<<11)) /**< Enabled Interrupt Bit that Combined position 1 and revolution count interrupt */ 00177 #define QEI_INTEN_POS2REV_Int ((uint32_t)(1<<12)) /**< Enabled Interrupt Bit that Combined position 2 and revolution count interrupt */ 00178 #define QEI_INTEN_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Enable register bit-mask */ 00179 00180 /* QEI Interrupt Enable Set register */ 00181 #define QEI_IESET_INX_Int ((uint32_t)(1<<0)) /**< Set Enable Interrupt Bit Indicates that an index pulse was detected */ 00182 #define QEI_IESET_TIM_Int ((uint32_t)(1<<1)) /**< Set Enable Interrupt Bit Indicates that a velocity timer overflow occurred */ 00183 #define QEI_IESET_VELC_Int ((uint32_t)(1<<2)) /**< Set Enable Interrupt Bit Indicates that capture velocity is less than compare velocity */ 00184 #define QEI_IESET_DIR_Int ((uint32_t)(1<<3)) /**< Set Enable Interrupt Bit Indicates that a change of direction was detected */ 00185 #define QEI_IESET_ERR_Int ((uint32_t)(1<<4)) /**< Set Enable Interrupt Bit Indicates that an encoder phase error was detected */ 00186 #define QEI_IESET_ENCLK_Int ((uint32_t)(1<<5)) /**< Set Enable Interrupt Bit Indicates that and encoder clock pulse was detected */ 00187 #define QEI_IESET_POS0_Int ((uint32_t)(1<<6)) /**< Set Enable Interrupt Bit Indicates that the position 0 compare value is equal to the 00188 current position */ 00189 #define QEI_IESET_POS1_Int ((uint32_t)(1<<7)) /**< Set Enable Interrupt Bit Indicates that the position 1compare value is equal to the 00190 current position */ 00191 #define QEI_IESET_POS2_Int ((uint32_t)(1<<8)) /**< Set Enable Interrupt Bit Indicates that the position 2 compare value is equal to the 00192 current position */ 00193 #define QEI_IESET_REV_Int ((uint32_t)(1<<9)) /**< Set Enable Interrupt Bit Indicates that the index compare value is equal to the current 00194 index count */ 00195 #define QEI_IESET_POS0REV_Int ((uint32_t)(1<<10)) /**< Set Enable Interrupt Bit that combined position 0 and revolution count interrupt */ 00196 #define QEI_IESET_POS1REV_Int ((uint32_t)(1<<11)) /**< Set Enable Interrupt Bit that Combined position 1 and revolution count interrupt */ 00197 #define QEI_IESET_POS2REV_Int ((uint32_t)(1<<12)) /**< Set Enable Interrupt Bit that Combined position 2 and revolution count interrupt */ 00198 #define QEI_IESET_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Enable Set register bit-mask */ 00199 00200 /* QEI Interrupt Enable Clear register */ 00201 #define QEI_IECLR_INX_Int ((uint32_t)(1<<0)) /**< Clear Enabled Interrupt Bit Indicates that an index pulse was detected */ 00202 #define QEI_IECLR_TIM_Int ((uint32_t)(1<<1)) /**< Clear Enabled Interrupt Bit Indicates that a velocity timer overflow occurred */ 00203 #define QEI_IECLR_VELC_Int ((uint32_t)(1<<2)) /**< Clear Enabled Interrupt Bit Indicates that capture velocity is less than compare velocity */ 00204 #define QEI_IECLR_DIR_Int ((uint32_t)(1<<3)) /**< Clear Enabled Interrupt Bit Indicates that a change of direction was detected */ 00205 #define QEI_IECLR_ERR_Int ((uint32_t)(1<<4)) /**< Clear Enabled Interrupt Bit Indicates that an encoder phase error was detected */ 00206 #define QEI_IECLR_ENCLK_Int ((uint32_t)(1<<5)) /**< Clear Enabled Interrupt Bit Indicates that and encoder clock pulse was detected */ 00207 #define QEI_IECLR_POS0_Int ((uint32_t)(1<<6)) /**< Clear Enabled Interrupt Bit Indicates that the position 0 compare value is equal to the 00208 current position */ 00209 #define QEI_IECLR_POS1_Int ((uint32_t)(1<<7)) /**< Clear Enabled Interrupt Bit Indicates that the position 1compare value is equal to the 00210 current position */ 00211 #define QEI_IECLR_POS2_Int ((uint32_t)(1<<8)) /**< Clear Enabled Interrupt Bit Indicates that the position 2 compare value is equal to the 00212 current position */ 00213 #define QEI_IECLR_REV_Int ((uint32_t)(1<<9)) /**< Clear Enabled Interrupt Bit Indicates that the index compare value is equal to the current 00214 index count */ 00215 #define QEI_IECLR_POS0REV_Int ((uint32_t)(1<<10)) /**< Clear Enabled Interrupt Bit that combined position 0 and revolution count interrupt */ 00216 #define QEI_IECLR_POS1REV_Int ((uint32_t)(1<<11)) /**< Clear Enabled Interrupt Bit that Combined position 1 and revolution count interrupt */ 00217 #define QEI_IECLR_POS2REV_Int ((uint32_t)(1<<12)) /**< Clear Enabled Interrupt Bit that Combined position 2 and revolution count interrupt */ 00218 #define QEI_IECLR_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Enable Clear register bit-mask */ 00219 00220 00221 /** 00222 * @} 00223 */ 00224 00225 /** 00226 * @} 00227 */ 00228 00229 00230 /* Public Types --------------------------------------------------------------- */ 00231 /** @defgroup QEI_Public_Types 00232 * @{ 00233 */ 00234 00235 /** 00236 * @brief QEI Configuration structure type definition 00237 */ 00238 typedef struct { 00239 uint32_t DirectionInvert :1; /**< Direction invert option: 00240 - QEI_DIRINV_NONE: QEI Direction is normal 00241 - QEI_DIRINV_CMPL: QEI Direction is complemented 00242 */ 00243 uint32_t SignalMode :1; /**< Signal mode Option: 00244 - QEI_SIGNALMODE_QUAD: Signal is in Quadrature phase mode 00245 - QEI_SIGNALMODE_CLKDIR: Signal is in Clock/Direction mode 00246 */ 00247 uint32_t CaptureMode :1; /**< Capture Mode Option: 00248 - QEI_CAPMODE_2X: Only Phase-A edges are counted (2X) 00249 - QEI_CAPMODE_4X: BOTH Phase-A and Phase-B edges are counted (4X) 00250 */ 00251 uint32_t InvertIndex :1; /**< Invert Index Option: 00252 - QEI_INVINX_NONE: the sense of the index input is normal 00253 - QEI_INVINX_EN: inverts the sense of the index input 00254 */ 00255 } QEI_CFG_Type; 00256 00257 /** 00258 * @brief Timer Reload Configuration structure type definition 00259 */ 00260 typedef struct { 00261 00262 uint8_t ReloadOption; /**< Velocity Timer Reload Option, should be: 00263 - QEI_TIMERRELOAD_TICKVAL: Reload value in absolute value 00264 - QEI_TIMERRELOAD_USVAL: Reload value in microsecond value 00265 */ 00266 uint8_t Reserved[3]; 00267 uint32_t ReloadValue; /**< Velocity Timer Reload Value, 32-bit long, should be matched 00268 with Velocity Timer Reload Option 00269 */ 00270 } QEI_RELOADCFG_Type; 00271 00272 /** 00273 * @} 00274 */ 00275 00276 00277 /* Public Macros -------------------------------------------------------------- */ 00278 /** @defgroup QEI_Public_Macros 00279 * @{ 00280 */ 00281 00282 #define PARAM_QEIx(n) ((n==LPC_QEI)) 00283 00284 /* QEI Reset types */ 00285 #define QEI_RESET_POS QEI_CON_RESP /**< Reset position counter */ 00286 #define QEI_RESET_POSOnIDX QEI_CON_RESPI /**< Reset Posistion Counter on Index */ 00287 #define QEI_RESET_VEL QEI_CON_RESV /**< Reset Velocity */ 00288 #define QEI_RESET_IDX QEI_CON_RESI /**< Reset Index Counter */ 00289 00290 #define PARAM_QEI_RESET(n) ((n==QEI_CON_RESP) \ 00291 || (n==QEI_RESET_POSOnIDX) \ 00292 || (n==QEI_RESET_VEL) \ 00293 || (n==QEI_RESET_IDX)) 00294 00295 /* QEI Direction Invert Type Option */ 00296 #define QEI_DIRINV_NONE ((uint32_t)(0)) /**< Direction is not inverted */ 00297 #define QEI_DIRINV_CMPL ((uint32_t)(1)) /**< Direction is complemented */ 00298 00299 #define PARAM_QEI_DIRINV(n) ((n==QEI_DIRINV_NONE) || (n==QEI_DIRINV_CMPL)) 00300 00301 /* QEI Signal Mode Option */ 00302 #define QEI_SIGNALMODE_QUAD ((uint32_t)(0)) /**< Signal operation: Quadrature phase mode */ 00303 #define QEI_SIGNALMODE_CLKDIR ((uint32_t)(1)) /**< Signal operation: Clock/Direction mode */ 00304 00305 #define PARAM_QEI_SIGNALMODE(n) ((n==QEI_SIGNALMODE_QUAD) || (n==QEI_SIGNALMODE_CLKDIR)) 00306 00307 /* QEI Capture Mode Option */ 00308 #define QEI_CAPMODE_2X ((uint32_t)(0)) /**< Capture mode: Only Phase-A edges are counted (2X) */ 00309 #define QEI_CAPMODE_4X ((uint32_t)(1)) /**< Capture mode: BOTH PhA and PhB edges are counted (4X)*/ 00310 00311 #define PARAM_QEI_CAPMODE(n) ((n==QEI_CAPMODE_2X) || (n==QEI_CAPMODE_4X)) 00312 00313 /* QEI Invert Index Signal Option */ 00314 #define QEI_INVINX_NONE ((uint32_t)(0)) /**< Invert Index signal option: None */ 00315 #define QEI_INVINX_EN ((uint32_t)(1)) /**< Invert Index signal option: Enable */ 00316 00317 #define PARAM_QEI_INVINX(n) ((n==QEI_INVINX_NONE) || (n==QEI_INVINX_EN)) 00318 00319 /* QEI timer reload option */ 00320 #define QEI_TIMERRELOAD_TICKVAL ((uint8_t)(0)) /**< Reload value in absolute value */ 00321 #define QEI_TIMERRELOAD_USVAL ((uint8_t)(1)) /**< Reload value in microsecond value */ 00322 #define PARAM_QEI_TIMERRELOAD(n) ((n==QEI_TIMERRELOAD_TICKVAL) || (n==QEI_TIMERRELOAD_USVAL)) 00323 00324 /* QEI Flag Status type */ 00325 #define QEI_STATUS_DIR ((uint32_t)(1<<0)) /**< Direction status */ 00326 #define PARAM_QEI_STATUS(n) ((n==QEI_STATUS_DIR)) 00327 00328 /* QEI Compare Position channel option */ 00329 #define QEI_COMPPOS_CH_0 ((uint8_t)(0)) /**< QEI compare position channel 0 */ 00330 #define QEI_COMPPOS_CH_1 ((uint8_t)(1)) /**< QEI compare position channel 1 */ 00331 #define QEI_COMPPOS_CH_2 ((uint8_t)(2)) /**< QEI compare position channel 2 */ 00332 #define PARAM_QEI_COMPPOS_CH(n) ((n==QEI_COMPPOS_CH_0) || (n==QEI_COMPPOS_CH_1) || (n==QEI_COMPPOS_CH_2)) 00333 00334 /* QEI interrupt flag type */ 00335 #define QEI_INTFLAG_INX_Int ((uint32_t)(1<<0)) /**< index pulse was detected interrupt */ 00336 #define QEI_INTFLAG_TIM_Int ((uint32_t)(1<<1)) /**< Velocity timer over flow interrupt */ 00337 #define QEI_INTFLAG_VELC_Int ((uint32_t)(1<<2)) /**< Capture velocity is less than compare interrupt */ 00338 #define QEI_INTFLAG_DIR_Int ((uint32_t)(1<<3)) /**< Change of direction interrupt */ 00339 #define QEI_INTFLAG_ERR_Int ((uint32_t)(1<<4)) /**< An encoder phase error interrupt */ 00340 #define QEI_INTFLAG_ENCLK_Int ((uint32_t)(1<<5)) /**< An encoder clock pulse was detected interrupt */ 00341 #define QEI_INTFLAG_POS0_Int ((uint32_t)(1<<6)) /**< position 0 compare value is equal to the 00342 current position interrupt */ 00343 #define QEI_INTFLAG_POS1_Int ((uint32_t)(1<<7)) /**< position 1 compare value is equal to the 00344 current position interrupt */ 00345 #define QEI_INTFLAG_POS2_Int ((uint32_t)(1<<8)) /**< position 2 compare value is equal to the 00346 current position interrupt */ 00347 #define QEI_INTFLAG_REV_Int ((uint32_t)(1<<9)) /**< Index compare value is equal to the current 00348 index count interrupt */ 00349 #define QEI_INTFLAG_POS0REV_Int ((uint32_t)(1<<10)) /**< Combined position 0 and revolution count interrupt */ 00350 #define QEI_INTFLAG_POS1REV_Int ((uint32_t)(1<<11)) /**< Combined position 1 and revolution count interrupt */ 00351 #define QEI_INTFLAG_POS2REV_Int ((uint32_t)(1<<12)) /**< Combined position 2 and revolution count interrupt */ 00352 00353 #define PARAM_QEI_INTFLAG(n) ((n==QEI_INTFLAG_INX_Int) \ 00354 || (n==QEI_INTFLAG_TIM_Int) \ 00355 || (n==QEI_INTFLAG_VELC_Int) \ 00356 || (n==QEI_INTFLAG_DIR_Int) \ 00357 || (n==QEI_INTFLAG_ERR_Int) \ 00358 || (n==QEI_INTFLAG_ENCLK_Int) \ 00359 || (n==QEI_INTFLAG_POS0_Int) \ 00360 || (n==QEI_INTFLAG_POS1_Int) \ 00361 || (n==QEI_INTFLAG_POS2_Int) \ 00362 || (n==QEI_INTFLAG_REV_Int) \ 00363 || (n==QEI_INTFLAG_POS0REV_Int) \ 00364 || (n==QEI_INTFLAG_POS1REV_Int) \ 00365 || (n==QEI_INTFLAG_POS2REV_Int)) 00366 00367 /** 00368 * @} 00369 */ 00370 00371 00372 /* Public Functions ----------------------------------------------------------- */ 00373 /** @defgroup QEI_Public_Functions 00374 * @{ 00375 */ 00376 00377 void QEI_Reset(LPC_QEI_TypeDef *QEIx, uint32_t ulResetType); 00378 void QEI_Init(LPC_QEI_TypeDef *QEIx, QEI_CFG_Type *QEI_ConfigStruct); 00379 void QEI_ConfigStructInit(QEI_CFG_Type *QIE_InitStruct); 00380 void QEI_DeInit(LPC_QEI_TypeDef *QEIx); 00381 FlagStatus QEI_GetStatus(LPC_QEI_TypeDef *QEIx, uint32_t ulFlagType); 00382 uint32_t QEI_GetPosition(LPC_QEI_TypeDef *QEIx); 00383 void QEI_SetMaxPosition(LPC_QEI_TypeDef *QEIx, uint32_t ulMaxPos); 00384 void QEI_SetPositionComp(LPC_QEI_TypeDef *QEIx, uint8_t bPosCompCh, uint32_t ulPosComp); 00385 uint32_t QEI_GetIndex(LPC_QEI_TypeDef *QEIx); 00386 void QEI_SetIndexComp(LPC_QEI_TypeDef *QEIx, uint32_t ulIndexComp); 00387 void QEI_SetTimerReload(LPC_QEI_TypeDef *QEIx, QEI_RELOADCFG_Type *QEIReloadStruct); 00388 uint32_t QEI_GetTimer(LPC_QEI_TypeDef *QEIx); 00389 uint32_t QEI_GetVelocity(LPC_QEI_TypeDef *QEIx); 00390 uint32_t QEI_GetVelocityCap(LPC_QEI_TypeDef *QEIx); 00391 void QEI_SetVelocityComp(LPC_QEI_TypeDef *QEIx, uint32_t ulVelComp); 00392 void QEI_SetDigiFilter(LPC_QEI_TypeDef *QEIx, uint32_t ulSamplingPulse); 00393 FlagStatus QEI_GetIntStatus(LPC_QEI_TypeDef *QEIx, uint32_t ulIntType); 00394 void QEI_IntCmd(LPC_QEI_TypeDef *QEIx, uint32_t ulIntType, FunctionalState NewState); 00395 void QEI_IntSet(LPC_QEI_TypeDef *QEIx, uint32_t ulIntType); 00396 void QEI_IntClear(LPC_QEI_TypeDef *QEIx, uint32_t ulIntType); 00397 uint32_t QEI_CalculateRPM(LPC_QEI_TypeDef *QEIx, uint32_t ulVelCapValue, uint32_t ulPPR); 00398 00399 00400 /** 00401 * @} 00402 */ 00403 00404 #ifdef __cplusplus 00405 } 00406 #endif 00407 00408 #endif /* LPC17XX_QEI_H_ */ 00409 00410 /** 00411 * @} 00412 */ 00413 00414 /* --------------------------------- End Of File ------------------------------ */
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