DriverLibrary - NXP's driver library for LPC17xx, ported to mbed'…

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Igor Skochinsky / Mbed 2 deprecated DriverLibrary

NXP's driver library for LPC17xx, ported to mbed's online compiler. Not tested! I had to fix a lot of warings and found a couple of pretty obvious bugs, so the chances are there are more. Original: http://ics.nxp.com/support/documents/microcontrollers/zip/lpc17xx.cmsis.driver.library.zip

Dependencies: mbed

include/lpc17xx_clkpwr.h@0:1063a091a062, 2010-02-17 (annotated)

Committer:: igorsk
Date:: Wed Feb 17 16:22:39 2010 +0000
Revision:: 0:1063a091a062

Who changed what in which revision?

User	Revision	Line number	New contents of line
igorsk	0:1063a091a062	1	/*********************************************************************//
igorsk	0:1063a091a062	2	* @file : lpc17xx_clkpwr.h
igorsk	0:1063a091a062	3	* @brief : Contains all macro definitions and function prototypes
igorsk	0:1063a091a062	4	* support for Clock and Power Control firmware library on LPC17xx
igorsk	0:1063a091a062	5	* @version : 1.0
igorsk	0:1063a091a062	6	* @date : 18. Mar. 2009
igorsk	0:1063a091a062	7	* @author : HieuNguyen
igorsk	0:1063a091a062	8	**************************************************************************
igorsk	0:1063a091a062	9	* Software that is described herein is for illustrative purposes only
igorsk	0:1063a091a062	10	* which provides customers with programming information regarding the
igorsk	0:1063a091a062	11	* products. This software is supplied "AS IS" without any warranties.
igorsk	0:1063a091a062	12	* NXP Semiconductors assumes no responsibility or liability for the
igorsk	0:1063a091a062	13	* use of the software, conveys no license or title under any patent,
igorsk	0:1063a091a062	14	* copyright, or mask work right to the product. NXP Semiconductors
igorsk	0:1063a091a062	15	* reserves the right to make changes in the software without
igorsk	0:1063a091a062	16	* notification. NXP Semiconductors also make no representation or
igorsk	0:1063a091a062	17	* warranty that such application will be suitable for the specified
igorsk	0:1063a091a062	18	* use without further testing or modification.
igorsk	0:1063a091a062	19	**************************************************************************/
igorsk	0:1063a091a062	20
igorsk	0:1063a091a062	21	/* Peripheral group ----------------------------------------------------------- */
igorsk	0:1063a091a062	22	/** @defgroup CLKPWR
igorsk	0:1063a091a062	23	* @ingroup LPC1700CMSIS_FwLib_Drivers
igorsk	0:1063a091a062	24	* @{
igorsk	0:1063a091a062	25	*/
igorsk	0:1063a091a062	26
igorsk	0:1063a091a062	27	#ifndef LPC17XX_CLKPWR_H_
igorsk	0:1063a091a062	28	#define LPC17XX_CLKPWR_H_
igorsk	0:1063a091a062	29
igorsk	0:1063a091a062	30	/* Includes ------------------------------------------------------------------- */
igorsk	0:1063a091a062	31	#include "cmsis.h"
igorsk	0:1063a091a062	32	#include "lpc_types.h"
igorsk	0:1063a091a062	33
igorsk	0:1063a091a062	34	#ifdef __cplusplus
igorsk	0:1063a091a062	35	extern "C"
igorsk	0:1063a091a062	36	{
igorsk	0:1063a091a062	37	#endif
igorsk	0:1063a091a062	38
igorsk	0:1063a091a062	39
igorsk	0:1063a091a062	40	/* Private Macros ------------------------------------------------------------- */
igorsk	0:1063a091a062	41	/** @defgroup CLKPWR_Private_Macros
igorsk	0:1063a091a062	42	* @{
igorsk	0:1063a091a062	43	*/
igorsk	0:1063a091a062	44
igorsk	0:1063a091a062	45	/** @defgroup CLKPPWR_REGISTER_BIT_DEFINITIONS
igorsk	0:1063a091a062	46	* @{
igorsk	0:1063a091a062	47	*/
igorsk	0:1063a091a062	48
igorsk	0:1063a091a062	49	/* Clock source selection multiplexer definition */
igorsk	0:1063a091a062	50	/** Internal RC oscillator */
igorsk	0:1063a091a062	51	#define CLKPWR_CLKSRCSEL_CLKSRC_IRC ((uint32_t)(0x00))
igorsk	0:1063a091a062	52	/** Main oscillator */
igorsk	0:1063a091a062	53	#define CLKPWR_CLKSRCSEL_CLKSRC_MAINOSC ((uint32_t)(0x01))
igorsk	0:1063a091a062	54	/** RTC oscillator */
igorsk	0:1063a091a062	55	#define CLKPWR_CLKSRCSEL_CLKSRC_RTC ((uint32_t)(0x02))
igorsk	0:1063a091a062	56	/** Clock source selection bit mask */
igorsk	0:1063a091a062	57	#define CLKPWR_CLKSRCSEL_BITMASK ((uint32_t)(0x03))
igorsk	0:1063a091a062	58
igorsk	0:1063a091a062	59
igorsk	0:1063a091a062	60	/* Clock Output Configuration register definition */
igorsk	0:1063a091a062	61	/** Selects the CPU clock as the CLKOUT source */
igorsk	0:1063a091a062	62	#define CLKPWR_CLKOUTCFG_CLKOUTSEL_CPU ((uint32_t)(0x00))
igorsk	0:1063a091a062	63	/** Selects the main oscillator as the CLKOUT source */
igorsk	0:1063a091a062	64	#define CLKPWR_CLKOUTCFG_CLKOUTSEL_MAINOSC ((uint32_t)(0x01))
igorsk	0:1063a091a062	65	/** Selects the Internal RC oscillator as the CLKOUT source */
igorsk	0:1063a091a062	66	#define CLKPWR_CLKOUTCFG_CLKOUTSEL_RC ((uint32_t)(0x02))
igorsk	0:1063a091a062	67	/** Selects the USB clock as the CLKOUT source */
igorsk	0:1063a091a062	68	#define CLKPWR_CLKOUTCFG_CLKOUTSEL_USB ((uint32_t)(0x03))
igorsk	0:1063a091a062	69	/** Selects the RTC oscillator as the CLKOUT source */
igorsk	0:1063a091a062	70	#define CLKPWR_CLKOUTCFG_CLKOUTSEL_RTC ((uint32_t)(0x04))
igorsk	0:1063a091a062	71	/** Integer value to divide the output clock by, minus one */
igorsk	0:1063a091a062	72	#define CLKPWR_CLKOUTCFG_CLKOUTDIV(n) ((uint32_t)((n&0x0F)<<4))
igorsk	0:1063a091a062	73	/** CLKOUT enable control */
igorsk	0:1063a091a062	74	#define CLKPWR_CLKOUTCFG_CLKOUT_EN ((uint32_t)(1<<8))
igorsk	0:1063a091a062	75	/** CLKOUT activity indication */
igorsk	0:1063a091a062	76	#define CLKPWR_CLKOUTCFG_CLKOUT_ACT ((uint32_t)(1<<9))
igorsk	0:1063a091a062	77	/** Clock source selection bit mask */
igorsk	0:1063a091a062	78	#define CLKPWR_CLKOUTCFG_BITMASK ((uint32_t)(0x3FF))
igorsk	0:1063a091a062	79
igorsk	0:1063a091a062	80
igorsk	0:1063a091a062	81	/* PLL 0 control definition */
igorsk	0:1063a091a062	82	/** PLL 0 control enable */
igorsk	0:1063a091a062	83	#define CLKPWR_PLL0CON_ENABLE ((uint32_t)(0x01))
igorsk	0:1063a091a062	84	/** PLL 0 control connect */
igorsk	0:1063a091a062	85	#define CLKPWR_PLL0CON_CONNECT ((uint32_t)(0x02))
igorsk	0:1063a091a062	86	/** PLL 0 control bit mask */
igorsk	0:1063a091a062	87	#define CLKPWR_PLL0CON_BITMASK ((uint32_t)(0x03))
igorsk	0:1063a091a062	88
igorsk	0:1063a091a062	89
igorsk	0:1063a091a062	90	/* PLL 0 Configuration register definition */
igorsk	0:1063a091a062	91	/** PLL 0 Configuration MSEL field */
igorsk	0:1063a091a062	92	#define CLKPWR_PLL0CFG_MSEL(n) ((uint32_t)(n&0x7FFF))
igorsk	0:1063a091a062	93	/** PLL 0 Configuration NSEL field */
igorsk	0:1063a091a062	94	#define CLKPWR_PLL0CFG_NSEL(n) ((uint32_t)((n<<16)&0xFF0000))
igorsk	0:1063a091a062	95	/** PLL 0 Configuration bit mask */
igorsk	0:1063a091a062	96	#define CLKPWR_PLL0CFG_BITMASK ((uint32_t)(0xFF7FFF))
igorsk	0:1063a091a062	97
igorsk	0:1063a091a062	98
igorsk	0:1063a091a062	99	/* PLL 0 status definition */
igorsk	0:1063a091a062	100	/** PLL 0 MSEL value */
igorsk	0:1063a091a062	101	#define CLKPWR_PLL0STAT_MSEL(n) ((uint32_t)(n&0x7FFF))
igorsk	0:1063a091a062	102	/** PLL NSEL get value */
igorsk	0:1063a091a062	103	#define CLKPWR_PLL0STAT_NSEL(n) ((uint32_t)((n>>16)&0xFF))
igorsk	0:1063a091a062	104	/** PLL status enable bit */
igorsk	0:1063a091a062	105	#define CLKPWR_PLL0STAT_PLLE ((uint32_t)(1<<24))
igorsk	0:1063a091a062	106	/** PLL status Connect bit */
igorsk	0:1063a091a062	107	#define CLKPWR_PLL0STAT_PLLC ((uint32_t)(1<<25))
igorsk	0:1063a091a062	108	/** PLL status lock */
igorsk	0:1063a091a062	109	#define CLKPWR_PLL0STAT_PLOCK ((uint32_t)(1<<26))
igorsk	0:1063a091a062	110
igorsk	0:1063a091a062	111
igorsk	0:1063a091a062	112	/* PLL0 Feed register definition */
igorsk	0:1063a091a062	113	/** PLL0 Feed bit mask */
igorsk	0:1063a091a062	114	#define CLKPWR_PLL0FEED_BITMASK ((uint32_t)0xFF)
igorsk	0:1063a091a062	115
igorsk	0:1063a091a062	116
igorsk	0:1063a091a062	117	/* USB PLL control definition */
igorsk	0:1063a091a062	118	/** USB PLL control enable */
igorsk	0:1063a091a062	119	#define CLKPWR_PLL1CON_ENABLE ((uint32_t)(0x01))
igorsk	0:1063a091a062	120	/** USB PLL control connect */
igorsk	0:1063a091a062	121	#define CLKPWR_PLL1CON_CONNECT ((uint32_t)(0x02))
igorsk	0:1063a091a062	122	/** USB PLL control bit mask */
igorsk	0:1063a091a062	123	#define CLKPWR_PLL1CON_BITMASK ((uint32_t)(0x03))
igorsk	0:1063a091a062	124
igorsk	0:1063a091a062	125
igorsk	0:1063a091a062	126	/* USB PLL configuration definition */
igorsk	0:1063a091a062	127	/** USB PLL MSEL set value */
igorsk	0:1063a091a062	128	#define CLKPWR_PLL1CFG_MSEL(n) ((uint32_t)(n&0x1F))
igorsk	0:1063a091a062	129	/** USB PLL PSEL set value */
igorsk	0:1063a091a062	130	#define CLKPWR_PLL1CFG_PSEL(n) ((uint32_t)((n&0x03)<<5))
igorsk	0:1063a091a062	131	/** USB PLL configuration bit mask */
igorsk	0:1063a091a062	132	#define CLKPWR_PLL1CFG_BITMASK ((uint32_t)(0x7F))
igorsk	0:1063a091a062	133
igorsk	0:1063a091a062	134
igorsk	0:1063a091a062	135	/* USB PLL status definition */
igorsk	0:1063a091a062	136	/** USB PLL MSEL get value */
igorsk	0:1063a091a062	137	#define CLKPWR_PLL1STAT_MSEL(n) ((uint32_t)(n&0x1F))
igorsk	0:1063a091a062	138	/** USB PLL PSEL get value */
igorsk	0:1063a091a062	139	#define CLKPWR_PLL1STAT_PSEL(n) ((uint32_t)((n>>5)&0x03))
igorsk	0:1063a091a062	140	/** USB PLL status enable bit */
igorsk	0:1063a091a062	141	#define CLKPWR_PLL1STAT_PLLE ((uint32_t)(1<<8))
igorsk	0:1063a091a062	142	/** USB PLL status Connect bit */
igorsk	0:1063a091a062	143	#define CLKPWR_PLL1STAT_PLLC ((uint32_t)(1<<9))
igorsk	0:1063a091a062	144	/** USB PLL status lock */
igorsk	0:1063a091a062	145	#define CLKPWR_PLL1STAT_PLOCK ((uint32_t)(1<<10))
igorsk	0:1063a091a062	146
igorsk	0:1063a091a062	147
igorsk	0:1063a091a062	148	/* PLL1 Feed register definition */
igorsk	0:1063a091a062	149	/** PLL1 Feed bit mask */
igorsk	0:1063a091a062	150	#define CLKPWR_PLL1FEED_BITMASK ((uint32_t)0xFF)
igorsk	0:1063a091a062	151
igorsk	0:1063a091a062	152
igorsk	0:1063a091a062	153	/* CPU Clock Configuration register definition */
igorsk	0:1063a091a062	154	/** CPU Clock configuration bit mask */
igorsk	0:1063a091a062	155	#define CLKPWR_CCLKCFG_BITMASK ((uint32_t)(0xFF))
igorsk	0:1063a091a062	156
igorsk	0:1063a091a062	157	/* USB Clock Configuration register definition */
igorsk	0:1063a091a062	158	/** USB Clock Configuration bit mask */
igorsk	0:1063a091a062	159	#define CLKPWR_USBCLKCFG_BITMASK ((uint32_t)(0x0F))
igorsk	0:1063a091a062	160
igorsk	0:1063a091a062	161	/* IRC Trim register definition */
igorsk	0:1063a091a062	162	/** IRC Trim bit mask */
igorsk	0:1063a091a062	163	#define CLKPWR_IRCTRIM_BITMASK ((uint32_t)(0x0F))
igorsk	0:1063a091a062	164
igorsk	0:1063a091a062	165
igorsk	0:1063a091a062	166	/* Peripheral clock divider bit position definition */
igorsk	0:1063a091a062	167	/** Peripheral Clock Selection 0 mask bit */
igorsk	0:1063a091a062	168	#define CLKPWR_PCLKSEL0_BITMASK ((uint32_t)(0xFFF3F3FF))
igorsk	0:1063a091a062	169	/** Peripheral Clock Selection 1 mask bit */
igorsk	0:1063a091a062	170	#define CLKPWR_PCLKSEL1_BITMASK ((uint32_t)(0xFCF3F0F3))
igorsk	0:1063a091a062	171
igorsk	0:1063a091a062	172
igorsk	0:1063a091a062	173	/** Macro to set peripheral clock of each type
igorsk	0:1063a091a062	174	* p: position of two bits that hold divider of peripheral clock
igorsk	0:1063a091a062	175	* n: value of divider of peripheral clock to be set */
igorsk	0:1063a091a062	176	#define CLKPWR_PCLKSEL_SET(p,n) _SBF(p,n)
igorsk	0:1063a091a062	177	/** Macro to mask peripheral clock of each type */
igorsk	0:1063a091a062	178	#define CLKPWR_PCLKSEL_BITMASK(p) _SBF(p,0x03)
igorsk	0:1063a091a062	179	/** Macro to get peripheral clock of each type */
igorsk	0:1063a091a062	180	#define CLKPWR_PCLKSEL_GET(p, n) ((uint32_t)((n>>p)&0x03))
igorsk	0:1063a091a062	181
igorsk	0:1063a091a062	182
igorsk	0:1063a091a062	183	/* Power Mode Control register definition */
igorsk	0:1063a091a062	184	/** Power mode control bit 0 */
igorsk	0:1063a091a062	185	#define CLKPWR_PCON_PM0 ((uint32_t)(1<<0))
igorsk	0:1063a091a062	186	/** Power mode control bit 1 */
igorsk	0:1063a091a062	187	#define CLKPWR_PCON_PM1 ((uint32_t)(1<<1))
igorsk	0:1063a091a062	188	/** Brown-Out Reduced Power Mode */
igorsk	0:1063a091a062	189	#define CLKPWR_PCON_BODPDM ((uint32_t)(1<<2))
igorsk	0:1063a091a062	190	/** Brown-Out Global Disable */
igorsk	0:1063a091a062	191	#define CLKPWR_PCON_BOGD ((uint32_t)(1<<3))
igorsk	0:1063a091a062	192	/** Brown Out Reset Disable */
igorsk	0:1063a091a062	193	#define CLKPWR_PCON_BORD ((uint32_t)(1<<4))
igorsk	0:1063a091a062	194	/** Sleep Mode entry flag */
igorsk	0:1063a091a062	195	#define CLKPWR_PCON_SMFLAG ((uint32_t)(1<<8))
igorsk	0:1063a091a062	196	/** Deep Sleep entry flag */
igorsk	0:1063a091a062	197	#define CLKPWR_PCON_DSFLAG ((uint32_t)(1<<9))
igorsk	0:1063a091a062	198	/** Power-down entry flag */
igorsk	0:1063a091a062	199	#define CLKPWR_PCON_PDFLAG ((uint32_t)(1<<10))
igorsk	0:1063a091a062	200	/** Deep Power-down entry flag */
igorsk	0:1063a091a062	201	#define CLKPWR_PCON_DPDFLAG ((uint32_t)(1<<11))
igorsk	0:1063a091a062	202
igorsk	0:1063a091a062	203
igorsk	0:1063a091a062	204	/** Power Control for Peripherals bit mask */
igorsk	0:1063a091a062	205	#define CLKPWR_PCONP_BITMASK 0xEFEFF7DE
igorsk	0:1063a091a062	206
igorsk	0:1063a091a062	207	/**
igorsk	0:1063a091a062	208	* @}
igorsk	0:1063a091a062	209	*/
igorsk	0:1063a091a062	210
igorsk	0:1063a091a062	211	/**
igorsk	0:1063a091a062	212	* @}
igorsk	0:1063a091a062	213	*/
igorsk	0:1063a091a062	214
igorsk	0:1063a091a062	215
igorsk	0:1063a091a062	216	/* Public Macros -------------------------------------------------------------- */
igorsk	0:1063a091a062	217	/** @defgroup CLKPWR_Public_Macros
igorsk	0:1063a091a062	218	* @{
igorsk	0:1063a091a062	219	*/
igorsk	0:1063a091a062	220
igorsk	0:1063a091a062	221	/**********************************************************************
igorsk	0:1063a091a062	222	* Peripheral Clock Selection Definitions
igorsk	0:1063a091a062	223	**********************************************************************/
igorsk	0:1063a091a062	224	/** Peripheral clock divider bit position for WDT */
igorsk	0:1063a091a062	225	#define CLKPWR_PCLKSEL_WDT ((uint32_t)(0))
igorsk	0:1063a091a062	226	/** Peripheral clock divider bit position for TIMER0 */
igorsk	0:1063a091a062	227	#define CLKPWR_PCLKSEL_TIMER0 ((uint32_t)(2))
igorsk	0:1063a091a062	228	/** Peripheral clock divider bit position for TIMER1 */
igorsk	0:1063a091a062	229	#define CLKPWR_PCLKSEL_TIMER1 ((uint32_t)(4))
igorsk	0:1063a091a062	230	/** Peripheral clock divider bit position for UART0 */
igorsk	0:1063a091a062	231	#define CLKPWR_PCLKSEL_UART0 ((uint32_t)(6))
igorsk	0:1063a091a062	232	/** Peripheral clock divider bit position for UART1 */
igorsk	0:1063a091a062	233	#define CLKPWR_PCLKSEL_UART1 ((uint32_t)(8))
igorsk	0:1063a091a062	234	/** Peripheral clock divider bit position for PWM1 */
igorsk	0:1063a091a062	235	#define CLKPWR_PCLKSEL_PWM1 ((uint32_t)(12))
igorsk	0:1063a091a062	236	/** Peripheral clock divider bit position for I2C0 */
igorsk	0:1063a091a062	237	#define CLKPWR_PCLKSEL_I2C0 ((uint32_t)(14))
igorsk	0:1063a091a062	238	/** Peripheral clock divider bit position for SPI */
igorsk	0:1063a091a062	239	#define CLKPWR_PCLKSEL_SPI ((uint32_t)(16))
igorsk	0:1063a091a062	240	/** Peripheral clock divider bit position for SSP1 */
igorsk	0:1063a091a062	241	#define CLKPWR_PCLKSEL_SSP1 ((uint32_t)(20))
igorsk	0:1063a091a062	242	/** Peripheral clock divider bit position for DAC */
igorsk	0:1063a091a062	243	#define CLKPWR_PCLKSEL_DAC ((uint32_t)(22))
igorsk	0:1063a091a062	244	/** Peripheral clock divider bit position for ADC */
igorsk	0:1063a091a062	245	#define CLKPWR_PCLKSEL_ADC ((uint32_t)(24))
igorsk	0:1063a091a062	246	/** Peripheral clock divider bit position for CAN1 */
igorsk	0:1063a091a062	247	#define CLKPWR_PCLKSEL_CAN1 ((uint32_t)(26))
igorsk	0:1063a091a062	248	/** Peripheral clock divider bit position for CAN2 */
igorsk	0:1063a091a062	249	#define CLKPWR_PCLKSEL_CAN2 ((uint32_t)(28))
igorsk	0:1063a091a062	250	/** Peripheral clock divider bit position for ACF */
igorsk	0:1063a091a062	251	#define CLKPWR_PCLKSEL_ACF ((uint32_t)(30))
igorsk	0:1063a091a062	252	/** Peripheral clock divider bit position for QEI */
igorsk	0:1063a091a062	253	#define CLKPWR_PCLKSEL_QEI ((uint32_t)(32))
igorsk	0:1063a091a062	254	/** Peripheral clock divider bit position for PCB */
igorsk	0:1063a091a062	255	#define CLKPWR_PCLKSEL_PCB ((uint32_t)(36))
igorsk	0:1063a091a062	256	/** Peripheral clock divider bit position for I2C1 */
igorsk	0:1063a091a062	257	#define CLKPWR_PCLKSEL_I2C1 ((uint32_t)(38))
igorsk	0:1063a091a062	258	/** Peripheral clock divider bit position for SSP0 */
igorsk	0:1063a091a062	259	#define CLKPWR_PCLKSEL_SSP0 ((uint32_t)(42))
igorsk	0:1063a091a062	260	/** Peripheral clock divider bit position for TIMER2 */
igorsk	0:1063a091a062	261	#define CLKPWR_PCLKSEL_TIMER2 ((uint32_t)(44))
igorsk	0:1063a091a062	262	/** Peripheral clock divider bit position for TIMER3 */
igorsk	0:1063a091a062	263	#define CLKPWR_PCLKSEL_TIMER3 ((uint32_t)(46))
igorsk	0:1063a091a062	264	/** Peripheral clock divider bit position for UART2 */
igorsk	0:1063a091a062	265	#define CLKPWR_PCLKSEL_UART2 ((uint32_t)(48))
igorsk	0:1063a091a062	266	/** Peripheral clock divider bit position for UART3 */
igorsk	0:1063a091a062	267	#define CLKPWR_PCLKSEL_UART3 ((uint32_t)(50))
igorsk	0:1063a091a062	268	/** Peripheral clock divider bit position for I2C2 */
igorsk	0:1063a091a062	269	#define CLKPWR_PCLKSEL_I2C2 ((uint32_t)(52))
igorsk	0:1063a091a062	270	/** Peripheral clock divider bit position for I2S */
igorsk	0:1063a091a062	271	#define CLKPWR_PCLKSEL_I2S ((uint32_t)(54))
igorsk	0:1063a091a062	272	/** Peripheral clock divider bit position for RIT */
igorsk	0:1063a091a062	273	#define CLKPWR_PCLKSEL_RIT ((uint32_t)(58))
igorsk	0:1063a091a062	274	/** Peripheral clock divider bit position for SYSCON */
igorsk	0:1063a091a062	275	#define CLKPWR_PCLKSEL_SYSCON ((uint32_t)(60))
igorsk	0:1063a091a062	276	/** Peripheral clock divider bit position for MC */
igorsk	0:1063a091a062	277	#define CLKPWR_PCLKSEL_MC ((uint32_t)(62))
igorsk	0:1063a091a062	278
igorsk	0:1063a091a062	279	/** Macro for Peripheral Clock Selection register bit values
igorsk	0:1063a091a062	280	* Note: When CCLK_DIV_8, Peripherals clock is selected to
igorsk	0:1063a091a062	281	* PCLK_xyz = CCLK/8 except for CAN1, CAN2, and CAN filtering
igorsk	0:1063a091a062	282	* when 11selects PCLK_xyz = CCLK/6 */
igorsk	0:1063a091a062	283	/* Peripheral clock divider is set to 4 from CCLK */
igorsk	0:1063a091a062	284	#define CLKPWR_PCLKSEL_CCLK_DIV_4 ((uint32_t)(0))
igorsk	0:1063a091a062	285	/** Peripheral clock divider is the same with CCLK */
igorsk	0:1063a091a062	286	#define CLKPWR_PCLKSEL_CCLK_DIV_1 ((uint32_t)(1))
igorsk	0:1063a091a062	287	/** Peripheral clock divider is set to 2 from CCLK */
igorsk	0:1063a091a062	288	#define CLKPWR_PCLKSEL_CCLK_DIV_2 ((uint32_t)(2))
igorsk	0:1063a091a062	289
igorsk	0:1063a091a062	290
igorsk	0:1063a091a062	291	/********************************************************************
igorsk	0:1063a091a062	292	* Power Control for Peripherals Definitions
igorsk	0:1063a091a062	293	**********************************************************************/
igorsk	0:1063a091a062	294	/** Timer/Counter 0 power/clock control bit */
igorsk	0:1063a091a062	295	#define CLKPWR_PCONP_PCTIM0 ((uint32_t)(1<<1))
igorsk	0:1063a091a062	296	/* Timer/Counter 1 power/clock control bit */
igorsk	0:1063a091a062	297	#define CLKPWR_PCONP_PCTIM1 ((uint32_t)(1<<2))
igorsk	0:1063a091a062	298	/** UART0 power/clock control bit */
igorsk	0:1063a091a062	299	#define CLKPWR_PCONP_PCUART0 ((uint32_t)(1<<3))
igorsk	0:1063a091a062	300	/** UART1 power/clock control bit */
igorsk	0:1063a091a062	301	#define CLKPWR_PCONP_PCUART1 ((uint32_t)(1<<4))
igorsk	0:1063a091a062	302	/** PWM1 power/clock control bit */
igorsk	0:1063a091a062	303	#define CLKPWR_PCONP_PCPWM1 ((uint32_t)(1<<6))
igorsk	0:1063a091a062	304	/** The I2C0 interface power/clock control bit */
igorsk	0:1063a091a062	305	#define CLKPWR_PCONP_PCI2C0 ((uint32_t)(1<<7))
igorsk	0:1063a091a062	306	/** The SPI interface power/clock control bit */
igorsk	0:1063a091a062	307	#define CLKPWR_PCONP_PCSPI ((uint32_t)(1<<8))
igorsk	0:1063a091a062	308	/** The RTC power/clock control bit */
igorsk	0:1063a091a062	309	#define CLKPWR_PCONP_PCRTC ((uint32_t)(1<<9))
igorsk	0:1063a091a062	310	/** The SSP1 interface power/clock control bit */
igorsk	0:1063a091a062	311	#define CLKPWR_PCONP_PCSSP1 ((uint32_t)(1<<10))
igorsk	0:1063a091a062	312	/** A/D converter 0 (ADC0) power/clock control bit */
igorsk	0:1063a091a062	313	#define CLKPWR_PCONP_PCAD ((uint32_t)(1<<12))
igorsk	0:1063a091a062	314	/** CAN Controller 1 power/clock control bit */
igorsk	0:1063a091a062	315	#define CLKPWR_PCONP_PCAN1 ((uint32_t)(1<<13))
igorsk	0:1063a091a062	316	/** CAN Controller 2 power/clock control bit */
igorsk	0:1063a091a062	317	#define CLKPWR_PCONP_PCAN2 ((uint32_t)(1<<14))
igorsk	0:1063a091a062	318	/** GPIO power/clock control bit */
igorsk	0:1063a091a062	319	#define CLKPWR_PCONP_PCGPIO ((uint32_t)(1<<15))
igorsk	0:1063a091a062	320	/** Repetitive Interrupt Timer power/clock control bit */
igorsk	0:1063a091a062	321	#define CLKPWR_PCONP_PCRIT ((uint32_t)(1<<16))
igorsk	0:1063a091a062	322	/** Motor Control PWM */
igorsk	0:1063a091a062	323	#define CLKPWR_PCONP_PCMC ((uint32_t)(1<<17))
igorsk	0:1063a091a062	324	/** Quadrature Encoder Interface power/clock control bit */
igorsk	0:1063a091a062	325	#define CLKPWR_PCONP_PCQEI ((uint32_t)(1<<18))
igorsk	0:1063a091a062	326	/** The I2C1 interface power/clock control bit */
igorsk	0:1063a091a062	327	#define CLKPWR_PCONP_PCI2C1 ((uint32_t)(1<<19))
igorsk	0:1063a091a062	328	/** The SSP0 interface power/clock control bit */
igorsk	0:1063a091a062	329	#define CLKPWR_PCONP_PCSSP0 ((uint32_t)(1<<21))
igorsk	0:1063a091a062	330	/** Timer 2 power/clock control bit */
igorsk	0:1063a091a062	331	#define CLKPWR_PCONP_PCTIM2 ((uint32_t)(1<<22))
igorsk	0:1063a091a062	332	/** Timer 3 power/clock control bit */
igorsk	0:1063a091a062	333	#define CLKPWR_PCONP_PCTIM3 ((uint32_t)(1<<23))
igorsk	0:1063a091a062	334	/** UART 2 power/clock control bit */
igorsk	0:1063a091a062	335	#define CLKPWR_PCONP_PCUART2 ((uint32_t)(1<<24))
igorsk	0:1063a091a062	336	/** UART 3 power/clock control bit */
igorsk	0:1063a091a062	337	#define CLKPWR_PCONP_PCUART3 ((uint32_t)(1<<25))
igorsk	0:1063a091a062	338	/** I2C interface 2 power/clock control bit */
igorsk	0:1063a091a062	339	#define CLKPWR_PCONP_PCI2C2 ((uint32_t)(1<<26))
igorsk	0:1063a091a062	340	/** I2S interface power/clock control bit*/
igorsk	0:1063a091a062	341	#define CLKPWR_PCONP_PCI2S ((uint32_t)(1<<27))
igorsk	0:1063a091a062	342	/** GP DMA function power/clock control bit*/
igorsk	0:1063a091a062	343	#define CLKPWR_PCONP_PCGPDMA ((uint32_t)(1<<29))
igorsk	0:1063a091a062	344	/** Ethernet block power/clock control bit*/
igorsk	0:1063a091a062	345	#define CLKPWR_PCONP_PCENET ((uint32_t)(1<<30))
igorsk	0:1063a091a062	346	/** USB interface power/clock control bit*/
igorsk	0:1063a091a062	347	#define CLKPWR_PCONP_PCUSB ((uint32_t)(1<<31))
igorsk	0:1063a091a062	348
igorsk	0:1063a091a062	349
igorsk	0:1063a091a062	350	/**
igorsk	0:1063a091a062	351	* @}
igorsk	0:1063a091a062	352	*/
igorsk	0:1063a091a062	353
igorsk	0:1063a091a062	354
igorsk	0:1063a091a062	355	/* Public Functions ----------------------------------------------------------- */
igorsk	0:1063a091a062	356	/** @defgroup CLKPWR_Public_Functions
igorsk	0:1063a091a062	357	* @{
igorsk	0:1063a091a062	358	*/
igorsk	0:1063a091a062	359
igorsk	0:1063a091a062	360	void CLKPWR_SetPCLKDiv (uint32_t ClkType, uint32_t DivVal);
igorsk	0:1063a091a062	361	uint32_t CLKPWR_GetPCLKSEL (uint32_t ClkType);
igorsk	0:1063a091a062	362	uint32_t CLKPWR_GetPCLK (uint32_t ClkType);
igorsk	0:1063a091a062	363	void CLKPWR_ConfigPPWR (uint32_t PPType, FunctionalState NewState);
igorsk	0:1063a091a062	364	void CLKPWR_Sleep(void);
igorsk	0:1063a091a062	365	void CLKPWR_DeepSleep(void);
igorsk	0:1063a091a062	366	void CLKPWR_PowerDown(void);
igorsk	0:1063a091a062	367	void CLKPWR_DeepPowerDown(void);
igorsk	0:1063a091a062	368
igorsk	0:1063a091a062	369	/**
igorsk	0:1063a091a062	370	* @}
igorsk	0:1063a091a062	371	*/
igorsk	0:1063a091a062	372
igorsk	0:1063a091a062	373
igorsk	0:1063a091a062	374	#ifdef __cplusplus
igorsk	0:1063a091a062	375	}
igorsk	0:1063a091a062	376	#endif
igorsk	0:1063a091a062	377
igorsk	0:1063a091a062	378	#endif /* LPC17XX_CLKPWR_H_ */
igorsk	0:1063a091a062	379
igorsk	0:1063a091a062	380	/**
igorsk	0:1063a091a062	381	* @}
igorsk	0:1063a091a062	382	*/
igorsk	0:1063a091a062	383
igorsk	0:1063a091a062	384	/* --------------------------------- End Of File ------------------------------ */

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Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	17 Feb 2010
Imports:	121
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	1
Followers:	5

include/lpc17xx_clkpwr.h@0:1063a091a062, 2010-02-17 (annotated)

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