DriverLibrary - NXP's driver library for LPC17xx, ported to mbed'…

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Igor Skochinsky / Mbed 2 deprecated DriverLibrary

NXP's driver library for LPC17xx, ported to mbed's online compiler. Not tested! I had to fix a lot of warings and found a couple of pretty obvious bugs, so the chances are there are more. Original: http://ics.nxp.com/support/documents/microcontrollers/zip/lpc17xx.cmsis.driver.library.zip

Dependencies: mbed

include/lpc17xx_pwm.h@0:1063a091a062, 2010-02-17 (annotated)

Committer:: igorsk
Date:: Wed Feb 17 16:22:39 2010 +0000
Revision:: 0:1063a091a062

Who changed what in which revision?

User	Revision	Line number	New contents of line
igorsk	0:1063a091a062	1	/*********************************************************************//
igorsk	0:1063a091a062	2	* @file : lpc17xx_pwm.h
igorsk	0:1063a091a062	3	* @brief : Contains all macro definitions and function prototypes
igorsk	0:1063a091a062	4	* support for PWM firmware library on LPC17xx
igorsk	0:1063a091a062	5	* @version : 1.0
igorsk	0:1063a091a062	6	* @date : 22. Apr. 2009
igorsk	0:1063a091a062	7	* @author : HieuNguyen
igorsk	0:1063a091a062	8	**************************************************************************
igorsk	0:1063a091a062	9	* Software that is described herein is for illustrative purposes only
igorsk	0:1063a091a062	10	* which provides customers with programming information regarding the
igorsk	0:1063a091a062	11	* products. This software is supplied "AS IS" without any warranties.
igorsk	0:1063a091a062	12	* NXP Semiconductors assumes no responsibility or liability for the
igorsk	0:1063a091a062	13	* use of the software, conveys no license or title under any patent,
igorsk	0:1063a091a062	14	* copyright, or mask work right to the product. NXP Semiconductors
igorsk	0:1063a091a062	15	* reserves the right to make changes in the software without
igorsk	0:1063a091a062	16	* notification. NXP Semiconductors also make no representation or
igorsk	0:1063a091a062	17	* warranty that such application will be suitable for the specified
igorsk	0:1063a091a062	18	* use without further testing or modification.
igorsk	0:1063a091a062	19	**************************************************************************/
igorsk	0:1063a091a062	20
igorsk	0:1063a091a062	21	/* Peripheral group ----------------------------------------------------------- */
igorsk	0:1063a091a062	22	/** @defgroup PWM
igorsk	0:1063a091a062	23	* @ingroup LPC1700CMSIS_FwLib_Drivers
igorsk	0:1063a091a062	24	* @{
igorsk	0:1063a091a062	25	*/
igorsk	0:1063a091a062	26
igorsk	0:1063a091a062	27	#ifndef LPC17XX_PWM_H_
igorsk	0:1063a091a062	28	#define LPC17XX_PWM_H_
igorsk	0:1063a091a062	29
igorsk	0:1063a091a062	30	/* Includes ------------------------------------------------------------------- */
igorsk	0:1063a091a062	31	#include "cmsis.h"
igorsk	0:1063a091a062	32	#include "lpc_types.h"
igorsk	0:1063a091a062	33
igorsk	0:1063a091a062	34
igorsk	0:1063a091a062	35	#ifdef __cplusplus
igorsk	0:1063a091a062	36	extern "C"
igorsk	0:1063a091a062	37	{
igorsk	0:1063a091a062	38	#endif
igorsk	0:1063a091a062	39
igorsk	0:1063a091a062	40
igorsk	0:1063a091a062	41	/* Private Macros ------------------------------------------------------------- */
igorsk	0:1063a091a062	42	/** @defgroup PWM_Private_Macros
igorsk	0:1063a091a062	43	* @{
igorsk	0:1063a091a062	44	*/
igorsk	0:1063a091a062	45
igorsk	0:1063a091a062	46	/** @defgroup PWM_REGISTER_BIT_DEFINITIONS
igorsk	0:1063a091a062	47	* @{
igorsk	0:1063a091a062	48	*/
igorsk	0:1063a091a062	49
igorsk	0:1063a091a062	50	/**********************************************************************
igorsk	0:1063a091a062	51	* IR register definitions
igorsk	0:1063a091a062	52	**********************************************************************/
igorsk	0:1063a091a062	53	/** Interrupt flag for PWM match channel for 6 channel */
igorsk	0:1063a091a062	54	#define PWM_IR_PWMMRn(n) ((uint32_t)((n<4)?(1<<n):(1<<(n+4))))
igorsk	0:1063a091a062	55	/** Interrupt flag for capture input */
igorsk	0:1063a091a062	56	#define PWM_IR_PWMCAPn(n) ((uint32_t)(1<<(n+4)))
igorsk	0:1063a091a062	57	/** IR register mask */
igorsk	0:1063a091a062	58	#define PWM_IR_BITMASK ((uint32_t)(0x0000073F))
igorsk	0:1063a091a062	59
igorsk	0:1063a091a062	60
igorsk	0:1063a091a062	61	/**********************************************************************
igorsk	0:1063a091a062	62	* TCR register definitions
igorsk	0:1063a091a062	63	**********************************************************************/
igorsk	0:1063a091a062	64	/** TCR register mask */
igorsk	0:1063a091a062	65	#define PWM_TCR_BITMASK ((uint32_t)(0x0000000B))
igorsk	0:1063a091a062	66	#define PWM_TCR_COUNTER_ENABLE ((uint32_t)(1<<0)) /!< PWM Counter Enable /
igorsk	0:1063a091a062	67	#define PWM_TCR_COUNTER_RESET ((uint32_t)(1<<1)) /!< PWM Counter Reset /
igorsk	0:1063a091a062	68	#define PWM_TCR_PWM_ENABLE ((uint32_t)(1<<3)) /!< PWM Enable /
igorsk	0:1063a091a062	69
igorsk	0:1063a091a062	70
igorsk	0:1063a091a062	71	/**********************************************************************
igorsk	0:1063a091a062	72	* CTCR register definitions
igorsk	0:1063a091a062	73	**********************************************************************/
igorsk	0:1063a091a062	74	/** CTCR register mask */
igorsk	0:1063a091a062	75	#define PWM_CTCR_BITMASK ((uint32_t)(0x0000000F))
igorsk	0:1063a091a062	76	/** PWM Counter-Timer Mode */
igorsk	0:1063a091a062	77	#define PWM_CTCR_MODE(n) ((uint32_t)(n&0x03))
igorsk	0:1063a091a062	78	/** PWM Capture input select */
igorsk	0:1063a091a062	79	#define PWM_CTCR_SELECT_INPUT(n) ((uint32_t)((n&0x03)<<2))
igorsk	0:1063a091a062	80
igorsk	0:1063a091a062	81
igorsk	0:1063a091a062	82	/**********************************************************************
igorsk	0:1063a091a062	83	* MCR register definitions
igorsk	0:1063a091a062	84	**********************************************************************/
igorsk	0:1063a091a062	85	/** MCR register mask */
igorsk	0:1063a091a062	86	#define PWM_MCR_BITMASK ((uint32_t)(0x001FFFFF))
igorsk	0:1063a091a062	87	/** generate a PWM interrupt when a MATCHn occurs */
igorsk	0:1063a091a062	88	#define PWM_MCR_INT_ON_MATCH(n) ((uint32_t)(1<<(((n&0x7)<<1)+(n&0x07))))
igorsk	0:1063a091a062	89	/** reset the PWM when a MATCHn occurs */
igorsk	0:1063a091a062	90	#define PWM_MCR_RESET_ON_MATCH(n) ((uint32_t)(1<<(((n&0x7)<<1)+(n&0x07)+1)))
igorsk	0:1063a091a062	91	/** stop the PWM when a MATCHn occurs */
igorsk	0:1063a091a062	92	#define PWM_MCR_STOP_ON_MATCH(n) ((uint32_t)(1<<(((n&0x7)<<1)+(n&0x07)+2)))
igorsk	0:1063a091a062	93
igorsk	0:1063a091a062	94
igorsk	0:1063a091a062	95	/**********************************************************************
igorsk	0:1063a091a062	96	* CCR register definitions
igorsk	0:1063a091a062	97	**********************************************************************/
igorsk	0:1063a091a062	98	/** CCR register mask */
igorsk	0:1063a091a062	99	#define PWM_CCR_BITMASK ((uint32_t)(0x0000003F))
igorsk	0:1063a091a062	100	/** PCAPn is rising edge sensitive */
igorsk	0:1063a091a062	101	#define PWM_CCR_CAP_RISING(n) ((uint32_t)(1<<(((n&0x2)<<1)+(n&0x1))))
igorsk	0:1063a091a062	102	/** PCAPn is falling edge sensitive */
igorsk	0:1063a091a062	103	#define PWM_CCR_CAP_FALLING(n) ((uint32_t)(1<<(((n&0x2)<<1)+(n&0x1)+1)))
igorsk	0:1063a091a062	104	/** PWM interrupt is generated on a PCAP event */
igorsk	0:1063a091a062	105	#define PWM_CCR_INT_ON_CAP(n) ((uint32_t)(1<<(((n&0x2)<<1)+(n&0x1)+2)))
igorsk	0:1063a091a062	106
igorsk	0:1063a091a062	107
igorsk	0:1063a091a062	108	/**********************************************************************
igorsk	0:1063a091a062	109	* PCR register definitions
igorsk	0:1063a091a062	110	**********************************************************************/
igorsk	0:1063a091a062	111	/** PCR register mask */
igorsk	0:1063a091a062	112	#define PWM_PCR_BITMASK (uint32_t)0x00007E7C
igorsk	0:1063a091a062	113	/** PWM output n is a single edge controlled output */
igorsk	0:1063a091a062	114	#define PWM_PCR_PWMSELn(n) ((uint32_t)(((n&0x7)<2) ? 0 : (1<<n)))
igorsk	0:1063a091a062	115	/** enable PWM output n */
igorsk	0:1063a091a062	116	#define PWM_PCR_PWMENAn(n) ((uint32_t)(((n&0x7)<1) ? 0 : (1<<(n+8))))
igorsk	0:1063a091a062	117
igorsk	0:1063a091a062	118
igorsk	0:1063a091a062	119	/**********************************************************************
igorsk	0:1063a091a062	120	* LER register definitions
igorsk	0:1063a091a062	121	**********************************************************************/
igorsk	0:1063a091a062	122	/** LER register mask*/
igorsk	0:1063a091a062	123	#define PWM_LER_BITMASK ((uint32_t)(0x0000007F))
igorsk	0:1063a091a062	124	/** PWM MATCHn register update control */
igorsk	0:1063a091a062	125	#define PWM_LER_EN_MATCHn_LATCH(n) ((uint32_t)((n<7) ? (1<<n) : 0))
igorsk	0:1063a091a062	126
igorsk	0:1063a091a062	127	/**
igorsk	0:1063a091a062	128	* @}
igorsk	0:1063a091a062	129	*/
igorsk	0:1063a091a062	130
igorsk	0:1063a091a062	131	/**
igorsk	0:1063a091a062	132	* @}
igorsk	0:1063a091a062	133	*/
igorsk	0:1063a091a062	134
igorsk	0:1063a091a062	135
igorsk	0:1063a091a062	136	/* Public Types --------------------------------------------------------------- */
igorsk	0:1063a091a062	137	/** @defgroup PWM_Public_Types
igorsk	0:1063a091a062	138	* @{
igorsk	0:1063a091a062	139	*/
igorsk	0:1063a091a062	140
igorsk	0:1063a091a062	141	/** @brief Configuration structure in PWM TIMER mode */
igorsk	0:1063a091a062	142	typedef struct {
igorsk	0:1063a091a062	143
igorsk	0:1063a091a062	144	uint8_t PrescaleOption; /**< Prescale option, should be:
igorsk	0:1063a091a062	145	- PWM_TIMER_PRESCALE_TICKVAL: Prescale in absolute value
igorsk	0:1063a091a062	146	- PWM_TIMER_PRESCALE_USVAL: Prescale in microsecond value
igorsk	0:1063a091a062	147	*/
igorsk	0:1063a091a062	148	uint8_t Reserved[3];
igorsk	0:1063a091a062	149	uint32_t PrescaleValue; /**< Prescale value, 32-bit long, should be matched
igorsk	0:1063a091a062	150	with PrescaleOption
igorsk	0:1063a091a062	151	*/
igorsk	0:1063a091a062	152	} PWM_TIMERCFG_Type;
igorsk	0:1063a091a062	153
igorsk	0:1063a091a062	154	/** @brief Configuration structure in PWM COUNTER mode */
igorsk	0:1063a091a062	155	typedef struct {
igorsk	0:1063a091a062	156
igorsk	0:1063a091a062	157	uint8_t CounterOption; /**< Counter Option, should be:
igorsk	0:1063a091a062	158	- PWM_COUNTER_RISING: Rising Edge
igorsk	0:1063a091a062	159	- PWM_COUNTER_FALLING: Falling Edge
igorsk	0:1063a091a062	160	- PWM_COUNTER_ANY: Both rising and falling mode
igorsk	0:1063a091a062	161	*/
igorsk	0:1063a091a062	162	uint8_t CountInputSelect; /**< Counter input select, should be:
igorsk	0:1063a091a062	163	- PWM_COUNTER_PCAP1_0: PWM Counter input selected is PCAP1.0 pin
igorsk	0:1063a091a062	164	- PWM_COUNTER_PCAP1_1: PWM Counter input selected is PCAP1.1 pin
igorsk	0:1063a091a062	165	*/
igorsk	0:1063a091a062	166	uint8_t Reserved[2];
igorsk	0:1063a091a062	167	} PWM_COUNTERCFG_Type;
igorsk	0:1063a091a062	168
igorsk	0:1063a091a062	169	/** @brief PWM Match channel configuration structure */
igorsk	0:1063a091a062	170	typedef struct {
igorsk	0:1063a091a062	171	uint8_t MatchChannel; /**< Match channel, should be in range
igorsk	0:1063a091a062	172	from 0..6 */
igorsk	0:1063a091a062	173	uint8_t IntOnMatch; /**< Interrupt On match, should be:
igorsk	0:1063a091a062	174	- ENABLE: Enable this function.
igorsk	0:1063a091a062	175	- DISABLE: Disable this function.
igorsk	0:1063a091a062	176	*/
igorsk	0:1063a091a062	177	uint8_t StopOnMatch; /**< Stop On match, should be:
igorsk	0:1063a091a062	178	- ENABLE: Enable this function.
igorsk	0:1063a091a062	179	- DISABLE: Disable this function.
igorsk	0:1063a091a062	180	*/
igorsk	0:1063a091a062	181	uint8_t ResetOnMatch; /**< Reset On match, should be:
igorsk	0:1063a091a062	182	- ENABLE: Enable this function.
igorsk	0:1063a091a062	183	- DISABLE: Disable this function.
igorsk	0:1063a091a062	184	*/
igorsk	0:1063a091a062	185	} PWM_MATCHCFG_Type;
igorsk	0:1063a091a062	186
igorsk	0:1063a091a062	187
igorsk	0:1063a091a062	188	/** @brief PWM Capture Input configuration structure */
igorsk	0:1063a091a062	189	typedef struct {
igorsk	0:1063a091a062	190	uint8_t CaptureChannel; /**< Capture channel, should be in range
igorsk	0:1063a091a062	191	from 0..1 */
igorsk	0:1063a091a062	192	uint8_t RisingEdge; /**< caption rising edge, should be:
igorsk	0:1063a091a062	193	- ENABLE: Enable rising edge.
igorsk	0:1063a091a062	194	- DISABLE: Disable this function.
igorsk	0:1063a091a062	195	*/
igorsk	0:1063a091a062	196	uint8_t FallingEdge; /**< caption falling edge, should be:
igorsk	0:1063a091a062	197	- ENABLE: Enable falling edge.
igorsk	0:1063a091a062	198	- DISABLE: Disable this function.
igorsk	0:1063a091a062	199	*/
igorsk	0:1063a091a062	200	uint8_t IntOnCaption; /**< Interrupt On caption, should be:
igorsk	0:1063a091a062	201	- ENABLE: Enable interrupt function.
igorsk	0:1063a091a062	202	- DISABLE: Disable this function.
igorsk	0:1063a091a062	203	*/
igorsk	0:1063a091a062	204	} PWM_CAPTURECFG_Type;
igorsk	0:1063a091a062	205
igorsk	0:1063a091a062	206
igorsk	0:1063a091a062	207	/** Macro to determine if it is valid PWM peripheral */
igorsk	0:1063a091a062	208	#define PARAM_PWMx(n) (((uint32_t )n)==((uint32_t )LPC_PWM1))
igorsk	0:1063a091a062	209
igorsk	0:1063a091a062	210	#define PARAM_PWM1_MATCH_CHANNEL(n) ((n<=6))
igorsk	0:1063a091a062	211	#define PARAM_PWM1_CHANNEL(n) ((n>=1) && (n<=6))
igorsk	0:1063a091a062	212	#define PARAM_PWM1_EDGE_MODE_CHANNEL(n) ((n>=2) && (n<=6))
igorsk	0:1063a091a062	213	#define PARAM_PWM1_CAPTURE_CHANNEL(n) ((n==0) \|\| (n==1))
igorsk	0:1063a091a062	214
igorsk	0:1063a091a062	215
igorsk	0:1063a091a062	216	/* Timer/Counter in PWM configuration type definition -----------------------------------*/
igorsk	0:1063a091a062	217
igorsk	0:1063a091a062	218	/** @brief PMW TC mode select option */
igorsk	0:1063a091a062	219	typedef enum {
igorsk	0:1063a091a062	220	PWM_MODE_TIMER = 0, /!< PWM using Timer mode /
igorsk	0:1063a091a062	221	PWM_MODE_COUNTER, /!< PWM using Counter mode /
igorsk	0:1063a091a062	222	} PWM_TC_MODE_OPT;
igorsk	0:1063a091a062	223
igorsk	0:1063a091a062	224	#define PARAM_PWM_TC_MODE(n) ((n==PWM_MODE_TIMER) \|\| (n==PWM_MODE_COUNTER))
igorsk	0:1063a091a062	225
igorsk	0:1063a091a062	226
igorsk	0:1063a091a062	227	/** @brief PWM Timer/Counter prescale option */
igorsk	0:1063a091a062	228	typedef enum
igorsk	0:1063a091a062	229	{
igorsk	0:1063a091a062	230	PWM_TIMER_PRESCALE_TICKVAL = 0, /!< Prescale in absolute value /
igorsk	0:1063a091a062	231	PWM_TIMER_PRESCALE_USVAL /!< Prescale in microsecond value /
igorsk	0:1063a091a062	232	} PWM_TIMER_PRESCALE_OPT;
igorsk	0:1063a091a062	233
igorsk	0:1063a091a062	234	#define PARAM_PWM_TIMER_PRESCALE(n) ((n==PWM_TIMER_PRESCALE_TICKVAL) \|\| (n==PWM_TIMER_PRESCALE_USVAL))
igorsk	0:1063a091a062	235
igorsk	0:1063a091a062	236
igorsk	0:1063a091a062	237	/** @brief PWM Input Select in counter mode */
igorsk	0:1063a091a062	238	typedef enum {
igorsk	0:1063a091a062	239	PWM_COUNTER_PCAP1_0 = 0, /!< PWM Counter input selected is PCAP1.0 pin /
igorsk	0:1063a091a062	240	PWM_COUNTER_PCAP1_1 /!< PWM counter input selected is CAP1.1 pin /
igorsk	0:1063a091a062	241	} PWM_COUNTER_INPUTSEL_OPT;
igorsk	0:1063a091a062	242
igorsk	0:1063a091a062	243	#define PARAM_PWM_COUNTER_INPUTSEL(n) ((n==PWM_COUNTER_PCAP1_0) \|\| (n==PWM_COUNTER_PCAP1_1))
igorsk	0:1063a091a062	244
igorsk	0:1063a091a062	245	/** @brief PWM Input Edge Option in counter mode */
igorsk	0:1063a091a062	246	typedef enum {
igorsk	0:1063a091a062	247	PWM_COUNTER_RISING = 1, /!< Rising edge mode /
igorsk	0:1063a091a062	248	PWM_COUNTER_FALLING = 2, /!< Falling edge mode /
igorsk	0:1063a091a062	249	PWM_COUNTER_ANY = 3 /!< Both rising and falling mode /
igorsk	0:1063a091a062	250	} PWM_COUNTER_EDGE_OPT;
igorsk	0:1063a091a062	251
igorsk	0:1063a091a062	252	#define PARAM_PWM_COUNTER_EDGE(n) ((n==PWM_COUNTER_RISING) \|\| (n==PWM_COUNTER_FALLING) \
igorsk	0:1063a091a062	253	\|\| (n==PWM_COUNTER_ANY))
igorsk	0:1063a091a062	254
igorsk	0:1063a091a062	255
igorsk	0:1063a091a062	256	/* PWM configuration type definition ----------------------------------------------------- */
igorsk	0:1063a091a062	257	/** @brief PWM operating mode options */
igorsk	0:1063a091a062	258	typedef enum {
igorsk	0:1063a091a062	259	PWM_CHANNEL_SINGLE_EDGE, /!< PWM Channel Single edge mode /
igorsk	0:1063a091a062	260	PWM_CHANNEL_DUAL_EDGE /!< PWM Channel Dual edge mode /
igorsk	0:1063a091a062	261	} PWM_CHANNEL_EDGE_OPT;
igorsk	0:1063a091a062	262
igorsk	0:1063a091a062	263	#define PARAM_PWM_CHANNEL_EDGE(n) ((n==PWM_CHANNEL_SINGLE_EDGE) \|\| (n==PWM_CHANNEL_DUAL_EDGE))
igorsk	0:1063a091a062	264
igorsk	0:1063a091a062	265
igorsk	0:1063a091a062	266	/** @brief PWM update type */
igorsk	0:1063a091a062	267	typedef enum {
igorsk	0:1063a091a062	268	PWM_MATCH_UPDATE_NOW = 0, /*< PWM Match Channel Update Now /
igorsk	0:1063a091a062	269	PWM_MATCH_UPDATE_NEXT_RST /**< PWM Match Channel Update on next
igorsk	0:1063a091a062	270	PWM Counter resetting */
igorsk	0:1063a091a062	271	} PWM_MATCH_UPDATE_OPT;
igorsk	0:1063a091a062	272
igorsk	0:1063a091a062	273	#define PARAM_PWM_MATCH_UPDATE(n) ((n==PWM_MATCH_UPDATE_NOW) \|\| (n==PWM_MATCH_UPDATE_NEXT_RST))
igorsk	0:1063a091a062	274
igorsk	0:1063a091a062	275
igorsk	0:1063a091a062	276	/** @brief PWM interrupt status type definition ----------------------------------------------------- */
igorsk	0:1063a091a062	277	/** @brief PWM Interrupt status type */
igorsk	0:1063a091a062	278	typedef enum
igorsk	0:1063a091a062	279	{
igorsk	0:1063a091a062	280	PWM_INTSTAT_MR0 = PWM_IR_PWMMRn(0), /*< Interrupt flag for PWM match channel 0 /
igorsk	0:1063a091a062	281	PWM_INTSTAT_MR1 = PWM_IR_PWMMRn(1), /*< Interrupt flag for PWM match channel 1 /
igorsk	0:1063a091a062	282	PWM_INTSTAT_MR2 = PWM_IR_PWMMRn(2), /*< Interrupt flag for PWM match channel 2 /
igorsk	0:1063a091a062	283	PWM_INTSTAT_MR3 = PWM_IR_PWMMRn(3), /*< Interrupt flag for PWM match channel 3 /
igorsk	0:1063a091a062	284	PWM_INTSTAT_CAP0 = PWM_IR_PWMCAPn(0), /*< Interrupt flag for capture input 0 /
igorsk	0:1063a091a062	285	PWM_INTSTAT_CAP1 = PWM_IR_PWMCAPn(1), /*< Interrupt flag for capture input 1 /
igorsk	0:1063a091a062	286	PWM_INTSTAT_MR4 = PWM_IR_PWMMRn(4), /*< Interrupt flag for PWM match channel 4 /
igorsk	0:1063a091a062	287	PWM_INTSTAT_MR6 = PWM_IR_PWMMRn(5), /*< Interrupt flag for PWM match channel 5 /
igorsk	0:1063a091a062	288	PWM_INTSTAT_MR5 = PWM_IR_PWMMRn(6), /*< Interrupt flag for PWM match channel 6 /
igorsk	0:1063a091a062	289	}PWM_INTSTAT_TYPE;
igorsk	0:1063a091a062	290
igorsk	0:1063a091a062	291	#define PARAM_PWM_INTSTAT(n) ((n==PWM_INTSTAT_MR0) \|\| (n==PWM_INTSTAT_MR1) \|\| (n==PWM_INTSTAT_MR2) \
igorsk	0:1063a091a062	292	\|\| (n==PWM_INTSTAT_MR3) \|\| (n==PWM_INTSTAT_MR4) \|\| (n==PWM_INTSTAT_MR5) \
igorsk	0:1063a091a062	293	\|\| (n==PWM_INTSTAT_MR6) \|\| (n==PWM_INTSTAT_CAP0) \|\| (n==PWM_INTSTAT_CAP1))
igorsk	0:1063a091a062	294
igorsk	0:1063a091a062	295	/**
igorsk	0:1063a091a062	296	* @}
igorsk	0:1063a091a062	297	*/
igorsk	0:1063a091a062	298
igorsk	0:1063a091a062	299
igorsk	0:1063a091a062	300	/* Public Functions ----------------------------------------------------------- */
igorsk	0:1063a091a062	301	/** @defgroup PWM_Public_Functions
igorsk	0:1063a091a062	302	* @{
igorsk	0:1063a091a062	303	*/
igorsk	0:1063a091a062	304
igorsk	0:1063a091a062	305	void PWM_PinConfig(LPC_PWM_TypeDef *PWMx, uint8_t PWM_Channel, uint8_t PinselOption);
igorsk	0:1063a091a062	306	IntStatus PWM_GetIntStatus(LPC_PWM_TypeDef *PWMx, uint32_t IntFlag);
igorsk	0:1063a091a062	307	void PWM_ClearIntPending(LPC_PWM_TypeDef *PWMx, uint32_t IntFlag);
igorsk	0:1063a091a062	308	void PWM_ConfigStructInit(uint8_t PWMTimerCounterMode, void *PWM_InitStruct);
igorsk	0:1063a091a062	309	void PWM_Init(LPC_PWM_TypeDef PWMx, uint32_t PWMTimerCounterMode, void PWM_ConfigStruct);
igorsk	0:1063a091a062	310	void PWM_DeInit (LPC_PWM_TypeDef *PWMx);
igorsk	0:1063a091a062	311	void PWM_Cmd(LPC_PWM_TypeDef *PWMx, FunctionalState NewState);
igorsk	0:1063a091a062	312	void PWM_CounterCmd(LPC_PWM_TypeDef *PWMx, FunctionalState NewState);
igorsk	0:1063a091a062	313	void PWM_ResetCounter(LPC_PWM_TypeDef *PWMx);
igorsk	0:1063a091a062	314	void PWM_ConfigMatch(LPC_PWM_TypeDef PWMx, PWM_MATCHCFG_Type PWM_MatchConfigStruct);
igorsk	0:1063a091a062	315	void PWM_ConfigCapture(LPC_PWM_TypeDef PWMx, PWM_CAPTURECFG_Type PWM_CaptureConfigStruct);
igorsk	0:1063a091a062	316	uint32_t PWM_GetCaptureValue(LPC_PWM_TypeDef *PWMx, uint8_t CaptureChannel);
igorsk	0:1063a091a062	317	void PWM_MatchUpdate(LPC_PWM_TypeDef *PWMx, uint8_t MatchChannel, \
igorsk	0:1063a091a062	318	uint32_t MatchValue, uint8_t UpdateType);
igorsk	0:1063a091a062	319	void PWM_ChannelConfig(LPC_PWM_TypeDef *PWMx, uint8_t PWMChannel, uint8_t ModeOption);
igorsk	0:1063a091a062	320	void PWM_ChannelCmd(LPC_PWM_TypeDef *PWMx, uint8_t PWMChannel, FunctionalState NewState);
igorsk	0:1063a091a062	321
igorsk	0:1063a091a062	322	/**
igorsk	0:1063a091a062	323	* @}
igorsk	0:1063a091a062	324	*/
igorsk	0:1063a091a062	325
igorsk	0:1063a091a062	326	#ifdef __cplusplus
igorsk	0:1063a091a062	327	}
igorsk	0:1063a091a062	328	#endif
igorsk	0:1063a091a062	329
igorsk	0:1063a091a062	330	#endif /* LPC17XX_PWM_H_ */
igorsk	0:1063a091a062	331
igorsk	0:1063a091a062	332	/**
igorsk	0:1063a091a062	333	* @}
igorsk	0:1063a091a062	334	*/
igorsk	0:1063a091a062	335
igorsk	0:1063a091a062	336	/* --------------------------------- End Of File ------------------------------ */

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Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	17 Feb 2010
Imports:	121
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	1
Followers:	5

include/lpc17xx_pwm.h@0:1063a091a062, 2010-02-17 (annotated)

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