DriverLibrary - NXP's driver library for LPC17xx, ported to mbed'…

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Igor Skochinsky / Mbed 2 deprecated DriverLibrary

NXP's driver library for LPC17xx, ported to mbed's online compiler. Not tested! I had to fix a lot of warings and found a couple of pretty obvious bugs, so the chances are there are more. Original: http://ics.nxp.com/support/documents/microcontrollers/zip/lpc17xx.cmsis.driver.library.zip

Dependencies: mbed

include/lpc17xx_emac.h@0:1063a091a062, 2010-02-17 (annotated)

Committer:: igorsk
Date:: Wed Feb 17 16:22:39 2010 +0000
Revision:: 0:1063a091a062

Who changed what in which revision?

User	Revision	Line number	New contents of line
igorsk	0:1063a091a062	1	/*********************************************************************//
igorsk	0:1063a091a062	2	* @file : lpc17xx_emac.h
igorsk	0:1063a091a062	3	* @brief : Contains all macro definitions and function prototypes
igorsk	0:1063a091a062	4	* support for Ethernet MAC firmware library on LPC17xx
igorsk	0:1063a091a062	5	* @version : 1.0
igorsk	0:1063a091a062	6	* @date : 02. Jun. 2009
igorsk	0:1063a091a062	7	* @author : HieuNguyen
igorsk	0:1063a091a062	8	**************************************************************************
igorsk	0:1063a091a062	9	* Software that is described herein is for illustrative purposes only
igorsk	0:1063a091a062	10	* which provides customers with programming information regarding the
igorsk	0:1063a091a062	11	* products. This software is supplied "AS IS" without any warranties.
igorsk	0:1063a091a062	12	* NXP Semiconductors assumes no responsibility or liability for the
igorsk	0:1063a091a062	13	* use of the software, conveys no license or title under any patent,
igorsk	0:1063a091a062	14	* copyright, or mask work right to the product. NXP Semiconductors
igorsk	0:1063a091a062	15	* reserves the right to make changes in the software without
igorsk	0:1063a091a062	16	* notification. NXP Semiconductors also make no representation or
igorsk	0:1063a091a062	17	* warranty that such application will be suitable for the specified
igorsk	0:1063a091a062	18	* use without further testing or modification.
igorsk	0:1063a091a062	19	**************************************************************************/
igorsk	0:1063a091a062	20
igorsk	0:1063a091a062	21	/* Peripheral group ----------------------------------------------------------- */
igorsk	0:1063a091a062	22	/** @defgroup EMAC
igorsk	0:1063a091a062	23	* @ingroup LPC1700CMSIS_FwLib_Drivers
igorsk	0:1063a091a062	24	* @{
igorsk	0:1063a091a062	25	*/
igorsk	0:1063a091a062	26
igorsk	0:1063a091a062	27	#ifndef LPC17XX_EMAC_H_
igorsk	0:1063a091a062	28	#define LPC17XX_EMAC_H_
igorsk	0:1063a091a062	29
igorsk	0:1063a091a062	30	/* Includes ------------------------------------------------------------------- */
igorsk	0:1063a091a062	31	#include "cmsis.h"
igorsk	0:1063a091a062	32	#include "lpc_types.h"
igorsk	0:1063a091a062	33
igorsk	0:1063a091a062	34
igorsk	0:1063a091a062	35	#ifdef __cplusplus
igorsk	0:1063a091a062	36	extern "C"
igorsk	0:1063a091a062	37	{
igorsk	0:1063a091a062	38	#endif
igorsk	0:1063a091a062	39
igorsk	0:1063a091a062	40
igorsk	0:1063a091a062	41	/* Private Macros ------------------------------------------------------------- */
igorsk	0:1063a091a062	42	/** @defgroup EMAC_Private_Macros
igorsk	0:1063a091a062	43	* @{
igorsk	0:1063a091a062	44	*/
igorsk	0:1063a091a062	45
igorsk	0:1063a091a062	46
igorsk	0:1063a091a062	47	/** @defgroup EMAC_REGISTER_BIT_DEFINITIONS
igorsk	0:1063a091a062	48	* @{
igorsk	0:1063a091a062	49	*/
igorsk	0:1063a091a062	50
igorsk	0:1063a091a062	51
igorsk	0:1063a091a062	52	/* EMAC Memory Buffer configuration for 16K Ethernet RAM */
igorsk	0:1063a091a062	53	#define EMAC_NUM_RX_FRAG 4 /*< Num.of RX Fragments 41536= 6.0kB */
igorsk	0:1063a091a062	54	#define EMAC_NUM_TX_FRAG 3 /*< Num.of TX Fragments 31536= 4.6kB */
igorsk	0:1063a091a062	55	#define EMAC_ETH_MAX_FLEN 1536 /*< Max. Ethernet Frame Size /
igorsk	0:1063a091a062	56	#define EMAC_TX_FRAME_TOUT 0x00100000 /*< Frame Transmit timeout count /
igorsk	0:1063a091a062	57
igorsk	0:1063a091a062	58	/* Ethernet MAC register definitions --------------------------------------------------------------------- */
igorsk	0:1063a091a062	59	/* MAC Configuration Register 1 */
igorsk	0:1063a091a062	60	#define EMAC_MAC1_REC_EN 0x00000001 /*< Receive Enable /
igorsk	0:1063a091a062	61	#define EMAC_MAC1_PASS_ALL 0x00000002 /*< Pass All Receive Frames /
igorsk	0:1063a091a062	62	#define EMAC_MAC1_RX_FLOWC 0x00000004 /*< RX Flow Control /
igorsk	0:1063a091a062	63	#define EMAC_MAC1_TX_FLOWC 0x00000008 /*< TX Flow Control /
igorsk	0:1063a091a062	64	#define EMAC_MAC1_LOOPB 0x00000010 /*< Loop Back Mode /
igorsk	0:1063a091a062	65	#define EMAC_MAC1_RES_TX 0x00000100 /*< Reset TX Logic /
igorsk	0:1063a091a062	66	#define EMAC_MAC1_RES_MCS_TX 0x00000200 /*< Reset MAC TX Control Sublayer /
igorsk	0:1063a091a062	67	#define EMAC_MAC1_RES_RX 0x00000400 /*< Reset RX Logic /
igorsk	0:1063a091a062	68	#define EMAC_MAC1_RES_MCS_RX 0x00000800 /*< Reset MAC RX Control Sublayer /
igorsk	0:1063a091a062	69	#define EMAC_MAC1_SIM_RES 0x00004000 /*< Simulation Reset /
igorsk	0:1063a091a062	70	#define EMAC_MAC1_SOFT_RES 0x00008000 /*< Soft Reset MAC /
igorsk	0:1063a091a062	71
igorsk	0:1063a091a062	72	/* MAC Configuration Register 2 */
igorsk	0:1063a091a062	73	#define EMAC_MAC2_FULL_DUP 0x00000001 /*< Full-Duplex Mode /
igorsk	0:1063a091a062	74	#define EMAC_MAC2_FRM_LEN_CHK 0x00000002 /*< Frame Length Checking /
igorsk	0:1063a091a062	75	#define EMAC_MAC2_HUGE_FRM_EN 0x00000004 /*< Huge Frame Enable /
igorsk	0:1063a091a062	76	#define EMAC_MAC2_DLY_CRC 0x00000008 /*< Delayed CRC Mode /
igorsk	0:1063a091a062	77	#define EMAC_MAC2_CRC_EN 0x00000010 /*< Append CRC to every Frame /
igorsk	0:1063a091a062	78	#define EMAC_MAC2_PAD_EN 0x00000020 /*< Pad all Short Frames /
igorsk	0:1063a091a062	79	#define EMAC_MAC2_VLAN_PAD_EN 0x00000040 /*< VLAN Pad Enable /
igorsk	0:1063a091a062	80	#define EMAC_MAC2_ADET_PAD_EN 0x00000080 /*< Auto Detect Pad Enable /
igorsk	0:1063a091a062	81	#define EMAC_MAC2_PPREAM_ENF 0x00000100 /*< Pure Preamble Enforcement /
igorsk	0:1063a091a062	82	#define EMAC_MAC2_LPREAM_ENF 0x00000200 /*< Long Preamble Enforcement /
igorsk	0:1063a091a062	83	#define EMAC_MAC2_NO_BACKOFF 0x00001000 /*< No Backoff Algorithm /
igorsk	0:1063a091a062	84	#define EMAC_MAC2_BACK_PRESSURE 0x00002000 /*< Backoff Presurre / No Backoff /
igorsk	0:1063a091a062	85	#define EMAC_MAC2_EXCESS_DEF 0x00004000 /*< Excess Defer /
igorsk	0:1063a091a062	86
igorsk	0:1063a091a062	87	/* Back-to-Back Inter-Packet-Gap Register */
igorsk	0:1063a091a062	88	/** Programmable field representing the nibble time offset of the minimum possible period
igorsk	0:1063a091a062	89	* between the end of any transmitted packet to the beginning of the next */
igorsk	0:1063a091a062	90	#define EMAC_IPGT_BBIPG(n) (n&0x7F)
igorsk	0:1063a091a062	91	/** Recommended value for Full Duplex of Programmable field representing the nibble time
igorsk	0:1063a091a062	92	* offset of the minimum possible period between the end of any transmitted packet to the
igorsk	0:1063a091a062	93	* beginning of the next */
igorsk	0:1063a091a062	94	#define EMAC_IPGT_FULL_DUP (EMAC_IPGT_BBIPG(0x15))
igorsk	0:1063a091a062	95	/** Recommended value for Half Duplex of Programmable field representing the nibble time
igorsk	0:1063a091a062	96	* offset of the minimum possible period between the end of any transmitted packet to the
igorsk	0:1063a091a062	97	* beginning of the next */
igorsk	0:1063a091a062	98	#define EMAC_IPGT_HALF_DUP (EMAC_IPGT_BBIPG(0x12))
igorsk	0:1063a091a062	99
igorsk	0:1063a091a062	100	/* Non Back-to-Back Inter-Packet-Gap Register */
igorsk	0:1063a091a062	101	/** Programmable field representing the Non-Back-to-Back Inter-Packet-Gap */
igorsk	0:1063a091a062	102	#define EMAC_IPGR_NBBIPG_P2(n) (n&0x7F)
igorsk	0:1063a091a062	103	/** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 1 */
igorsk	0:1063a091a062	104	#define EMAC_IPGR_P2_DEF (EMAC_IPGR_NBBIPG_P2(0x12))
igorsk	0:1063a091a062	105	/** Programmable field representing the optional carrierSense window referenced in
igorsk	0:1063a091a062	106	* IEEE 802.3/4.2.3.2.1 'Carrier Deference' */
igorsk	0:1063a091a062	107	#define EMAC_IPGR_NBBIPG_P1(n) ((n&0x7F)<<8)
igorsk	0:1063a091a062	108	/** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 2 */
igorsk	0:1063a091a062	109	#define EMAC_IPGR_P1_DEF EMAC_IPGR_NBBIPG_P1(0x0C)
igorsk	0:1063a091a062	110
igorsk	0:1063a091a062	111	/* Collision Window/Retry Register */
igorsk	0:1063a091a062	112	/** Programmable field specifying the number of retransmission attempts following a collision before
igorsk	0:1063a091a062	113	* aborting the packet due to excessive collisions */
igorsk	0:1063a091a062	114	#define EMAC_CLRT_MAX_RETX(n) (n&0x0F)
igorsk	0:1063a091a062	115	/** Programmable field representing the slot time or collision window during which collisions occur
igorsk	0:1063a091a062	116	* in properly configured networks */
igorsk	0:1063a091a062	117	#define EMAC_CLRT_COLL(n) ((n&0x3F)<<8)
igorsk	0:1063a091a062	118	/** Default value for Collision Window / Retry register */
igorsk	0:1063a091a062	119	#define EMAC_CLRT_DEF ((EMAC_CLRT_MAX_RETX(0x0F))\|(EMAC_CLRT_COLL(0x37)))
igorsk	0:1063a091a062	120
igorsk	0:1063a091a062	121	/* Maximum Frame Register */
igorsk	0:1063a091a062	122	/** Represents a maximum receive frame of 1536 octets */
igorsk	0:1063a091a062	123	#define EMAC_MAXF_MAXFRMLEN(n) (n&0xFFFF)
igorsk	0:1063a091a062	124
igorsk	0:1063a091a062	125	/* PHY Support Register */
igorsk	0:1063a091a062	126	#define EMAC_SUPP_SPEED 0x00000100 /*< Reduced MII Logic Current Speed /
igorsk	0:1063a091a062	127	#define EMAC_SUPP_RES_RMII 0x00000800 /*< Reset Reduced MII Logic /
igorsk	0:1063a091a062	128
igorsk	0:1063a091a062	129	/* Test Register */
igorsk	0:1063a091a062	130	#define EMAC_TEST_SHCUT_PQUANTA 0x00000001 /*< Shortcut Pause Quanta /
igorsk	0:1063a091a062	131	#define EMAC_TEST_TST_PAUSE 0x00000002 /*< Test Pause /
igorsk	0:1063a091a062	132	#define EMAC_TEST_TST_BACKP 0x00000004 /*< Test Back Pressure /
igorsk	0:1063a091a062	133
igorsk	0:1063a091a062	134	/* MII Management Configuration Register */
igorsk	0:1063a091a062	135	#define EMAC_MCFG_SCAN_INC 0x00000001 /*< Scan Increment PHY Address /
igorsk	0:1063a091a062	136	#define EMAC_MCFG_SUPP_PREAM 0x00000002 /*< Suppress Preamble /
igorsk	0:1063a091a062	137	#define EMAC_MCFG_CLK_SEL(n) ((n&0x0F)<<2) /*< Clock Select Field /
igorsk	0:1063a091a062	138	#define EMAC_MCFG_RES_MII 0x00008000 /*< Reset MII Management Hardware /
igorsk	0:1063a091a062	139	#define EMAC_MCFG_MII_MAXCLK 2500000UL /*< MII Clock max /
igorsk	0:1063a091a062	140
igorsk	0:1063a091a062	141	/* MII Management Command Register */
igorsk	0:1063a091a062	142	#define EMAC_MCMD_READ 0x00000001 /*< MII Read /
igorsk	0:1063a091a062	143	#define EMAC_MCMD_SCAN 0x00000002 /*< MII Scan continuously /
igorsk	0:1063a091a062	144
igorsk	0:1063a091a062	145	#define EMAC_MII_WR_TOUT 0x00050000 /*< MII Write timeout count /
igorsk	0:1063a091a062	146	#define EMAC_MII_RD_TOUT 0x00050000 /*< MII Read timeout count /
igorsk	0:1063a091a062	147
igorsk	0:1063a091a062	148	/* MII Management Address Register */
igorsk	0:1063a091a062	149	#define EMAC_MADR_REG_ADR(n) (n&0x1F) /*< MII Register Address field /
igorsk	0:1063a091a062	150	#define EMAC_MADR_PHY_ADR(n) ((n&0x1F)<<8) /*< PHY Address Field /
igorsk	0:1063a091a062	151
igorsk	0:1063a091a062	152	/* MII Management Write Data Register */
igorsk	0:1063a091a062	153	#define EMAC_MWTD_DATA(n) (n&0xFFFF) /*< Data field for MMI Management Write Data register /
igorsk	0:1063a091a062	154
igorsk	0:1063a091a062	155	/* MII Management Read Data Register */
igorsk	0:1063a091a062	156	#define EMAC_MRDD_DATA(n) (n&0xFFFF) /*< Data field for MMI Management Read Data register /
igorsk	0:1063a091a062	157
igorsk	0:1063a091a062	158	/* MII Management Indicators Register */
igorsk	0:1063a091a062	159	#define EMAC_MIND_BUSY 0x00000001 /*< MII is Busy /
igorsk	0:1063a091a062	160	#define EMAC_MIND_SCAN 0x00000002 /*< MII Scanning in Progress /
igorsk	0:1063a091a062	161	#define EMAC_MIND_NOT_VAL 0x00000004 /*< MII Read Data not valid /
igorsk	0:1063a091a062	162	#define EMAC_MIND_MII_LINK_FAIL 0x00000008 /*< MII Link Failed /
igorsk	0:1063a091a062	163
igorsk	0:1063a091a062	164	/* Station Address 0 Register */
igorsk	0:1063a091a062	165	/* Station Address 1 Register */
igorsk	0:1063a091a062	166	/* Station Address 2 Register */
igorsk	0:1063a091a062	167
igorsk	0:1063a091a062	168
igorsk	0:1063a091a062	169	/* Control register definitions --------------------------------------------------------------------------- */
igorsk	0:1063a091a062	170	/* Command Register */
igorsk	0:1063a091a062	171	#define EMAC_CR_RX_EN 0x00000001 /*< Enable Receive /
igorsk	0:1063a091a062	172	#define EMAC_CR_TX_EN 0x00000002 /*< Enable Transmit /
igorsk	0:1063a091a062	173	#define EMAC_CR_REG_RES 0x00000008 /*< Reset Host Registers /
igorsk	0:1063a091a062	174	#define EMAC_CR_TX_RES 0x00000010 /*< Reset Transmit Datapath /
igorsk	0:1063a091a062	175	#define EMAC_CR_RX_RES 0x00000020 /*< Reset Receive Datapath /
igorsk	0:1063a091a062	176	#define EMAC_CR_PASS_RUNT_FRM 0x00000040 /*< Pass Runt Frames /
igorsk	0:1063a091a062	177	#define EMAC_CR_PASS_RX_FILT 0x00000080 /*< Pass RX Filter /
igorsk	0:1063a091a062	178	#define EMAC_CR_TX_FLOW_CTRL 0x00000100 /*< TX Flow Control /
igorsk	0:1063a091a062	179	#define EMAC_CR_RMII 0x00000200 /*< Reduced MII Interface /
igorsk	0:1063a091a062	180	#define EMAC_CR_FULL_DUP 0x00000400 /*< Full Duplex /
igorsk	0:1063a091a062	181
igorsk	0:1063a091a062	182	/* Status Register */
igorsk	0:1063a091a062	183	#define EMAC_SR_RX_EN 0x00000001 /*< Enable Receive /
igorsk	0:1063a091a062	184	#define EMAC_SR_TX_EN 0x00000002 /*< Enable Transmit /
igorsk	0:1063a091a062	185
igorsk	0:1063a091a062	186	/* Receive Descriptor Base Address Register */
igorsk	0:1063a091a062	187	//
igorsk	0:1063a091a062	188
igorsk	0:1063a091a062	189	/* Receive Status Base Address Register */
igorsk	0:1063a091a062	190	//
igorsk	0:1063a091a062	191
igorsk	0:1063a091a062	192	/* Receive Number of Descriptors Register */
igorsk	0:1063a091a062	193	//
igorsk	0:1063a091a062	194
igorsk	0:1063a091a062	195	/* Receive Produce Index Register */
igorsk	0:1063a091a062	196	//
igorsk	0:1063a091a062	197
igorsk	0:1063a091a062	198	/* Receive Consume Index Register */
igorsk	0:1063a091a062	199	//
igorsk	0:1063a091a062	200
igorsk	0:1063a091a062	201	/* Transmit Descriptor Base Address Register */
igorsk	0:1063a091a062	202	//
igorsk	0:1063a091a062	203
igorsk	0:1063a091a062	204	/* Transmit Status Base Address Register */
igorsk	0:1063a091a062	205	//
igorsk	0:1063a091a062	206
igorsk	0:1063a091a062	207	/* Transmit Number of Descriptors Register */
igorsk	0:1063a091a062	208	//
igorsk	0:1063a091a062	209
igorsk	0:1063a091a062	210	/* Transmit Produce Index Register */
igorsk	0:1063a091a062	211	//
igorsk	0:1063a091a062	212
igorsk	0:1063a091a062	213	/* Transmit Consume Index Register */
igorsk	0:1063a091a062	214	//
igorsk	0:1063a091a062	215
igorsk	0:1063a091a062	216	/* Transmit Status Vector 0 Register */
igorsk	0:1063a091a062	217	#define EMAC_TSV0_CRC_ERR 0x00000001 /*< CRC error /
igorsk	0:1063a091a062	218	#define EMAC_TSV0_LEN_CHKERR 0x00000002 /*< Length Check Error /
igorsk	0:1063a091a062	219	#define EMAC_TSV0_LEN_OUTRNG 0x00000004 /*< Length Out of Range /
igorsk	0:1063a091a062	220	#define EMAC_TSV0_DONE 0x00000008 /*< Tramsmission Completed /
igorsk	0:1063a091a062	221	#define EMAC_TSV0_MCAST 0x00000010 /*< Multicast Destination /
igorsk	0:1063a091a062	222	#define EMAC_TSV0_BCAST 0x00000020 /*< Broadcast Destination /
igorsk	0:1063a091a062	223	#define EMAC_TSV0_PKT_DEFER 0x00000040 /*< Packet Deferred /
igorsk	0:1063a091a062	224	#define EMAC_TSV0_EXC_DEFER 0x00000080 /*< Excessive Packet Deferral /
igorsk	0:1063a091a062	225	#define EMAC_TSV0_EXC_COLL 0x00000100 /*< Excessive Collision /
igorsk	0:1063a091a062	226	#define EMAC_TSV0_LATE_COLL 0x00000200 /*< Late Collision Occured /
igorsk	0:1063a091a062	227	#define EMAC_TSV0_GIANT 0x00000400 /*< Giant Frame /
igorsk	0:1063a091a062	228	#define EMAC_TSV0_UNDERRUN 0x00000800 /*< Buffer Underrun /
igorsk	0:1063a091a062	229	#define EMAC_TSV0_BYTES 0x0FFFF000 /*< Total Bytes Transferred /
igorsk	0:1063a091a062	230	#define EMAC_TSV0_CTRL_FRAME 0x10000000 /*< Control Frame /
igorsk	0:1063a091a062	231	#define EMAC_TSV0_PAUSE 0x20000000 /*< Pause Frame /
igorsk	0:1063a091a062	232	#define EMAC_TSV0_BACK_PRESS 0x40000000 /*< Backpressure Method Applied /
igorsk	0:1063a091a062	233	#define EMAC_TSV0_VLAN 0x80000000 /*< VLAN Frame /
igorsk	0:1063a091a062	234
igorsk	0:1063a091a062	235	/* Transmit Status Vector 1 Register */
igorsk	0:1063a091a062	236	#define EMAC_TSV1_BYTE_CNT 0x0000FFFF /*< Transmit Byte Count /
igorsk	0:1063a091a062	237	#define EMAC_TSV1_COLL_CNT 0x000F0000 /*< Transmit Collision Count /
igorsk	0:1063a091a062	238
igorsk	0:1063a091a062	239	/* Receive Status Vector Register */
igorsk	0:1063a091a062	240	#define EMAC_RSV_BYTE_CNT 0x0000FFFF /*< Receive Byte Count /
igorsk	0:1063a091a062	241	#define EMAC_RSV_PKT_IGNORED 0x00010000 /*< Packet Previously Ignored /
igorsk	0:1063a091a062	242	#define EMAC_RSV_RXDV_SEEN 0x00020000 /*< RXDV Event Previously Seen /
igorsk	0:1063a091a062	243	#define EMAC_RSV_CARR_SEEN 0x00040000 /*< Carrier Event Previously Seen /
igorsk	0:1063a091a062	244	#define EMAC_RSV_REC_CODEV 0x00080000 /*< Receive Code Violation /
igorsk	0:1063a091a062	245	#define EMAC_RSV_CRC_ERR 0x00100000 /*< CRC Error /
igorsk	0:1063a091a062	246	#define EMAC_RSV_LEN_CHKERR 0x00200000 /*< Length Check Error /
igorsk	0:1063a091a062	247	#define EMAC_RSV_LEN_OUTRNG 0x00400000 /*< Length Out of Range /
igorsk	0:1063a091a062	248	#define EMAC_RSV_REC_OK 0x00800000 /*< Frame Received OK /
igorsk	0:1063a091a062	249	#define EMAC_RSV_MCAST 0x01000000 /*< Multicast Frame /
igorsk	0:1063a091a062	250	#define EMAC_RSV_BCAST 0x02000000 /*< Broadcast Frame /
igorsk	0:1063a091a062	251	#define EMAC_RSV_DRIB_NIBB 0x04000000 /*< Dribble Nibble /
igorsk	0:1063a091a062	252	#define EMAC_RSV_CTRL_FRAME 0x08000000 /*< Control Frame /
igorsk	0:1063a091a062	253	#define EMAC_RSV_PAUSE 0x10000000 /*< Pause Frame /
igorsk	0:1063a091a062	254	#define EMAC_RSV_UNSUPP_OPC 0x20000000 /*< Unsupported Opcode /
igorsk	0:1063a091a062	255	#define EMAC_RSV_VLAN 0x40000000 /*< VLAN Frame /
igorsk	0:1063a091a062	256
igorsk	0:1063a091a062	257	/* Flow Control Counter Register */
igorsk	0:1063a091a062	258	#define EMAC_FCC_MIRR_CNT(n) (n&0xFFFF) /*< Mirror Counter /
igorsk	0:1063a091a062	259	#define EMAC_FCC_PAUSE_TIM(n) ((n&0xFFFF)<<16) /*< Pause Timer /
igorsk	0:1063a091a062	260
igorsk	0:1063a091a062	261	/* Flow Control Status Register */
igorsk	0:1063a091a062	262	#define EMAC_FCS_MIRR_CNT(n) (n&0xFFFF) /*< Mirror Counter Current /
igorsk	0:1063a091a062	263
igorsk	0:1063a091a062	264
igorsk	0:1063a091a062	265	/* Receive filter register definitions -------------------------------------------------------- */
igorsk	0:1063a091a062	266	/* Receive Filter Control Register */
igorsk	0:1063a091a062	267	#define EMAC_RFC_UCAST_EN 0x00000001 /*< Accept Unicast Frames Enable /
igorsk	0:1063a091a062	268	#define EMAC_RFC_BCAST_EN 0x00000002 /*< Accept Broadcast Frames Enable /
igorsk	0:1063a091a062	269	#define EMAC_RFC_MCAST_EN 0x00000004 /*< Accept Multicast Frames Enable /
igorsk	0:1063a091a062	270	#define EMAC_RFC_UCAST_HASH_EN 0x00000008 /*< Accept Unicast Hash Filter Frames /
igorsk	0:1063a091a062	271	#define EMAC_RFC_MCAST_HASH_EN 0x00000010 /*< Accept Multicast Hash Filter Fram./
igorsk	0:1063a091a062	272	#define EMAC_RFC_PERFECT_EN 0x00000020 /*< Accept Perfect Match Enable /
igorsk	0:1063a091a062	273	#define EMAC_RFC_MAGP_WOL_EN 0x00001000 /*< Magic Packet Filter WoL Enable /
igorsk	0:1063a091a062	274	#define EMAC_RFC_PFILT_WOL_EN 0x00002000 /*< Perfect Filter WoL Enable /
igorsk	0:1063a091a062	275
igorsk	0:1063a091a062	276	/* Receive Filter WoL Status/Clear Registers */
igorsk	0:1063a091a062	277	#define EMAC_WOL_UCAST 0x00000001 /*< Unicast Frame caused WoL /
igorsk	0:1063a091a062	278	#define EMAC_WOL_BCAST 0x00000002 /*< Broadcast Frame caused WoL /
igorsk	0:1063a091a062	279	#define EMAC_WOL_MCAST 0x00000004 /*< Multicast Frame caused WoL /
igorsk	0:1063a091a062	280	#define EMAC_WOL_UCAST_HASH 0x00000008 /*< Unicast Hash Filter Frame WoL /
igorsk	0:1063a091a062	281	#define EMAC_WOL_MCAST_HASH 0x00000010 /*< Multicast Hash Filter Frame WoL /
igorsk	0:1063a091a062	282	#define EMAC_WOL_PERFECT 0x00000020 /*< Perfect Filter WoL /
igorsk	0:1063a091a062	283	#define EMAC_WOL_RX_FILTER 0x00000080 /*< RX Filter caused WoL /
igorsk	0:1063a091a062	284	#define EMAC_WOL_MAG_PACKET 0x00000100 /*< Magic Packet Filter caused WoL /
igorsk	0:1063a091a062	285	#define EMAC_WOL_BITMASK 0x01BF /*< Receive Filter WoL Status/Clear bitmasl value /
igorsk	0:1063a091a062	286
igorsk	0:1063a091a062	287	/* Hash Filter Table LSBs Register */
igorsk	0:1063a091a062	288	//
igorsk	0:1063a091a062	289
igorsk	0:1063a091a062	290	/* Hash Filter Table MSBs Register */
igorsk	0:1063a091a062	291	//
igorsk	0:1063a091a062	292
igorsk	0:1063a091a062	293
igorsk	0:1063a091a062	294	/* Module control register definitions ---------------------------------------------------- */
igorsk	0:1063a091a062	295	/* Interrupt Status/Enable/Clear/Set Registers */
igorsk	0:1063a091a062	296	#define EMAC_INT_RX_OVERRUN 0x00000001 /*< Overrun Error in RX Queue /
igorsk	0:1063a091a062	297	#define EMAC_INT_RX_ERR 0x00000002 /*< Receive Error /
igorsk	0:1063a091a062	298	#define EMAC_INT_RX_FIN 0x00000004 /*< RX Finished Process Descriptors /
igorsk	0:1063a091a062	299	#define EMAC_INT_RX_DONE 0x00000008 /*< Receive Done /
igorsk	0:1063a091a062	300	#define EMAC_INT_TX_UNDERRUN 0x00000010 /*< Transmit Underrun /
igorsk	0:1063a091a062	301	#define EMAC_INT_TX_ERR 0x00000020 /*< Transmit Error /
igorsk	0:1063a091a062	302	#define EMAC_INT_TX_FIN 0x00000040 /*< TX Finished Process Descriptors /
igorsk	0:1063a091a062	303	#define EMAC_INT_TX_DONE 0x00000080 /*< Transmit Done /
igorsk	0:1063a091a062	304	#define EMAC_INT_SOFT_INT 0x00001000 /*< Software Triggered Interrupt /
igorsk	0:1063a091a062	305	#define EMAC_INT_WAKEUP 0x00002000 /*< Wakeup Event Interrupt /
igorsk	0:1063a091a062	306
igorsk	0:1063a091a062	307	/* Power Down Register */
igorsk	0:1063a091a062	308	#define EMAC_PD_POWER_DOWN 0x80000000 /*< Power Down MAC /
igorsk	0:1063a091a062	309
igorsk	0:1063a091a062	310	/* RX Descriptor Control Word */
igorsk	0:1063a091a062	311	#define EMAC_RCTRL_SIZE(n) (n&0x7FF) /*< Buffer size field /
igorsk	0:1063a091a062	312	#define EMAC_RCTRL_INT 0x80000000 /*< Generate RxDone Interrupt /
igorsk	0:1063a091a062	313
igorsk	0:1063a091a062	314	/* RX Status Hash CRC Word */
igorsk	0:1063a091a062	315	#define EMAC_RHASH_SA 0x000001FF /*< Hash CRC for Source Address /
igorsk	0:1063a091a062	316	#define EMAC_RHASH_DA 0x001FF000 /*< Hash CRC for Destination Address /
igorsk	0:1063a091a062	317
igorsk	0:1063a091a062	318	/* RX Status Information Word */
igorsk	0:1063a091a062	319	#define EMAC_RINFO_SIZE 0x000007FF /*< Data size in bytes /
igorsk	0:1063a091a062	320	#define EMAC_RINFO_CTRL_FRAME 0x00040000 /*< Control Frame /
igorsk	0:1063a091a062	321	#define EMAC_RINFO_VLAN 0x00080000 /*< VLAN Frame /
igorsk	0:1063a091a062	322	#define EMAC_RINFO_FAIL_FILT 0x00100000 /*< RX Filter Failed /
igorsk	0:1063a091a062	323	#define EMAC_RINFO_MCAST 0x00200000 /*< Multicast Frame /
igorsk	0:1063a091a062	324	#define EMAC_RINFO_BCAST 0x00400000 /*< Broadcast Frame /
igorsk	0:1063a091a062	325	#define EMAC_RINFO_CRC_ERR 0x00800000 /*< CRC Error in Frame /
igorsk	0:1063a091a062	326	#define EMAC_RINFO_SYM_ERR 0x01000000 /*< Symbol Error from PHY /
igorsk	0:1063a091a062	327	#define EMAC_RINFO_LEN_ERR 0x02000000 /*< Length Error /
igorsk	0:1063a091a062	328	#define EMAC_RINFO_RANGE_ERR 0x04000000 /*< Range Error (exceeded max. size) /
igorsk	0:1063a091a062	329	#define EMAC_RINFO_ALIGN_ERR 0x08000000 /*< Alignment Error /
igorsk	0:1063a091a062	330	#define EMAC_RINFO_OVERRUN 0x10000000 /*< Receive overrun /
igorsk	0:1063a091a062	331	#define EMAC_RINFO_NO_DESCR 0x20000000 /*< No new Descriptor available /
igorsk	0:1063a091a062	332	#define EMAC_RINFO_LAST_FLAG 0x40000000 /*< Last Fragment in Frame /
igorsk	0:1063a091a062	333	#define EMAC_RINFO_ERR 0x80000000 /*< Error Occured (OR of all errors) /
igorsk	0:1063a091a062	334
igorsk	0:1063a091a062	335	/** RX Status Information word mask */
igorsk	0:1063a091a062	336	#define EMAC_RINFO_ERR_MASK (EMAC_RINFO_FAIL_FILT \| EMAC_RINFO_CRC_ERR \| EMAC_RINFO_SYM_ERR \| \
igorsk	0:1063a091a062	337	EMAC_RINFO_LEN_ERR \| EMAC_RINFO_ALIGN_ERR \| EMAC_RINFO_OVERRUN)
igorsk	0:1063a091a062	338
igorsk	0:1063a091a062	339	/* TX Descriptor Control Word */
igorsk	0:1063a091a062	340	#define EMAC_TCTRL_SIZE 0x000007FF /*< Size of data buffer in bytes /
igorsk	0:1063a091a062	341	#define EMAC_TCTRL_OVERRIDE 0x04000000 /*< Override Default MAC Registers /
igorsk	0:1063a091a062	342	#define EMAC_TCTRL_HUGE 0x08000000 /*< Enable Huge Frame /
igorsk	0:1063a091a062	343	#define EMAC_TCTRL_PAD 0x10000000 /*< Pad short Frames to 64 bytes /
igorsk	0:1063a091a062	344	#define EMAC_TCTRL_CRC 0x20000000 /*< Append a hardware CRC to Frame /
igorsk	0:1063a091a062	345	#define EMAC_TCTRL_LAST 0x40000000 /*< Last Descriptor for TX Frame /
igorsk	0:1063a091a062	346	#define EMAC_TCTRL_INT 0x80000000 /*< Generate TxDone Interrupt /
igorsk	0:1063a091a062	347
igorsk	0:1063a091a062	348	/* TX Status Information Word */
igorsk	0:1063a091a062	349	#define EMAC_TINFO_COL_CNT 0x01E00000 /*< Collision Count /
igorsk	0:1063a091a062	350	#define EMAC_TINFO_DEFER 0x02000000 /*< Packet Deferred (not an error) /
igorsk	0:1063a091a062	351	#define EMAC_TINFO_EXCESS_DEF 0x04000000 /*< Excessive Deferral /
igorsk	0:1063a091a062	352	#define EMAC_TINFO_EXCESS_COL 0x08000000 /*< Excessive Collision /
igorsk	0:1063a091a062	353	#define EMAC_TINFO_LATE_COL 0x10000000 /*< Late Collision Occured /
igorsk	0:1063a091a062	354	#define EMAC_TINFO_UNDERRUN 0x20000000 /*< Transmit Underrun /
igorsk	0:1063a091a062	355	#define EMAC_TINFO_NO_DESCR 0x40000000 /*< No new Descriptor available /
igorsk	0:1063a091a062	356	#define EMAC_TINFO_ERR 0x80000000 /*< Error Occured (OR of all errors) /
igorsk	0:1063a091a062	357
igorsk	0:1063a091a062	358
igorsk	0:1063a091a062	359	/* DP83848C PHY definition ------------------------------------------------------------ */
igorsk	0:1063a091a062	360
igorsk	0:1063a091a062	361	/** PHY device reset time out definition */
igorsk	0:1063a091a062	362	#define EMAC_PHY_RESP_TOUT 0x100000UL
igorsk	0:1063a091a062	363
igorsk	0:1063a091a062	364	/* ENET Device Revision ID */
igorsk	0:1063a091a062	365	#define EMAC_OLD_EMAC_MODULE_ID 0x39022000 /*< Rev. ID for first rev '-' /
igorsk	0:1063a091a062	366
igorsk	0:1063a091a062	367	/* DP83848C PHY Registers */
igorsk	0:1063a091a062	368	#define EMAC_PHY_REG_BMCR 0x00 /*< Basic Mode Control Register /
igorsk	0:1063a091a062	369	#define EMAC_PHY_REG_BMSR 0x01 /*< Basic Mode Status Register /
igorsk	0:1063a091a062	370	#define EMAC_PHY_REG_IDR1 0x02 /*< PHY Identifier 1 /
igorsk	0:1063a091a062	371	#define EMAC_PHY_REG_IDR2 0x03 /*< PHY Identifier 2 /
igorsk	0:1063a091a062	372	#define EMAC_PHY_REG_ANAR 0x04 /*< Auto-Negotiation Advertisement /
igorsk	0:1063a091a062	373	#define EMAC_PHY_REG_ANLPAR 0x05 /*< Auto-Neg. Link Partner Abitily /
igorsk	0:1063a091a062	374	#define EMAC_PHY_REG_ANER 0x06 /*< Auto-Neg. Expansion Register /
igorsk	0:1063a091a062	375	#define EMAC_PHY_REG_ANNPTR 0x07 /*< Auto-Neg. Next Page TX /
igorsk	0:1063a091a062	376	#define EMAC_PHY_REG_LPNPA 0x08
igorsk	0:1063a091a062	377
igorsk	0:1063a091a062	378
igorsk	0:1063a091a062	379	/* PHY Extended Registers */
igorsk	0:1063a091a062	380	#define EMAC_PHY_REG_STS 0x10 /*< Status Register /
igorsk	0:1063a091a062	381	#define EMAC_PHY_REG_MICR 0x11 /*< MII Interrupt Control Register /
igorsk	0:1063a091a062	382	#define EMAC_PHY_REG_MISR 0x12 /*< MII Interrupt Status Register /
igorsk	0:1063a091a062	383	#define EMAC_PHY_REG_FCSCR 0x14 /*< False Carrier Sense Counter /
igorsk	0:1063a091a062	384	#define EMAC_PHY_REG_RECR 0x15 /*< Receive Error Counter /
igorsk	0:1063a091a062	385	#define EMAC_PHY_REG_PCSR 0x16 /*< PCS Sublayer Config. and Status /
igorsk	0:1063a091a062	386	#define EMAC_PHY_REG_RBR 0x17 /*< RMII and Bypass Register /
igorsk	0:1063a091a062	387	#define EMAC_PHY_REG_LEDCR 0x18 /*< LED Direct Control Register /
igorsk	0:1063a091a062	388	#define EMAC_PHY_REG_PHYCR 0x19 /*< PHY Control Register /
igorsk	0:1063a091a062	389	#define EMAC_PHY_REG_10BTSCR 0x1A /*< 10Base-T Status/Control Register /
igorsk	0:1063a091a062	390	#define EMAC_PHY_REG_CDCTRL1 0x1B /*< CD Test Control and BIST Extens. /
igorsk	0:1063a091a062	391	#define EMAC_PHY_REG_EDCR 0x1D /*< Energy Detect Control Register /
igorsk	0:1063a091a062	392
igorsk	0:1063a091a062	393
igorsk	0:1063a091a062	394	/* PHY Basic Mode Control Register (BMCR) bitmap definitions */
igorsk	0:1063a091a062	395	#define EMAC_PHY_BMCR_RESET (1<<15) /*< Reset bit /
igorsk	0:1063a091a062	396	#define EMAC_PHY_BMCR_LOOPBACK (1<<14) /*< Loop back /
igorsk	0:1063a091a062	397	#define EMAC_PHY_BMCR_SPEED_SEL (1<<13) /*< Speed selection /
igorsk	0:1063a091a062	398	#define EMAC_PHY_BMCR_AN (1<<12) /*< Auto Negotiation /
igorsk	0:1063a091a062	399	#define EMAC_PHY_BMCR_POWERDOWN (1<<11) /*< Power down mode /
igorsk	0:1063a091a062	400	#define EMAC_PHY_BMCR_ISOLATE (1<<10) /*< Isolate /
igorsk	0:1063a091a062	401	#define EMAC_PHY_BMCR_RE_AN (1<<9) /*< Restart auto negotiation /
igorsk	0:1063a091a062	402	#define EMAC_PHY_BMCR_DUPLEX (1<<8) /*< Duplex mode /
igorsk	0:1063a091a062	403
igorsk	0:1063a091a062	404	/* PHY Basic Mode Status Status Register (BMSR) bitmap definitions */
igorsk	0:1063a091a062	405	#define EMAC_PHY_BMSR_100BE_T4 (1<<15) /*< 100 base T4 /
igorsk	0:1063a091a062	406	#define EMAC_PHY_BMSR_100TX_FULL (1<<14) /*< 100 base full duplex /
igorsk	0:1063a091a062	407	#define EMAC_PHY_BMSR_100TX_HALF (1<<13) /*< 100 base half duplex /
igorsk	0:1063a091a062	408	#define EMAC_PHY_BMSR_10BE_FULL (1<<12) /*< 10 base T full duplex /
igorsk	0:1063a091a062	409	#define EMAC_PHY_BMSR_10BE_HALF (1<<11) /*< 10 base T half duplex /
igorsk	0:1063a091a062	410	#define EMAC_PHY_BMSR_NOPREAM (1<<6) /*< MF Preamable Supress /
igorsk	0:1063a091a062	411	#define EMAC_PHY_BMSR_AUTO_DONE (1<<5) /*< Auto negotiation complete /
igorsk	0:1063a091a062	412	#define EMAC_PHY_BMSR_REMOTE_FAULT (1<<4) /*< Remote fault /
igorsk	0:1063a091a062	413	#define EMAC_PHY_BMSR_NO_AUTO (1<<3) /*< Auto Negotiation ability /
igorsk	0:1063a091a062	414	#define EMAC_PHY_BMSR_LINK_ESTABLISHED (1<<2) /*< Link status /
igorsk	0:1063a091a062	415
igorsk	0:1063a091a062	416	/* PHY Status Register bitmap definitions */
igorsk	0:1063a091a062	417	#define EMAC_PHY_SR_REMOTE_FAULT (1<<6) /*< Remote Fault /
igorsk	0:1063a091a062	418	#define EMAC_PHY_SR_JABBER (1<<5) /*< Jabber detect /
igorsk	0:1063a091a062	419	#define EMAC_PHY_SR_AUTO_DONE (1<<4) /*< Auto Negotiation complete /
igorsk	0:1063a091a062	420	#define EMAC_PHY_SR_LOOPBACK (1<<3) /*< Loop back status /
igorsk	0:1063a091a062	421	#define EMAC_PHY_SR_DUP (1<<2) /*< Duplex status /
igorsk	0:1063a091a062	422	#define EMAC_PHY_SR_SPEED (1<<1) /*< Speed status /
igorsk	0:1063a091a062	423	#define EMAC_PHY_SR_LINK (1<<0) /*< Link Status /
igorsk	0:1063a091a062	424
igorsk	0:1063a091a062	425
igorsk	0:1063a091a062	426	#define EMAC_PHY_FULLD_100M 0x2100 /*< Full Duplex 100Mbit /
igorsk	0:1063a091a062	427	#define EMAC_PHY_HALFD_100M 0x2000 /*< Half Duplex 100Mbit /
igorsk	0:1063a091a062	428	#define EMAC_PHY_FULLD_10M 0x0100 /*< Full Duplex 10Mbit /
igorsk	0:1063a091a062	429	#define EMAC_PHY_HALFD_10M 0x0000 /*< Half Duplex 10MBit /
igorsk	0:1063a091a062	430	#define EMAC_PHY_AUTO_NEG 0x3000 /*< Select Auto Negotiation /
igorsk	0:1063a091a062	431
igorsk	0:1063a091a062	432	#define EMAC_DP83848C_DEF_ADR 0x0100 /*< Default PHY device address /
igorsk	0:1063a091a062	433	#define EMAC_DP83848C_ID 0x20005C90 /*< PHY Identifier /
igorsk	0:1063a091a062	434
igorsk	0:1063a091a062	435
igorsk	0:1063a091a062	436	/**
igorsk	0:1063a091a062	437	* @}
igorsk	0:1063a091a062	438	*/
igorsk	0:1063a091a062	439
igorsk	0:1063a091a062	440	/**
igorsk	0:1063a091a062	441	* @}
igorsk	0:1063a091a062	442	*/
igorsk	0:1063a091a062	443
igorsk	0:1063a091a062	444
igorsk	0:1063a091a062	445	/* Public Types --------------------------------------------------------------- */
igorsk	0:1063a091a062	446	/** @defgroup EMAC_Public_Types
igorsk	0:1063a091a062	447	* @{
igorsk	0:1063a091a062	448	*/
igorsk	0:1063a091a062	449
igorsk	0:1063a091a062	450	/* Descriptor and status formats ---------------------------------------------- */
igorsk	0:1063a091a062	451
igorsk	0:1063a091a062	452	/**
igorsk	0:1063a091a062	453	* @brief RX Descriptor structure type definition
igorsk	0:1063a091a062	454	*/
igorsk	0:1063a091a062	455	typedef struct {
igorsk	0:1063a091a062	456	uint32_t Packet; /*< Receive Packet Descriptor /
igorsk	0:1063a091a062	457	uint32_t Ctrl; /*< Receive Control Descriptor /
igorsk	0:1063a091a062	458	} RX_Desc;
igorsk	0:1063a091a062	459
igorsk	0:1063a091a062	460	/**
igorsk	0:1063a091a062	461	* @brief RX Status structure type definition
igorsk	0:1063a091a062	462	*/
igorsk	0:1063a091a062	463	typedef struct {
igorsk	0:1063a091a062	464	uint32_t Info; /*< Receive Information Status /
igorsk	0:1063a091a062	465	uint32_t HashCRC; /*< Receive Hash CRC Status /
igorsk	0:1063a091a062	466	} RX_Stat;
igorsk	0:1063a091a062	467
igorsk	0:1063a091a062	468	/**
igorsk	0:1063a091a062	469	* @brief TX Descriptor structure type definition
igorsk	0:1063a091a062	470	*/
igorsk	0:1063a091a062	471	typedef struct {
igorsk	0:1063a091a062	472	uint32_t Packet; /*< Transmit Packet Descriptor /
igorsk	0:1063a091a062	473	uint32_t Ctrl; /*< Transmit Control Descriptor /
igorsk	0:1063a091a062	474	} TX_Desc;
igorsk	0:1063a091a062	475
igorsk	0:1063a091a062	476	/**
igorsk	0:1063a091a062	477	* @brief TX Status structure type definition
igorsk	0:1063a091a062	478	*/
igorsk	0:1063a091a062	479	typedef struct {
igorsk	0:1063a091a062	480	uint32_t Info; /*< Transmit Information Status /
igorsk	0:1063a091a062	481	} TX_Stat;
igorsk	0:1063a091a062	482
igorsk	0:1063a091a062	483
igorsk	0:1063a091a062	484	/**
igorsk	0:1063a091a062	485	* @brief TX Data Buffer structure definition
igorsk	0:1063a091a062	486	*/
igorsk	0:1063a091a062	487	typedef struct {
igorsk	0:1063a091a062	488	uint32_t ulDataLen; /*< Data length /
igorsk	0:1063a091a062	489	uint32_t pbDataBuf; /< A word-align data pointer to data buffer /
igorsk	0:1063a091a062	490	} EMAC_PACKETBUF_Type;
igorsk	0:1063a091a062	491
igorsk	0:1063a091a062	492	/**
igorsk	0:1063a091a062	493	* @brief EMAC configuration structure definition
igorsk	0:1063a091a062	494	*/
igorsk	0:1063a091a062	495	typedef struct {
igorsk	0:1063a091a062	496	uint32_t Mode; /**< Supported EMAC PHY device speed, should be one of the following:
igorsk	0:1063a091a062	497	- EMAC_MODE_AUTO
igorsk	0:1063a091a062	498	- EMAC_MODE_10M_FULL
igorsk	0:1063a091a062	499	- EMAC_MODE_10M_HALF
igorsk	0:1063a091a062	500	- EMAC_MODE_100M_FULL
igorsk	0:1063a091a062	501	- EMAC_MODE_100M_HALF
igorsk	0:1063a091a062	502	*/
igorsk	0:1063a091a062	503	uint8_t pbEMAC_Addr; /*< Pointer to EMAC Station address that contains 6-bytes
igorsk	0:1063a091a062	504	of MAC address, it must be sorted in order (bEMAC_Addr[0]..[5])
igorsk	0:1063a091a062	505	*/
igorsk	0:1063a091a062	506	} EMAC_CFG_Type;
igorsk	0:1063a091a062	507
igorsk	0:1063a091a062	508	/** EMAC Call back function type definition */
igorsk	0:1063a091a062	509	typedef void (EMAC_IntCBSType)(void);
igorsk	0:1063a091a062	510
igorsk	0:1063a091a062	511
igorsk	0:1063a091a062	512	/**
igorsk	0:1063a091a062	513	* @}
igorsk	0:1063a091a062	514	*/
igorsk	0:1063a091a062	515
igorsk	0:1063a091a062	516
igorsk	0:1063a091a062	517	/* Public Macros -------------------------------------------------------------- */
igorsk	0:1063a091a062	518	/** @defgroup EMAC_Public_Macros
igorsk	0:1063a091a062	519	* @{
igorsk	0:1063a091a062	520	*/
igorsk	0:1063a091a062	521
igorsk	0:1063a091a062	522
igorsk	0:1063a091a062	523	/* EMAC PHY status type definitions */
igorsk	0:1063a091a062	524	#define EMAC_PHY_STAT_LINK (0) /*< Link Status /
igorsk	0:1063a091a062	525	#define EMAC_PHY_STAT_SPEED (1) /*< Speed Status /
igorsk	0:1063a091a062	526	#define EMAC_PHY_STAT_DUP (2) /*< Duplex Status /
igorsk	0:1063a091a062	527
igorsk	0:1063a091a062	528	/* EMAC PHY device Speed definitions */
igorsk	0:1063a091a062	529	#define EMAC_MODE_AUTO (0) /*< Auto-negotiation mode /
igorsk	0:1063a091a062	530	#define EMAC_MODE_10M_FULL (1) /*< 10Mbps FullDuplex mode /
igorsk	0:1063a091a062	531	#define EMAC_MODE_10M_HALF (2) /*< 10Mbps HalfDuplex mode /
igorsk	0:1063a091a062	532	#define EMAC_MODE_100M_FULL (3) /*< 100Mbps FullDuplex mode /
igorsk	0:1063a091a062	533	#define EMAC_MODE_100M_HALF (4) /*< 100Mbps HalfDuplex mode /
igorsk	0:1063a091a062	534
igorsk	0:1063a091a062	535	/**
igorsk	0:1063a091a062	536	* @}
igorsk	0:1063a091a062	537	*/
igorsk	0:1063a091a062	538
igorsk	0:1063a091a062	539
igorsk	0:1063a091a062	540	/* Public Functions ----------------------------------------------------------- */
igorsk	0:1063a091a062	541	/** @defgroup EMAC_Public_Functions
igorsk	0:1063a091a062	542	* @{
igorsk	0:1063a091a062	543	*/
igorsk	0:1063a091a062	544
igorsk	0:1063a091a062	545	Status EMAC_Init(EMAC_CFG_Type *EMAC_ConfigStruct);
igorsk	0:1063a091a062	546	void EMAC_DeInit(void);
igorsk	0:1063a091a062	547	int32_t EMAC_CheckPHYStatus(uint32_t ulPHYState);
igorsk	0:1063a091a062	548	int32_t EMAC_SetPHYMode(uint32_t ulPHYMode);
igorsk	0:1063a091a062	549	int32_t EMAC_UpdatePHYStatus(void);
igorsk	0:1063a091a062	550	void EMAC_SetHashFilter(uint8_t dstMAC_addr[], FunctionalState NewState);
igorsk	0:1063a091a062	551	int32_t EMAC_CRCCalc(uint8_t frame_no_fcs[], int32_t frame_len);
igorsk	0:1063a091a062	552	void EMAC_SetFilterMode(uint32_t ulFilterMode, FunctionalState NewState);
igorsk	0:1063a091a062	553	FlagStatus EMAC_GetWoLStatus(uint32_t ulWoLMode);
igorsk	0:1063a091a062	554	void EMAC_WritePacketBuffer(EMAC_PACKETBUF_Type *pDataStruct);
igorsk	0:1063a091a062	555	void EMAC_ReadPacketBuffer(EMAC_PACKETBUF_Type *pDataStruct);
igorsk	0:1063a091a062	556	void EMAC_StandardIRQHandler(void);
igorsk	0:1063a091a062	557	void EMAC_SetupIntCBS(uint32_t ulIntType, EMAC_IntCBSType *pfnIntCb);
igorsk	0:1063a091a062	558	void EMAC_IntCmd(uint32_t ulIntType, FunctionalState NewState);
igorsk	0:1063a091a062	559	IntStatus EMAC_IntGetStatus(uint32_t ulIntType);
igorsk	0:1063a091a062	560	Bool EMAC_CheckReceiveIndex(void);
igorsk	0:1063a091a062	561	Bool EMAC_CheckTransmitIndex(void);
igorsk	0:1063a091a062	562	FlagStatus EMAC_CheckReceiveDataStatus(uint32_t ulRxStatType);
igorsk	0:1063a091a062	563	uint32_t EMAC_GetReceiveDataSize(void);
igorsk	0:1063a091a062	564	void EMAC_UpdateRxConsumeIndex(void);
igorsk	0:1063a091a062	565	void EMAC_UpdateTxProduceIndex(void);
igorsk	0:1063a091a062	566
igorsk	0:1063a091a062	567
igorsk	0:1063a091a062	568	/**
igorsk	0:1063a091a062	569	* @}
igorsk	0:1063a091a062	570	*/
igorsk	0:1063a091a062	571
igorsk	0:1063a091a062	572	#ifdef __cplusplus
igorsk	0:1063a091a062	573	}
igorsk	0:1063a091a062	574	#endif
igorsk	0:1063a091a062	575
igorsk	0:1063a091a062	576	#endif /* LPC17XX_EMAC_H_ */
igorsk	0:1063a091a062	577
igorsk	0:1063a091a062	578	/**
igorsk	0:1063a091a062	579	* @}
igorsk	0:1063a091a062	580	*/
igorsk	0:1063a091a062	581
igorsk	0:1063a091a062	582	/* --------------------------------- End Of File ------------------------------ */

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Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	17 Feb 2010
Imports:	121
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	1
Followers:	5

include/lpc17xx_emac.h@0:1063a091a062, 2010-02-17 (annotated)

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