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core_cm3.c@11:af609f6dee46, 2016-02-01 (annotated)
- Committer:
- igor_v
- Date:
- Mon Feb 01 16:40:49 2016 +0000
- Revision:
- 11:af609f6dee46
- Child:
- 21:bc8c1cec3da6
hreny
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
igor_v | 11:af609f6dee46 | 1 | /**************************************************************************//** |
igor_v | 11:af609f6dee46 | 2 | * @file core_cm3.c |
igor_v | 11:af609f6dee46 | 3 | * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File |
igor_v | 11:af609f6dee46 | 4 | * @version V1.30 |
igor_v | 11:af609f6dee46 | 5 | * @date 30. October 2009 |
igor_v | 11:af609f6dee46 | 6 | * |
igor_v | 11:af609f6dee46 | 7 | * @note |
igor_v | 11:af609f6dee46 | 8 | * Copyright (C) 2009 ARM Limited. All rights reserved. |
igor_v | 11:af609f6dee46 | 9 | * |
igor_v | 11:af609f6dee46 | 10 | * @par |
igor_v | 11:af609f6dee46 | 11 | * ARM Limited (ARM) is supplying this software for use with Cortex-M |
igor_v | 11:af609f6dee46 | 12 | * processor based microcontrollers. This file can be freely distributed |
igor_v | 11:af609f6dee46 | 13 | * within development tools that are supporting such ARM based processors. |
igor_v | 11:af609f6dee46 | 14 | * |
igor_v | 11:af609f6dee46 | 15 | * @par |
igor_v | 11:af609f6dee46 | 16 | * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
igor_v | 11:af609f6dee46 | 17 | * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
igor_v | 11:af609f6dee46 | 18 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
igor_v | 11:af609f6dee46 | 19 | * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
igor_v | 11:af609f6dee46 | 20 | * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
igor_v | 11:af609f6dee46 | 21 | * |
igor_v | 11:af609f6dee46 | 22 | ******************************************************************************/ |
igor_v | 11:af609f6dee46 | 23 | |
igor_v | 11:af609f6dee46 | 24 | #include <stdint.h> |
igor_v | 11:af609f6dee46 | 25 | |
igor_v | 11:af609f6dee46 | 26 | /* define compiler specific symbols */ |
igor_v | 11:af609f6dee46 | 27 | #if defined ( __CC_ARM ) |
igor_v | 11:af609f6dee46 | 28 | #define __ASM __asm /*!< asm keyword for ARM Compiler */ |
igor_v | 11:af609f6dee46 | 29 | #define __INLINE __inline /*!< inline keyword for ARM Compiler */ |
igor_v | 11:af609f6dee46 | 30 | |
igor_v | 11:af609f6dee46 | 31 | #elif defined ( __ICCARM__ ) |
igor_v | 11:af609f6dee46 | 32 | #define __ASM __asm /*!< asm keyword for IAR Compiler */ |
igor_v | 11:af609f6dee46 | 33 | #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ |
igor_v | 11:af609f6dee46 | 34 | |
igor_v | 11:af609f6dee46 | 35 | #elif defined ( __GNUC__ ) |
igor_v | 11:af609f6dee46 | 36 | #define __ASM __asm /*!< asm keyword for GNU Compiler */ |
igor_v | 11:af609f6dee46 | 37 | #define __INLINE inline /*!< inline keyword for GNU Compiler */ |
igor_v | 11:af609f6dee46 | 38 | |
igor_v | 11:af609f6dee46 | 39 | #elif defined ( __TASKING__ ) |
igor_v | 11:af609f6dee46 | 40 | #define __ASM __asm /*!< asm keyword for TASKING Compiler */ |
igor_v | 11:af609f6dee46 | 41 | #define __INLINE inline /*!< inline keyword for TASKING Compiler */ |
igor_v | 11:af609f6dee46 | 42 | |
igor_v | 11:af609f6dee46 | 43 | #endif |
igor_v | 11:af609f6dee46 | 44 | |
igor_v | 11:af609f6dee46 | 45 | |
igor_v | 11:af609f6dee46 | 46 | /* ################### Compiler specific Intrinsics ########################### */ |
igor_v | 11:af609f6dee46 | 47 | |
igor_v | 11:af609f6dee46 | 48 | #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ |
igor_v | 11:af609f6dee46 | 49 | /* ARM armcc specific functions */ |
igor_v | 11:af609f6dee46 | 50 | |
igor_v | 11:af609f6dee46 | 51 | /** |
igor_v | 11:af609f6dee46 | 52 | * @brief Return the Process Stack Pointer |
igor_v | 11:af609f6dee46 | 53 | * |
igor_v | 11:af609f6dee46 | 54 | * @return ProcessStackPointer |
igor_v | 11:af609f6dee46 | 55 | * |
igor_v | 11:af609f6dee46 | 56 | * Return the actual process stack pointer |
igor_v | 11:af609f6dee46 | 57 | */ |
igor_v | 11:af609f6dee46 | 58 | __ASM uint32_t __get_PSP(void) |
igor_v | 11:af609f6dee46 | 59 | { |
igor_v | 11:af609f6dee46 | 60 | mrs r0, psp |
igor_v | 11:af609f6dee46 | 61 | bx lr |
igor_v | 11:af609f6dee46 | 62 | } |
igor_v | 11:af609f6dee46 | 63 | |
igor_v | 11:af609f6dee46 | 64 | /** |
igor_v | 11:af609f6dee46 | 65 | * @brief Set the Process Stack Pointer |
igor_v | 11:af609f6dee46 | 66 | * |
igor_v | 11:af609f6dee46 | 67 | * @param topOfProcStack Process Stack Pointer |
igor_v | 11:af609f6dee46 | 68 | * |
igor_v | 11:af609f6dee46 | 69 | * Assign the value ProcessStackPointer to the MSP |
igor_v | 11:af609f6dee46 | 70 | * (process stack pointer) Cortex processor register |
igor_v | 11:af609f6dee46 | 71 | */ |
igor_v | 11:af609f6dee46 | 72 | __ASM void __set_PSP(uint32_t topOfProcStack) |
igor_v | 11:af609f6dee46 | 73 | { |
igor_v | 11:af609f6dee46 | 74 | msr psp, r0 |
igor_v | 11:af609f6dee46 | 75 | bx lr |
igor_v | 11:af609f6dee46 | 76 | } |
igor_v | 11:af609f6dee46 | 77 | |
igor_v | 11:af609f6dee46 | 78 | /** |
igor_v | 11:af609f6dee46 | 79 | * @brief Return the Main Stack Pointer |
igor_v | 11:af609f6dee46 | 80 | * |
igor_v | 11:af609f6dee46 | 81 | * @return Main Stack Pointer |
igor_v | 11:af609f6dee46 | 82 | * |
igor_v | 11:af609f6dee46 | 83 | * Return the current value of the MSP (main stack pointer) |
igor_v | 11:af609f6dee46 | 84 | * Cortex processor register |
igor_v | 11:af609f6dee46 | 85 | */ |
igor_v | 11:af609f6dee46 | 86 | __ASM uint32_t __get_MSP(void) |
igor_v | 11:af609f6dee46 | 87 | { |
igor_v | 11:af609f6dee46 | 88 | mrs r0, msp |
igor_v | 11:af609f6dee46 | 89 | bx lr |
igor_v | 11:af609f6dee46 | 90 | } |
igor_v | 11:af609f6dee46 | 91 | |
igor_v | 11:af609f6dee46 | 92 | /** |
igor_v | 11:af609f6dee46 | 93 | * @brief Set the Main Stack Pointer |
igor_v | 11:af609f6dee46 | 94 | * |
igor_v | 11:af609f6dee46 | 95 | * @param topOfMainStack Main Stack Pointer |
igor_v | 11:af609f6dee46 | 96 | * |
igor_v | 11:af609f6dee46 | 97 | * Assign the value mainStackPointer to the MSP |
igor_v | 11:af609f6dee46 | 98 | * (main stack pointer) Cortex processor register |
igor_v | 11:af609f6dee46 | 99 | */ |
igor_v | 11:af609f6dee46 | 100 | __ASM void __set_MSP(uint32_t mainStackPointer) |
igor_v | 11:af609f6dee46 | 101 | { |
igor_v | 11:af609f6dee46 | 102 | msr msp, r0 |
igor_v | 11:af609f6dee46 | 103 | bx lr |
igor_v | 11:af609f6dee46 | 104 | } |
igor_v | 11:af609f6dee46 | 105 | |
igor_v | 11:af609f6dee46 | 106 | /** |
igor_v | 11:af609f6dee46 | 107 | * @brief Reverse byte order in unsigned short value |
igor_v | 11:af609f6dee46 | 108 | * |
igor_v | 11:af609f6dee46 | 109 | * @param value value to reverse |
igor_v | 11:af609f6dee46 | 110 | * @return reversed value |
igor_v | 11:af609f6dee46 | 111 | * |
igor_v | 11:af609f6dee46 | 112 | * Reverse byte order in unsigned short value |
igor_v | 11:af609f6dee46 | 113 | */ |
igor_v | 11:af609f6dee46 | 114 | __ASM uint32_t __REV16(uint16_t value) |
igor_v | 11:af609f6dee46 | 115 | { |
igor_v | 11:af609f6dee46 | 116 | rev16 r0, r0 |
igor_v | 11:af609f6dee46 | 117 | bx lr |
igor_v | 11:af609f6dee46 | 118 | } |
igor_v | 11:af609f6dee46 | 119 | |
igor_v | 11:af609f6dee46 | 120 | /** |
igor_v | 11:af609f6dee46 | 121 | * @brief Reverse byte order in signed short value with sign extension to integer |
igor_v | 11:af609f6dee46 | 122 | * |
igor_v | 11:af609f6dee46 | 123 | * @param value value to reverse |
igor_v | 11:af609f6dee46 | 124 | * @return reversed value |
igor_v | 11:af609f6dee46 | 125 | * |
igor_v | 11:af609f6dee46 | 126 | * Reverse byte order in signed short value with sign extension to integer |
igor_v | 11:af609f6dee46 | 127 | */ |
igor_v | 11:af609f6dee46 | 128 | __ASM int32_t __REVSH(int16_t value) |
igor_v | 11:af609f6dee46 | 129 | { |
igor_v | 11:af609f6dee46 | 130 | revsh r0, r0 |
igor_v | 11:af609f6dee46 | 131 | bx lr |
igor_v | 11:af609f6dee46 | 132 | } |
igor_v | 11:af609f6dee46 | 133 | |
igor_v | 11:af609f6dee46 | 134 | |
igor_v | 11:af609f6dee46 | 135 | #if (__ARMCC_VERSION < 400000) |
igor_v | 11:af609f6dee46 | 136 | |
igor_v | 11:af609f6dee46 | 137 | /** |
igor_v | 11:af609f6dee46 | 138 | * @brief Remove the exclusive lock created by ldrex |
igor_v | 11:af609f6dee46 | 139 | * |
igor_v | 11:af609f6dee46 | 140 | * Removes the exclusive lock which is created by ldrex. |
igor_v | 11:af609f6dee46 | 141 | */ |
igor_v | 11:af609f6dee46 | 142 | __ASM void __CLREX(void) |
igor_v | 11:af609f6dee46 | 143 | { |
igor_v | 11:af609f6dee46 | 144 | clrex |
igor_v | 11:af609f6dee46 | 145 | } |
igor_v | 11:af609f6dee46 | 146 | |
igor_v | 11:af609f6dee46 | 147 | /** |
igor_v | 11:af609f6dee46 | 148 | * @brief Return the Base Priority value |
igor_v | 11:af609f6dee46 | 149 | * |
igor_v | 11:af609f6dee46 | 150 | * @return BasePriority |
igor_v | 11:af609f6dee46 | 151 | * |
igor_v | 11:af609f6dee46 | 152 | * Return the content of the base priority register |
igor_v | 11:af609f6dee46 | 153 | */ |
igor_v | 11:af609f6dee46 | 154 | __ASM uint32_t __get_BASEPRI(void) |
igor_v | 11:af609f6dee46 | 155 | { |
igor_v | 11:af609f6dee46 | 156 | mrs r0, basepri |
igor_v | 11:af609f6dee46 | 157 | bx lr |
igor_v | 11:af609f6dee46 | 158 | } |
igor_v | 11:af609f6dee46 | 159 | |
igor_v | 11:af609f6dee46 | 160 | /** |
igor_v | 11:af609f6dee46 | 161 | * @brief Set the Base Priority value |
igor_v | 11:af609f6dee46 | 162 | * |
igor_v | 11:af609f6dee46 | 163 | * @param basePri BasePriority |
igor_v | 11:af609f6dee46 | 164 | * |
igor_v | 11:af609f6dee46 | 165 | * Set the base priority register |
igor_v | 11:af609f6dee46 | 166 | */ |
igor_v | 11:af609f6dee46 | 167 | __ASM void __set_BASEPRI(uint32_t basePri) |
igor_v | 11:af609f6dee46 | 168 | { |
igor_v | 11:af609f6dee46 | 169 | msr basepri, r0 |
igor_v | 11:af609f6dee46 | 170 | bx lr |
igor_v | 11:af609f6dee46 | 171 | } |
igor_v | 11:af609f6dee46 | 172 | |
igor_v | 11:af609f6dee46 | 173 | /** |
igor_v | 11:af609f6dee46 | 174 | * @brief Return the Priority Mask value |
igor_v | 11:af609f6dee46 | 175 | * |
igor_v | 11:af609f6dee46 | 176 | * @return PriMask |
igor_v | 11:af609f6dee46 | 177 | * |
igor_v | 11:af609f6dee46 | 178 | * Return state of the priority mask bit from the priority mask register |
igor_v | 11:af609f6dee46 | 179 | */ |
igor_v | 11:af609f6dee46 | 180 | __ASM uint32_t __get_PRIMASK(void) |
igor_v | 11:af609f6dee46 | 181 | { |
igor_v | 11:af609f6dee46 | 182 | mrs r0, primask |
igor_v | 11:af609f6dee46 | 183 | bx lr |
igor_v | 11:af609f6dee46 | 184 | } |
igor_v | 11:af609f6dee46 | 185 | |
igor_v | 11:af609f6dee46 | 186 | /** |
igor_v | 11:af609f6dee46 | 187 | * @brief Set the Priority Mask value |
igor_v | 11:af609f6dee46 | 188 | * |
igor_v | 11:af609f6dee46 | 189 | * @param priMask PriMask |
igor_v | 11:af609f6dee46 | 190 | * |
igor_v | 11:af609f6dee46 | 191 | * Set the priority mask bit in the priority mask register |
igor_v | 11:af609f6dee46 | 192 | */ |
igor_v | 11:af609f6dee46 | 193 | __ASM void __set_PRIMASK(uint32_t priMask) |
igor_v | 11:af609f6dee46 | 194 | { |
igor_v | 11:af609f6dee46 | 195 | msr primask, r0 |
igor_v | 11:af609f6dee46 | 196 | bx lr |
igor_v | 11:af609f6dee46 | 197 | } |
igor_v | 11:af609f6dee46 | 198 | |
igor_v | 11:af609f6dee46 | 199 | /** |
igor_v | 11:af609f6dee46 | 200 | * @brief Return the Fault Mask value |
igor_v | 11:af609f6dee46 | 201 | * |
igor_v | 11:af609f6dee46 | 202 | * @return FaultMask |
igor_v | 11:af609f6dee46 | 203 | * |
igor_v | 11:af609f6dee46 | 204 | * Return the content of the fault mask register |
igor_v | 11:af609f6dee46 | 205 | */ |
igor_v | 11:af609f6dee46 | 206 | __ASM uint32_t __get_FAULTMASK(void) |
igor_v | 11:af609f6dee46 | 207 | { |
igor_v | 11:af609f6dee46 | 208 | mrs r0, faultmask |
igor_v | 11:af609f6dee46 | 209 | bx lr |
igor_v | 11:af609f6dee46 | 210 | } |
igor_v | 11:af609f6dee46 | 211 | |
igor_v | 11:af609f6dee46 | 212 | /** |
igor_v | 11:af609f6dee46 | 213 | * @brief Set the Fault Mask value |
igor_v | 11:af609f6dee46 | 214 | * |
igor_v | 11:af609f6dee46 | 215 | * @param faultMask faultMask value |
igor_v | 11:af609f6dee46 | 216 | * |
igor_v | 11:af609f6dee46 | 217 | * Set the fault mask register |
igor_v | 11:af609f6dee46 | 218 | */ |
igor_v | 11:af609f6dee46 | 219 | __ASM void __set_FAULTMASK(uint32_t faultMask) |
igor_v | 11:af609f6dee46 | 220 | { |
igor_v | 11:af609f6dee46 | 221 | msr faultmask, r0 |
igor_v | 11:af609f6dee46 | 222 | bx lr |
igor_v | 11:af609f6dee46 | 223 | } |
igor_v | 11:af609f6dee46 | 224 | |
igor_v | 11:af609f6dee46 | 225 | /** |
igor_v | 11:af609f6dee46 | 226 | * @brief Return the Control Register value |
igor_v | 11:af609f6dee46 | 227 | * |
igor_v | 11:af609f6dee46 | 228 | * @return Control value |
igor_v | 11:af609f6dee46 | 229 | * |
igor_v | 11:af609f6dee46 | 230 | * Return the content of the control register |
igor_v | 11:af609f6dee46 | 231 | */ |
igor_v | 11:af609f6dee46 | 232 | __ASM uint32_t __get_CONTROL(void) |
igor_v | 11:af609f6dee46 | 233 | { |
igor_v | 11:af609f6dee46 | 234 | mrs r0, control |
igor_v | 11:af609f6dee46 | 235 | bx lr |
igor_v | 11:af609f6dee46 | 236 | } |
igor_v | 11:af609f6dee46 | 237 | |
igor_v | 11:af609f6dee46 | 238 | /** |
igor_v | 11:af609f6dee46 | 239 | * @brief Set the Control Register value |
igor_v | 11:af609f6dee46 | 240 | * |
igor_v | 11:af609f6dee46 | 241 | * @param control Control value |
igor_v | 11:af609f6dee46 | 242 | * |
igor_v | 11:af609f6dee46 | 243 | * Set the control register |
igor_v | 11:af609f6dee46 | 244 | */ |
igor_v | 11:af609f6dee46 | 245 | __ASM void __set_CONTROL(uint32_t control) |
igor_v | 11:af609f6dee46 | 246 | { |
igor_v | 11:af609f6dee46 | 247 | msr control, r0 |
igor_v | 11:af609f6dee46 | 248 | bx lr |
igor_v | 11:af609f6dee46 | 249 | } |
igor_v | 11:af609f6dee46 | 250 | |
igor_v | 11:af609f6dee46 | 251 | #endif /* __ARMCC_VERSION */ |
igor_v | 11:af609f6dee46 | 252 | |
igor_v | 11:af609f6dee46 | 253 | |
igor_v | 11:af609f6dee46 | 254 | |
igor_v | 11:af609f6dee46 | 255 | #elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ |
igor_v | 11:af609f6dee46 | 256 | /* IAR iccarm specific functions */ |
igor_v | 11:af609f6dee46 | 257 | #pragma diag_suppress=Pe940 |
igor_v | 11:af609f6dee46 | 258 | |
igor_v | 11:af609f6dee46 | 259 | /** |
igor_v | 11:af609f6dee46 | 260 | * @brief Return the Process Stack Pointer |
igor_v | 11:af609f6dee46 | 261 | * |
igor_v | 11:af609f6dee46 | 262 | * @return ProcessStackPointer |
igor_v | 11:af609f6dee46 | 263 | * |
igor_v | 11:af609f6dee46 | 264 | * Return the actual process stack pointer |
igor_v | 11:af609f6dee46 | 265 | */ |
igor_v | 11:af609f6dee46 | 266 | uint32_t __get_PSP(void) |
igor_v | 11:af609f6dee46 | 267 | { |
igor_v | 11:af609f6dee46 | 268 | __ASM("mrs r0, psp"); |
igor_v | 11:af609f6dee46 | 269 | __ASM("bx lr"); |
igor_v | 11:af609f6dee46 | 270 | } |
igor_v | 11:af609f6dee46 | 271 | |
igor_v | 11:af609f6dee46 | 272 | /** |
igor_v | 11:af609f6dee46 | 273 | * @brief Set the Process Stack Pointer |
igor_v | 11:af609f6dee46 | 274 | * |
igor_v | 11:af609f6dee46 | 275 | * @param topOfProcStack Process Stack Pointer |
igor_v | 11:af609f6dee46 | 276 | * |
igor_v | 11:af609f6dee46 | 277 | * Assign the value ProcessStackPointer to the MSP |
igor_v | 11:af609f6dee46 | 278 | * (process stack pointer) Cortex processor register |
igor_v | 11:af609f6dee46 | 279 | */ |
igor_v | 11:af609f6dee46 | 280 | void __set_PSP(uint32_t topOfProcStack) |
igor_v | 11:af609f6dee46 | 281 | { |
igor_v | 11:af609f6dee46 | 282 | __ASM("msr psp, r0"); |
igor_v | 11:af609f6dee46 | 283 | __ASM("bx lr"); |
igor_v | 11:af609f6dee46 | 284 | } |
igor_v | 11:af609f6dee46 | 285 | |
igor_v | 11:af609f6dee46 | 286 | /** |
igor_v | 11:af609f6dee46 | 287 | * @brief Return the Main Stack Pointer |
igor_v | 11:af609f6dee46 | 288 | * |
igor_v | 11:af609f6dee46 | 289 | * @return Main Stack Pointer |
igor_v | 11:af609f6dee46 | 290 | * |
igor_v | 11:af609f6dee46 | 291 | * Return the current value of the MSP (main stack pointer) |
igor_v | 11:af609f6dee46 | 292 | * Cortex processor register |
igor_v | 11:af609f6dee46 | 293 | */ |
igor_v | 11:af609f6dee46 | 294 | uint32_t __get_MSP(void) |
igor_v | 11:af609f6dee46 | 295 | { |
igor_v | 11:af609f6dee46 | 296 | __ASM("mrs r0, msp"); |
igor_v | 11:af609f6dee46 | 297 | __ASM("bx lr"); |
igor_v | 11:af609f6dee46 | 298 | } |
igor_v | 11:af609f6dee46 | 299 | |
igor_v | 11:af609f6dee46 | 300 | /** |
igor_v | 11:af609f6dee46 | 301 | * @brief Set the Main Stack Pointer |
igor_v | 11:af609f6dee46 | 302 | * |
igor_v | 11:af609f6dee46 | 303 | * @param topOfMainStack Main Stack Pointer |
igor_v | 11:af609f6dee46 | 304 | * |
igor_v | 11:af609f6dee46 | 305 | * Assign the value mainStackPointer to the MSP |
igor_v | 11:af609f6dee46 | 306 | * (main stack pointer) Cortex processor register |
igor_v | 11:af609f6dee46 | 307 | */ |
igor_v | 11:af609f6dee46 | 308 | void __set_MSP(uint32_t topOfMainStack) |
igor_v | 11:af609f6dee46 | 309 | { |
igor_v | 11:af609f6dee46 | 310 | __ASM("msr msp, r0"); |
igor_v | 11:af609f6dee46 | 311 | __ASM("bx lr"); |
igor_v | 11:af609f6dee46 | 312 | } |
igor_v | 11:af609f6dee46 | 313 | |
igor_v | 11:af609f6dee46 | 314 | /** |
igor_v | 11:af609f6dee46 | 315 | * @brief Reverse byte order in unsigned short value |
igor_v | 11:af609f6dee46 | 316 | * |
igor_v | 11:af609f6dee46 | 317 | * @param value value to reverse |
igor_v | 11:af609f6dee46 | 318 | * @return reversed value |
igor_v | 11:af609f6dee46 | 319 | * |
igor_v | 11:af609f6dee46 | 320 | * Reverse byte order in unsigned short value |
igor_v | 11:af609f6dee46 | 321 | */ |
igor_v | 11:af609f6dee46 | 322 | uint32_t __REV16(uint16_t value) |
igor_v | 11:af609f6dee46 | 323 | { |
igor_v | 11:af609f6dee46 | 324 | __ASM("rev16 r0, r0"); |
igor_v | 11:af609f6dee46 | 325 | __ASM("bx lr"); |
igor_v | 11:af609f6dee46 | 326 | } |
igor_v | 11:af609f6dee46 | 327 | |
igor_v | 11:af609f6dee46 | 328 | /** |
igor_v | 11:af609f6dee46 | 329 | * @brief Reverse bit order of value |
igor_v | 11:af609f6dee46 | 330 | * |
igor_v | 11:af609f6dee46 | 331 | * @param value value to reverse |
igor_v | 11:af609f6dee46 | 332 | * @return reversed value |
igor_v | 11:af609f6dee46 | 333 | * |
igor_v | 11:af609f6dee46 | 334 | * Reverse bit order of value |
igor_v | 11:af609f6dee46 | 335 | */ |
igor_v | 11:af609f6dee46 | 336 | uint32_t __RBIT(uint32_t value) |
igor_v | 11:af609f6dee46 | 337 | { |
igor_v | 11:af609f6dee46 | 338 | __ASM("rbit r0, r0"); |
igor_v | 11:af609f6dee46 | 339 | __ASM("bx lr"); |
igor_v | 11:af609f6dee46 | 340 | } |
igor_v | 11:af609f6dee46 | 341 | |
igor_v | 11:af609f6dee46 | 342 | /** |
igor_v | 11:af609f6dee46 | 343 | * @brief LDR Exclusive (8 bit) |
igor_v | 11:af609f6dee46 | 344 | * |
igor_v | 11:af609f6dee46 | 345 | * @param *addr address pointer |
igor_v | 11:af609f6dee46 | 346 | * @return value of (*address) |
igor_v | 11:af609f6dee46 | 347 | * |
igor_v | 11:af609f6dee46 | 348 | * Exclusive LDR command for 8 bit values) |
igor_v | 11:af609f6dee46 | 349 | */ |
igor_v | 11:af609f6dee46 | 350 | uint8_t __LDREXB(uint8_t *addr) |
igor_v | 11:af609f6dee46 | 351 | { |
igor_v | 11:af609f6dee46 | 352 | __ASM("ldrexb r0, [r0]"); |
igor_v | 11:af609f6dee46 | 353 | __ASM("bx lr"); |
igor_v | 11:af609f6dee46 | 354 | } |
igor_v | 11:af609f6dee46 | 355 | |
igor_v | 11:af609f6dee46 | 356 | /** |
igor_v | 11:af609f6dee46 | 357 | * @brief LDR Exclusive (16 bit) |
igor_v | 11:af609f6dee46 | 358 | * |
igor_v | 11:af609f6dee46 | 359 | * @param *addr address pointer |
igor_v | 11:af609f6dee46 | 360 | * @return value of (*address) |
igor_v | 11:af609f6dee46 | 361 | * |
igor_v | 11:af609f6dee46 | 362 | * Exclusive LDR command for 16 bit values |
igor_v | 11:af609f6dee46 | 363 | */ |
igor_v | 11:af609f6dee46 | 364 | uint16_t __LDREXH(uint16_t *addr) |
igor_v | 11:af609f6dee46 | 365 | { |
igor_v | 11:af609f6dee46 | 366 | __ASM("ldrexh r0, [r0]"); |
igor_v | 11:af609f6dee46 | 367 | __ASM("bx lr"); |
igor_v | 11:af609f6dee46 | 368 | } |
igor_v | 11:af609f6dee46 | 369 | |
igor_v | 11:af609f6dee46 | 370 | /** |
igor_v | 11:af609f6dee46 | 371 | * @brief LDR Exclusive (32 bit) |
igor_v | 11:af609f6dee46 | 372 | * |
igor_v | 11:af609f6dee46 | 373 | * @param *addr address pointer |
igor_v | 11:af609f6dee46 | 374 | * @return value of (*address) |
igor_v | 11:af609f6dee46 | 375 | * |
igor_v | 11:af609f6dee46 | 376 | * Exclusive LDR command for 32 bit values |
igor_v | 11:af609f6dee46 | 377 | */ |
igor_v | 11:af609f6dee46 | 378 | uint32_t __LDREXW(uint32_t *addr) |
igor_v | 11:af609f6dee46 | 379 | { |
igor_v | 11:af609f6dee46 | 380 | __ASM("ldrex r0, [r0]"); |
igor_v | 11:af609f6dee46 | 381 | __ASM("bx lr"); |
igor_v | 11:af609f6dee46 | 382 | } |
igor_v | 11:af609f6dee46 | 383 | |
igor_v | 11:af609f6dee46 | 384 | /** |
igor_v | 11:af609f6dee46 | 385 | * @brief STR Exclusive (8 bit) |
igor_v | 11:af609f6dee46 | 386 | * |
igor_v | 11:af609f6dee46 | 387 | * @param value value to store |
igor_v | 11:af609f6dee46 | 388 | * @param *addr address pointer |
igor_v | 11:af609f6dee46 | 389 | * @return successful / failed |
igor_v | 11:af609f6dee46 | 390 | * |
igor_v | 11:af609f6dee46 | 391 | * Exclusive STR command for 8 bit values |
igor_v | 11:af609f6dee46 | 392 | */ |
igor_v | 11:af609f6dee46 | 393 | uint32_t __STREXB(uint8_t value, uint8_t *addr) |
igor_v | 11:af609f6dee46 | 394 | { |
igor_v | 11:af609f6dee46 | 395 | __ASM("strexb r0, r0, [r1]"); |
igor_v | 11:af609f6dee46 | 396 | __ASM("bx lr"); |
igor_v | 11:af609f6dee46 | 397 | } |
igor_v | 11:af609f6dee46 | 398 | |
igor_v | 11:af609f6dee46 | 399 | /** |
igor_v | 11:af609f6dee46 | 400 | * @brief STR Exclusive (16 bit) |
igor_v | 11:af609f6dee46 | 401 | * |
igor_v | 11:af609f6dee46 | 402 | * @param value value to store |
igor_v | 11:af609f6dee46 | 403 | * @param *addr address pointer |
igor_v | 11:af609f6dee46 | 404 | * @return successful / failed |
igor_v | 11:af609f6dee46 | 405 | * |
igor_v | 11:af609f6dee46 | 406 | * Exclusive STR command for 16 bit values |
igor_v | 11:af609f6dee46 | 407 | */ |
igor_v | 11:af609f6dee46 | 408 | uint32_t __STREXH(uint16_t value, uint16_t *addr) |
igor_v | 11:af609f6dee46 | 409 | { |
igor_v | 11:af609f6dee46 | 410 | __ASM("strexh r0, r0, [r1]"); |
igor_v | 11:af609f6dee46 | 411 | __ASM("bx lr"); |
igor_v | 11:af609f6dee46 | 412 | } |
igor_v | 11:af609f6dee46 | 413 | |
igor_v | 11:af609f6dee46 | 414 | /** |
igor_v | 11:af609f6dee46 | 415 | * @brief STR Exclusive (32 bit) |
igor_v | 11:af609f6dee46 | 416 | * |
igor_v | 11:af609f6dee46 | 417 | * @param value value to store |
igor_v | 11:af609f6dee46 | 418 | * @param *addr address pointer |
igor_v | 11:af609f6dee46 | 419 | * @return successful / failed |
igor_v | 11:af609f6dee46 | 420 | * |
igor_v | 11:af609f6dee46 | 421 | * Exclusive STR command for 32 bit values |
igor_v | 11:af609f6dee46 | 422 | */ |
igor_v | 11:af609f6dee46 | 423 | uint32_t __STREXW(uint32_t value, uint32_t *addr) |
igor_v | 11:af609f6dee46 | 424 | { |
igor_v | 11:af609f6dee46 | 425 | __ASM("strex r0, r0, [r1]"); |
igor_v | 11:af609f6dee46 | 426 | __ASM("bx lr"); |
igor_v | 11:af609f6dee46 | 427 | } |
igor_v | 11:af609f6dee46 | 428 | |
igor_v | 11:af609f6dee46 | 429 | #pragma diag_default=Pe940 |
igor_v | 11:af609f6dee46 | 430 | |
igor_v | 11:af609f6dee46 | 431 | |
igor_v | 11:af609f6dee46 | 432 | #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ |
igor_v | 11:af609f6dee46 | 433 | /* GNU gcc specific functions */ |
igor_v | 11:af609f6dee46 | 434 | |
igor_v | 11:af609f6dee46 | 435 | /** |
igor_v | 11:af609f6dee46 | 436 | * @brief Return the Process Stack Pointer |
igor_v | 11:af609f6dee46 | 437 | * |
igor_v | 11:af609f6dee46 | 438 | * @return ProcessStackPointer |
igor_v | 11:af609f6dee46 | 439 | * |
igor_v | 11:af609f6dee46 | 440 | * Return the actual process stack pointer |
igor_v | 11:af609f6dee46 | 441 | */ |
igor_v | 11:af609f6dee46 | 442 | uint32_t __get_PSP(void) __attribute__( ( naked ) ); |
igor_v | 11:af609f6dee46 | 443 | uint32_t __get_PSP(void) |
igor_v | 11:af609f6dee46 | 444 | { |
igor_v | 11:af609f6dee46 | 445 | uint32_t result=0; |
igor_v | 11:af609f6dee46 | 446 | |
igor_v | 11:af609f6dee46 | 447 | __ASM volatile ("MRS %0, psp\n\t" |
igor_v | 11:af609f6dee46 | 448 | "MOV r0, %0 \n\t" |
igor_v | 11:af609f6dee46 | 449 | "BX lr \n\t" : "=r" (result) ); |
igor_v | 11:af609f6dee46 | 450 | return(result); |
igor_v | 11:af609f6dee46 | 451 | } |
igor_v | 11:af609f6dee46 | 452 | |
igor_v | 11:af609f6dee46 | 453 | /** |
igor_v | 11:af609f6dee46 | 454 | * @brief Set the Process Stack Pointer |
igor_v | 11:af609f6dee46 | 455 | * |
igor_v | 11:af609f6dee46 | 456 | * @param topOfProcStack Process Stack Pointer |
igor_v | 11:af609f6dee46 | 457 | * |
igor_v | 11:af609f6dee46 | 458 | * Assign the value ProcessStackPointer to the MSP |
igor_v | 11:af609f6dee46 | 459 | * (process stack pointer) Cortex processor register |
igor_v | 11:af609f6dee46 | 460 | */ |
igor_v | 11:af609f6dee46 | 461 | void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) ); |
igor_v | 11:af609f6dee46 | 462 | void __set_PSP(uint32_t topOfProcStack) |
igor_v | 11:af609f6dee46 | 463 | { |
igor_v | 11:af609f6dee46 | 464 | __ASM volatile ("MSR psp, %0\n\t" |
igor_v | 11:af609f6dee46 | 465 | "BX lr \n\t" : : "r" (topOfProcStack) ); |
igor_v | 11:af609f6dee46 | 466 | } |
igor_v | 11:af609f6dee46 | 467 | |
igor_v | 11:af609f6dee46 | 468 | /** |
igor_v | 11:af609f6dee46 | 469 | * @brief Return the Main Stack Pointer |
igor_v | 11:af609f6dee46 | 470 | * |
igor_v | 11:af609f6dee46 | 471 | * @return Main Stack Pointer |
igor_v | 11:af609f6dee46 | 472 | * |
igor_v | 11:af609f6dee46 | 473 | * Return the current value of the MSP (main stack pointer) |
igor_v | 11:af609f6dee46 | 474 | * Cortex processor register |
igor_v | 11:af609f6dee46 | 475 | */ |
igor_v | 11:af609f6dee46 | 476 | uint32_t __get_MSP(void) __attribute__( ( naked ) ); |
igor_v | 11:af609f6dee46 | 477 | uint32_t __get_MSP(void) |
igor_v | 11:af609f6dee46 | 478 | { |
igor_v | 11:af609f6dee46 | 479 | uint32_t result=0; |
igor_v | 11:af609f6dee46 | 480 | |
igor_v | 11:af609f6dee46 | 481 | __ASM volatile ("MRS %0, msp\n\t" |
igor_v | 11:af609f6dee46 | 482 | "MOV r0, %0 \n\t" |
igor_v | 11:af609f6dee46 | 483 | "BX lr \n\t" : "=r" (result) ); |
igor_v | 11:af609f6dee46 | 484 | return(result); |
igor_v | 11:af609f6dee46 | 485 | } |
igor_v | 11:af609f6dee46 | 486 | |
igor_v | 11:af609f6dee46 | 487 | /** |
igor_v | 11:af609f6dee46 | 488 | * @brief Set the Main Stack Pointer |
igor_v | 11:af609f6dee46 | 489 | * |
igor_v | 11:af609f6dee46 | 490 | * @param topOfMainStack Main Stack Pointer |
igor_v | 11:af609f6dee46 | 491 | * |
igor_v | 11:af609f6dee46 | 492 | * Assign the value mainStackPointer to the MSP |
igor_v | 11:af609f6dee46 | 493 | * (main stack pointer) Cortex processor register |
igor_v | 11:af609f6dee46 | 494 | */ |
igor_v | 11:af609f6dee46 | 495 | void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) ); |
igor_v | 11:af609f6dee46 | 496 | void __set_MSP(uint32_t topOfMainStack) |
igor_v | 11:af609f6dee46 | 497 | { |
igor_v | 11:af609f6dee46 | 498 | __ASM volatile ("MSR msp, %0\n\t" |
igor_v | 11:af609f6dee46 | 499 | "BX lr \n\t" : : "r" (topOfMainStack) ); |
igor_v | 11:af609f6dee46 | 500 | } |
igor_v | 11:af609f6dee46 | 501 | |
igor_v | 11:af609f6dee46 | 502 | /** |
igor_v | 11:af609f6dee46 | 503 | * @brief Return the Base Priority value |
igor_v | 11:af609f6dee46 | 504 | * |
igor_v | 11:af609f6dee46 | 505 | * @return BasePriority |
igor_v | 11:af609f6dee46 | 506 | * |
igor_v | 11:af609f6dee46 | 507 | * Return the content of the base priority register |
igor_v | 11:af609f6dee46 | 508 | */ |
igor_v | 11:af609f6dee46 | 509 | uint32_t __get_BASEPRI(void) |
igor_v | 11:af609f6dee46 | 510 | { |
igor_v | 11:af609f6dee46 | 511 | uint32_t result=0; |
igor_v | 11:af609f6dee46 | 512 | |
igor_v | 11:af609f6dee46 | 513 | __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); |
igor_v | 11:af609f6dee46 | 514 | return(result); |
igor_v | 11:af609f6dee46 | 515 | } |
igor_v | 11:af609f6dee46 | 516 | |
igor_v | 11:af609f6dee46 | 517 | /** |
igor_v | 11:af609f6dee46 | 518 | * @brief Set the Base Priority value |
igor_v | 11:af609f6dee46 | 519 | * |
igor_v | 11:af609f6dee46 | 520 | * @param basePri BasePriority |
igor_v | 11:af609f6dee46 | 521 | * |
igor_v | 11:af609f6dee46 | 522 | * Set the base priority register |
igor_v | 11:af609f6dee46 | 523 | */ |
igor_v | 11:af609f6dee46 | 524 | void __set_BASEPRI(uint32_t value) |
igor_v | 11:af609f6dee46 | 525 | { |
igor_v | 11:af609f6dee46 | 526 | __ASM volatile ("MSR basepri, %0" : : "r" (value) ); |
igor_v | 11:af609f6dee46 | 527 | } |
igor_v | 11:af609f6dee46 | 528 | |
igor_v | 11:af609f6dee46 | 529 | /** |
igor_v | 11:af609f6dee46 | 530 | * @brief Return the Priority Mask value |
igor_v | 11:af609f6dee46 | 531 | * |
igor_v | 11:af609f6dee46 | 532 | * @return PriMask |
igor_v | 11:af609f6dee46 | 533 | * |
igor_v | 11:af609f6dee46 | 534 | * Return state of the priority mask bit from the priority mask register |
igor_v | 11:af609f6dee46 | 535 | */ |
igor_v | 11:af609f6dee46 | 536 | uint32_t __get_PRIMASK(void) |
igor_v | 11:af609f6dee46 | 537 | { |
igor_v | 11:af609f6dee46 | 538 | uint32_t result=0; |
igor_v | 11:af609f6dee46 | 539 | |
igor_v | 11:af609f6dee46 | 540 | __ASM volatile ("MRS %0, primask" : "=r" (result) ); |
igor_v | 11:af609f6dee46 | 541 | return(result); |
igor_v | 11:af609f6dee46 | 542 | } |
igor_v | 11:af609f6dee46 | 543 | |
igor_v | 11:af609f6dee46 | 544 | /** |
igor_v | 11:af609f6dee46 | 545 | * @brief Set the Priority Mask value |
igor_v | 11:af609f6dee46 | 546 | * |
igor_v | 11:af609f6dee46 | 547 | * @param priMask PriMask |
igor_v | 11:af609f6dee46 | 548 | * |
igor_v | 11:af609f6dee46 | 549 | * Set the priority mask bit in the priority mask register |
igor_v | 11:af609f6dee46 | 550 | */ |
igor_v | 11:af609f6dee46 | 551 | void __set_PRIMASK(uint32_t priMask) |
igor_v | 11:af609f6dee46 | 552 | { |
igor_v | 11:af609f6dee46 | 553 | __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); |
igor_v | 11:af609f6dee46 | 554 | } |
igor_v | 11:af609f6dee46 | 555 | |
igor_v | 11:af609f6dee46 | 556 | /** |
igor_v | 11:af609f6dee46 | 557 | * @brief Return the Fault Mask value |
igor_v | 11:af609f6dee46 | 558 | * |
igor_v | 11:af609f6dee46 | 559 | * @return FaultMask |
igor_v | 11:af609f6dee46 | 560 | * |
igor_v | 11:af609f6dee46 | 561 | * Return the content of the fault mask register |
igor_v | 11:af609f6dee46 | 562 | */ |
igor_v | 11:af609f6dee46 | 563 | uint32_t __get_FAULTMASK(void) |
igor_v | 11:af609f6dee46 | 564 | { |
igor_v | 11:af609f6dee46 | 565 | uint32_t result=0; |
igor_v | 11:af609f6dee46 | 566 | |
igor_v | 11:af609f6dee46 | 567 | __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); |
igor_v | 11:af609f6dee46 | 568 | return(result); |
igor_v | 11:af609f6dee46 | 569 | } |
igor_v | 11:af609f6dee46 | 570 | |
igor_v | 11:af609f6dee46 | 571 | /** |
igor_v | 11:af609f6dee46 | 572 | * @brief Set the Fault Mask value |
igor_v | 11:af609f6dee46 | 573 | * |
igor_v | 11:af609f6dee46 | 574 | * @param faultMask faultMask value |
igor_v | 11:af609f6dee46 | 575 | * |
igor_v | 11:af609f6dee46 | 576 | * Set the fault mask register |
igor_v | 11:af609f6dee46 | 577 | */ |
igor_v | 11:af609f6dee46 | 578 | void __set_FAULTMASK(uint32_t faultMask) |
igor_v | 11:af609f6dee46 | 579 | { |
igor_v | 11:af609f6dee46 | 580 | __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); |
igor_v | 11:af609f6dee46 | 581 | } |
igor_v | 11:af609f6dee46 | 582 | |
igor_v | 11:af609f6dee46 | 583 | /** |
igor_v | 11:af609f6dee46 | 584 | * @brief Return the Control Register value |
igor_v | 11:af609f6dee46 | 585 | * |
igor_v | 11:af609f6dee46 | 586 | * @return Control value |
igor_v | 11:af609f6dee46 | 587 | * |
igor_v | 11:af609f6dee46 | 588 | * Return the content of the control register |
igor_v | 11:af609f6dee46 | 589 | */ |
igor_v | 11:af609f6dee46 | 590 | uint32_t __get_CONTROL(void) |
igor_v | 11:af609f6dee46 | 591 | { |
igor_v | 11:af609f6dee46 | 592 | uint32_t result=0; |
igor_v | 11:af609f6dee46 | 593 | |
igor_v | 11:af609f6dee46 | 594 | __ASM volatile ("MRS %0, control" : "=r" (result) ); |
igor_v | 11:af609f6dee46 | 595 | return(result); |
igor_v | 11:af609f6dee46 | 596 | } |
igor_v | 11:af609f6dee46 | 597 | |
igor_v | 11:af609f6dee46 | 598 | /** |
igor_v | 11:af609f6dee46 | 599 | * @brief Set the Control Register value |
igor_v | 11:af609f6dee46 | 600 | * |
igor_v | 11:af609f6dee46 | 601 | * @param control Control value |
igor_v | 11:af609f6dee46 | 602 | * |
igor_v | 11:af609f6dee46 | 603 | * Set the control register |
igor_v | 11:af609f6dee46 | 604 | */ |
igor_v | 11:af609f6dee46 | 605 | void __set_CONTROL(uint32_t control) |
igor_v | 11:af609f6dee46 | 606 | { |
igor_v | 11:af609f6dee46 | 607 | __ASM volatile ("MSR control, %0" : : "r" (control) ); |
igor_v | 11:af609f6dee46 | 608 | } |
igor_v | 11:af609f6dee46 | 609 | |
igor_v | 11:af609f6dee46 | 610 | |
igor_v | 11:af609f6dee46 | 611 | /** |
igor_v | 11:af609f6dee46 | 612 | * @brief Reverse byte order in integer value |
igor_v | 11:af609f6dee46 | 613 | * |
igor_v | 11:af609f6dee46 | 614 | * @param value value to reverse |
igor_v | 11:af609f6dee46 | 615 | * @return reversed value |
igor_v | 11:af609f6dee46 | 616 | * |
igor_v | 11:af609f6dee46 | 617 | * Reverse byte order in integer value |
igor_v | 11:af609f6dee46 | 618 | */ |
igor_v | 11:af609f6dee46 | 619 | uint32_t __REV(uint32_t value) |
igor_v | 11:af609f6dee46 | 620 | { |
igor_v | 11:af609f6dee46 | 621 | uint32_t result=0; |
igor_v | 11:af609f6dee46 | 622 | |
igor_v | 11:af609f6dee46 | 623 | __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); |
igor_v | 11:af609f6dee46 | 624 | return(result); |
igor_v | 11:af609f6dee46 | 625 | } |
igor_v | 11:af609f6dee46 | 626 | |
igor_v | 11:af609f6dee46 | 627 | /** |
igor_v | 11:af609f6dee46 | 628 | * @brief Reverse byte order in unsigned short value |
igor_v | 11:af609f6dee46 | 629 | * |
igor_v | 11:af609f6dee46 | 630 | * @param value value to reverse |
igor_v | 11:af609f6dee46 | 631 | * @return reversed value |
igor_v | 11:af609f6dee46 | 632 | * |
igor_v | 11:af609f6dee46 | 633 | * Reverse byte order in unsigned short value |
igor_v | 11:af609f6dee46 | 634 | */ |
igor_v | 11:af609f6dee46 | 635 | uint32_t __REV16(uint16_t value) |
igor_v | 11:af609f6dee46 | 636 | { |
igor_v | 11:af609f6dee46 | 637 | uint32_t result=0; |
igor_v | 11:af609f6dee46 | 638 | |
igor_v | 11:af609f6dee46 | 639 | __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); |
igor_v | 11:af609f6dee46 | 640 | return(result); |
igor_v | 11:af609f6dee46 | 641 | } |
igor_v | 11:af609f6dee46 | 642 | |
igor_v | 11:af609f6dee46 | 643 | /** |
igor_v | 11:af609f6dee46 | 644 | * @brief Reverse byte order in signed short value with sign extension to integer |
igor_v | 11:af609f6dee46 | 645 | * |
igor_v | 11:af609f6dee46 | 646 | * @param value value to reverse |
igor_v | 11:af609f6dee46 | 647 | * @return reversed value |
igor_v | 11:af609f6dee46 | 648 | * |
igor_v | 11:af609f6dee46 | 649 | * Reverse byte order in signed short value with sign extension to integer |
igor_v | 11:af609f6dee46 | 650 | */ |
igor_v | 11:af609f6dee46 | 651 | int32_t __REVSH(int16_t value) |
igor_v | 11:af609f6dee46 | 652 | { |
igor_v | 11:af609f6dee46 | 653 | uint32_t result=0; |
igor_v | 11:af609f6dee46 | 654 | |
igor_v | 11:af609f6dee46 | 655 | __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); |
igor_v | 11:af609f6dee46 | 656 | return(result); |
igor_v | 11:af609f6dee46 | 657 | } |
igor_v | 11:af609f6dee46 | 658 | |
igor_v | 11:af609f6dee46 | 659 | /** |
igor_v | 11:af609f6dee46 | 660 | * @brief Reverse bit order of value |
igor_v | 11:af609f6dee46 | 661 | * |
igor_v | 11:af609f6dee46 | 662 | * @param value value to reverse |
igor_v | 11:af609f6dee46 | 663 | * @return reversed value |
igor_v | 11:af609f6dee46 | 664 | * |
igor_v | 11:af609f6dee46 | 665 | * Reverse bit order of value |
igor_v | 11:af609f6dee46 | 666 | */ |
igor_v | 11:af609f6dee46 | 667 | uint32_t __RBIT(uint32_t value) |
igor_v | 11:af609f6dee46 | 668 | { |
igor_v | 11:af609f6dee46 | 669 | uint32_t result=0; |
igor_v | 11:af609f6dee46 | 670 | |
igor_v | 11:af609f6dee46 | 671 | __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); |
igor_v | 11:af609f6dee46 | 672 | return(result); |
igor_v | 11:af609f6dee46 | 673 | } |
igor_v | 11:af609f6dee46 | 674 | |
igor_v | 11:af609f6dee46 | 675 | /** |
igor_v | 11:af609f6dee46 | 676 | * @brief LDR Exclusive (8 bit) |
igor_v | 11:af609f6dee46 | 677 | * |
igor_v | 11:af609f6dee46 | 678 | * @param *addr address pointer |
igor_v | 11:af609f6dee46 | 679 | * @return value of (*address) |
igor_v | 11:af609f6dee46 | 680 | * |
igor_v | 11:af609f6dee46 | 681 | * Exclusive LDR command for 8 bit value |
igor_v | 11:af609f6dee46 | 682 | */ |
igor_v | 11:af609f6dee46 | 683 | uint8_t __LDREXB(uint8_t *addr) |
igor_v | 11:af609f6dee46 | 684 | { |
igor_v | 11:af609f6dee46 | 685 | uint8_t result=0; |
igor_v | 11:af609f6dee46 | 686 | |
igor_v | 11:af609f6dee46 | 687 | __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); |
igor_v | 11:af609f6dee46 | 688 | return(result); |
igor_v | 11:af609f6dee46 | 689 | } |
igor_v | 11:af609f6dee46 | 690 | |
igor_v | 11:af609f6dee46 | 691 | /** |
igor_v | 11:af609f6dee46 | 692 | * @brief LDR Exclusive (16 bit) |
igor_v | 11:af609f6dee46 | 693 | * |
igor_v | 11:af609f6dee46 | 694 | * @param *addr address pointer |
igor_v | 11:af609f6dee46 | 695 | * @return value of (*address) |
igor_v | 11:af609f6dee46 | 696 | * |
igor_v | 11:af609f6dee46 | 697 | * Exclusive LDR command for 16 bit values |
igor_v | 11:af609f6dee46 | 698 | */ |
igor_v | 11:af609f6dee46 | 699 | uint16_t __LDREXH(uint16_t *addr) |
igor_v | 11:af609f6dee46 | 700 | { |
igor_v | 11:af609f6dee46 | 701 | uint16_t result=0; |
igor_v | 11:af609f6dee46 | 702 | |
igor_v | 11:af609f6dee46 | 703 | __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); |
igor_v | 11:af609f6dee46 | 704 | return(result); |
igor_v | 11:af609f6dee46 | 705 | } |
igor_v | 11:af609f6dee46 | 706 | |
igor_v | 11:af609f6dee46 | 707 | /** |
igor_v | 11:af609f6dee46 | 708 | * @brief LDR Exclusive (32 bit) |
igor_v | 11:af609f6dee46 | 709 | * |
igor_v | 11:af609f6dee46 | 710 | * @param *addr address pointer |
igor_v | 11:af609f6dee46 | 711 | * @return value of (*address) |
igor_v | 11:af609f6dee46 | 712 | * |
igor_v | 11:af609f6dee46 | 713 | * Exclusive LDR command for 32 bit values |
igor_v | 11:af609f6dee46 | 714 | */ |
igor_v | 11:af609f6dee46 | 715 | uint32_t __LDREXW(uint32_t *addr) |
igor_v | 11:af609f6dee46 | 716 | { |
igor_v | 11:af609f6dee46 | 717 | uint32_t result=0; |
igor_v | 11:af609f6dee46 | 718 | |
igor_v | 11:af609f6dee46 | 719 | __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); |
igor_v | 11:af609f6dee46 | 720 | return(result); |
igor_v | 11:af609f6dee46 | 721 | } |
igor_v | 11:af609f6dee46 | 722 | |
igor_v | 11:af609f6dee46 | 723 | /** |
igor_v | 11:af609f6dee46 | 724 | * @brief STR Exclusive (8 bit) |
igor_v | 11:af609f6dee46 | 725 | * |
igor_v | 11:af609f6dee46 | 726 | * @param value value to store |
igor_v | 11:af609f6dee46 | 727 | * @param *addr address pointer |
igor_v | 11:af609f6dee46 | 728 | * @return successful / failed |
igor_v | 11:af609f6dee46 | 729 | * |
igor_v | 11:af609f6dee46 | 730 | * Exclusive STR command for 8 bit values |
igor_v | 11:af609f6dee46 | 731 | */ |
igor_v | 11:af609f6dee46 | 732 | uint32_t __STREXB(uint8_t value, uint8_t *addr) |
igor_v | 11:af609f6dee46 | 733 | { |
igor_v | 11:af609f6dee46 | 734 | uint32_t result=0; |
igor_v | 11:af609f6dee46 | 735 | |
igor_v | 11:af609f6dee46 | 736 | __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); |
igor_v | 11:af609f6dee46 | 737 | return(result); |
igor_v | 11:af609f6dee46 | 738 | } |
igor_v | 11:af609f6dee46 | 739 | |
igor_v | 11:af609f6dee46 | 740 | /** |
igor_v | 11:af609f6dee46 | 741 | * @brief STR Exclusive (16 bit) |
igor_v | 11:af609f6dee46 | 742 | * |
igor_v | 11:af609f6dee46 | 743 | * @param value value to store |
igor_v | 11:af609f6dee46 | 744 | * @param *addr address pointer |
igor_v | 11:af609f6dee46 | 745 | * @return successful / failed |
igor_v | 11:af609f6dee46 | 746 | * |
igor_v | 11:af609f6dee46 | 747 | * Exclusive STR command for 16 bit values |
igor_v | 11:af609f6dee46 | 748 | */ |
igor_v | 11:af609f6dee46 | 749 | uint32_t __STREXH(uint16_t value, uint16_t *addr) |
igor_v | 11:af609f6dee46 | 750 | { |
igor_v | 11:af609f6dee46 | 751 | uint32_t result=0; |
igor_v | 11:af609f6dee46 | 752 | |
igor_v | 11:af609f6dee46 | 753 | __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); |
igor_v | 11:af609f6dee46 | 754 | return(result); |
igor_v | 11:af609f6dee46 | 755 | } |
igor_v | 11:af609f6dee46 | 756 | |
igor_v | 11:af609f6dee46 | 757 | /** |
igor_v | 11:af609f6dee46 | 758 | * @brief STR Exclusive (32 bit) |
igor_v | 11:af609f6dee46 | 759 | * |
igor_v | 11:af609f6dee46 | 760 | * @param value value to store |
igor_v | 11:af609f6dee46 | 761 | * @param *addr address pointer |
igor_v | 11:af609f6dee46 | 762 | * @return successful / failed |
igor_v | 11:af609f6dee46 | 763 | * |
igor_v | 11:af609f6dee46 | 764 | * Exclusive STR command for 32 bit values |
igor_v | 11:af609f6dee46 | 765 | */ |
igor_v | 11:af609f6dee46 | 766 | uint32_t __STREXW(uint32_t value, uint32_t *addr) |
igor_v | 11:af609f6dee46 | 767 | { |
igor_v | 11:af609f6dee46 | 768 | uint32_t result=0; |
igor_v | 11:af609f6dee46 | 769 | |
igor_v | 11:af609f6dee46 | 770 | __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); |
igor_v | 11:af609f6dee46 | 771 | return(result); |
igor_v | 11:af609f6dee46 | 772 | } |
igor_v | 11:af609f6dee46 | 773 | |
igor_v | 11:af609f6dee46 | 774 | |
igor_v | 11:af609f6dee46 | 775 | #elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ |
igor_v | 11:af609f6dee46 | 776 | /* TASKING carm specific functions */ |
igor_v | 11:af609f6dee46 | 777 | |
igor_v | 11:af609f6dee46 | 778 | /* |
igor_v | 11:af609f6dee46 | 779 | * The CMSIS functions have been implemented as intrinsics in the compiler. |
igor_v | 11:af609f6dee46 | 780 | * Please use "carm -?i" to get an up to date list of all instrinsics, |
igor_v | 11:af609f6dee46 | 781 | * Including the CMSIS ones. |
igor_v | 11:af609f6dee46 | 782 | */ |
igor_v | 11:af609f6dee46 | 783 | |
igor_v | 11:af609f6dee46 | 784 | #endif |
igor_v | 11:af609f6dee46 | 785 |