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Diff: system_LPC17xx.c
- Revision:
- 44:80289a836583
- Parent:
- 12:74bd0ecf7f83
- Child:
- 46:2670fa0fcebc
--- a/system_LPC17xx.c Sun Feb 07 16:01:14 2016 +0000 +++ b/system_LPC17xx.c Tue Feb 09 07:47:33 2016 +0000 @@ -280,16 +280,82 @@ // // </e> */ + #define CLOCK_SETUP 1 -#define SCS_Val 0x00000020 -#define CLKSRCSEL_Val 0x00000001 +//System control - system control and status register: +// bit 4 - main oscillator range: +// 0 - 1...20MHz +// 1 - 15...25MHz +// bit 5 - main oscillator enable +// 0 - disabled +// 1 - enabled +// bit 6 - main oscillator status +// 0 - not ready +// 1 - ready +#define SCS_Val 0x00000020 //Enable main oscillator,1...20MHz +//Clock Source Select register +// bits 0-1: +// 00 - Selects the Internal RC oscillator as the PLL0 clock source (default) +// 01 - Selects the main oscillator as the PLL0 clock source +// 10 - Selects the RTC oscillator as the PLL0 clock source +// 11 - Reserved, do not use this setting +#define CLKSRCSEL_Val 0x00000001//Select the main oscillator as the PLL0 clock source #define PLL0_SETUP 1 -#define PLL0CFG_Val 0x00050063 +//PLL0 Configuration register +// bits 0...14 - PLL0 multiplier value minus 1. Supported multiplier M range 6...512 +// bits 16...23 - PLL0 Pre-Divider value minus 1. Supported divider N range 1...32 +// Fcc0 = (2 * M * Fin) / N +#define PLL0CFG_Val 0x00050063//M - 100, N - 6, output = 2 * 100 * 12MHz / 6 = 400MHz #define PLL1_SETUP 1 -#define PLL1CFG_Val 0x00000023 -#define CCLKCFG_Val 0x00000003 -#define USBCLKCFG_Val 0x00000000 -#define PCLKSEL0_Val 0x00000010 +#define PLL1CFG_Val 0x00000023//M - 36, N - 1, output = 2 * 36 * 12MHz / 1 = 864MHz? +//CPU Clock Configure Register +#define CCLKCFG_Val 0x00000003 //Divide by 4 +//USB Clock Configuration register +// bits 0...3 +// 5 - PLL0 output is divided by 6. PLL0 output must be 288 MHz +// 7 - PLL0 output is divided by 8. PLL0 output must be 384 MHz +// 9 - PLL0 output is divided by 10. PLL0 output must be 480 MHz +#define USBCLKCFG_Val 0x00000000//default +//Peripheral Clock Selection register 0 +// 1:0 PCLK_WDT Peripheral clock selection for WDT. 00 +// 3:2 PCLK_TIMER0 Peripheral clock selection for TIMER0. 00 +// 5:4 PCLK_TIMER1 Peripheral clock selection for TIMER1. 00 +// 7:6 PCLK_UART0 Peripheral clock selection for UART0. 00 +// 9:8 PCLK_UART1 Peripheral clock selection for UART1. 00 +// 11:10 - Reserved. NA +// 13:12 PCLK_PWM1 Peripheral clock selection for PWM1. 00 +// 15:14 PCLK_I2C0 Peripheral clock selection for I2C0. 00 +// 17:16 PCLK_SPI Peripheral clock selection for SPI. 00 +// 19:18 - Reserved. NA +// 21:20 PCLK_SSP1 Peripheral clock selection for SSP1. 00 +// 23:22 PCLK_DAC Peripheral clock selection for DAC. 00 +// 25:24 PCLK_ADC Peripheral clock selection for ADC. 00 +// 27:26 PCLK_CAN1 Peripheral clock selection for CAN1.[1] 00 +// 29:28 PCLK_CAN2 Peripheral clock selection for CAN2.[1] 00 +// 31:30 PCLK_ACF Peripheral clock selection for CAN acceptance filtering +// bits values: +// 00 PCLK_peripheral = CCLK/4 +// 01 PCLK_peripheral = CCLK +// 10 PCLK_peripheral = CCLK/2 +// 11 PCLK_peripheral = CCLK/8, except for CAN1, CAN2, and CAN filtering when “11” selects = CCLK/6. +#define PCLKSEL0_Val 0x00000010//Peripheral clock selection for TIMER1 - CCLK +//Peripheral Clock Selection register 1 +// 1:0 PCLK_QEI Peripheral clock selection for the Quadrature Encoder Interface.00 +// 3:2 PCLK_GPIOINT Peripheral clock selection for GPIO interrupts. 00 +// 5:4 PCLK_PCB Peripheral clock selection for the Pin Connect block. 00 +// 7:6 PCLK_I2C1 Peripheral clock selection for I2C1. 00 +// 9:8 - Reserved. NA +// 11:10 PCLK_SSP0 Peripheral clock selection for SSP0. 00 +// 13:12 PCLK_TIMER2 Peripheral clock selection for TIMER2. 00 +// 15:14 PCLK_TIMER3 Peripheral clock selection for TIMER3. 00 +// 17:16 PCLK_UART2 Peripheral clock selection for UART2. 00 +// 19:18 PCLK_UART3 Peripheral clock selection for UART3. 00 +// 21:20 PCLK_I2C2 Peripheral clock selection for I2C2. 00 +// 23:22 PCLK_I2S Peripheral clock selection for I2S. 00 +// 25:24 - Reserved. NA +// 27:26 PCLK_RIT Peripheral clock selection for Repetitive Interrupt Timer. 00 +// 29:28 PCLK_SYSCON Peripheral clock selection for the System Control block. 00 +// 31:30 PCLK_MC Peripheral clock selection for the Motor Control PWM #define PCLKSEL1_Val 0x00000000 #define PCONP_Val 0x046887DE #define CLKOUTCFG_Val 0x00000000 @@ -482,33 +548,48 @@ void SystemInit1 (void) { #if (CLOCK_SETUP) /* Clock Setup */ - LPC_SC->SCS = SCS_Val; + //Init system control and status register + LPC_SC->SCS = SCS_Val;//0x20 - enable main oscillator,1...20MHz (12MHz) if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */ while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */ } - LPC_SC->CCLKCFG = CCLKCFG_Val; /* Setup Clock Divider */ + //Init CPU Clock Configure Register - select the divide value for creating the CPU clock (CCLK) from the PLL0 output + LPC_SC->CCLKCFG = CCLKCFG_Val; //3 - divide to 4 (3MHz) #if (PLL0_SETUP) - LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for PLL0 */ - - LPC_SC->PLL0CFG = PLL0CFG_Val; /* configure PLL0 */ + //Init Clock Source Select register + LPC_SC->CLKSRCSEL = CLKSRCSEL_Val;//1 - Select the main oscillator as the PLL0 clock source + //Init PLL0 Configuration register + LPC_SC->PLL0CFG = PLL0CFG_Val;//0x00050063: M - 100, N - 6, PLL0output = 2 * 100 * 12MHz / 6 = 400MHz, CPU clock 100MHz + //Init PLL0 Feed Register. This register enables loading of the PLL0 control and configuration information from the PLL0CON and PLL0CFG + //registers into the shadow registers that actually affect PLL0 operation. + //Write 0xAA and 0x55 sequentially to update shadow registers and settings to take effect LPC_SC->PLL0FEED = 0xAA; LPC_SC->PLL0FEED = 0x55; - - LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */ + //Init PLL0 Control register + // bit 0 - PLL0 Enable + // bit 1 - PLL0 connect + LPC_SC->PLL0CON = 0x01;//PLL0 Enable + //Update shadow registers to settings take effect LPC_SC->PLL0FEED = 0xAA; LPC_SC->PLL0FEED = 0x55; - while (!(LPC_SC->PLL0STAT & (1<<26)));/* Wait for PLOCK0 */ + //PLL0 Status register + // bits 0...14 - Read-back for the PLL0 Multiplier value + // bits 16...23 - Read-back for the PLL0 Pre-Divider value + // bit 24 - Read-back for the PLL0 Enable bit + // bit 25 - Read-back for the PLL0 Connect bit + // bit 26 - Reflects the PLL0 Lock status: 1 - locked + while (!(LPC_SC->PLL0STAT & (1<<26)));//Wait while PLL0 locked (PLOCK0) - LPC_SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */ + LPC_SC->PLL0CON = 0x03;//PLL0 Enable & Connect LPC_SC->PLL0FEED = 0xAA; LPC_SC->PLL0FEED = 0x55; - while (!(LPC_SC->PLL0STAT & ((1<<25) | (1<<24))));/* Wait for PLLC0_STAT & PLLE0_STAT */ + while (!(LPC_SC->PLL0STAT & ((1<<25) | (1<<24))));//Wait while PLL0 connected (PLLC0_STAT & PLLE0_STAT) #endif #if (PLL1_SETUP) - LPC_SC->PLL1CFG = PLL1CFG_Val; + LPC_SC->PLL1CFG = PLL1CFG_Val;//0x23 M - 36, N - 1, output = 2 * 36 * 12MHz / 1 = 864MHz? LPC_SC->PLL1FEED = 0xAA; LPC_SC->PLL1FEED = 0x55;