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DeviceUserPort.c@161:efd949e8d536, 2016-05-15 (annotated)
- Committer:
- Diletant
- Date:
- Sun May 15 19:12:12 2016 +0000
- Revision:
- 161:efd949e8d536
- Child:
- 167:bedc0a9d559a
Device & ... update. Not final!!!
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
Diletant | 161:efd949e8d536 | 1 | #include "Device.h" |
Diletant | 161:efd949e8d536 | 2 | |
Diletant | 161:efd949e8d536 | 3 | extern Device device; |
Diletant | 161:efd949e8d536 | 4 | extern unsigned int SystemCoreClock1; |
Diletant | 161:efd949e8d536 | 5 | |
Diletant | 161:efd949e8d536 | 6 | void InitUserPortWithDefaults(void) { |
Diletant | 161:efd949e8d536 | 7 | device.controller.uart[1].settings.baudRate = 38400; |
Diletant | 161:efd949e8d536 | 8 | } |
Diletant | 161:efd949e8d536 | 9 | |
Diletant | 161:efd949e8d536 | 10 | void InitUserPort(void) |
Diletant | 161:efd949e8d536 | 11 | { |
Diletant | 161:efd949e8d536 | 12 | uint32_t Fdiv; |
Diletant | 161:efd949e8d536 | 13 | uint32_t pclkdiv, pclk; |
Diletant | 161:efd949e8d536 | 14 | |
Diletant | 161:efd949e8d536 | 15 | LPC_PINCON->PINSEL4 &= ~0x0000000F; |
Diletant | 161:efd949e8d536 | 16 | LPC_PINCON->PINSEL4 |= 0x0000000A; //Enable RxD1 P2.1, TxD1 P2.0 |
Diletant | 161:efd949e8d536 | 17 | |
Diletant | 161:efd949e8d536 | 18 | //By default, the PCLKSELx value is zero, thus, the PCLK for all the peripherals is 1/4 of the SystemFrequency. |
Diletant | 161:efd949e8d536 | 19 | //Bit 8,9 are for UART1 |
Diletant | 161:efd949e8d536 | 20 | pclkdiv = (LPC_SC->PCLKSEL0 >> 8) & 0x03; |
Diletant | 161:efd949e8d536 | 21 | switch ( pclkdiv ) { |
Diletant | 161:efd949e8d536 | 22 | case 0x00: |
Diletant | 161:efd949e8d536 | 23 | default: |
Diletant | 161:efd949e8d536 | 24 | pclk = SystemCoreClock1/4; |
Diletant | 161:efd949e8d536 | 25 | break; |
Diletant | 161:efd949e8d536 | 26 | case 0x01: |
Diletant | 161:efd949e8d536 | 27 | pclk = SystemCoreClock1; |
Diletant | 161:efd949e8d536 | 28 | break; |
Diletant | 161:efd949e8d536 | 29 | case 0x02: |
Diletant | 161:efd949e8d536 | 30 | pclk = SystemCoreClock1/2; |
Diletant | 161:efd949e8d536 | 31 | break; |
Diletant | 161:efd949e8d536 | 32 | case 0x03: |
Diletant | 161:efd949e8d536 | 33 | pclk = SystemCoreClock1/8; |
Diletant | 161:efd949e8d536 | 34 | break; |
Diletant | 161:efd949e8d536 | 35 | } |
Diletant | 161:efd949e8d536 | 36 | |
Diletant | 161:efd949e8d536 | 37 | device.controller.uart[1].state.LCR = 0x83; |
Diletant | 161:efd949e8d536 | 38 | LPC_UART1->LCR = device.controller.uart[1].state.LCR; //8 bits, no Parity, 1 Stop bit |
Diletant | 161:efd949e8d536 | 39 | |
Diletant | 161:efd949e8d536 | 40 | Fdiv = ( pclk / 16 ) / device.controller.uart[1].settings.baudRate; /*baud rate */ |
Diletant | 161:efd949e8d536 | 41 | |
Diletant | 161:efd949e8d536 | 42 | device.controller.uart[1].state.DLM = Fdiv / 256; |
Diletant | 161:efd949e8d536 | 43 | LPC_UART1->DLM = device.controller.uart[1].state.DLM; |
Diletant | 161:efd949e8d536 | 44 | |
Diletant | 161:efd949e8d536 | 45 | device.controller.uart[1].state.DLL = Fdiv % 256; |
Diletant | 161:efd949e8d536 | 46 | LPC_UART1->DLL = device.controller.uart[1].state.DLL; |
Diletant | 161:efd949e8d536 | 47 | |
Diletant | 161:efd949e8d536 | 48 | device.controller.uart[1].state.LCR = 0x03; |
Diletant | 161:efd949e8d536 | 49 | LPC_UART1->LCR = device.controller.uart[1].state.LCR; //DLAB = 0 |
Diletant | 161:efd949e8d536 | 50 | |
Diletant | 161:efd949e8d536 | 51 | device.controller.uart[1].state.FCR = 0x03; |
Diletant | 161:efd949e8d536 | 52 | LPC_UART1->FCR = device.controller.uart[1].state.FCR; //Enable and reset TX and RX FIFO. |
Diletant | 161:efd949e8d536 | 53 | |
Diletant | 161:efd949e8d536 | 54 | //Uncomment to use interrupts |
Diletant | 161:efd949e8d536 | 55 | //NVIC_EnableIRQ(UART1_IRQn); |
Diletant | 161:efd949e8d536 | 56 | //LPC_UART1->IER = IER_RBR | IER_THRE | IER_RLS; /* Enable UART1 interrupt */ |
Diletant | 161:efd949e8d536 | 57 | } |
Diletant | 161:efd949e8d536 | 58 | |
Diletant | 161:efd949e8d536 | 59 | void DeviceUserPortReceive(void){ |
Diletant | 161:efd949e8d536 | 60 | if (LPC_UART1->LSR & 0x01) { |
Diletant | 161:efd949e8d536 | 61 | device.user.request.buffer.data[device.user.request.buffer.end] = LPC_UART1->RBR; |
Diletant | 161:efd949e8d536 | 62 | device.user.request.buffer.end = (device.user.request.buffer.end + 1) % InputBufferSize; |
Diletant | 161:efd949e8d536 | 63 | device.user.request.buffer.empty = 0; |
Diletant | 161:efd949e8d536 | 64 | device.user.decoder.canceled = 0; //Clear decode canceled flag |
Diletant | 161:efd949e8d536 | 65 | } |
Diletant | 161:efd949e8d536 | 66 | } |
Diletant | 161:efd949e8d536 | 67 | |
Diletant | 161:efd949e8d536 | 68 | void DeviceUserPortTransmit(void){ |
Diletant | 161:efd949e8d536 | 69 | if (device.user.response.ready) { |
Diletant | 161:efd949e8d536 | 70 | if ((device.user.response.type == RESPONSE_DELAYED) && (!device.user.response.triggered)) return; |
Diletant | 161:efd949e8d536 | 71 | |
Diletant | 161:efd949e8d536 | 72 | if (device.user.response.buffer.position < device.user.response.buffer.count) { |
Diletant | 161:efd949e8d536 | 73 | if (LPC_UART1->LSR & 0x20) { |
Diletant | 161:efd949e8d536 | 74 | LPC_UART1->THR = device.user.response.buffer.data[device.user.response.buffer.position]; |
Diletant | 161:efd949e8d536 | 75 | device.user.response.buffer.position++; |
Diletant | 161:efd949e8d536 | 76 | if (device.user.response.buffer.position == device.user.response.buffer.count){ |
Diletant | 161:efd949e8d536 | 77 | device.user.response.ready = 0; |
Diletant | 161:efd949e8d536 | 78 | if (device.user.response.type == RESPONSE_PERIODIC) { |
Diletant | 161:efd949e8d536 | 79 | device.user.response.enabled = 1; //next response required |
Diletant | 161:efd949e8d536 | 80 | } |
Diletant | 161:efd949e8d536 | 81 | device.user.response.buffer.count = 0; |
Diletant | 161:efd949e8d536 | 82 | device.user.response.buffer.position = 0; |
Diletant | 161:efd949e8d536 | 83 | } |
Diletant | 161:efd949e8d536 | 84 | } |
Diletant | 161:efd949e8d536 | 85 | } |
Diletant | 161:efd949e8d536 | 86 | } |
Diletant | 161:efd949e8d536 | 87 | } |
Diletant | 161:efd949e8d536 | 88 | |
Diletant | 161:efd949e8d536 | 89 | //Not used |
Diletant | 161:efd949e8d536 | 90 | /* |
Diletant | 161:efd949e8d536 | 91 | #define IER_RBR 0x01 |
Diletant | 161:efd949e8d536 | 92 | #define IER_THRE 0x02 |
Diletant | 161:efd949e8d536 | 93 | #define IER_RLS 0x04 |
Diletant | 161:efd949e8d536 | 94 | |
Diletant | 161:efd949e8d536 | 95 | #define IIR_PEND 0x01 |
Diletant | 161:efd949e8d536 | 96 | #define IIR_RLS 0x03 |
Diletant | 161:efd949e8d536 | 97 | #define IIR_RDA 0x02 |
Diletant | 161:efd949e8d536 | 98 | #define IIR_CTI 0x06 |
Diletant | 161:efd949e8d536 | 99 | #define IIR_THRE 0x01 |
Diletant | 161:efd949e8d536 | 100 | |
Diletant | 161:efd949e8d536 | 101 | #define LSR_RDR 0x01 |
Diletant | 161:efd949e8d536 | 102 | #define LSR_OE 0x02 |
Diletant | 161:efd949e8d536 | 103 | #define LSR_PE 0x04 |
Diletant | 161:efd949e8d536 | 104 | #define LSR_FE 0x08 |
Diletant | 161:efd949e8d536 | 105 | #define LSR_BI 0x10 |
Diletant | 161:efd949e8d536 | 106 | #define LSR_THRE 0x20 |
Diletant | 161:efd949e8d536 | 107 | #define LSR_TEMT 0x40 |
Diletant | 161:efd949e8d536 | 108 | #define LSR_RXFE 0x80 |
Diletant | 161:efd949e8d536 | 109 | |
Diletant | 161:efd949e8d536 | 110 | void UART1Send(void) |
Diletant | 161:efd949e8d536 | 111 | { |
Diletant | 161:efd949e8d536 | 112 | uint8_t pos = 0; |
Diletant | 161:efd949e8d536 | 113 | while (device.host.response.buffer.count != pos ) { |
Diletant | 161:efd949e8d536 | 114 | //THRE status, contain valid data |
Diletant | 161:efd949e8d536 | 115 | while ( !(device.host.port.TxEmpty & 0x01) ); |
Diletant | 161:efd949e8d536 | 116 | LPC_UART1->THR = device.host.response.buffer.data[pos]; |
Diletant | 161:efd949e8d536 | 117 | device.host.port.TxEmpty = 0; //not empty in the THR until it shifts out |
Diletant | 161:efd949e8d536 | 118 | pos++; |
Diletant | 161:efd949e8d536 | 119 | } |
Diletant | 161:efd949e8d536 | 120 | device.host.response.buffer.count = 0; |
Diletant | 161:efd949e8d536 | 121 | } |
Diletant | 161:efd949e8d536 | 122 | |
Diletant | 161:efd949e8d536 | 123 | //Not used |
Diletant | 161:efd949e8d536 | 124 | __irq void UART1_IRQHandler (void) |
Diletant | 161:efd949e8d536 | 125 | { |
Diletant | 161:efd949e8d536 | 126 | uint8_t IIRValue, LSRValue; |
Diletant | 161:efd949e8d536 | 127 | uint8_t Dummy = Dummy; |
Diletant | 161:efd949e8d536 | 128 | |
Diletant | 161:efd949e8d536 | 129 | IIRValue = LPC_UART1->IIR; |
Diletant | 161:efd949e8d536 | 130 | |
Diletant | 161:efd949e8d536 | 131 | IIRValue >>= 1; //skip pending bit in IIR |
Diletant | 161:efd949e8d536 | 132 | IIRValue &= 0x07; //check bit 1~3, interrupt identification |
Diletant | 161:efd949e8d536 | 133 | if ( IIRValue == IIR_RLS ) // Receive Line Status |
Diletant | 161:efd949e8d536 | 134 | { |
Diletant | 161:efd949e8d536 | 135 | LSRValue = LPC_UART1->LSR; |
Diletant | 161:efd949e8d536 | 136 | //Receive Line Status |
Diletant | 161:efd949e8d536 | 137 | if ( LSRValue & (LSR_OE|LSR_PE|LSR_FE|LSR_RXFE|LSR_BI) ) |
Diletant | 161:efd949e8d536 | 138 | { |
Diletant | 161:efd949e8d536 | 139 | //There are errors or break interrupt |
Diletant | 161:efd949e8d536 | 140 | //Read LSR will clear the interrupt |
Diletant | 161:efd949e8d536 | 141 | device.host.port.status = LSRValue; |
Diletant | 161:efd949e8d536 | 142 | Dummy = LPC_UART1->RBR;//Dummy read on RX to clear interrupt, then bail out |
Diletant | 161:efd949e8d536 | 143 | return; |
Diletant | 161:efd949e8d536 | 144 | } |
Diletant | 161:efd949e8d536 | 145 | if ( LSRValue & LSR_RDR )//Receive Data Ready |
Diletant | 161:efd949e8d536 | 146 | { |
Diletant | 161:efd949e8d536 | 147 | //If no error on RLS, normal ready, save into the data buffer. |
Diletant | 161:efd949e8d536 | 148 | //Note: read RBR will clear the interrupt |
Diletant | 161:efd949e8d536 | 149 | device.host.request.buffer.data[device.host.request.buffer.end] = LPC_UART1->RBR; |
Diletant | 161:efd949e8d536 | 150 | device.host.request.buffer.end = (device.host.request.buffer.end + 1) % InputBufferSize; |
Diletant | 161:efd949e8d536 | 151 | } |
Diletant | 161:efd949e8d536 | 152 | } |
Diletant | 161:efd949e8d536 | 153 | else if ( IIRValue == IIR_RDA ) //Receive Data Available |
Diletant | 161:efd949e8d536 | 154 | { |
Diletant | 161:efd949e8d536 | 155 | device.host.request.buffer.data[device.host.request.buffer.end] = LPC_UART1->RBR; |
Diletant | 161:efd949e8d536 | 156 | device.host.request.buffer.end = (device.host.request.buffer.end + 1) % InputBufferSize; |
Diletant | 161:efd949e8d536 | 157 | } |
Diletant | 161:efd949e8d536 | 158 | else if ( IIRValue == IIR_CTI ) //Character timeout indicator |
Diletant | 161:efd949e8d536 | 159 | { |
Diletant | 161:efd949e8d536 | 160 | //Character Time-out indicator |
Diletant | 161:efd949e8d536 | 161 | device.host.port.status |= 0x100; //Bit 9 as the CTI error |
Diletant | 161:efd949e8d536 | 162 | } |
Diletant | 161:efd949e8d536 | 163 | else if ( IIRValue == IIR_THRE ) //THRE, transmit holding register empty |
Diletant | 161:efd949e8d536 | 164 | { |
Diletant | 161:efd949e8d536 | 165 | //THRE interrupt |
Diletant | 161:efd949e8d536 | 166 | LSRValue = LPC_UART1->LSR; //Check status in the LSR to see if valid data in U0THR or not |
Diletant | 161:efd949e8d536 | 167 | if ( LSRValue & LSR_THRE ) |
Diletant | 161:efd949e8d536 | 168 | { |
Diletant | 161:efd949e8d536 | 169 | device.host.port.TxEmpty = 1; |
Diletant | 161:efd949e8d536 | 170 | } |
Diletant | 161:efd949e8d536 | 171 | else |
Diletant | 161:efd949e8d536 | 172 | { |
Diletant | 161:efd949e8d536 | 173 | device.host.port.TxEmpty = 0; |
Diletant | 161:efd949e8d536 | 174 | } |
Diletant | 161:efd949e8d536 | 175 | } |
Diletant | 161:efd949e8d536 | 176 | }*/ |