Lukasz Uszko
SX1278 RA-01, RA-02 LoRa library
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sx1278.c
00001 /** 00002 * @brief: Implementation of a SX1278 radio functions 00003 * @author: luk6xff based on SEMTCH code: https://github.com/Lora-net/LoRaMac-node 00004 * @email: luszko@op.pl 00005 * @date: 2019-11-15 00006 */ 00007 #include "registers.h" 00008 #include "sx1278.h" 00009 00010 #include <math.h> 00011 #include <string.h> 00012 00013 /** 00014 * ============================================================================ 00015 * @brief Private global constants 00016 * ============================================================================ 00017 */ 00018 //----------------------------------------------------------------------------- 00019 /** 00020 * Precomputed FSK bandwidth registers values 00021 */ 00022 static const BandwidthMap_t SX1278FskBandwidths[] = 00023 { 00024 { 2600 , 0x17 }, 00025 { 3100 , 0x0F }, 00026 { 3900 , 0x07 }, 00027 { 5200 , 0x16 }, 00028 { 6300 , 0x0E }, 00029 { 7800 , 0x06 }, 00030 { 10400 , 0x15 }, 00031 { 12500 , 0x0D }, 00032 { 15600 , 0x05 }, 00033 { 20800 , 0x14 }, 00034 { 25000 , 0x0C }, 00035 { 31300 , 0x04 }, 00036 { 41700 , 0x13 }, 00037 { 50000 , 0x0B }, 00038 { 62500 , 0x03 }, 00039 { 83333 , 0x12 }, 00040 { 100000, 0x0A }, 00041 { 125000, 0x02 }, 00042 { 166700, 0x11 }, 00043 { 200000, 0x09 }, 00044 { 250000, 0x01 }, 00045 { 300000, 0x00 }, // Invalid Bandwidth 00046 }; 00047 00048 //----------------------------------------------------------------------------- 00049 /** 00050 * @brief Precomputed LORA bandwidth registers values 00051 */ 00052 static const BandwidthMap_t SX1278LoRaBandwidths[] = 00053 { 00054 { 7800, 0 }, // 7.8 kHz requires TCXO 00055 { 10400, 1 }, // 10.4 kHz requires TCXO 00056 { 15600, 2 }, // 15.6 kHz requires TCXO 00057 { 20800, 3 }, // 20.8 kHz requires TCXO 00058 { 31250, 4 }, // 31.25 kHz requires TCXO 00059 { 41700, 5 }, // 41.7 kHz requires TCXO 00060 { 62500, 6 }, // 62.5 kHz requires TCXO 00061 { 125000, 7 }, // 125 kHz the LoRa protocol default 00062 { 250000, 8 }, // 250 kHz 00063 { 500000, 9 }, // 500 kHz 00064 { 600000, 10 },// Invalid Bandwidth, reserved 00065 }; 00066 00067 //----------------------------------------------------------------------------- 00068 /** 00069 * @brief Radio hardware registers initialization definition 00070 */ 00071 static const RadioRegisters_t SX1278RadioRegsInit[] = 00072 { \ 00073 { MODEM_FSK , REG_LNA , 0x23 },\ 00074 { MODEM_FSK , REG_RXCONFIG , 0x1E },\ 00075 { MODEM_FSK , REG_RSSICONFIG , 0xD2 },\ 00076 { MODEM_FSK , REG_AFCFEI , 0x01 },\ 00077 { MODEM_FSK , REG_PREAMBLEDETECT , 0xAA },\ 00078 { MODEM_FSK , REG_OSC , 0x07 },\ 00079 { MODEM_FSK , REG_SYNCCONFIG , 0x12 },\ 00080 { MODEM_FSK , REG_SYNCVALUE1 , 0xC1 },\ 00081 { MODEM_FSK , REG_SYNCVALUE2 , 0x94 },\ 00082 { MODEM_FSK , REG_SYNCVALUE3 , 0xC1 },\ 00083 { MODEM_FSK , REG_PACKETCONFIG1 , 0xD8 },\ 00084 { MODEM_FSK , REG_FIFOTHRESH , 0x8F },\ 00085 { MODEM_FSK , REG_IMAGECAL , 0x02 },\ 00086 { MODEM_FSK , REG_DIOMAPPING1 , 0x00 },\ 00087 { MODEM_FSK , REG_DIOMAPPING2 , 0x30 },\ 00088 { MODEM_LORA, REG_LR_PAYLOADMAXLENGTH, 0x40 },\ 00089 }; 00090 00091 00092 /** 00093 * ============================================================================ 00094 * @brief Private functions prototypes 00095 * ============================================================================ 00096 */ 00097 00098 /** 00099 * @brief Performs the Rx chain calibration for LF and HF bands 00100 * @note Must be called just after the reset so all registers are at their 00101 * default values 00102 */ 00103 static void RxChainCalibration(void); 00104 00105 /** 00106 * Returns the known FSK bandwidth registers value 00107 * 00108 * @param [IN] bandwidth Bandwidth value in Hz 00109 * @retval regValue Bandwidth register value. 00110 */ 00111 static uint8_t GetFskBandwidthRegValue(uint32_t bandwidth); 00112 00113 /** 00114 * Returns the known LORA bandwidth registers value 00115 * 00116 * @param [IN] bandwidth Bandwidth value in Hz 00117 * @retval regValue Bandwidth register value. 00118 */ 00119 static uint8_t GetLoRaBandwidthRegValue(uint32_t bandwidth); 00120 00121 00122 /** 00123 * @brief DIO 0 IRQ callback 00124 */ 00125 static void OnDio0Irq(); 00126 00127 /** 00128 * @brief DIO 1 IRQ callback 00129 */ 00130 static void OnDio1Irq(); 00131 00132 /** 00133 * @brief DIO 2 IRQ callback 00134 */ 00135 static void OnDio2Irq(); 00136 00137 /** 00138 * @brief DIO 3 IRQ callback 00139 */ 00140 static void OnDio3Irq(); 00141 00142 /** 00143 * @brief DIO 4 IRQ callback 00144 */ 00145 static void OnDio4Irq(); 00146 00147 /** 00148 * @brief DIO 5 IRQ callback 00149 */ 00150 static void OnDio5Irq(); 00151 00152 /** 00153 * @brief Tx & Rx timeout timer callback 00154 */ 00155 static void OnTimeoutIrq(); 00156 00157 00158 00159 /** 00160 * ============================================================================ 00161 * @brief Private global variables 00162 * ============================================================================ 00163 */ 00164 00165 /** 00166 * Radio callbacks variable 00167 */ 00168 static RadioEvents_t* RadioEvents; 00169 00170 /** 00171 * Reception buffer 00172 */ 00173 static uint8_t RxTxBuffer[RX_BUFFER_SIZE]; 00174 00175 /** 00176 * Hardware DIO IRQ functions 00177 */ 00178 DioIrqHandler dioIrq[] = { OnDio0Irq, OnDio1Irq, 00179 OnDio2Irq, OnDio3Irq, 00180 OnDio4Irq, NULL }; 00181 00182 /** 00183 * Radio settings 00184 */ 00185 RadioSettings_t settings; 00186 00187 00188 00189 /** 00190 * ============================================================================ 00191 * @brief Public functions definitions 00192 * ============================================================================ 00193 */ 00194 //----------------------------------------------------------------------------- 00195 bool SX1278Init(RadioEvents_t *events) 00196 { 00197 RadioEvents = events; 00198 00199 if (SX1278Read(REG_VERSION) == 0x00) 00200 { 00201 return false; 00202 } 00203 00204 SX1278Reset(); 00205 RxChainCalibration(); 00206 SX1278SetOpMode(RF_OPMODE_SLEEP); 00207 00208 SX1278IoIrqInit(dioIrq); 00209 SX1278RadioRegistersInit(); 00210 SX1278SetModem(MODEM_FSK); 00211 settings.State = RF_IDLE; 00212 return true; 00213 } 00214 00215 //----------------------------------------------------------------------------- 00216 void SX1278RadioRegistersInit() 00217 { 00218 uint8_t i = 0; 00219 for(i = 0; i < sizeof(SX1278RadioRegsInit) / sizeof(RadioRegisters_t); i++) 00220 { 00221 SX1278SetModem(SX1278RadioRegsInit[i].Modem); 00222 SX1278Write(SX1278RadioRegsInit[i].Addr, SX1278RadioRegsInit[i].Value); 00223 } 00224 } 00225 00226 //----------------------------------------------------------------------------- 00227 RadioState_t SX1278GetStatus(void) 00228 { 00229 return settings.State; 00230 } 00231 00232 //----------------------------------------------------------------------------- 00233 void SX1278SetChannel(uint32_t freq) 00234 { 00235 settings.Channel = freq; 00236 freq = (uint32_t)((double)freq / (double)FREQ_STEP); 00237 SX1278Write(REG_FRFMSB, (uint8_t)((freq >> 16) & 0xFF)); 00238 SX1278Write(REG_FRFMID, (uint8_t)((freq >> 8) & 0xFF)); 00239 SX1278Write(REG_FRFLSB, (uint8_t)(freq & 0xFF)); 00240 } 00241 00242 //----------------------------------------------------------------------------- 00243 bool SX1278IsChannelFree(RadioModems_t modem, uint32_t freq, int16_t rssiThresh, uint32_t maxCarrierSenseTime) 00244 { 00245 // TODO handle carrierSenseTime 00246 int16_t rssi = 0; 00247 00248 SX1278SetModem(modem); 00249 00250 SX1278SetChannel(freq); 00251 00252 SX1278SetOpMode(RF_OPMODE_RECEIVER); 00253 00254 SX1278DelayMs(1); 00255 00256 rssi = SX1278GetRssi(modem); 00257 00258 SX1278SetSleep(); 00259 if (rssi > rssiThresh) 00260 { 00261 return false; 00262 } 00263 return true; 00264 } 00265 00266 //----------------------------------------------------------------------------- 00267 uint32_t SX1278Random(void) 00268 { 00269 uint8_t i; 00270 uint32_t rnd = 0; 00271 00272 /* 00273 * Radio setup for random number generation 00274 */ 00275 // Set LoRa modem ON 00276 SX1278SetModem(MODEM_LORA); 00277 00278 // Disable LoRa modem interrupts 00279 SX1278Write(REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT | 00280 RFLR_IRQFLAGS_RXDONE | 00281 RFLR_IRQFLAGS_PAYLOADCRCERROR | 00282 RFLR_IRQFLAGS_VALIDHEADER | 00283 RFLR_IRQFLAGS_TXDONE | 00284 RFLR_IRQFLAGS_CADDONE | 00285 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL | 00286 RFLR_IRQFLAGS_CADDETECTED); 00287 00288 // Set radio in continuous reception 00289 SX1278SetOpMode(RF_OPMODE_RECEIVER); 00290 00291 for(i = 0; i < 32; i++) 00292 { 00293 SX1278DelayMs(1); 00294 // Unfiltered RSSI value SX1278Reading. Only takes the LSB value 00295 rnd |= ((uint32_t)SX1278Read(REG_LR_RSSIWIDEBAND) & 0x01) << i; 00296 } 00297 00298 SX1278SetSleep(); 00299 00300 return rnd; 00301 } 00302 00303 //----------------------------------------------------------------------------- 00304 void SX1278SetRxConfig(RadioModems_t modem, uint32_t bandwidth, 00305 uint32_t datarate, uint8_t coderate, 00306 uint32_t bandwidthAfc, uint16_t preambleLen, 00307 uint16_t symbTimeout, bool fixLen, 00308 uint8_t payloadLen, 00309 bool crcOn, bool freqHopOn, uint8_t hopPeriod, 00310 bool iqInverted, bool rxContinuous) 00311 { 00312 SX1278SetModem(modem); 00313 00314 switch (modem) 00315 { 00316 case MODEM_FSK: 00317 { 00318 settings.Fsk.Bandwidth = bandwidth; 00319 settings.Fsk.Datarate = datarate; 00320 settings.Fsk.BandwidthAfc = bandwidthAfc; 00321 settings.Fsk.FixLen = fixLen; 00322 settings.Fsk.PayloadLen = payloadLen; 00323 settings.Fsk.CrcOn = crcOn; 00324 settings.Fsk.IqInverted = iqInverted; 00325 settings.Fsk.RxContinuous = rxContinuous; 00326 settings.Fsk.PreambleLen = preambleLen; 00327 settings.Fsk.RxSingleTimeout = symbTimeout * ((1.0 / (double)datarate) * 8.0) * 1000; 00328 00329 datarate = (uint16_t)((double)XTAL_FREQ / (double)datarate); 00330 SX1278Write(REG_BITRATEMSB, (uint8_t)(datarate >> 8)); 00331 SX1278Write(REG_BITRATELSB, (uint8_t)(datarate & 0xFF)); 00332 00333 SX1278Write(REG_RXBW, GetFskBandwidthRegValue(bandwidth)); 00334 SX1278Write(REG_AFCBW, GetFskBandwidthRegValue(bandwidthAfc)); 00335 00336 SX1278Write(REG_PREAMBLEMSB, (uint8_t)((preambleLen >> 8) & 0xFF)); 00337 SX1278Write(REG_PREAMBLELSB, (uint8_t)(preambleLen & 0xFF)); 00338 00339 if (fixLen == 1) 00340 { 00341 SX1278Write(REG_PAYLOADLENGTH, payloadLen); 00342 } 00343 else 00344 { 00345 SX1278Write(REG_PAYLOADLENGTH, 0xFF); // Set payload length to the maximum 00346 } 00347 00348 SX1278Write(REG_PACKETCONFIG1, 00349 (SX1278Read(REG_PACKETCONFIG1) & 00350 RF_PACKETCONFIG1_CRC_MASK & 00351 RF_PACKETCONFIG1_PACKETFORMAT_MASK) | 00352 ((fixLen == 1) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE) | 00353 (crcOn << 4)); 00354 SX1278Write(REG_PACKETCONFIG2, (SX1278Read(REG_PACKETCONFIG2) | RF_PACKETCONFIG2_DATAMODE_PACKET)); 00355 } 00356 break; 00357 case MODEM_LORA: 00358 { 00359 if (bandwidth > 11) // specified in Hz, needs mapping 00360 { 00361 bandwidth = GetLoRaBandwidthRegValue(bandwidth); 00362 } 00363 if (bandwidth > LORA_BANDWIDTH_500kHz) 00364 { 00365 // Fatal error: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported 00366 while(1); 00367 } 00368 settings.LoRa.Bandwidth = bandwidth; 00369 settings.LoRa.Datarate = datarate; 00370 settings.LoRa.Coderate = coderate; 00371 settings.LoRa.PreambleLen = preambleLen; 00372 settings.LoRa.FixLen = fixLen; 00373 settings.LoRa.PayloadLen = payloadLen; 00374 settings.LoRa.CrcOn = crcOn; 00375 settings.LoRa.FreqHopOn = freqHopOn; 00376 settings.LoRa.HopPeriod = hopPeriod; 00377 settings.LoRa.IqInverted = iqInverted; 00378 settings.LoRa.RxContinuous = rxContinuous; 00379 00380 if (datarate > LORA_SF12) 00381 { 00382 datarate = LORA_SF12; 00383 } 00384 else if (datarate < LORA_SF6) 00385 { 00386 datarate = LORA_SF6; 00387 } 00388 00389 if (((bandwidth == LORA_BANDWIDTH_125kHz) && ((datarate == LORA_SF11) || (datarate == LORA_SF12))) || 00390 ((bandwidth == LORA_BANDWIDTH_250kHz) && (datarate == LORA_SF12))) 00391 { 00392 settings.LoRa.LowDatarateOptimize = 0x01; 00393 } 00394 else 00395 { 00396 settings.LoRa.LowDatarateOptimize = 0x00; 00397 } 00398 00399 SX1278Write(REG_LR_MODEMCONFIG1, 00400 (SX1278Read(REG_LR_MODEMCONFIG1) & 00401 RFLR_MODEMCONFIG1_BW_MASK & 00402 RFLR_MODEMCONFIG1_CODINGRATE_MASK & 00403 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK) | 00404 (bandwidth << 4) | (coderate << 1) | 00405 fixLen); 00406 00407 SX1278Write(REG_LR_MODEMCONFIG2, 00408 (SX1278Read(REG_LR_MODEMCONFIG2) & 00409 RFLR_MODEMCONFIG2_SF_MASK & 00410 RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK & 00411 RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK) | 00412 (datarate << 4) | (crcOn << 2) | 00413 ((symbTimeout >> 8) & ~RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK)); 00414 00415 SX1278Write(REG_LR_MODEMCONFIG3, 00416 (SX1278Read(REG_LR_MODEMCONFIG3) & 00417 RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK) | 00418 (settings.LoRa.LowDatarateOptimize << 3)); 00419 00420 SX1278Write(REG_LR_SYMBTIMEOUTLSB, (uint8_t)(symbTimeout & 0xFF)); 00421 00422 SX1278Write(REG_LR_PREAMBLEMSB, (uint8_t)((preambleLen >> 8) & 0xFF)); 00423 SX1278Write(REG_LR_PREAMBLELSB, (uint8_t)(preambleLen & 0xFF)); 00424 00425 if (fixLen == 1) 00426 { 00427 SX1278Write(REG_LR_PAYLOADLENGTH, payloadLen); 00428 } 00429 00430 if (settings.LoRa.FreqHopOn == true) 00431 { 00432 SX1278Write(REG_LR_PLLHOP, (SX1278Read(REG_LR_PLLHOP) & RFLR_PLLHOP_FASTHOP_MASK) | RFLR_PLLHOP_FASTHOP_ON); 00433 SX1278Write(REG_LR_HOPPERIOD, settings.LoRa.HopPeriod); 00434 } 00435 00436 if ((bandwidth == LORA_BANDWIDTH_500kHz) && (settings.Channel > RF_MID_BAND_THRESH)) 00437 { 00438 // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth 00439 SX1278Write(REG_LR_HIGHBWOPTIMIZE1, 0x02); 00440 SX1278Write(REG_LR_HIGHBWOPTIMIZE2, 0x64); 00441 } 00442 else if (bandwidth == LORA_BANDWIDTH_500kHz) 00443 { 00444 // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth 00445 SX1278Write(REG_LR_HIGHBWOPTIMIZE1, 0x02); 00446 SX1278Write(REG_LR_HIGHBWOPTIMIZE2, 0x7F); 00447 } 00448 else 00449 { 00450 // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth 00451 SX1278Write(REG_LR_HIGHBWOPTIMIZE1, 0x03); 00452 } 00453 00454 if (datarate == LORA_SF6) 00455 { 00456 SX1278Write(REG_LR_DETECTOPTIMIZE, 00457 (SX1278Read(REG_LR_DETECTOPTIMIZE) & 00458 RFLR_DETECTIONOPTIMIZE_MASK) | 00459 RFLR_DETECTIONOPTIMIZE_SF6); 00460 SX1278Write(REG_LR_DETECTIONTHRESHOLD, 00461 RFLR_DETECTIONTHRESH_SF6); 00462 } 00463 else 00464 { 00465 SX1278Write(REG_LR_DETECTOPTIMIZE, 00466 (SX1278Read(REG_LR_DETECTOPTIMIZE) & 00467 RFLR_DETECTIONOPTIMIZE_MASK) | 00468 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12); 00469 SX1278Write(REG_LR_DETECTIONTHRESHOLD, 00470 RFLR_DETECTIONTHRESH_SF7_TO_SF12); 00471 } 00472 } 00473 break; 00474 } 00475 } 00476 00477 //----------------------------------------------------------------------------- 00478 void SX1278SetTxConfig(RadioModems_t modem, int8_t power, uint32_t fdev, 00479 uint32_t bandwidth, uint32_t datarate, 00480 uint8_t coderate, uint16_t preambleLen, 00481 bool fixLen, bool crcOn, bool freqHopOn, 00482 uint8_t hopPeriod, bool iqInverted, uint32_t timeout) 00483 { 00484 SX1278SetModem(modem); 00485 SX1278SetRfTxPower(power); 00486 00487 switch (modem) 00488 { 00489 case MODEM_FSK: 00490 { 00491 settings.Fsk.Power = power; 00492 settings.Fsk.Fdev = fdev; 00493 settings.Fsk.Bandwidth = bandwidth; 00494 settings.Fsk.Datarate = datarate; 00495 settings.Fsk.PreambleLen = preambleLen; 00496 settings.Fsk.FixLen = fixLen; 00497 settings.Fsk.CrcOn = crcOn; 00498 settings.Fsk.IqInverted = iqInverted; 00499 settings.Fsk.TxTimeout = timeout; 00500 00501 fdev = (uint16_t)((double)fdev / (double)FREQ_STEP); 00502 SX1278Write(REG_FDEVMSB, (uint8_t)(fdev >> 8)); 00503 SX1278Write(REG_FDEVLSB, (uint8_t)(fdev & 0xFF)); 00504 00505 datarate = (uint16_t)((double)XTAL_FREQ / (double)datarate); 00506 SX1278Write(REG_BITRATEMSB, (uint8_t)(datarate >> 8)); 00507 SX1278Write(REG_BITRATELSB, (uint8_t)(datarate & 0xFF)); 00508 00509 SX1278Write(REG_PREAMBLEMSB, (preambleLen >> 8) & 0x00FF); 00510 SX1278Write(REG_PREAMBLELSB, preambleLen & 0xFF); 00511 00512 SX1278Write(REG_PACKETCONFIG1, 00513 (SX1278Read(REG_PACKETCONFIG1) & 00514 RF_PACKETCONFIG1_CRC_MASK & 00515 RF_PACKETCONFIG1_PACKETFORMAT_MASK) | 00516 ((fixLen == 1) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE) | 00517 (crcOn << 4)); 00518 SX1278Write(REG_PACKETCONFIG2, (SX1278Read(REG_PACKETCONFIG2) | RF_PACKETCONFIG2_DATAMODE_PACKET)); 00519 } 00520 break; 00521 case MODEM_LORA: 00522 { 00523 settings.LoRa.Power = power; 00524 if (bandwidth > LORA_BANDWIDTH_500kHz) 00525 { 00526 // Fatal error: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported 00527 while(1); 00528 } 00529 00530 settings.LoRa.Bandwidth = bandwidth; 00531 settings.LoRa.Datarate = datarate; 00532 settings.LoRa.Coderate = coderate; 00533 settings.LoRa.PreambleLen = preambleLen; 00534 settings.LoRa.FixLen = fixLen; 00535 settings.LoRa.FreqHopOn = freqHopOn; 00536 settings.LoRa.HopPeriod = hopPeriod; 00537 settings.LoRa.CrcOn = crcOn; 00538 settings.LoRa.IqInverted = iqInverted; 00539 settings.LoRa.TxTimeout = timeout; 00540 00541 if (datarate > LORA_SF12) 00542 { 00543 datarate = LORA_SF12; 00544 } 00545 else if (datarate < LORA_SF6) 00546 { 00547 datarate = LORA_SF6; 00548 } 00549 if (((bandwidth == LORA_BANDWIDTH_125kHz) && ((datarate == LORA_SF11) || (datarate == LORA_SF12))) || 00550 ((bandwidth == LORA_BANDWIDTH_250kHz) && (datarate == LORA_SF12))) 00551 { 00552 settings.LoRa.LowDatarateOptimize = 0x01; 00553 } 00554 else 00555 { 00556 settings.LoRa.LowDatarateOptimize = 0x00; 00557 } 00558 00559 if (settings.LoRa.FreqHopOn == true) 00560 { 00561 SX1278Write(REG_LR_PLLHOP, (SX1278Read(REG_LR_PLLHOP) & RFLR_PLLHOP_FASTHOP_MASK) | RFLR_PLLHOP_FASTHOP_ON); 00562 SX1278Write(REG_LR_HOPPERIOD, settings.LoRa.HopPeriod); 00563 } 00564 00565 SX1278Write(REG_LR_MODEMCONFIG1, 00566 (SX1278Read(REG_LR_MODEMCONFIG1) & 00567 RFLR_MODEMCONFIG1_BW_MASK & 00568 RFLR_MODEMCONFIG1_CODINGRATE_MASK & 00569 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK) | 00570 (bandwidth << 4) | (coderate << 1) | 00571 fixLen); 00572 00573 SX1278Write(REG_LR_MODEMCONFIG2, 00574 (SX1278Read(REG_LR_MODEMCONFIG2) & 00575 RFLR_MODEMCONFIG2_SF_MASK & 00576 RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK) | 00577 (datarate << 4) | (crcOn << 2)); 00578 00579 SX1278Write(REG_LR_MODEMCONFIG3, 00580 (SX1278Read(REG_LR_MODEMCONFIG3) & 00581 RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK) | 00582 (settings.LoRa.LowDatarateOptimize << 3)); 00583 00584 SX1278Write(REG_LR_PREAMBLEMSB, (preambleLen >> 8) & 0x00FF); 00585 SX1278Write(REG_LR_PREAMBLELSB, preambleLen & 0xFF); 00586 00587 if (datarate == LORA_SF6) 00588 { 00589 SX1278Write(REG_LR_DETECTOPTIMIZE, 00590 (SX1278Read(REG_LR_DETECTOPTIMIZE) & 00591 RFLR_DETECTIONOPTIMIZE_MASK) | 00592 RFLR_DETECTIONOPTIMIZE_SF6); 00593 SX1278Write(REG_LR_DETECTIONTHRESHOLD, 00594 RFLR_DETECTIONTHRESH_SF6); 00595 } 00596 else 00597 { 00598 SX1278Write(REG_LR_DETECTOPTIMIZE, 00599 (SX1278Read(REG_LR_DETECTOPTIMIZE) & 00600 RFLR_DETECTIONOPTIMIZE_MASK) | 00601 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12); 00602 SX1278Write(REG_LR_DETECTIONTHRESHOLD, 00603 RFLR_DETECTIONTHRESH_SF7_TO_SF12); 00604 } 00605 } 00606 break; 00607 } 00608 } 00609 00610 //----------------------------------------------------------------------------- 00611 uint32_t SX1278TimeOnAir(RadioModems_t modem, uint8_t pktLen) 00612 { 00613 uint32_t airTime = 0; 00614 00615 switch (modem) 00616 { 00617 case MODEM_FSK: 00618 { 00619 airTime = rint((8 * (settings.Fsk.PreambleLen + 00620 ((SX1278Read(REG_SYNCCONFIG) & ~RF_SYNCCONFIG_SYNCSIZE_MASK) + 1) + 00621 ((settings.Fsk.FixLen == 0x01) ? 0.0 : 1.0) + 00622 (((SX1278Read(REG_PACKETCONFIG1) & ~RF_PACKETCONFIG1_ADDRSFILTERING_MASK) != 0x00) ? 1.0 : 0) + 00623 pktLen + 00624 ((settings.Fsk.CrcOn == 0x01) ? 2.0 : 0)) / 00625 settings.Fsk.Datarate) * 1000); 00626 } 00627 break; 00628 case MODEM_LORA: 00629 { 00630 double bw = 0.0; 00631 // NOTE: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported 00632 switch (settings.LoRa.Bandwidth) 00633 { 00634 case LORA_BANDWIDTH_7kHz: // 7.8 kHz 00635 bw = 78e2; 00636 break; 00637 case LORA_BANDWIDTH_10kHz: // 10.4 kHz 00638 bw = 104e2; 00639 break; 00640 case LORA_BANDWIDTH_15kHz: // 15.6 kHz 00641 bw = 156e2; 00642 break; 00643 case LORA_BANDWIDTH_20kHz: // 20.8 kHz 00644 bw = 208e2; 00645 break; 00646 case LORA_BANDWIDTH_31kHz: // 31.25 kHz 00647 bw = 312e2; 00648 break; 00649 case LORA_BANDWIDTH_41kHz: // 41.7 kHz 00650 bw = 414e2; 00651 break; 00652 case LORA_BANDWIDTH_62kHz: // 62.5 kHz 00653 bw = 625e2; 00654 break; 00655 case LORA_BANDWIDTH_125kHz: // 125 kHz 00656 bw = 125e3; 00657 break; 00658 case LORA_BANDWIDTH_250kHz: // 250 kHz 00659 bw = 250e3; 00660 break; 00661 case LORA_BANDWIDTH_500kHz: // 500 kHz 00662 bw = 500e3; 00663 break; 00664 } 00665 00666 // Symbol rate : time for one symbol (secs) 00667 double rs = bw / (1 << settings.LoRa.Datarate); 00668 double ts = 1 / rs; 00669 // time of preamble 00670 double tPreamble = (settings.LoRa.PreambleLen + 4.25) * ts; 00671 // Symbol length of payload and time 00672 double tmp = ceil((8 * pktLen - 4 * settings.LoRa.Datarate + 00673 28 + 16 * settings.LoRa.CrcOn - 00674 (settings.LoRa.FixLen ? 20 : 0)) / 00675 (double)(4 * (settings.LoRa.Datarate - 00676 ((settings.LoRa.LowDatarateOptimize > 0) ? 2 : 0)))) * 00677 (settings.LoRa.Coderate + 4); 00678 double nPayload = 8 + ((tmp > 0) ? tmp : 0); 00679 double tPayload = nPayload * ts; 00680 // Time on air 00681 double tOnAir = tPreamble + tPayload; 00682 // return ms secs 00683 airTime = floor(tOnAir * 1000 + 0.999); 00684 } 00685 break; 00686 } 00687 return airTime; 00688 } 00689 00690 //----------------------------------------------------------------------------- 00691 void SX1278Send(uint8_t *buffer, uint8_t size) 00692 { 00693 uint32_t txTimeout = 0; 00694 00695 switch (settings.Modem) 00696 { 00697 case MODEM_FSK: 00698 { 00699 settings.FskPacketHandler.NbBytes = 0; 00700 settings.FskPacketHandler.Size = size; 00701 00702 if (settings.Fsk.FixLen == false) 00703 { 00704 SX1278WriteFifo((uint8_t*)&size, 1); 00705 } 00706 else 00707 { 00708 SX1278Write(REG_PAYLOADLENGTH, size); 00709 } 00710 00711 if ((size > 0) && (size <= 64)) 00712 { 00713 settings.FskPacketHandler.ChunkSize = size; 00714 } 00715 else 00716 { 00717 memcpy(RxTxBuffer, buffer, size); 00718 settings.FskPacketHandler.ChunkSize = 32; 00719 } 00720 00721 // Write payload buffer 00722 SX1278WriteFifo(buffer, settings.FskPacketHandler.ChunkSize); 00723 settings.FskPacketHandler.NbBytes += settings.FskPacketHandler.ChunkSize; 00724 txTimeout = settings.Fsk.TxTimeout; 00725 } 00726 break; 00727 case MODEM_LORA: 00728 { 00729 if (settings.LoRa.IqInverted == true) 00730 { 00731 SX1278Write(REG_LR_INVERTIQ, ((SX1278Read(REG_LR_INVERTIQ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_ON)); 00732 SX1278Write(REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON); 00733 } 00734 else 00735 { 00736 SX1278Write(REG_LR_INVERTIQ, ((SX1278Read(REG_LR_INVERTIQ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF)); 00737 SX1278Write(REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF); 00738 } 00739 00740 settings.LoRaPacketHandler.Size = size; 00741 00742 // Initializes the payload size 00743 SX1278Write(REG_LR_PAYLOADLENGTH, size); 00744 00745 // Full buffer used for Tx 00746 SX1278Write(REG_LR_FIFOTXBASEADDR, 0); 00747 SX1278Write(REG_LR_FIFOADDRPTR, 0); 00748 00749 // FIFO operations can not take place in SX1278SetSleep mode 00750 if ((SX1278Read(REG_OPMODE) & ~RF_OPMODE_MASK) == RF_OPMODE_SLEEP) 00751 { 00752 SX1278SetStandby(); 00753 SX1278DelayMs(1); 00754 } 00755 // SX1278Write payload buffer 00756 SX1278WriteFifo(buffer, size); 00757 txTimeout = settings.LoRa.TxTimeout; 00758 } 00759 break; 00760 } 00761 00762 SX1278SetTx(txTimeout); 00763 } 00764 00765 //----------------------------------------------------------------------------- 00766 void SX1278SetSleep(void) 00767 { 00768 SX1278SetTimeout(TXTimeoutTimer, NULL, 0); 00769 SX1278SetTimeout(RXTimeoutTimer, NULL, 0); 00770 00771 SX1278SetOpMode(RF_OPMODE_SLEEP); 00772 //TODO Disable TCXO radio is in SLEEP mode if available 00773 settings.State = RF_IDLE; 00774 } 00775 00776 //----------------------------------------------------------------------------- 00777 void SX1278SetStandby(void) 00778 { 00779 SX1278SetTimeout(TXTimeoutTimer, NULL, 0); 00780 SX1278SetTimeout(RXTimeoutTimer, NULL, 0); 00781 SX1278SetTimeout(RXTimeoutSyncWordTimer, NULL, 0); 00782 00783 SX1278SetOpMode(RF_OPMODE_STANDBY); 00784 settings.State = RF_IDLE; 00785 } 00786 00787 //----------------------------------------------------------------------------- 00788 void SX1278SetRx(uint32_t timeout) 00789 { 00790 bool rxContinuous = false; 00791 00792 switch (settings.Modem) 00793 { 00794 case MODEM_FSK: 00795 { 00796 rxContinuous = settings.Fsk.RxContinuous; 00797 00798 // DIO0=PayloadSX1278Ready 00799 // DIO1=FifoLevel 00800 // DIO2=SyncAddr 00801 // DIO3=FifoEmpty 00802 // DIO4=Preamble 00803 // DIO5=ModeSX1278Ready 00804 SX1278Write(REG_DIOMAPPING1, (SX1278Read(REG_DIOMAPPING1) & RF_DIOMAPPING1_DIO0_MASK & 00805 RF_DIOMAPPING1_DIO1_MASK & 00806 RF_DIOMAPPING1_DIO2_MASK) | 00807 RF_DIOMAPPING1_DIO0_00 | 00808 RF_DIOMAPPING1_DIO1_00 | 00809 RF_DIOMAPPING1_DIO2_11); 00810 00811 SX1278Write(REG_DIOMAPPING2, (SX1278Read(REG_DIOMAPPING2) & RF_DIOMAPPING2_DIO4_MASK & 00812 RF_DIOMAPPING2_MAP_MASK) | 00813 RF_DIOMAPPING2_DIO4_11 | 00814 RF_DIOMAPPING2_MAP_PREAMBLEDETECT); 00815 00816 settings.FskPacketHandler.FifoThresh = SX1278Read(REG_FIFOTHRESH) & 0x3F; 00817 00818 SX1278Write(REG_RXCONFIG, RF_RXCONFIG_AFCAUTO_ON | RF_RXCONFIG_AGCAUTO_ON | RF_RXCONFIG_RXTRIGER_PREAMBLEDETECT); 00819 00820 settings.FskPacketHandler.PreambleDetected = false; 00821 settings.FskPacketHandler.SyncWordDetected = false; 00822 settings.FskPacketHandler.NbBytes = 0; 00823 settings.FskPacketHandler.Size = 0; 00824 } 00825 break; 00826 case MODEM_LORA: 00827 { 00828 if (settings.LoRa.IqInverted == true) 00829 { 00830 SX1278Write(REG_LR_INVERTIQ, ((SX1278Read(REG_LR_INVERTIQ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK) | RFLR_INVERTIQ_RX_ON | RFLR_INVERTIQ_TX_OFF)); 00831 SX1278Write(REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON); 00832 } 00833 else 00834 { 00835 SX1278Write(REG_LR_INVERTIQ, ((SX1278Read(REG_LR_INVERTIQ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF)); 00836 SX1278Write(REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF); 00837 } 00838 00839 // ERRATA 2.3 - Receiver Spurious Reception of a LoRa Signal 00840 if (settings.LoRa.Bandwidth < LORA_BANDWIDTH_500kHz) 00841 { 00842 SX1278Write(REG_LR_DETECTOPTIMIZE, SX1278Read(REG_LR_DETECTOPTIMIZE) & 0x7F); 00843 SX1278Write(REG_LR_IFFREQ2, 0x00); 00844 switch (settings.LoRa.Bandwidth) 00845 { 00846 case LORA_BANDWIDTH_7kHz: // 7.8 kHz 00847 SX1278Write(REG_LR_IFFREQ1, 0x48 ); 00848 SX1278SetChannel(settings.Channel + 7810); 00849 break; 00850 case LORA_BANDWIDTH_10kHz: // 10.4 kHz 00851 SX1278Write(REG_LR_IFFREQ1, 0x44 ); 00852 SX1278SetChannel(settings.Channel + 10420); 00853 break; 00854 case LORA_BANDWIDTH_15kHz: // 15.6 kHz 00855 SX1278Write(REG_LR_IFFREQ1, 0x44 ); 00856 SX1278SetChannel(settings.Channel + 15620); 00857 break; 00858 case LORA_BANDWIDTH_20kHz: // 20.8 kHz 00859 SX1278Write(REG_LR_IFFREQ1, 0x44 ); 00860 SX1278SetChannel(settings.Channel + 20830); 00861 break; 00862 case LORA_BANDWIDTH_31kHz: // 31.25 kHz 00863 SX1278Write(REG_LR_IFFREQ1, 0x44 ); 00864 SX1278SetChannel(settings.Channel + 31250); 00865 break; 00866 case LORA_BANDWIDTH_41kHz: // 41.4 kHz 00867 SX1278Write(REG_LR_IFFREQ1, 0x44 ); 00868 SX1278SetChannel(settings.Channel + 41670); 00869 break; 00870 case LORA_BANDWIDTH_62kHz: // 62.5 kHz 00871 SX1278Write(REG_LR_IFFREQ1, 0x40 ); 00872 break; 00873 case LORA_BANDWIDTH_125kHz: // 125 kHz 00874 SX1278Write(REG_LR_IFFREQ1, 0x40 ); 00875 break; 00876 case LORA_BANDWIDTH_250kHz: // 250 kHz 00877 SX1278Write(REG_LR_IFFREQ1, 0x40 ); 00878 break; 00879 } 00880 } 00881 else 00882 { 00883 SX1278Write(REG_LR_DETECTOPTIMIZE, SX1278Read(REG_LR_DETECTOPTIMIZE) | 0x80); 00884 } 00885 00886 rxContinuous = settings.LoRa.RxContinuous; 00887 00888 if (settings.LoRa.FreqHopOn == true) 00889 { 00890 SX1278Write(REG_LR_IRQFLAGSMASK,//RFLR_IRQFLAGS_RXTIMEOUT | 00891 //RFLR_IRQFLAGS_RXDONE | 00892 //RFLR_IRQFLAGS_PAYLOADCRCERROR | 00893 RFLR_IRQFLAGS_VALIDHEADER | 00894 RFLR_IRQFLAGS_TXDONE | 00895 RFLR_IRQFLAGS_CADDONE | 00896 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL | 00897 RFLR_IRQFLAGS_CADDETECTED); 00898 00899 // DIO0=RxDone, DIO2=FhssChangeChannel 00900 SX1278Write(REG_DIOMAPPING1, (SX1278Read(REG_DIOMAPPING1) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_00 | RFLR_DIOMAPPING1_DIO2_00); 00901 } 00902 else 00903 { 00904 SX1278Write(REG_LR_IRQFLAGSMASK,//RFLR_IRQFLAGS_RXTIMEOUT | 00905 //RFLR_IRQFLAGS_RXDONE | 00906 //RFLR_IRQFLAGS_PAYLOADCRCERROR | 00907 RFLR_IRQFLAGS_VALIDHEADER | 00908 RFLR_IRQFLAGS_TXDONE | 00909 RFLR_IRQFLAGS_CADDONE | 00910 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL | 00911 RFLR_IRQFLAGS_CADDETECTED); 00912 00913 // DIO0=RxDone 00914 SX1278Write(REG_DIOMAPPING1, (SX1278Read(REG_DIOMAPPING1) & RFLR_DIOMAPPING1_DIO0_MASK) | RFLR_DIOMAPPING1_DIO0_00); 00915 } 00916 SX1278Write(REG_LR_FIFORXBASEADDR, 0); 00917 SX1278Write(REG_LR_FIFOADDRPTR, 0); 00918 } 00919 break; 00920 } 00921 00922 memset(RxTxBuffer, 0, (size_t)RX_BUFFER_SIZE); 00923 00924 settings.State = RF_RX_RUNNING; 00925 if (timeout != 0) 00926 { 00927 SX1278SetTimeout(RXTimeoutTimer, &OnTimeoutIrq, timeout); 00928 } 00929 00930 if (settings.Modem == MODEM_FSK) 00931 { 00932 SX1278SetOpMode(RF_OPMODE_RECEIVER); 00933 00934 if (rxContinuous == false) 00935 { 00936 SX1278SetTimeout(RXTimeoutSyncWordTimer, &OnTimeoutIrq, settings.Fsk.RxSingleTimeout); 00937 } 00938 } 00939 else // MODEM_LORA 00940 { 00941 if (rxContinuous == true) 00942 { 00943 SX1278SetOpMode(RFLR_OPMODE_RECEIVER); 00944 } 00945 else 00946 { 00947 SX1278SetOpMode(RFLR_OPMODE_RECEIVER_SINGLE); 00948 } 00949 } 00950 } 00951 00952 //----------------------------------------------------------------------------- 00953 void SX1278SetTx(uint32_t timeout) 00954 { 00955 00956 switch (settings.Modem) 00957 { 00958 case MODEM_FSK: 00959 { 00960 // DIO0=PacketSent 00961 // DIO1=FifoEmpty 00962 // DIO2=FifoFull 00963 // DIO3=FifoEmpty 00964 // DIO4=LowBat 00965 // DIO5=ModeSX1278Ready 00966 SX1278Write(REG_DIOMAPPING1, (SX1278Read(REG_DIOMAPPING1) & RF_DIOMAPPING1_DIO0_MASK & 00967 RF_DIOMAPPING1_DIO1_MASK & 00968 RF_DIOMAPPING1_DIO2_MASK) | 00969 RF_DIOMAPPING1_DIO1_01); 00970 00971 SX1278Write(REG_DIOMAPPING2, (SX1278Read(REG_DIOMAPPING2) & RF_DIOMAPPING2_DIO4_MASK & 00972 RF_DIOMAPPING2_MAP_MASK)); 00973 settings.FskPacketHandler.FifoThresh = SX1278Read(REG_FIFOTHRESH) & 0x3F; 00974 } 00975 break; 00976 case MODEM_LORA: 00977 { 00978 if (settings.LoRa.FreqHopOn == true) 00979 { 00980 SX1278Write(REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT | 00981 RFLR_IRQFLAGS_RXDONE | 00982 RFLR_IRQFLAGS_PAYLOADCRCERROR | 00983 RFLR_IRQFLAGS_VALIDHEADER | 00984 //RFLR_IRQFLAGS_TXDONE | 00985 RFLR_IRQFLAGS_CADDONE | 00986 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL | 00987 RFLR_IRQFLAGS_CADDETECTED); 00988 00989 // DIO0=TxDone, DIO2=FhssChangeChannel 00990 SX1278Write(REG_DIOMAPPING1, (SX1278Read(REG_DIOMAPPING1) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK) | RFLR_DIOMAPPING1_DIO0_01 | RFLR_DIOMAPPING1_DIO2_00); 00991 } 00992 else 00993 { 00994 SX1278Write(REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT | 00995 RFLR_IRQFLAGS_RXDONE | 00996 RFLR_IRQFLAGS_PAYLOADCRCERROR | 00997 RFLR_IRQFLAGS_VALIDHEADER | 00998 //RFLR_IRQFLAGS_TXDONE | 00999 RFLR_IRQFLAGS_CADDONE | 01000 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL | 01001 RFLR_IRQFLAGS_CADDETECTED); 01002 01003 // DIO0=TxDone 01004 SX1278Write(REG_DIOMAPPING1, (SX1278Read(REG_DIOMAPPING1) & RFLR_DIOMAPPING1_DIO0_MASK) | RFLR_DIOMAPPING1_DIO0_01); 01005 } 01006 } 01007 break; 01008 } 01009 01010 settings.State = RF_TX_RUNNING; 01011 SX1278SetTimeout(TXTimeoutTimer, &OnTimeoutIrq, timeout); 01012 SX1278SetOpMode(RF_OPMODE_TRANSMITTER); 01013 } 01014 01015 //----------------------------------------------------------------------------- 01016 void SX1278StartCad(void) 01017 { 01018 switch (settings.Modem) 01019 { 01020 case MODEM_FSK: 01021 { 01022 01023 } 01024 break; 01025 case MODEM_LORA: 01026 { 01027 SX1278Write(REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT | 01028 RFLR_IRQFLAGS_RXDONE | 01029 RFLR_IRQFLAGS_PAYLOADCRCERROR | 01030 RFLR_IRQFLAGS_VALIDHEADER | 01031 RFLR_IRQFLAGS_TXDONE | 01032 //RFLR_IRQFLAGS_CADDONE | 01033 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL // | 01034 //RFLR_IRQFLAGS_CADDETECTED 01035 ); 01036 01037 if (dioIrq[3]) 01038 { 01039 // DIO3=CADDone 01040 SX1278Write(REG_DIOMAPPING1, (SX1278Read(REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO3_MASK ) | RFLR_DIOMAPPING1_DIO3_00 ); 01041 } 01042 else 01043 { 01044 // DIO0=CADDone 01045 SX1278Write(REG_DIOMAPPING1, (SX1278Read(REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_10 ); 01046 } 01047 01048 settings.State = RF_CAD; 01049 SX1278SetOpMode(RFLR_OPMODE_CAD); 01050 } 01051 break; 01052 default: 01053 break; 01054 } 01055 } 01056 01057 //----------------------------------------------------------------------------- 01058 void SX1278SetTxContinuousWave(uint32_t freq, int8_t power, uint16_t time) 01059 { 01060 uint32_t timeout = (uint32_t)(time); 01061 01062 SX1278SetChannel(freq); 01063 01064 SX1278SetTxConfig(MODEM_FSK, power, 0, 0, 4800, 0, 5, false, false, 0, 0, 0, timeout); 01065 01066 SX1278Write(REG_PACKETCONFIG2, (SX1278Read(REG_PACKETCONFIG2) & RF_PACKETCONFIG2_DATAMODE_MASK)); 01067 // Disable radio interrupts 01068 SX1278Write(REG_DIOMAPPING1, RF_DIOMAPPING1_DIO0_11 | RF_DIOMAPPING1_DIO1_11); 01069 SX1278Write(REG_DIOMAPPING2, RF_DIOMAPPING2_DIO4_10 | RF_DIOMAPPING2_DIO5_10); 01070 01071 settings.State = RF_TX_RUNNING; 01072 SX1278SetTimeout(TXTimeoutTimer, &OnTimeoutIrq, timeout); 01073 SX1278SetOpMode(RF_OPMODE_TRANSMITTER); 01074 } 01075 01076 //----------------------------------------------------------------------------- 01077 int16_t SX1278GetRssi(RadioModems_t modem) 01078 { 01079 int16_t rssi = 0; 01080 01081 switch (modem) 01082 { 01083 case MODEM_FSK: 01084 rssi = -(SX1278Read(REG_RSSIVALUE) >> 1); 01085 break; 01086 case MODEM_LORA: 01087 if (settings.Channel > RF_MID_BAND_THRESH) 01088 { 01089 rssi = RSSI_OFFSET_HF + SX1278Read(REG_LR_RSSIVALUE); 01090 } 01091 else 01092 { 01093 rssi = RSSI_OFFSET_LF + SX1278Read(REG_LR_RSSIVALUE); 01094 } 01095 break; 01096 default: 01097 rssi = -1; 01098 break; 01099 } 01100 return rssi; 01101 } 01102 01103 //----------------------------------------------------------------------------- 01104 int32_t SX1278GetFrequencyError(RadioModems_t modem ) 01105 { 01106 int32_t val = 0; 01107 01108 if (modem != MODEM_LORA) 01109 return 0; 01110 01111 val = (SX1278Read(REG_LR_FEIMSB) & 0b1111) << 16; // high word, 4 valid bits only 01112 val |= ((SX1278Read(REG_LR_FEIMID) << 8) | SX1278Read(REG_LR_FEILSB)); // high byte, low byte 01113 if (val & 0x80000) //convert sign bit 01114 val |= 0xfff00000; 01115 01116 int32_t bandwidth = 0; 01117 for (int i = 0; i < (int)(sizeof(SX1278LoRaBandwidths) / sizeof(BandwidthMap_t)) -1; i++ ) { 01118 if (SX1278LoRaBandwidths[i].RegValue == settings.LoRa.Bandwidth) { 01119 bandwidth = SX1278LoRaBandwidths[i].bandwidth; 01120 break; 01121 } 01122 } 01123 if (!bandwidth) 01124 return 0; 01125 01126 float bandWidthkHz = (float)bandwidth/1000; 01127 01128 int32_t hz = (((float)val * (float)(1<<24)) / ((float)XTAL_FREQ)) * (bandWidthkHz / 500.0); 01129 01130 return hz; 01131 } 01132 01133 //----------------------------------------------------------------------------- 01134 void SX1278SetOpMode(uint8_t opMode) 01135 { 01136 // if(opMode == RF_OPMODE_SLEEP ) // TODO NOT USED on RA-01 01137 // { 01138 // SX1278SetAntSwLowPower( true ); 01139 // } 01140 // else 01141 // { 01142 // // Enable TCXO if operating mode different from SLEEP. 01143 // SX1278SetBoardTcxo( true ); 01144 // SX1278SetAntSwLowPower( false ); 01145 // SX1278SetAntSw( opMode ); 01146 // } 01147 SX1278Write(REG_OPMODE, (SX1278Read(REG_OPMODE) & RF_OPMODE_MASK) | opMode); 01148 } 01149 01150 //----------------------------------------------------------------------------- 01151 void SX1278SetModem(RadioModems_t modem) 01152 { 01153 if ((SX1278Read(REG_OPMODE) & RFLR_OPMODE_LONGRANGEMODE_ON) != 0) 01154 { 01155 settings.Modem = MODEM_LORA; 01156 } 01157 else 01158 { 01159 settings.Modem = MODEM_FSK; 01160 } 01161 01162 if (settings.Modem == modem) 01163 { 01164 return; 01165 } 01166 01167 settings.Modem = modem; 01168 switch (settings.Modem) 01169 { 01170 default: 01171 case MODEM_FSK: 01172 SX1278SetSleep(); 01173 SX1278Write(REG_OPMODE, (SX1278Read(REG_OPMODE) & RFLR_OPMODE_LONGRANGEMODE_MASK) | RFLR_OPMODE_LONGRANGEMODE_OFF); 01174 01175 SX1278Write(REG_DIOMAPPING1, 0x00); 01176 SX1278Write(REG_DIOMAPPING2, 0x30); // DIO5=ModeSX1278Ready 01177 break; 01178 case MODEM_LORA: 01179 SX1278SetSleep(); 01180 SX1278Write(REG_OPMODE, (SX1278Read(REG_OPMODE) & RFLR_OPMODE_LONGRANGEMODE_MASK) | RFLR_OPMODE_LONGRANGEMODE_ON); 01181 01182 SX1278Write(REG_DIOMAPPING1, 0x00); 01183 SX1278Write(REG_DIOMAPPING2, 0x00); 01184 break; 01185 } 01186 } 01187 01188 //----------------------------------------------------------------------------- 01189 void SX1278SetMaxPayloadLength(RadioModems_t modem, uint8_t max) 01190 { 01191 SX1278SetModem(modem); 01192 01193 switch (modem) 01194 { 01195 case MODEM_FSK: 01196 if (settings.Fsk.FixLen == false) 01197 { 01198 SX1278Write(REG_PAYLOADLENGTH, max); 01199 } 01200 break; 01201 case MODEM_LORA: 01202 SX1278Write(REG_LR_PAYLOADMAXLENGTH, max); 01203 break; 01204 } 01205 } 01206 01207 //----------------------------------------------------------------------------- 01208 void SX1278SetPublicNetwork(bool enable) 01209 { 01210 SX1278SetModem(MODEM_LORA); 01211 settings.LoRa.PublicNetwork = enable; 01212 if (enable == true) 01213 { 01214 // Change LoRa modem SyncWord 01215 SX1278Write(REG_LR_SYNCWORD, LORA_MAC_PUBLIC_SYNCWORD); 01216 } 01217 else 01218 { 01219 // Change LoRa modem SyncWord 01220 SX1278Write(REG_LR_SYNCWORD, LORA_MAC_PRIVATE_SYNCWORD); 01221 } 01222 } 01223 01224 //----------------------------------------------------------------------------- 01225 void OnTimeoutIrq() 01226 { 01227 switch (settings.State) 01228 { 01229 case RF_RX_RUNNING: 01230 if (settings.Modem == MODEM_FSK) 01231 { 01232 settings.FskPacketHandler.PreambleDetected = false; 01233 settings.FskPacketHandler.SyncWordDetected = false; 01234 settings.FskPacketHandler.NbBytes = 0; 01235 settings.FskPacketHandler.Size = 0; 01236 01237 // Clear Irqs 01238 SX1278Write(REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI | 01239 RF_IRQFLAGS1_PREAMBLEDETECT | 01240 RF_IRQFLAGS1_SYNCADDRESSMATCH); 01241 SX1278Write(REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN); 01242 01243 if (settings.Fsk.RxContinuous == true) 01244 { 01245 // Continuous mode restart Rx chain 01246 SX1278Write(REG_RXCONFIG, SX1278Read(REG_RXCONFIG) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK); 01247 SX1278SetTimeout(RXTimeoutSyncWordTimer, &OnTimeoutIrq, settings.Fsk.RxSingleTimeout); 01248 } 01249 else 01250 { 01251 settings.State = RF_IDLE; 01252 SX1278SetTimeout(RXTimeoutSyncWordTimer, NULL, 0); 01253 } 01254 } 01255 if ((RadioEvents != NULL) && (RadioEvents->RxTimeout != NULL)) 01256 { 01257 RadioEvents->RxTimeout(); 01258 } 01259 break; 01260 case RF_TX_RUNNING: 01261 // Tx timeout shouldn't happen. 01262 // But it has been observed that when it happens it is a result of a corrupted SPI transfer 01263 // it depends on the platform design. 01264 // 01265 // The workaround is to put the radio in a known state. Thus, we re-initialize it. 01266 01267 // BEGIN WORKAROUND 01268 01269 // Reset the radio 01270 SX1278Reset(); 01271 01272 // Calibrate Rx chain 01273 RxChainCalibration(); 01274 01275 // Initialize radio default values 01276 SX1278SetOpMode(RF_OPMODE_SLEEP); 01277 SX1278RadioRegistersInit(); 01278 01279 SX1278SetModem(MODEM_FSK); 01280 01281 // Restore previous network type setting. 01282 SX1278SetPublicNetwork(settings.LoRa.PublicNetwork); 01283 // END WORKAROUND 01284 01285 settings.State = RF_IDLE; 01286 if ((RadioEvents != NULL) && (RadioEvents->TxTimeout != NULL)) 01287 { 01288 RadioEvents->TxTimeout(); 01289 } 01290 break; 01291 default: 01292 break; 01293 } 01294 } 01295 01296 //----------------------------------------------------------------------------- 01297 void SX1278SetRfTxPower(int8_t power) 01298 { 01299 uint8_t paConfig = 0; 01300 uint8_t paDac = 0; 01301 01302 paConfig = SX1278Read(REG_PACONFIG); 01303 paDac = SX1278Read(REG_PADAC); 01304 01305 paConfig = (paConfig & RF_PACONFIG_PASELECT_MASK) | SX1278GetPaSelect(settings.Channel); 01306 paConfig = (paConfig & RF_PACONFIG_MAX_POWER_MASK) | 0x70; 01307 01308 if((paConfig & RF_PACONFIG_PASELECT_PABOOST) == RF_PACONFIG_PASELECT_PABOOST) 01309 { 01310 if(power > 17) 01311 { 01312 paDac = (paDac & RF_PADAC_20DBM_MASK) | RF_PADAC_20DBM_ON; 01313 } 01314 else 01315 { 01316 paDac = (paDac & RF_PADAC_20DBM_MASK) | RF_PADAC_20DBM_OFF; 01317 } 01318 if((paDac & RF_PADAC_20DBM_ON) == RF_PADAC_20DBM_ON) 01319 { 01320 if(power < 5) 01321 { 01322 power = 5; 01323 } 01324 if(power > 20) 01325 { 01326 power = 20; 01327 } 01328 paConfig = (paConfig & RF_PACONFIG_OUTPUTPOWER_MASK) | (uint8_t)((uint16_t)(power - 5) & 0x0F); 01329 } 01330 else 01331 { 01332 if(power < 2) 01333 { 01334 power = 2; 01335 } 01336 if(power > 17) 01337 { 01338 power = 17; 01339 } 01340 paConfig = (paConfig & RF_PACONFIG_OUTPUTPOWER_MASK) | (uint8_t)((uint16_t)(power - 2) & 0x0F); 01341 } 01342 } 01343 else 01344 { 01345 if(power < -1) 01346 { 01347 power = -1; 01348 } 01349 if(power > 14) 01350 { 01351 power = 14; 01352 } 01353 paConfig = (paConfig & RF_PACONFIG_OUTPUTPOWER_MASK) | (uint8_t)((uint16_t)(power + 1) & 0x0F); 01354 } 01355 SX1278Write(REG_PACONFIG, paConfig); 01356 SX1278Write(REG_PADAC, paDac); 01357 } 01358 01359 //----------------------------------------------------------------------------- 01360 uint8_t SX1278GetPaSelect(uint32_t channel) 01361 { 01362 if(channel > RF_MID_BAND_THRESH) 01363 { 01364 return RF_PACONFIG_PASELECT_PABOOST; 01365 } 01366 else 01367 { 01368 return RF_PACONFIG_PASELECT_RFO; 01369 } 01370 } 01371 01372 //----------------------------------------------------------------------------- 01373 bool SX1278CheckRfFrequency(uint32_t frequency) 01374 { 01375 // Implement check. Currently all frequencies are supported 01376 return true; 01377 } 01378 01379 //----------------------------------------------------------------------------- 01380 void SX1278Write(uint8_t addr, uint8_t data) 01381 { 01382 SX1278WriteBuffer(addr, &data, 1); 01383 } 01384 01385 //----------------------------------------------------------------------------- 01386 uint8_t SX1278Read(uint8_t addr) 01387 { 01388 uint8_t data; 01389 SX1278ReadBuffer(addr, &data, 1); 01390 return data; 01391 } 01392 01393 //----------------------------------------------------------------------------- 01394 void SX1278WriteFifo(uint8_t *buffer, uint8_t size) 01395 { 01396 SX1278WriteBuffer(0, buffer, size); 01397 } 01398 01399 //----------------------------------------------------------------------------- 01400 void SX1278ReadFifo(uint8_t *buffer, uint8_t size) 01401 { 01402 SX1278ReadBuffer(0, buffer, size); 01403 } 01404 01405 01406 //----------------------------------------------------------------------------- 01407 01408 01409 01410 /** 01411 * ============================================================================ 01412 * @brief Private functions definitions 01413 * ============================================================================ 01414 */ 01415 //----------------------------------------------------------------------------- 01416 void RxChainCalibration(void) 01417 { 01418 uint8_t regPaConfigInitVal; 01419 uint32_t initialFreq; 01420 01421 // Save context 01422 regPaConfigInitVal = SX1278Read(REG_PACONFIG); 01423 initialFreq = (double)(((uint32_t)SX1278Read(REG_FRFMSB) << 16) | 01424 ((uint32_t)SX1278Read(REG_FRFMID) << 8) | 01425 ((uint32_t)SX1278Read(REG_FRFLSB))) * (double)FREQ_STEP; 01426 01427 // Cut the PA just in case, RFO output, power = -1 dBm 01428 SX1278Write(REG_PACONFIG, 0x00); 01429 01430 // Launch Rx chain calibration for LF band 01431 SX1278Write (REG_IMAGECAL, (SX1278Read(REG_IMAGECAL) & RF_IMAGECAL_IMAGECAL_MASK) | RF_IMAGECAL_IMAGECAL_START); 01432 while((SX1278Read(REG_IMAGECAL) & RF_IMAGECAL_IMAGECAL_RUNNING) == RF_IMAGECAL_IMAGECAL_RUNNING) 01433 { 01434 } 01435 01436 // Sets a Frequency in HF band 01437 SX1278SetChannel(868000000); 01438 01439 // Launch Rx chain calibration for HF band 01440 SX1278Write(REG_IMAGECAL, (SX1278Read(REG_IMAGECAL) & RF_IMAGECAL_IMAGECAL_MASK) | RF_IMAGECAL_IMAGECAL_START); 01441 while((SX1278Read(REG_IMAGECAL) & RF_IMAGECAL_IMAGECAL_RUNNING) == RF_IMAGECAL_IMAGECAL_RUNNING) 01442 { 01443 } 01444 01445 // Restore context 01446 SX1278Write(REG_PACONFIG, regPaConfigInitVal); 01447 SX1278SetChannel(initialFreq); 01448 } 01449 01450 //----------------------------------------------------------------------------- 01451 uint8_t GetFskBandwidthRegValue(uint32_t bandwidth) 01452 { 01453 uint8_t i; 01454 01455 for (i = 0; i < (sizeof(SX1278FskBandwidths) / sizeof(BandwidthMap_t)) - 1; i++) 01456 { 01457 if ((bandwidth >= SX1278FskBandwidths[i].bandwidth) && (bandwidth < SX1278FskBandwidths[i + 1].bandwidth)) 01458 { 01459 return SX1278FskBandwidths[i].RegValue; 01460 } 01461 } 01462 // ERROR: Value not found 01463 while(1); 01464 } 01465 01466 //----------------------------------------------------------------------------- 01467 uint8_t GetLoRaBandwidthRegValue(uint32_t bandwidth) 01468 { 01469 uint8_t i; 01470 01471 for (i = 0; i < (sizeof(SX1278LoRaBandwidths) / sizeof(BandwidthMap_t)) - 1; i++) 01472 { 01473 if ((bandwidth >= SX1278LoRaBandwidths[i].bandwidth) && (bandwidth < SX1278LoRaBandwidths[i + 1].bandwidth)) 01474 { 01475 return SX1278LoRaBandwidths[i].RegValue; 01476 } 01477 } 01478 // ERROR: Value not found 01479 while(1); 01480 } 01481 01482 //----------------------------------------------------------------------------- 01483 void OnDio0Irq() 01484 { 01485 volatile uint8_t irqFlags = 0; 01486 01487 switch (settings.State) 01488 { 01489 case RF_RX_RUNNING: 01490 //TimerStop(&RxTimeoutTimer); 01491 // RxDone interrupt 01492 switch (settings.Modem) 01493 { 01494 case MODEM_FSK: 01495 if (settings.Fsk.CrcOn == true) 01496 { 01497 irqFlags = SX1278Read(REG_IRQFLAGS2); 01498 if ((irqFlags & RF_IRQFLAGS2_CRCOK) != RF_IRQFLAGS2_CRCOK) 01499 { 01500 // Clear Irqs 01501 SX1278Write(REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI | 01502 RF_IRQFLAGS1_PREAMBLEDETECT | 01503 RF_IRQFLAGS1_SYNCADDRESSMATCH); 01504 SX1278Write(REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN); 01505 01506 SX1278SetTimeout(RXTimeoutTimer, NULL, 0); 01507 01508 if (settings.Fsk.RxContinuous == false) 01509 { 01510 SX1278SetTimeout(RXTimeoutSyncWordTimer, NULL, 0); 01511 settings.State = RF_IDLE; 01512 } 01513 else 01514 { 01515 // Continuous mode restart Rx chain 01516 SX1278Write(REG_RXCONFIG, SX1278Read(REG_RXCONFIG) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK); 01517 SX1278SetTimeout(RXTimeoutSyncWordTimer, &OnTimeoutIrq, settings.Fsk.RxSingleTimeout); 01518 } 01519 01520 if ((RadioEvents != NULL) && (RadioEvents->RxError != NULL)) 01521 { 01522 RadioEvents->RxError(); 01523 } 01524 settings.FskPacketHandler.PreambleDetected = false; 01525 settings.FskPacketHandler.SyncWordDetected = false; 01526 settings.FskPacketHandler.NbBytes = 0; 01527 settings.FskPacketHandler.Size = 0; 01528 break; 01529 } 01530 } 01531 01532 // SX1278Read received packet size 01533 if ((settings.FskPacketHandler.Size == 0) && (settings.FskPacketHandler.NbBytes == 0)) 01534 { 01535 if (settings.Fsk.FixLen == false) 01536 { 01537 SX1278ReadFifo((uint8_t*)&settings.FskPacketHandler.Size, 1); 01538 } 01539 else 01540 { 01541 settings.FskPacketHandler.Size = SX1278Read(REG_PAYLOADLENGTH); 01542 } 01543 SX1278ReadFifo(RxTxBuffer + settings.FskPacketHandler.NbBytes, settings.FskPacketHandler.Size - settings.FskPacketHandler.NbBytes); 01544 settings.FskPacketHandler.NbBytes += (settings.FskPacketHandler.Size - settings.FskPacketHandler.NbBytes); 01545 } 01546 else 01547 { 01548 SX1278ReadFifo(RxTxBuffer + settings.FskPacketHandler.NbBytes, settings.FskPacketHandler.Size - settings.FskPacketHandler.NbBytes); 01549 settings.FskPacketHandler.NbBytes += (settings.FskPacketHandler.Size - settings.FskPacketHandler.NbBytes); 01550 } 01551 01552 SX1278SetTimeout(RXTimeoutTimer, NULL, 0); 01553 01554 if (settings.Fsk.RxContinuous == false) 01555 { 01556 settings.State = RF_IDLE; 01557 SX1278SetTimeout(RXTimeoutSyncWordTimer, NULL, 0); 01558 } 01559 else 01560 { 01561 // Continuous mode restart Rx chain 01562 SX1278Write(REG_RXCONFIG, SX1278Read(REG_RXCONFIG) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK); 01563 SX1278SetTimeout(RXTimeoutSyncWordTimer, &OnTimeoutIrq, settings.Fsk.RxSingleTimeout); 01564 } 01565 01566 if ((RadioEvents != NULL) && (RadioEvents->RxDone != NULL)) 01567 { 01568 RadioEvents->RxDone(RxTxBuffer, settings.FskPacketHandler.Size, settings.FskPacketHandler.RssiValue, 0); 01569 } 01570 settings.FskPacketHandler.PreambleDetected = false; 01571 settings.FskPacketHandler.SyncWordDetected = false; 01572 settings.FskPacketHandler.NbBytes = 0; 01573 settings.FskPacketHandler.Size = 0; 01574 break; 01575 case MODEM_LORA: 01576 { 01577 // Clear Irq 01578 SX1278Write(REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXDONE); 01579 01580 irqFlags = SX1278Read(REG_LR_IRQFLAGS); 01581 if ((irqFlags & RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK) == RFLR_IRQFLAGS_PAYLOADCRCERROR) 01582 { 01583 // Clear Irq 01584 SX1278Write(REG_LR_IRQFLAGS, RFLR_IRQFLAGS_PAYLOADCRCERROR); 01585 01586 if (settings.LoRa.RxContinuous == false) 01587 { 01588 settings.State = RF_IDLE; 01589 } 01590 SX1278SetTimeout(RXTimeoutTimer, NULL, 0); 01591 01592 if ((RadioEvents != NULL) && (RadioEvents->RxError != NULL)) 01593 { 01594 RadioEvents->RxError(); 01595 } 01596 break; 01597 } 01598 // Returns SNR value [dB] rounded to the nearest integer value 01599 settings.LoRaPacketHandler.SnrValue = (((int8_t)SX1278Read(REG_LR_PKTSNRVALUE)) + 2) >> 2; 01600 int16_t rssi = SX1278Read(REG_LR_PKTRSSIVALUE); 01601 if (settings.LoRaPacketHandler.SnrValue < 0) 01602 { 01603 if (settings.Channel > RF_MID_BAND_THRESH) 01604 { 01605 settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_HF + rssi + ( rssi >> 4 ) + 01606 settings.LoRaPacketHandler.SnrValue; 01607 } 01608 else 01609 { 01610 settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_LF + rssi + ( rssi >> 4 ) + 01611 settings.LoRaPacketHandler.SnrValue; 01612 } 01613 } 01614 else 01615 { 01616 if(settings.Channel > RF_MID_BAND_THRESH) 01617 { 01618 settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_HF + rssi + ( rssi >> 4 ); 01619 } 01620 else 01621 { 01622 settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_LF + rssi + ( rssi >> 4 ); 01623 } 01624 } 01625 01626 settings.LoRaPacketHandler.Size = SX1278Read( REG_LR_RXNBBYTES); 01627 SX1278Write( REG_LR_FIFOADDRPTR, SX1278Read( REG_LR_FIFORXCURRENTADDR)); 01628 SX1278ReadFifo( RxTxBuffer, settings.LoRaPacketHandler.Size); 01629 01630 if(settings.LoRa.RxContinuous == false) 01631 { 01632 settings.State = RF_IDLE; 01633 } 01634 01635 SX1278SetTimeout(RXTimeoutTimer, NULL, 0); 01636 01637 if ((RadioEvents != NULL) && (RadioEvents->RxDone != NULL)) 01638 { 01639 RadioEvents->RxDone(RxTxBuffer, settings.LoRaPacketHandler.Size, settings.LoRaPacketHandler.RssiValue, settings.LoRaPacketHandler.SnrValue); 01640 } 01641 } 01642 break; 01643 default: 01644 break; 01645 } 01646 break; 01647 case RF_TX_RUNNING: 01648 SX1278SetTimeout(TXTimeoutTimer, NULL, 0); 01649 // TxDone interrupt 01650 switch (settings.Modem) 01651 { 01652 case MODEM_LORA: 01653 // Clear Irq 01654 SX1278Write(REG_LR_IRQFLAGS, RFLR_IRQFLAGS_TXDONE); 01655 // Intentional fall through 01656 case MODEM_FSK: 01657 default: 01658 settings.State = RF_IDLE; 01659 if ((RadioEvents != NULL) && (RadioEvents->TxDone != NULL)) 01660 { 01661 RadioEvents->TxDone(); 01662 } 01663 break; 01664 } 01665 break; 01666 default: 01667 break; 01668 } 01669 } 01670 01671 //----------------------------------------------------------------------------- 01672 void OnDio1Irq() 01673 { 01674 switch (settings.State) 01675 { 01676 case RF_RX_RUNNING: 01677 switch (settings.Modem) 01678 { 01679 case MODEM_FSK: 01680 // Stop Timer 01681 SX1278SetTimeout(RXTimeoutSyncWordTimer, NULL, 0); 01682 01683 // FifoLevel interrupt 01684 // SX1278Read received packet size 01685 if ((settings.FskPacketHandler.Size == 0) && (settings.FskPacketHandler.NbBytes == 0)) 01686 { 01687 if (settings.Fsk.FixLen == false) 01688 { 01689 SX1278ReadFifo((uint8_t*)&settings.FskPacketHandler.Size, 1); 01690 } 01691 else 01692 { 01693 settings.FskPacketHandler.Size = SX1278Read(REG_PAYLOADLENGTH); 01694 } 01695 } 01696 // ERRATA 3.1 - PayloadReady Set for 31.25ns if FIFO is Empty 01697 // 01698 // When FifoLevel interrupt is used to offload the 01699 // FIFO, the microcontroller should monitor both 01700 // PayloadReady and FifoLevel interrupts, and 01701 // read only (FifoThreshold-1) bytes off the FIFO 01702 // when FifoLevel fires 01703 if ((settings.FskPacketHandler.Size - settings.FskPacketHandler.NbBytes) > settings.FskPacketHandler.FifoThresh) 01704 { 01705 SX1278ReadFifo((RxTxBuffer + settings.FskPacketHandler.NbBytes), settings.FskPacketHandler.FifoThresh); 01706 settings.FskPacketHandler.NbBytes += settings.FskPacketHandler.FifoThresh; 01707 } 01708 else 01709 { 01710 SX1278ReadFifo((RxTxBuffer + settings.FskPacketHandler.NbBytes), settings.FskPacketHandler.Size - settings.FskPacketHandler.NbBytes); 01711 settings.FskPacketHandler.NbBytes += (settings.FskPacketHandler.Size - settings.FskPacketHandler.NbBytes); 01712 } 01713 break; 01714 case MODEM_LORA: 01715 // Sync time out 01716 SX1278SetTimeout(RXTimeoutTimer, NULL, 0); 01717 // Clear Irq 01718 SX1278Write(REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXTIMEOUT); 01719 01720 settings.State = RF_IDLE; 01721 if ((RadioEvents != NULL) && (RadioEvents->RxTimeout != NULL)) 01722 { 01723 RadioEvents->RxTimeout(); 01724 } 01725 break; 01726 default: 01727 break; 01728 } 01729 break; 01730 case RF_TX_RUNNING: 01731 switch (settings.Modem) 01732 { 01733 case MODEM_FSK: 01734 // FifoEmpty interrupt 01735 if ((settings.FskPacketHandler.Size - settings.FskPacketHandler.NbBytes) > settings.FskPacketHandler.ChunkSize) 01736 { 01737 SX1278WriteFifo((RxTxBuffer + settings.FskPacketHandler.NbBytes), settings.FskPacketHandler.ChunkSize); 01738 settings.FskPacketHandler.NbBytes += settings.FskPacketHandler.ChunkSize; 01739 } 01740 else 01741 { 01742 // SX1278Write the last chunk of data 01743 SX1278WriteFifo(RxTxBuffer + settings.FskPacketHandler.NbBytes, settings.FskPacketHandler.Size - settings.FskPacketHandler.NbBytes); 01744 settings.FskPacketHandler.NbBytes += settings.FskPacketHandler.Size - settings.FskPacketHandler.NbBytes; 01745 } 01746 break; 01747 case MODEM_LORA: 01748 break; 01749 default: 01750 break; 01751 } 01752 break; 01753 default: 01754 break; 01755 } 01756 } 01757 01758 //----------------------------------------------------------------------------- 01759 void OnDio2Irq() 01760 { 01761 switch (settings.State) 01762 { 01763 case RF_RX_RUNNING: 01764 switch (settings.Modem) 01765 { 01766 case MODEM_FSK: 01767 // Checks if DIO4 is connected. If it is not PreambleDtected is set to true. 01768 if (dioIrq[4] == NULL) 01769 { 01770 settings.FskPacketHandler.PreambleDetected = true; 01771 } 01772 01773 if ((settings.FskPacketHandler.PreambleDetected == true) && (settings.FskPacketHandler.SyncWordDetected == false)) 01774 { 01775 SX1278SetTimeout(RXTimeoutSyncWordTimer, NULL, 0); 01776 01777 settings.FskPacketHandler.SyncWordDetected = true; 01778 01779 settings.FskPacketHandler.RssiValue = -(SX1278Read(REG_RSSIVALUE) >> 1); 01780 01781 settings.FskPacketHandler.AfcValue = (int32_t)(double)(((uint16_t)SX1278Read(REG_AFCMSB) << 8) | 01782 (uint16_t)SX1278Read(REG_AFCLSB)) * 01783 (double)FREQ_STEP; 01784 settings.FskPacketHandler.RxGain = (SX1278Read(REG_LNA) >> 5) & 0x07; 01785 } 01786 break; 01787 case MODEM_LORA: 01788 if (settings.LoRa.FreqHopOn == true) 01789 { 01790 // Clear Irq 01791 SX1278Write(REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL); 01792 01793 if ((RadioEvents != NULL) && (RadioEvents->FhssChangeChannel != NULL)) 01794 { 01795 RadioEvents->FhssChangeChannel((SX1278Read(REG_LR_HOPCHANNEL) & RFLR_HOPCHANNEL_CHANNEL_MASK)); 01796 } 01797 } 01798 break; 01799 default: 01800 break; 01801 } 01802 break; 01803 case RF_TX_RUNNING: 01804 switch (settings.Modem) 01805 { 01806 case MODEM_FSK: 01807 break; 01808 case MODEM_LORA: 01809 if (settings.LoRa.FreqHopOn == true) 01810 { 01811 // Clear Irq 01812 SX1278Write(REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL); 01813 01814 if ((RadioEvents != NULL) && (RadioEvents->FhssChangeChannel != NULL)) 01815 { 01816 RadioEvents->FhssChangeChannel((SX1278Read(REG_LR_HOPCHANNEL) & RFLR_HOPCHANNEL_CHANNEL_MASK)); 01817 } 01818 } 01819 break; 01820 default: 01821 break; 01822 } 01823 break; 01824 default: 01825 break; 01826 } 01827 } 01828 01829 //----------------------------------------------------------------------------- 01830 void OnDio3Irq() 01831 { 01832 switch (settings.Modem) 01833 { 01834 case MODEM_FSK: 01835 break; 01836 case MODEM_LORA: 01837 if ((SX1278Read(REG_LR_IRQFLAGS) & RFLR_IRQFLAGS_CADDETECTED) == RFLR_IRQFLAGS_CADDETECTED) 01838 { 01839 // Clear Irq 01840 SX1278Write(REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDETECTED | RFLR_IRQFLAGS_CADDONE); 01841 if ((RadioEvents != NULL) && (RadioEvents->CadDone != NULL)) 01842 { 01843 RadioEvents->CadDone(true); 01844 } 01845 } 01846 else 01847 { 01848 // Clear Irq 01849 SX1278Write(REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDONE); 01850 if ((RadioEvents != NULL) && (RadioEvents->CadDone != NULL)) 01851 { 01852 RadioEvents->CadDone(false); 01853 } 01854 } 01855 break; 01856 default: 01857 break; 01858 } 01859 } 01860 01861 //----------------------------------------------------------------------------- 01862 void OnDio4Irq() 01863 { 01864 switch (settings.Modem) 01865 { 01866 case MODEM_FSK: 01867 { 01868 if (settings.FskPacketHandler.PreambleDetected == false) 01869 { 01870 settings.FskPacketHandler.PreambleDetected = true; 01871 } 01872 } 01873 break; 01874 case MODEM_LORA: 01875 break; 01876 default: 01877 break; 01878 } 01879 } 01880 01881 //----------------------------------------------------------------------------- 01882 void OnDio5Irq() 01883 { 01884 switch (settings.Modem) 01885 { 01886 case MODEM_FSK: 01887 break; 01888 case MODEM_LORA: 01889 break; 01890 default: 01891 break; 01892 } 01893 } 01894 01895 //-----------------------------------------------------------------------------
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