Diff: targets/TARGET_ONSEMI/TARGET_NCS36510/i2c.h

Revision:

159:612c381a210f

Parent:

149:156823d33999

diff -r b23ee177fd68 -r 612c381a210f targets/TARGET_ONSEMI/TARGET_NCS36510/i2c.h
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/i2c.h	Tue Feb 14 14:44:10 2017 +0000
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/i2c.h	Tue Feb 28 17:13:35 2017 +0000
@@ -83,14 +83,18 @@
 #define I2C_APB_CLK_DIVIDER_VAL_MASK    0x1FE0
 
 /* Error check */
-#define I2C_UFL_CHECK         (d->membase->STATUS.WORD & 0x80)
-#define FIFO_OFL_CHECK        (d->membase->STATUS.WORD & 0x10)
-#define I2C_BUS_ERR_CHECK     (d->membase->STATUS.WORD & 0x04)
-#define RD_DATA_READY         (d->membase->STATUS.WORD & 0x02)
+#define I2C_UFL_CHECK         (obj->membase->STATUS.WORD & 0x80)
+#define I2C_FIFO_FULL         (obj->membase->STATUS.WORD & 0x20)
+#define FIFO_OFL_CHECK        (obj->membase->STATUS.WORD & 0x10)
+#define I2C_BUS_ERR_CHECK     (obj->membase->STATUS.WORD & 0x04)
+#define RD_DATA_READY         (obj->membase->STATUS.WORD & 0x02)
+#define I2C_FIFO_EMPTY        (obj->membase->STATUS.WORD & 0x01)
 
 #define I2C_API_STATUS_SUCCESS    0
 #define PAD_REG_ADRS_BYTE_SIZE    4
 
+#define SEND_COMMAND(cmd)  while(!I2C_FIFO_EMPTY); wait_us(1); obj->membase->CMD_REG = cmd;
+
 /** Init I2C device.
  * @details
  * Sets the necessary registers. The baud rate is set default to 100K
@@ -154,4 +158,4 @@
  */
 extern int32_t fI2cWriteB(i2c_t *d, const char *buf, int len);
 
-#endif /* I2C_H_ */
+#endif /* I2C_H_ */
\ No newline at end of file