Iftikhar Aziz / mbed-dev

4545

Dependents:   LSS_Rev_1

Fork of mbed-dev by Umar Naeem

targets/TARGET_STM/stm_spi_api.c@153:fa9ff456f731, 2016-12-20 (annotated)

Committer:
<>
Date:
Tue Dec 20 17:27:56 2016 +0000
Revision:
153:fa9ff456f731
Parent:
149:156823d33999
Child:
156:95d6b41a828b
This updates the lib to the mbed lib v132

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /* mbed Microcontroller Library
<> 149:156823d33999 2 *******************************************************************************
<> 149:156823d33999 3 * Copyright (c) 2015, STMicroelectronics
<> 149:156823d33999 4 * All rights reserved.
<> 149:156823d33999 5 *
<> 149:156823d33999 6 * Redistribution and use in source and binary forms, with or without
<> 149:156823d33999 7 * modification, are permitted provided that the following conditions are met:
<> 149:156823d33999 8 *
<> 149:156823d33999 9 * 1. Redistributions of source code must retain the above copyright notice,
<> 149:156823d33999 10 * this list of conditions and the following disclaimer.
<> 149:156823d33999 11 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 149:156823d33999 12 * this list of conditions and the following disclaimer in the documentation
<> 149:156823d33999 13 * and/or other materials provided with the distribution.
<> 149:156823d33999 14 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 149:156823d33999 15 * may be used to endorse or promote products derived from this software
<> 149:156823d33999 16 * without specific prior written permission.
<> 149:156823d33999 17 *
<> 149:156823d33999 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 149:156823d33999 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 149:156823d33999 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 149:156823d33999 21 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 149:156823d33999 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 149:156823d33999 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 149:156823d33999 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 149:156823d33999 25 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 149:156823d33999 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 149:156823d33999 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 149:156823d33999 28 *******************************************************************************
<> 149:156823d33999 29 */
<> 149:156823d33999 30 #include "mbed_assert.h"
<> 149:156823d33999 31 #include "mbed_error.h"
<> 149:156823d33999 32 #include "spi_api.h"
<> 149:156823d33999 33
<> 149:156823d33999 34 #if DEVICE_SPI
<> 149:156823d33999 35 #include <stdbool.h>
<> 149:156823d33999 36 #include <math.h>
<> 149:156823d33999 37 #include <string.h>
<> 149:156823d33999 38 #include "cmsis.h"
<> 149:156823d33999 39 #include "pinmap.h"
<> 149:156823d33999 40 #include "PeripheralPins.h"
<> 149:156823d33999 41
<> 149:156823d33999 42 #if DEVICE_SPI_ASYNCH
<> 149:156823d33999 43 #define SPI_INST(obj) ((SPI_TypeDef *)(obj->spi.spi))
<> 149:156823d33999 44 #else
<> 149:156823d33999 45 #define SPI_INST(obj) ((SPI_TypeDef *)(obj->spi))
<> 149:156823d33999 46 #endif
<> 149:156823d33999 47
<> 149:156823d33999 48 #if DEVICE_SPI_ASYNCH
<> 149:156823d33999 49 #define SPI_S(obj) (( struct spi_s *)(&(obj->spi)))
<> 149:156823d33999 50 #else
<> 149:156823d33999 51 #define SPI_S(obj) (( struct spi_s *)(obj))
<> 149:156823d33999 52 #endif
<> 149:156823d33999 53
<> 149:156823d33999 54 #ifndef DEBUG_STDIO
<> 149:156823d33999 55 # define DEBUG_STDIO 0
<> 149:156823d33999 56 #endif
<> 149:156823d33999 57
<> 149:156823d33999 58 #if DEBUG_STDIO
<> 149:156823d33999 59 # include <stdio.h>
<> 149:156823d33999 60 # define DEBUG_PRINTF(...) do { printf(__VA_ARGS__); } while(0)
<> 149:156823d33999 61 #else
<> 149:156823d33999 62 # define DEBUG_PRINTF(...) {}
<> 149:156823d33999 63 #endif
<> 149:156823d33999 64
<> 149:156823d33999 65 void init_spi(spi_t *obj)
<> 149:156823d33999 66 {
<> 149:156823d33999 67 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 68 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 69
<> 149:156823d33999 70 __HAL_SPI_DISABLE(handle);
<> 149:156823d33999 71
<> 149:156823d33999 72 DEBUG_PRINTF("init_spi: instance=0x%8X\r\n", (int)handle->Instance);
<> 149:156823d33999 73 if (HAL_SPI_Init(handle) != HAL_OK) {
<> 149:156823d33999 74 error("Cannot initialize SPI");
<> 149:156823d33999 75 }
<> 149:156823d33999 76
<> 149:156823d33999 77 __HAL_SPI_ENABLE(handle);
<> 149:156823d33999 78 }
<> 149:156823d33999 79
<> 149:156823d33999 80 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
<> 149:156823d33999 81 {
<> 149:156823d33999 82 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 83 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 84
<> 149:156823d33999 85 // Determine the SPI to use
<> 149:156823d33999 86 SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
<> 149:156823d33999 87 SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
<> 149:156823d33999 88 SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
<> 149:156823d33999 89 SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
<> 149:156823d33999 90
<> 149:156823d33999 91 SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
<> 149:156823d33999 92 SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
<> 149:156823d33999 93
<> 149:156823d33999 94 spiobj->spi = (SPIName)pinmap_merge(spi_data, spi_cntl);
<> 149:156823d33999 95 MBED_ASSERT(spiobj->spi != (SPIName)NC);
<> 149:156823d33999 96
<> 149:156823d33999 97 #if defined SPI1_BASE
<> 149:156823d33999 98 // Enable SPI clock
<> 149:156823d33999 99 if (spiobj->spi == SPI_1) {
<> 149:156823d33999 100 __HAL_RCC_SPI1_CLK_ENABLE();
<> 149:156823d33999 101 spiobj->spiIRQ = SPI1_IRQn;
<> 149:156823d33999 102 }
<> 149:156823d33999 103 #endif
<> 149:156823d33999 104
<> 149:156823d33999 105 #if defined SPI2_BASE
<> 149:156823d33999 106 if (spiobj->spi == SPI_2) {
<> 149:156823d33999 107 __HAL_RCC_SPI2_CLK_ENABLE();
<> 149:156823d33999 108 spiobj->spiIRQ = SPI2_IRQn;
<> 149:156823d33999 109 }
<> 149:156823d33999 110 #endif
<> 149:156823d33999 111
<> 149:156823d33999 112 #if defined SPI3_BASE
<> 149:156823d33999 113 if (spiobj->spi == SPI_3) {
<> 149:156823d33999 114 __HAL_RCC_SPI3_CLK_ENABLE();
<> 149:156823d33999 115 spiobj->spiIRQ = SPI3_IRQn;
<> 149:156823d33999 116 }
<> 149:156823d33999 117 #endif
<> 149:156823d33999 118
<> 149:156823d33999 119 #if defined SPI4_BASE
<> 149:156823d33999 120 if (spiobj->spi == SPI_4) {
<> 149:156823d33999 121 __HAL_RCC_SPI4_CLK_ENABLE();
<> 149:156823d33999 122 spiobj->spiIRQ = SPI4_IRQn;
<> 149:156823d33999 123 }
<> 149:156823d33999 124 #endif
<> 149:156823d33999 125
<> 149:156823d33999 126 #if defined SPI5_BASE
<> 149:156823d33999 127 if (spiobj->spi == SPI_5) {
<> 149:156823d33999 128 __HAL_RCC_SPI5_CLK_ENABLE();
<> 149:156823d33999 129 spiobj->spiIRQ = SPI5_IRQn;
<> 149:156823d33999 130 }
<> 149:156823d33999 131 #endif
<> 149:156823d33999 132
<> 149:156823d33999 133 #if defined SPI6_BASE
<> 149:156823d33999 134 if (spiobj->spi == SPI_6) {
<> 149:156823d33999 135 __HAL_RCC_SPI6_CLK_ENABLE();
<> 149:156823d33999 136 spiobj->spiIRQ = SPI6_IRQn;
<> 149:156823d33999 137 }
<> 149:156823d33999 138 #endif
<> 149:156823d33999 139
<> 149:156823d33999 140 // Configure the SPI pins
<> 149:156823d33999 141 pinmap_pinout(mosi, PinMap_SPI_MOSI);
<> 149:156823d33999 142 pinmap_pinout(miso, PinMap_SPI_MISO);
<> 149:156823d33999 143 pinmap_pinout(sclk, PinMap_SPI_SCLK);
<> 149:156823d33999 144 spiobj->pin_miso = miso;
<> 149:156823d33999 145 spiobj->pin_mosi = mosi;
<> 149:156823d33999 146 spiobj->pin_sclk = sclk;
<> 149:156823d33999 147 spiobj->pin_ssel = ssel;
<> 149:156823d33999 148 if (ssel != NC) {
<> 149:156823d33999 149 pinmap_pinout(ssel, PinMap_SPI_SSEL);
<> 149:156823d33999 150 } else {
<> 149:156823d33999 151 handle->Init.NSS = SPI_NSS_SOFT;
<> 149:156823d33999 152 }
<> 149:156823d33999 153
<> 149:156823d33999 154 /* Fill default value */
<> 149:156823d33999 155 handle->Instance = SPI_INST(obj);
<> 149:156823d33999 156 handle->Init.Mode = SPI_MODE_MASTER;
<> 149:156823d33999 157 handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_256;
<> 149:156823d33999 158 handle->Init.Direction = SPI_DIRECTION_2LINES;
<> 149:156823d33999 159 handle->Init.CLKPhase = SPI_PHASE_1EDGE;
<> 149:156823d33999 160 handle->Init.CLKPolarity = SPI_POLARITY_LOW;
<> 149:156823d33999 161 handle->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLED;
<> 149:156823d33999 162 handle->Init.CRCPolynomial = 7;
<> 149:156823d33999 163 handle->Init.DataSize = SPI_DATASIZE_8BIT;
<> 149:156823d33999 164 handle->Init.FirstBit = SPI_FIRSTBIT_MSB;
<> 149:156823d33999 165 handle->Init.TIMode = SPI_TIMODE_DISABLED;
<> 149:156823d33999 166
<> 149:156823d33999 167 init_spi(obj);
<> 149:156823d33999 168 }
<> 149:156823d33999 169
<> 149:156823d33999 170 void spi_free(spi_t *obj)
<> 149:156823d33999 171 {
<> 149:156823d33999 172 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 173 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 174
<> 149:156823d33999 175 DEBUG_PRINTF("spi_free\r\n");
<> 149:156823d33999 176
<> 149:156823d33999 177 __HAL_SPI_DISABLE(handle);
<> 149:156823d33999 178 HAL_SPI_DeInit(handle);
<> 149:156823d33999 179
<> 149:156823d33999 180 #if defined SPI1_BASE
<> 149:156823d33999 181 // Reset SPI and disable clock
<> 149:156823d33999 182 if (spiobj->spi == SPI_1) {
<> 149:156823d33999 183 __HAL_RCC_SPI1_FORCE_RESET();
<> 149:156823d33999 184 __HAL_RCC_SPI1_RELEASE_RESET();
<> 149:156823d33999 185 __HAL_RCC_SPI1_CLK_DISABLE();
<> 149:156823d33999 186 }
<> 149:156823d33999 187 #endif
<> 149:156823d33999 188 #if defined SPI2_BASE
<> 149:156823d33999 189 if (spiobj->spi == SPI_2) {
<> 149:156823d33999 190 __HAL_RCC_SPI2_FORCE_RESET();
<> 149:156823d33999 191 __HAL_RCC_SPI2_RELEASE_RESET();
<> 149:156823d33999 192 __HAL_RCC_SPI2_CLK_DISABLE();
<> 149:156823d33999 193 }
<> 149:156823d33999 194 #endif
<> 149:156823d33999 195
<> 149:156823d33999 196 #if defined SPI3_BASE
<> 149:156823d33999 197 if (spiobj->spi == SPI_3) {
<> 149:156823d33999 198 __HAL_RCC_SPI3_FORCE_RESET();
<> 149:156823d33999 199 __HAL_RCC_SPI3_RELEASE_RESET();
<> 149:156823d33999 200 __HAL_RCC_SPI3_CLK_DISABLE();
<> 149:156823d33999 201 }
<> 149:156823d33999 202 #endif
<> 149:156823d33999 203
<> 149:156823d33999 204 #if defined SPI4_BASE
<> 149:156823d33999 205 if (spiobj->spi == SPI_4) {
<> 149:156823d33999 206 __HAL_RCC_SPI4_FORCE_RESET();
<> 149:156823d33999 207 __HAL_RCC_SPI4_RELEASE_RESET();
<> 149:156823d33999 208 __HAL_RCC_SPI4_CLK_DISABLE();
<> 149:156823d33999 209 }
<> 149:156823d33999 210 #endif
<> 149:156823d33999 211
<> 149:156823d33999 212 #if defined SPI5_BASE
<> 149:156823d33999 213 if (spiobj->spi == SPI_5) {
<> 149:156823d33999 214 __HAL_RCC_SPI5_FORCE_RESET();
<> 149:156823d33999 215 __HAL_RCC_SPI5_RELEASE_RESET();
<> 149:156823d33999 216 __HAL_RCC_SPI5_CLK_DISABLE();
<> 149:156823d33999 217 }
<> 149:156823d33999 218 #endif
<> 149:156823d33999 219
<> 149:156823d33999 220 #if defined SPI6_BASE
<> 149:156823d33999 221 if (spiobj->spi == SPI_6) {
<> 149:156823d33999 222 __HAL_RCC_SPI6_FORCE_RESET();
<> 149:156823d33999 223 __HAL_RCC_SPI6_RELEASE_RESET();
<> 149:156823d33999 224 __HAL_RCC_SPI6_CLK_DISABLE();
<> 149:156823d33999 225 }
<> 149:156823d33999 226 #endif
<> 149:156823d33999 227
<> 149:156823d33999 228 // Configure GPIOs
<> 149:156823d33999 229 pin_function(spiobj->pin_miso, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
<> 149:156823d33999 230 pin_function(spiobj->pin_mosi, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
<> 149:156823d33999 231 pin_function(spiobj->pin_sclk, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
<> 149:156823d33999 232 if (handle->Init.NSS != SPI_NSS_SOFT) {
<> 149:156823d33999 233 pin_function(spiobj->pin_ssel, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
<> 149:156823d33999 234 }
<> 149:156823d33999 235 }
<> 149:156823d33999 236
<> 149:156823d33999 237 void spi_format(spi_t *obj, int bits, int mode, int slave)
<> 149:156823d33999 238 {
<> 149:156823d33999 239 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 240 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 241
<> 149:156823d33999 242 DEBUG_PRINTF("spi_format, bits:%d, mode:%d, slave?:%d\r\n", bits, mode, slave);
<> 149:156823d33999 243
<> 149:156823d33999 244 // Save new values
<> 149:156823d33999 245 handle->Init.DataSize = (bits == 16) ? SPI_DATASIZE_16BIT : SPI_DATASIZE_8BIT;
<> 149:156823d33999 246
<> 149:156823d33999 247 switch (mode) {
<> 149:156823d33999 248 case 0:
<> 149:156823d33999 249 handle->Init.CLKPolarity = SPI_POLARITY_LOW;
<> 149:156823d33999 250 handle->Init.CLKPhase = SPI_PHASE_1EDGE;
<> 149:156823d33999 251 break;
<> 149:156823d33999 252 case 1:
<> 149:156823d33999 253 handle->Init.CLKPolarity = SPI_POLARITY_LOW;
<> 149:156823d33999 254 handle->Init.CLKPhase = SPI_PHASE_2EDGE;
<> 149:156823d33999 255 break;
<> 149:156823d33999 256 case 2:
<> 149:156823d33999 257 handle->Init.CLKPolarity = SPI_POLARITY_HIGH;
<> 149:156823d33999 258 handle->Init.CLKPhase = SPI_PHASE_1EDGE;
<> 149:156823d33999 259 break;
<> 149:156823d33999 260 default:
<> 149:156823d33999 261 handle->Init.CLKPolarity = SPI_POLARITY_HIGH;
<> 149:156823d33999 262 handle->Init.CLKPhase = SPI_PHASE_2EDGE;
<> 149:156823d33999 263 break;
<> 149:156823d33999 264 }
<> 149:156823d33999 265
<> 149:156823d33999 266 if (handle->Init.NSS != SPI_NSS_SOFT) {
<> 149:156823d33999 267 handle->Init.NSS = (slave) ? SPI_NSS_HARD_INPUT : SPI_NSS_HARD_OUTPUT;
<> 149:156823d33999 268 }
<> 149:156823d33999 269
<> 149:156823d33999 270 handle->Init.Mode = (slave) ? SPI_MODE_SLAVE : SPI_MODE_MASTER;
<> 149:156823d33999 271
<> 149:156823d33999 272 init_spi(obj);
<> 149:156823d33999 273 }
<> 149:156823d33999 274
<> 149:156823d33999 275 /*
<> 149:156823d33999 276 * Only the IP clock input is family dependant so it computed
<> 149:156823d33999 277 * separately in spi_get_clock_freq
<> 149:156823d33999 278 */
<> 149:156823d33999 279 extern int spi_get_clock_freq(spi_t *obj);
<> 149:156823d33999 280
<> 149:156823d33999 281 static const uint16_t baudrate_prescaler_table[] = {SPI_BAUDRATEPRESCALER_2,
<> 149:156823d33999 282 SPI_BAUDRATEPRESCALER_4,
<> 149:156823d33999 283 SPI_BAUDRATEPRESCALER_8,
<> 149:156823d33999 284 SPI_BAUDRATEPRESCALER_16,
<> 149:156823d33999 285 SPI_BAUDRATEPRESCALER_32,
<> 149:156823d33999 286 SPI_BAUDRATEPRESCALER_64,
<> 149:156823d33999 287 SPI_BAUDRATEPRESCALER_128,
<> 149:156823d33999 288 SPI_BAUDRATEPRESCALER_256};
<> 149:156823d33999 289
<> 149:156823d33999 290 void spi_frequency(spi_t *obj, int hz) {
<> 149:156823d33999 291 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 292 int spi_hz = 0;
<> 149:156823d33999 293 uint8_t prescaler_rank = 0;
<> 149:156823d33999 294 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 295
<> 149:156823d33999 296 /* Get the clock of the peripheral */
<> 149:156823d33999 297 spi_hz = spi_get_clock_freq(obj);
<> 149:156823d33999 298
<> 149:156823d33999 299 /* Define pre-scaler in order to get highest available frequency below requested frequency */
<> 149:156823d33999 300 while ((spi_hz > hz) && (prescaler_rank < sizeof(baudrate_prescaler_table)/sizeof(baudrate_prescaler_table[0]))){
<> 149:156823d33999 301 spi_hz = spi_hz / 2;
<> 149:156823d33999 302 prescaler_rank++;
<> 149:156823d33999 303 }
<> 149:156823d33999 304
<> 149:156823d33999 305 if (prescaler_rank <= sizeof(baudrate_prescaler_table)/sizeof(baudrate_prescaler_table[0])) {
<> 149:156823d33999 306 handle->Init.BaudRatePrescaler = baudrate_prescaler_table[prescaler_rank-1];
<> 149:156823d33999 307 } else {
<> 149:156823d33999 308 error("Couldn't setup requested SPI frequency");
<> 149:156823d33999 309 }
<> 149:156823d33999 310
<> 149:156823d33999 311 init_spi(obj);
<> 149:156823d33999 312 }
<> 149:156823d33999 313
<> 149:156823d33999 314 static inline int ssp_readable(spi_t *obj)
<> 149:156823d33999 315 {
<> 149:156823d33999 316 int status;
<> 149:156823d33999 317 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 318 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 319
<> 149:156823d33999 320 // Check if data is received
<> 149:156823d33999 321 status = ((__HAL_SPI_GET_FLAG(handle, SPI_FLAG_RXNE) != RESET) ? 1 : 0);
<> 149:156823d33999 322 return status;
<> 149:156823d33999 323 }
<> 149:156823d33999 324
<> 149:156823d33999 325 static inline int ssp_writeable(spi_t *obj)
<> 149:156823d33999 326 {
<> 149:156823d33999 327 int status;
<> 149:156823d33999 328 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 329 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 330
<> 149:156823d33999 331 // Check if data is transmitted
<> 149:156823d33999 332 status = ((__HAL_SPI_GET_FLAG(handle, SPI_FLAG_TXE) != RESET) ? 1 : 0);
<> 149:156823d33999 333 return status;
<> 149:156823d33999 334 }
<> 149:156823d33999 335
<> 149:156823d33999 336 static inline int ssp_busy(spi_t *obj)
<> 149:156823d33999 337 {
<> 149:156823d33999 338 int status;
<> 149:156823d33999 339 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 340 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 341 status = ((__HAL_SPI_GET_FLAG(handle, SPI_FLAG_BSY) != RESET) ? 1 : 0);
<> 149:156823d33999 342 return status;
<> 149:156823d33999 343 }
<> 149:156823d33999 344
<> 149:156823d33999 345 int spi_master_write(spi_t *obj, int value)
<> 149:156823d33999 346 {
<> 149:156823d33999 347 uint16_t size, Rx, ret;
<> 149:156823d33999 348 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 349 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 350
<> 149:156823d33999 351 size = (handle->Init.DataSize == SPI_DATASIZE_16BIT) ? 2 : 1;
<> 149:156823d33999 352
<> 149:156823d33999 353 /* Use 10ms timeout */
<> 149:156823d33999 354 ret = HAL_SPI_TransmitReceive(handle,(uint8_t*)&value,(uint8_t*)&Rx,size,10);
<> 149:156823d33999 355
<> 149:156823d33999 356 if(ret == HAL_OK) {
<> 149:156823d33999 357 return Rx;
<> 149:156823d33999 358 } else {
<> 149:156823d33999 359 DEBUG_PRINTF("SPI inst=0x%8X ERROR in write\r\n", (int)handle->Instance);
<> 149:156823d33999 360 return -1;
<> 149:156823d33999 361 }
<> 149:156823d33999 362 }
<> 149:156823d33999 363
<> 149:156823d33999 364 int spi_slave_receive(spi_t *obj)
<> 149:156823d33999 365 {
<> 149:156823d33999 366 return ((ssp_readable(obj) && !ssp_busy(obj)) ? 1 : 0);
<> 149:156823d33999 367 };
<> 149:156823d33999 368
<> 149:156823d33999 369 int spi_slave_read(spi_t *obj)
<> 149:156823d33999 370 {
<> 149:156823d33999 371 SPI_TypeDef *spi = SPI_INST(obj);
<> 149:156823d33999 372 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 373 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 374 while (!ssp_readable(obj));
<> 149:156823d33999 375 if (handle->Init.DataSize == SPI_DATASIZE_8BIT) {
<> 149:156823d33999 376 // Force 8-bit access to the data register
<> 149:156823d33999 377 uint8_t *p_spi_dr = 0;
<> 149:156823d33999 378 p_spi_dr = (uint8_t *) & (spi->DR);
<> 149:156823d33999 379 return (int)(*p_spi_dr);
<> 149:156823d33999 380 } else {
<> 149:156823d33999 381 return (int)spi->DR;
<> 149:156823d33999 382 }
<> 149:156823d33999 383 }
<> 149:156823d33999 384
<> 149:156823d33999 385 void spi_slave_write(spi_t *obj, int value)
<> 149:156823d33999 386 {
<> 149:156823d33999 387 SPI_TypeDef *spi = SPI_INST(obj);
<> 149:156823d33999 388 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 389 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 390 while (!ssp_writeable(obj));
<> 149:156823d33999 391 if (handle->Init.DataSize == SPI_DATASIZE_8BIT) {
<> 149:156823d33999 392 // Force 8-bit access to the data register
<> 149:156823d33999 393 uint8_t *p_spi_dr = 0;
<> 149:156823d33999 394 p_spi_dr = (uint8_t *) & (spi->DR);
<> 149:156823d33999 395 *p_spi_dr = (uint8_t)value;
<> 149:156823d33999 396 } else { // SPI_DATASIZE_16BIT
<> 149:156823d33999 397 spi->DR = (uint16_t)value;
<> 149:156823d33999 398 }
<> 149:156823d33999 399 }
<> 149:156823d33999 400
<> 149:156823d33999 401 int spi_busy(spi_t *obj)
<> 149:156823d33999 402 {
<> 149:156823d33999 403 return ssp_busy(obj);
<> 149:156823d33999 404 }
<> 149:156823d33999 405
<> 149:156823d33999 406 #ifdef DEVICE_SPI_ASYNCH
<> 149:156823d33999 407 typedef enum {
<> 149:156823d33999 408 SPI_TRANSFER_TYPE_NONE = 0,
<> 149:156823d33999 409 SPI_TRANSFER_TYPE_TX = 1,
<> 149:156823d33999 410 SPI_TRANSFER_TYPE_RX = 2,
<> 149:156823d33999 411 SPI_TRANSFER_TYPE_TXRX = 3,
<> 149:156823d33999 412 } transfer_type_t;
<> 149:156823d33999 413
<> 149:156823d33999 414
<> 149:156823d33999 415 /// @returns the number of bytes transferred, or `0` if nothing transferred
<> 149:156823d33999 416 static int spi_master_start_asynch_transfer(spi_t *obj, transfer_type_t transfer_type, const void *tx, void *rx, size_t length)
<> 149:156823d33999 417 {
<> 149:156823d33999 418 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 419 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 420 bool is16bit = (handle->Init.DataSize == SPI_DATASIZE_16BIT);
<> 149:156823d33999 421 // the HAL expects number of transfers instead of number of bytes
<> 149:156823d33999 422 // so for 16 bit transfer width the count needs to be halved
<> 149:156823d33999 423 size_t words;
<> 149:156823d33999 424
<> 149:156823d33999 425 DEBUG_PRINTF("SPI inst=0x%8X Start: %u, %u\r\n", (int)handle->Instance, transfer_type, length);
<> 149:156823d33999 426
<> 149:156823d33999 427 obj->spi.transfer_type = transfer_type;
<> 149:156823d33999 428
<> 149:156823d33999 429 if (is16bit) {
<> 149:156823d33999 430 words = length / 2;
<> 149:156823d33999 431 } else {
<> 149:156823d33999 432 words = length;
<> 149:156823d33999 433 }
<> 149:156823d33999 434
<> 149:156823d33999 435 // enable the interrupt
<> 149:156823d33999 436 IRQn_Type irq_n = spiobj->spiIRQ;
<> 153:fa9ff456f731 437 NVIC_DisableIRQ(irq_n);
<> 149:156823d33999 438 NVIC_ClearPendingIRQ(irq_n);
<> 149:156823d33999 439 NVIC_SetPriority(irq_n, 1);
<> 149:156823d33999 440 NVIC_EnableIRQ(irq_n);
<> 149:156823d33999 441
<> 149:156823d33999 442 // enable the right hal transfer
<> 149:156823d33999 443 int rc = 0;
<> 149:156823d33999 444 switch(transfer_type) {
<> 149:156823d33999 445 case SPI_TRANSFER_TYPE_TXRX:
<> 149:156823d33999 446 rc = HAL_SPI_TransmitReceive_IT(handle, (uint8_t*)tx, (uint8_t*)rx, words);
<> 149:156823d33999 447 break;
<> 149:156823d33999 448 case SPI_TRANSFER_TYPE_TX:
<> 149:156823d33999 449 rc = HAL_SPI_Transmit_IT(handle, (uint8_t*)tx, words);
<> 149:156823d33999 450 break;
<> 149:156823d33999 451 case SPI_TRANSFER_TYPE_RX:
<> 149:156823d33999 452 // the receive function also "transmits" the receive buffer so in order
<> 149:156823d33999 453 // to guarantee that 0xff is on the line, we explicitly memset it here
<> 149:156823d33999 454 memset(rx, SPI_FILL_WORD, length);
<> 149:156823d33999 455 rc = HAL_SPI_Receive_IT(handle, (uint8_t*)rx, words);
<> 149:156823d33999 456 break;
<> 149:156823d33999 457 default:
<> 149:156823d33999 458 length = 0;
<> 149:156823d33999 459 }
<> 149:156823d33999 460
<> 149:156823d33999 461 if (rc) {
<> 149:156823d33999 462 DEBUG_PRINTF("SPI: RC=%u\n", rc);
<> 149:156823d33999 463 length = 0;
<> 149:156823d33999 464 }
<> 149:156823d33999 465
<> 149:156823d33999 466 return length;
<> 149:156823d33999 467 }
<> 149:156823d33999 468
<> 149:156823d33999 469 // asynchronous API
<> 149:156823d33999 470 void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint)
<> 149:156823d33999 471 {
<> 149:156823d33999 472 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 473 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 474
<> 149:156823d33999 475 // TODO: DMA usage is currently ignored
<> 149:156823d33999 476 (void) hint;
<> 149:156823d33999 477
<> 149:156823d33999 478 // check which use-case we have
<> 149:156823d33999 479 bool use_tx = (tx != NULL && tx_length > 0);
<> 149:156823d33999 480 bool use_rx = (rx != NULL && rx_length > 0);
<> 149:156823d33999 481 bool is16bit = (handle->Init.DataSize == SPI_DATASIZE_16BIT);
<> 149:156823d33999 482
<> 149:156823d33999 483 // don't do anything, if the buffers aren't valid
<> 149:156823d33999 484 if (!use_tx && !use_rx)
<> 149:156823d33999 485 return;
<> 149:156823d33999 486
<> 149:156823d33999 487 // copy the buffers to the SPI object
<> 149:156823d33999 488 obj->tx_buff.buffer = (void *) tx;
<> 149:156823d33999 489 obj->tx_buff.length = tx_length;
<> 149:156823d33999 490 obj->tx_buff.pos = 0;
<> 149:156823d33999 491 obj->tx_buff.width = is16bit ? 16 : 8;
<> 149:156823d33999 492
<> 149:156823d33999 493 obj->rx_buff.buffer = rx;
<> 149:156823d33999 494 obj->rx_buff.length = rx_length;
<> 149:156823d33999 495 obj->rx_buff.pos = 0;
<> 149:156823d33999 496 obj->rx_buff.width = obj->tx_buff.width;
<> 149:156823d33999 497
<> 149:156823d33999 498 obj->spi.event = event;
<> 149:156823d33999 499
<> 149:156823d33999 500 DEBUG_PRINTF("SPI: Transfer: %u, %u\n", tx_length, rx_length);
<> 149:156823d33999 501
<> 149:156823d33999 502 // register the thunking handler
<> 149:156823d33999 503 IRQn_Type irq_n = spiobj->spiIRQ;
<> 149:156823d33999 504 NVIC_SetVector(irq_n, (uint32_t)handler);
<> 149:156823d33999 505
<> 149:156823d33999 506 // enable the right hal transfer
<> 149:156823d33999 507 if (use_tx && use_rx) {
<> 149:156823d33999 508 // we cannot manage different rx / tx sizes, let's use smaller one
<> 149:156823d33999 509 size_t size = (tx_length < rx_length)? tx_length : rx_length;
<> 149:156823d33999 510 if(tx_length != rx_length) {
<> 149:156823d33999 511 DEBUG_PRINTF("SPI: Full duplex transfer only 1 size: %d\n", size);
<> 149:156823d33999 512 obj->tx_buff.length = size;
<> 149:156823d33999 513 obj->rx_buff.length = size;
<> 149:156823d33999 514 }
<> 149:156823d33999 515 spi_master_start_asynch_transfer(obj, SPI_TRANSFER_TYPE_TXRX, tx, rx, size);
<> 149:156823d33999 516 } else if (use_tx) {
<> 149:156823d33999 517 spi_master_start_asynch_transfer(obj, SPI_TRANSFER_TYPE_TX, tx, NULL, tx_length);
<> 149:156823d33999 518 } else if (use_rx) {
<> 149:156823d33999 519 spi_master_start_asynch_transfer(obj, SPI_TRANSFER_TYPE_RX, NULL, rx, rx_length);
<> 149:156823d33999 520 }
<> 149:156823d33999 521 }
<> 149:156823d33999 522
<> 153:fa9ff456f731 523 inline uint32_t spi_irq_handler_asynch(spi_t *obj)
<> 149:156823d33999 524 {
<> 149:156823d33999 525 int event = 0;
<> 149:156823d33999 526
<> 149:156823d33999 527 // call the CubeF4 handler, this will update the handle
<> 153:fa9ff456f731 528 HAL_SPI_IRQHandler(&obj->spi.handle);
<> 149:156823d33999 529
<> 153:fa9ff456f731 530 if (obj->spi.handle.State == HAL_SPI_STATE_READY) {
<> 149:156823d33999 531 // When HAL SPI is back to READY state, check if there was an error
<> 153:fa9ff456f731 532 int error = obj->spi.handle.ErrorCode;
<> 149:156823d33999 533 if(error != HAL_SPI_ERROR_NONE) {
<> 149:156823d33999 534 // something went wrong and the transfer has definitely completed
<> 149:156823d33999 535 event = SPI_EVENT_ERROR | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE;
<> 149:156823d33999 536
<> 149:156823d33999 537 if (error & HAL_SPI_ERROR_OVR) {
<> 149:156823d33999 538 // buffer overrun
<> 149:156823d33999 539 event |= SPI_EVENT_RX_OVERFLOW;
<> 149:156823d33999 540 }
<> 149:156823d33999 541 } else {
<> 149:156823d33999 542 // else we're done
<> 149:156823d33999 543 event = SPI_EVENT_COMPLETE | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE;
<> 149:156823d33999 544 }
<> 153:fa9ff456f731 545 // enable the interrupt
<> 153:fa9ff456f731 546 NVIC_DisableIRQ(obj->spi.spiIRQ);
<> 153:fa9ff456f731 547 NVIC_ClearPendingIRQ(obj->spi.spiIRQ);
<> 149:156823d33999 548 }
<> 149:156823d33999 549
<> 149:156823d33999 550
<> 149:156823d33999 551 return (event & (obj->spi.event | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE));
<> 149:156823d33999 552 }
<> 149:156823d33999 553
<> 149:156823d33999 554 uint8_t spi_active(spi_t *obj)
<> 149:156823d33999 555 {
<> 149:156823d33999 556 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 557 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 558 HAL_SPI_StateTypeDef state = HAL_SPI_GetState(handle);
<> 149:156823d33999 559
<> 149:156823d33999 560 switch(state) {
<> 149:156823d33999 561 case HAL_SPI_STATE_RESET:
<> 149:156823d33999 562 case HAL_SPI_STATE_READY:
<> 149:156823d33999 563 case HAL_SPI_STATE_ERROR:
<> 149:156823d33999 564 return 0;
<> 149:156823d33999 565 default:
<> 149:156823d33999 566 return 1;
<> 149:156823d33999 567 }
<> 149:156823d33999 568 }
<> 149:156823d33999 569
<> 149:156823d33999 570 void spi_abort_asynch(spi_t *obj)
<> 149:156823d33999 571 {
<> 149:156823d33999 572 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 573 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 574
<> 149:156823d33999 575 // disable interrupt
<> 149:156823d33999 576 IRQn_Type irq_n = spiobj->spiIRQ;
<> 149:156823d33999 577 NVIC_ClearPendingIRQ(irq_n);
<> 149:156823d33999 578 NVIC_DisableIRQ(irq_n);
<> 149:156823d33999 579
<> 149:156823d33999 580 // clean-up
<> 149:156823d33999 581 __HAL_SPI_DISABLE(handle);
<> 149:156823d33999 582 HAL_SPI_DeInit(handle);
<> 149:156823d33999 583 HAL_SPI_Init(handle);
<> 149:156823d33999 584 __HAL_SPI_ENABLE(handle);
<> 149:156823d33999 585 }
<> 149:156823d33999 586
<> 149:156823d33999 587 #endif //DEVICE_SPI_ASYNCH
<> 149:156823d33999 588
<> 149:156823d33999 589 #endif