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targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/LPC11U6x.h@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:: bogdanm
Date:: Thu Oct 01 15:25:22 2015 +0300
Revision:: 0:9b334a45a8ff
Child:: 144:ef7eb2e8f9f7

Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1
bogdanm	0:9b334a45a8ff	2	/**************************************************************************************************//
bogdanm	0:9b334a45a8ff	3	* @file LPC11U6x.h
bogdanm	0:9b334a45a8ff	4	*
bogdanm	0:9b334a45a8ff	5	* @brief CMSIS Cortex-M0PLUS Peripheral Access Layer Header File for
bogdanm	0:9b334a45a8ff	6	* LPC11U6x from .
bogdanm	0:9b334a45a8ff	7	*
bogdanm	0:9b334a45a8ff	8	* @version V0.4
bogdanm	0:9b334a45a8ff	9	* @date 22. October 2013
bogdanm	0:9b334a45a8ff	10	*
bogdanm	0:9b334a45a8ff	11	* @note Generated with SVDConv V2.81a
bogdanm	0:9b334a45a8ff	12	* from CMSIS SVD File 'LPC11U6x.svd' Version 0.4,
bogdanm	0:9b334a45a8ff	13	*
bogdanm	0:9b334a45a8ff	14	* modified by Keil
bogdanm	0:9b334a45a8ff	15	*******************************************************************************************************/
bogdanm	0:9b334a45a8ff	16
bogdanm	0:9b334a45a8ff	17
bogdanm	0:9b334a45a8ff	18
bogdanm	0:9b334a45a8ff	19	/** @addtogroup (null)
bogdanm	0:9b334a45a8ff	20	* @{
bogdanm	0:9b334a45a8ff	21	*/
bogdanm	0:9b334a45a8ff	22
bogdanm	0:9b334a45a8ff	23	/** @addtogroup LPC11U6x
bogdanm	0:9b334a45a8ff	24	* @{
bogdanm	0:9b334a45a8ff	25	*/
bogdanm	0:9b334a45a8ff	26
bogdanm	0:9b334a45a8ff	27	#ifndef LPC11U6X_H
bogdanm	0:9b334a45a8ff	28	#define LPC11U6X_H
bogdanm	0:9b334a45a8ff	29
bogdanm	0:9b334a45a8ff	30	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	31	extern "C" {
bogdanm	0:9b334a45a8ff	32	#endif
bogdanm	0:9b334a45a8ff	33
bogdanm	0:9b334a45a8ff	34
bogdanm	0:9b334a45a8ff	35	/* ------------------------- Interrupt Number Definition ------------------------ */
bogdanm	0:9b334a45a8ff	36
bogdanm	0:9b334a45a8ff	37	typedef enum {
bogdanm	0:9b334a45a8ff	38	/* ----------------- Cortex-M0PLUS Processor Exceptions Numbers ----------------- */
bogdanm	0:9b334a45a8ff	39	Reset_IRQn = -15, /!< 1 Reset Vector, invoked on Power up and warm reset /
bogdanm	0:9b334a45a8ff	40	NonMaskableInt_IRQn = -14, /!< 2 Non maskable Interrupt, cannot be stopped or preempted /
bogdanm	0:9b334a45a8ff	41	HardFault_IRQn = -13, /!< 3 Hard Fault, all classes of Fault /
bogdanm	0:9b334a45a8ff	42
bogdanm	0:9b334a45a8ff	43
bogdanm	0:9b334a45a8ff	44
bogdanm	0:9b334a45a8ff	45	SVCall_IRQn = -5, /!< 11 System Service Call via SVC instruction /
bogdanm	0:9b334a45a8ff	46
bogdanm	0:9b334a45a8ff	47
bogdanm	0:9b334a45a8ff	48	PendSV_IRQn = -2, /!< 14 Pendable request for system service /
bogdanm	0:9b334a45a8ff	49	SysTick_IRQn = -1, /!< 15 System Tick Timer /
bogdanm	0:9b334a45a8ff	50	/* --------------------- LPC11U6x Specific Interrupt Numbers -------------------- */
bogdanm	0:9b334a45a8ff	51	PIN_INT0_IRQn = 0, /!< 0 PIN_INT0 /
bogdanm	0:9b334a45a8ff	52	PIN_INT1_IRQn = 1, /!< 1 PIN_INT1 /
bogdanm	0:9b334a45a8ff	53	PIN_INT2_IRQn = 2, /!< 2 PIN_INT2 /
bogdanm	0:9b334a45a8ff	54	PIN_INT3_IRQn = 3, /!< 3 PIN_INT3 /
bogdanm	0:9b334a45a8ff	55	PIN_INT4_IRQn = 4, /!< 4 PIN_INT4 /
bogdanm	0:9b334a45a8ff	56	PIN_INT5_IRQn = 5, /!< 5 PIN_INT5 /
bogdanm	0:9b334a45a8ff	57	PIN_INT6_IRQn = 6, /!< 6 PIN_INT6 /
bogdanm	0:9b334a45a8ff	58	PIN_INT7_IRQn = 7, /!< 7 PIN_INT7 /
bogdanm	0:9b334a45a8ff	59	GINT0_IRQn = 8, /!< 8 GINT0 /
bogdanm	0:9b334a45a8ff	60	GINT1_IRQn = 9, /!< 9 GINT1 /
bogdanm	0:9b334a45a8ff	61	I2C1_IRQn = 10, /!< 10 I2C1 /
bogdanm	0:9b334a45a8ff	62	USART1_4_IRQn = 11, /!< 11 USART1_4 /
bogdanm	0:9b334a45a8ff	63	USART2_3_IRQn = 12, /!< 12 USART2_3 /
bogdanm	0:9b334a45a8ff	64	SCT0_1_IRQn = 13, /!< 13 SCT0_1 /
bogdanm	0:9b334a45a8ff	65	SSP1_IRQn = 14, /!< 14 SSP1 /
bogdanm	0:9b334a45a8ff	66	I2C0_IRQn = 15, /!< 15 I2C0 /
bogdanm	0:9b334a45a8ff	67	CT16B0_IRQn = 16, /!< 16 CT16B0 /
bogdanm	0:9b334a45a8ff	68	CT16B1_IRQn = 17, /!< 17 CT16B1 /
bogdanm	0:9b334a45a8ff	69	CT32B0_IRQn = 18, /!< 18 CT32B0 /
bogdanm	0:9b334a45a8ff	70	CT32B1_IRQn = 19, /!< 19 CT32B1 /
bogdanm	0:9b334a45a8ff	71	SSP0_IRQn = 20, /!< 20 SSP0 /
bogdanm	0:9b334a45a8ff	72	USART0_IRQn = 21, /!< 21 USART0 /
bogdanm	0:9b334a45a8ff	73	USB_IRQn = 22, /!< 22 USB /
bogdanm	0:9b334a45a8ff	74	USB_FIQ_IRQn = 23, /!< 23 USB_FIQ /
bogdanm	0:9b334a45a8ff	75	ADC_A_IRQn = 24, /!< 24 ADC_A /
bogdanm	0:9b334a45a8ff	76	RTC_IRQn = 25, /!< 25 RTC /
bogdanm	0:9b334a45a8ff	77	BOD_WDT_IRQn = 26, /!< 26 BOD_WDT /
bogdanm	0:9b334a45a8ff	78	FLASH_IRQn = 27, /!< 27 FLASH /
bogdanm	0:9b334a45a8ff	79	DMA_IRQn = 28, /!< 28 DMA /
bogdanm	0:9b334a45a8ff	80	ADC_B_IRQn = 29, /!< 29 ADC_B /
bogdanm	0:9b334a45a8ff	81	USBWAKEUP_IRQn = 30 /!< 30 USBWAKEUP /
bogdanm	0:9b334a45a8ff	82	} IRQn_Type;
bogdanm	0:9b334a45a8ff	83
bogdanm	0:9b334a45a8ff	84
bogdanm	0:9b334a45a8ff	85	/** @addtogroup Configuration_of_CMSIS
bogdanm	0:9b334a45a8ff	86	* @{
bogdanm	0:9b334a45a8ff	87	*/
bogdanm	0:9b334a45a8ff	88
bogdanm	0:9b334a45a8ff	89
bogdanm	0:9b334a45a8ff	90	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	91	/* ================ Processor and Core Peripheral Section ================ */
bogdanm	0:9b334a45a8ff	92	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	93
bogdanm	0:9b334a45a8ff	94	/* ----------------Configuration of the Cortex-M0PLUS Processor and Core Peripherals---------------- */
bogdanm	0:9b334a45a8ff	95	#define __CM0PLUS_REV 0x0000 /!< Cortex-M0PLUS Core Revision /
bogdanm	0:9b334a45a8ff	96	#define __MPU_PRESENT 0 /!< MPU present or not /
bogdanm	0:9b334a45a8ff	97	#define __NVIC_PRIO_BITS 2 /!< Number of Bits used for Priority Levels /
bogdanm	0:9b334a45a8ff	98	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
bogdanm	0:9b334a45a8ff	99	#define __VTOR_PRESENT 1 /!< Set to 1 if CPU supports Vector Table Offset Register /
bogdanm	0:9b334a45a8ff	100	/** @} / / End of group Configuration_of_CMSIS */
bogdanm	0:9b334a45a8ff	101
bogdanm	0:9b334a45a8ff	102	#include "core_cm0plus.h" /!< Cortex-M0PLUS processor and core peripherals /
bogdanm	0:9b334a45a8ff	103	#include "system_LPC11U6x.h" /!< LPC11U6x System /
bogdanm	0:9b334a45a8ff	104
bogdanm	0:9b334a45a8ff	105
bogdanm	0:9b334a45a8ff	106	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	107	/* ================ Device Specific Peripheral Section ================ */
bogdanm	0:9b334a45a8ff	108	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	109
bogdanm	0:9b334a45a8ff	110
bogdanm	0:9b334a45a8ff	111	/** @addtogroup Device_Peripheral_Registers
bogdanm	0:9b334a45a8ff	112	* @{
bogdanm	0:9b334a45a8ff	113	*/
bogdanm	0:9b334a45a8ff	114
bogdanm	0:9b334a45a8ff	115
bogdanm	0:9b334a45a8ff	116	/* ------------------- Start of section using anonymous unions ------------------ */
bogdanm	0:9b334a45a8ff	117	#if defined(__CC_ARM)
bogdanm	0:9b334a45a8ff	118	#pragma push
bogdanm	0:9b334a45a8ff	119	#pragma anon_unions
bogdanm	0:9b334a45a8ff	120	#elif defined(__ICCARM__)
bogdanm	0:9b334a45a8ff	121	#pragma language=extended
bogdanm	0:9b334a45a8ff	122	#elif defined(__GNUC__)
bogdanm	0:9b334a45a8ff	123	/* anonymous unions are enabled by default */
bogdanm	0:9b334a45a8ff	124	#elif defined(__TMS470__)
bogdanm	0:9b334a45a8ff	125	/* anonymous unions are enabled by default */
bogdanm	0:9b334a45a8ff	126	#elif defined(__TASKING__)
bogdanm	0:9b334a45a8ff	127	#pragma warning 586
bogdanm	0:9b334a45a8ff	128	#else
bogdanm	0:9b334a45a8ff	129	#warning Not supported compiler type
bogdanm	0:9b334a45a8ff	130	#endif
bogdanm	0:9b334a45a8ff	131
bogdanm	0:9b334a45a8ff	132
bogdanm	0:9b334a45a8ff	133
bogdanm	0:9b334a45a8ff	134	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	135	/* ================ I2C0 ================ */
bogdanm	0:9b334a45a8ff	136	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	137
bogdanm	0:9b334a45a8ff	138
bogdanm	0:9b334a45a8ff	139	/**
bogdanm	0:9b334a45a8ff	140	* @brief I2C-bus controller (I2C0)
bogdanm	0:9b334a45a8ff	141	*/
bogdanm	0:9b334a45a8ff	142
bogdanm	0:9b334a45a8ff	143	typedef struct { /!< I2C0 Structure /
bogdanm	0:9b334a45a8ff	144	__IO uint32_t CONSET; /*!< I2C Control Set Register. When a one is written to a bit of
bogdanm	0:9b334a45a8ff	145	this register, the corresponding bit in the I2C control register
bogdanm	0:9b334a45a8ff	146	is set. Writing a zero has no effect on the corresponding bit
bogdanm	0:9b334a45a8ff	147	in the I2C control register. */
bogdanm	0:9b334a45a8ff	148	__I uint32_t STAT; /*!< I2C Status Register. During I2C operation, this register provides
bogdanm	0:9b334a45a8ff	149	detailed status codes that allow software to determine the next
bogdanm	0:9b334a45a8ff	150	action needed. */
bogdanm	0:9b334a45a8ff	151	__IO uint32_t DAT; /*!< I2C Data Register. During master or slave transmit mode, data
bogdanm	0:9b334a45a8ff	152	to be transmitted is written to this register. During master
bogdanm	0:9b334a45a8ff	153	or slave receive mode, data that has been received may be read
bogdanm	0:9b334a45a8ff	154	from this register. */
bogdanm	0:9b334a45a8ff	155	__IO uint32_t ADR0; /*!< I2C Slave Address Register 0. Contains the 7-bit slave address
bogdanm	0:9b334a45a8ff	156	for operation of the I2C interface in slave mode, and is not
bogdanm	0:9b334a45a8ff	157	used in master mode. The least significant bit determines whether
bogdanm	0:9b334a45a8ff	158	a slave responds to the General Call address. */
bogdanm	0:9b334a45a8ff	159	__IO uint32_t SCLH; /*!< SCH Duty Cycle Register High Half Word. Determines the high
bogdanm	0:9b334a45a8ff	160	time of the I2C clock. */
bogdanm	0:9b334a45a8ff	161	__IO uint32_t SCLL; /*!< SCL Duty Cycle Register Low Half Word. Determines the low time
bogdanm	0:9b334a45a8ff	162	of the I2C clock. I2nSCLL and I2nSCLH together determine the
bogdanm	0:9b334a45a8ff	163	clock frequency generated by an I2C master and certain times
bogdanm	0:9b334a45a8ff	164	used in slave mode. */
bogdanm	0:9b334a45a8ff	165	__O uint32_t CONCLR; /*!< I2C Control Clear Register. When a one is written to a bit of
bogdanm	0:9b334a45a8ff	166	this register, the corresponding bit in the I2C control register
bogdanm	0:9b334a45a8ff	167	is cleared. Writing a zero has no effect on the corresponding
bogdanm	0:9b334a45a8ff	168	bit in the I2C control register. */
bogdanm	0:9b334a45a8ff	169	__IO uint32_t MMCTRL; /!< Monitor mode control register. /
bogdanm	0:9b334a45a8ff	170	__IO uint32_t ADR1; /*!< I2C Slave Address Register. Contains the 7-bit slave address
bogdanm	0:9b334a45a8ff	171	for operation of the I2C interface in slave mode, and is not
bogdanm	0:9b334a45a8ff	172	used in master mode. The least significant bit determines whether
bogdanm	0:9b334a45a8ff	173	a slave responds to the General Call address. */
bogdanm	0:9b334a45a8ff	174	__IO uint32_t ADR2; /*!< I2C Slave Address Register. Contains the 7-bit slave address
bogdanm	0:9b334a45a8ff	175	for operation of the I2C interface in slave mode, and is not
bogdanm	0:9b334a45a8ff	176	used in master mode. The least significant bit determines whether
bogdanm	0:9b334a45a8ff	177	a slave responds to the General Call address. */
bogdanm	0:9b334a45a8ff	178	__IO uint32_t ADR3; /*!< I2C Slave Address Register. Contains the 7-bit slave address
bogdanm	0:9b334a45a8ff	179	for operation of the I2C interface in slave mode, and is not
bogdanm	0:9b334a45a8ff	180	used in master mode. The least significant bit determines whether
bogdanm	0:9b334a45a8ff	181	a slave responds to the General Call address. */
bogdanm	0:9b334a45a8ff	182	__I uint32_t DATA_BUFFER; /*!< Data buffer register. The contents of the 8 MSBs of the I2DAT
bogdanm	0:9b334a45a8ff	183	shift register will be transferred to the DATA_BUFFER automatically
bogdanm	0:9b334a45a8ff	184	after every nine bits (8 bits of data plus ACK or NACK) has
bogdanm	0:9b334a45a8ff	185	been received on the bus. */
bogdanm	0:9b334a45a8ff	186	__IO uint32_t MASK0; /*!< I2C Slave address mask register. This mask register is associated
bogdanm	0:9b334a45a8ff	187	with I2ADR0 to determine an address match. The mask register
bogdanm	0:9b334a45a8ff	188	has no effect when comparing to the General Call address (0000000). */
bogdanm	0:9b334a45a8ff	189	__IO uint32_t MASK1; /*!< I2C Slave address mask register. This mask register is associated
bogdanm	0:9b334a45a8ff	190	with I2ADR0 to determine an address match. The mask register
bogdanm	0:9b334a45a8ff	191	has no effect when comparing to the General Call address (0000000). */
bogdanm	0:9b334a45a8ff	192	__IO uint32_t MASK2; /*!< I2C Slave address mask register. This mask register is associated
bogdanm	0:9b334a45a8ff	193	with I2ADR0 to determine an address match. The mask register
bogdanm	0:9b334a45a8ff	194	has no effect when comparing to the General Call address (0000000). */
bogdanm	0:9b334a45a8ff	195	__IO uint32_t MASK3; /*!< I2C Slave address mask register. This mask register is associated
bogdanm	0:9b334a45a8ff	196	with I2ADR0 to determine an address match. The mask register
bogdanm	0:9b334a45a8ff	197	has no effect when comparing to the General Call address (0000000). */
bogdanm	0:9b334a45a8ff	198	} LPC_I2C0_Type;
bogdanm	0:9b334a45a8ff	199
bogdanm	0:9b334a45a8ff	200
bogdanm	0:9b334a45a8ff	201	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	202	/* ================ WWDT ================ */
bogdanm	0:9b334a45a8ff	203	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	204
bogdanm	0:9b334a45a8ff	205
bogdanm	0:9b334a45a8ff	206	/**
bogdanm	0:9b334a45a8ff	207	* @brief Windowed Watchdog Timer (WWDT) (WWDT)
bogdanm	0:9b334a45a8ff	208	*/
bogdanm	0:9b334a45a8ff	209
bogdanm	0:9b334a45a8ff	210	typedef struct { /!< WWDT Structure /
bogdanm	0:9b334a45a8ff	211	__IO uint32_t MOD; /*!< Watchdog mode register. This register contains the basic mode
bogdanm	0:9b334a45a8ff	212	and status of the Watchdog Timer. */
bogdanm	0:9b334a45a8ff	213	__IO uint32_t TC; /*!< Watchdog timer constant register. This 24-bit register determines
bogdanm	0:9b334a45a8ff	214	the time-out value. */
bogdanm	0:9b334a45a8ff	215	__O uint32_t FEED; /*!< Watchdog feed sequence register. Writing 0xAA followed by 0x55
bogdanm	0:9b334a45a8ff	216	to this register reloads the Watchdog timer with the value contained
bogdanm	0:9b334a45a8ff	217	in WDTC. */
bogdanm	0:9b334a45a8ff	218	__I uint32_t TV; /*!< Watchdog timer value register. This 24-bit register reads out
bogdanm	0:9b334a45a8ff	219	the current value of the Watchdog timer. */
bogdanm	0:9b334a45a8ff	220	__IO uint32_t CLKSEL; /!< Watchdog clock select register. /
bogdanm	0:9b334a45a8ff	221	__IO uint32_t WARNINT; /!< Watchdog Warning Interrupt compare value. /
bogdanm	0:9b334a45a8ff	222	__IO uint32_t WINDOW; /!< Watchdog Window compare value. /
bogdanm	0:9b334a45a8ff	223	} LPC_WWDT_Type;
bogdanm	0:9b334a45a8ff	224
bogdanm	0:9b334a45a8ff	225
bogdanm	0:9b334a45a8ff	226	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	227	/* ================ USART0 ================ */
bogdanm	0:9b334a45a8ff	228	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	229
bogdanm	0:9b334a45a8ff	230
bogdanm	0:9b334a45a8ff	231	/**
bogdanm	0:9b334a45a8ff	232	* @brief USART0 (USART0)
bogdanm	0:9b334a45a8ff	233	*/
bogdanm	0:9b334a45a8ff	234
bogdanm	0:9b334a45a8ff	235	typedef struct { /!< USART0 Structure /
bogdanm	0:9b334a45a8ff	236
bogdanm	0:9b334a45a8ff	237	union {
bogdanm	0:9b334a45a8ff	238	__IO uint32_t DLL; /*!< Divisor Latch LSB. Least significant byte of the baud rate divisor
bogdanm	0:9b334a45a8ff	239	value. The full divisor is used to generate a baud rate from
bogdanm	0:9b334a45a8ff	240	the fractional rate divider. (DLAB=1) */
bogdanm	0:9b334a45a8ff	241	__O uint32_t THR; /*!< Transmit Holding Register. The next character to be transmitted
bogdanm	0:9b334a45a8ff	242	is written here. (DLAB=0) */
bogdanm	0:9b334a45a8ff	243	__I uint32_t RBR; /*!< Receiver Buffer Register. Contains the next received character
bogdanm	0:9b334a45a8ff	244	to be read. (DLAB=0) */
bogdanm	0:9b334a45a8ff	245	};
bogdanm	0:9b334a45a8ff	246
bogdanm	0:9b334a45a8ff	247	union {
bogdanm	0:9b334a45a8ff	248	__IO uint32_t IER; /*!< Interrupt Enable Register. Contains individual interrupt enable
bogdanm	0:9b334a45a8ff	249	bits for the 7 potential USART interrupts. (DLAB=0) */
bogdanm	0:9b334a45a8ff	250	__IO uint32_t DLM; /*!< Divisor Latch MSB. Most significant byte of the baud rate divisor
bogdanm	0:9b334a45a8ff	251	value. The full divisor is used to generate a baud rate from
bogdanm	0:9b334a45a8ff	252	the fractional rate divider. (DLAB=1) */
bogdanm	0:9b334a45a8ff	253	};
bogdanm	0:9b334a45a8ff	254
bogdanm	0:9b334a45a8ff	255	union {
bogdanm	0:9b334a45a8ff	256	__O uint32_t FCR; /!< FIFO Control Register. Controls USART FIFO usage and modes. /
bogdanm	0:9b334a45a8ff	257	__I uint32_t IIR; /!< Interrupt ID Register. Identifies which interrupt(s) are pending. /
bogdanm	0:9b334a45a8ff	258	};
bogdanm	0:9b334a45a8ff	259	__IO uint32_t LCR; /*!< Line Control Register. Contains controls for frame formatting
bogdanm	0:9b334a45a8ff	260	and break generation. */
bogdanm	0:9b334a45a8ff	261	__IO uint32_t MCR; /!< Modem Control Register. /
bogdanm	0:9b334a45a8ff	262	__I uint32_t LSR; /*!< Line Status Register. Contains flags for transmit and receive
bogdanm	0:9b334a45a8ff	263	status, including line errors. */
bogdanm	0:9b334a45a8ff	264	__I uint32_t MSR; /!< Modem Status Register. /
bogdanm	0:9b334a45a8ff	265	__IO uint32_t SCR; /!< Scratch Pad Register. Eight-bit temporary storage for software. /
bogdanm	0:9b334a45a8ff	266	__IO uint32_t ACR; /*!< Auto-baud Control Register. Contains controls for the auto-baud
bogdanm	0:9b334a45a8ff	267	feature. */
bogdanm	0:9b334a45a8ff	268	__IO uint32_t ICR; /*!< IrDA Control Register. Enables and configures the IrDA (remote
bogdanm	0:9b334a45a8ff	269	control) mode. */
bogdanm	0:9b334a45a8ff	270	__IO uint32_t FDR; /*!< Fractional Divider Register. Generates a clock input for the
bogdanm	0:9b334a45a8ff	271	baud rate divider. */
bogdanm	0:9b334a45a8ff	272	__IO uint32_t OSR; /*!< Oversampling Register. Controls the degree of oversampling during
bogdanm	0:9b334a45a8ff	273	each bit time. */
bogdanm	0:9b334a45a8ff	274	__IO uint32_t TER; /*!< Transmit Enable Register. Turns off USART transmitter for use
bogdanm	0:9b334a45a8ff	275	with software flow control. */
bogdanm	0:9b334a45a8ff	276	__I uint32_t RESERVED0[3];
bogdanm	0:9b334a45a8ff	277	__IO uint32_t HDEN; /!< Half duplex enable register. /
bogdanm	0:9b334a45a8ff	278	__I uint32_t RESERVED1;
bogdanm	0:9b334a45a8ff	279	__IO uint32_t SCICTRL; /*!< Smart Card Interface Control register. Enables and configures
bogdanm	0:9b334a45a8ff	280	the Smart Card Interface feature. */
bogdanm	0:9b334a45a8ff	281	__IO uint32_t RS485CTRL; /*!< RS-485/EIA-485 Control. Contains controls to configure various
bogdanm	0:9b334a45a8ff	282	aspects of RS-485/EIA-485 modes. */
bogdanm	0:9b334a45a8ff	283	__IO uint32_t RS485ADRMATCH; /*!< RS-485/EIA-485 address match. Contains the address match value
bogdanm	0:9b334a45a8ff	284	for RS-485/EIA-485 mode. */
bogdanm	0:9b334a45a8ff	285	__IO uint32_t RS485DLY; /!< RS-485/EIA-485 direction control delay. /
bogdanm	0:9b334a45a8ff	286	__IO uint32_t SYNCCTRL; /!< Synchronous mode control register. /
bogdanm	0:9b334a45a8ff	287	} LPC_USART0_Type;
bogdanm	0:9b334a45a8ff	288
bogdanm	0:9b334a45a8ff	289
bogdanm	0:9b334a45a8ff	290	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	291	/* ================ CT16B0 ================ */
bogdanm	0:9b334a45a8ff	292	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	293
bogdanm	0:9b334a45a8ff	294
bogdanm	0:9b334a45a8ff	295	/**
bogdanm	0:9b334a45a8ff	296	* @brief 16-bit counter/timers CT16B0 (CT16B0)
bogdanm	0:9b334a45a8ff	297	*/
bogdanm	0:9b334a45a8ff	298
bogdanm	0:9b334a45a8ff	299	typedef struct { /!< CT16B0 Structure /
bogdanm	0:9b334a45a8ff	300	__IO uint32_t IR; /*!< Interrupt Register. The IR can be written to clear interrupts.
bogdanm	0:9b334a45a8ff	301	The IR can be read to identify which of eight possible interrupt
bogdanm	0:9b334a45a8ff	302	sources are pending. */
bogdanm	0:9b334a45a8ff	303	__IO uint32_t TCR; /*!< Timer Control Register. The TCR is used to control the Timer
bogdanm	0:9b334a45a8ff	304	Counter functions. The Timer Counter can be disabled or reset
bogdanm	0:9b334a45a8ff	305	through the TCR. */
bogdanm	0:9b334a45a8ff	306	__IO uint32_t TC; /*!< Timer Counter. The 16-bit TC is incremented every PR+1 cycles
bogdanm	0:9b334a45a8ff	307	of PCLK. The TC is controlled through the TCR. */
bogdanm	0:9b334a45a8ff	308	__IO uint32_t PR; /*!< Prescale Register. When the Prescale Counter (below) is equal
bogdanm	0:9b334a45a8ff	309	to this value, the next clock increments the TC and clears the
bogdanm	0:9b334a45a8ff	310	PC. */
bogdanm	0:9b334a45a8ff	311	__IO uint32_t PC; /*!< Prescale Counter. The 16-bit PC is a counter which is incremented
bogdanm	0:9b334a45a8ff	312	to the value stored in PR. When the value in PR is reached,
bogdanm	0:9b334a45a8ff	313	the TC is incremented and the PC is cleared. The PC is observable
bogdanm	0:9b334a45a8ff	314	and controllable through the bus interface. */
bogdanm	0:9b334a45a8ff	315	__IO uint32_t MCR; /*!< Match Control Register. The MCR is used to control if an interrupt
bogdanm	0:9b334a45a8ff	316	is generated and if the TC is reset when a Match occurs. */
bogdanm	0:9b334a45a8ff	317	__IO uint32_t MR0; /*!< Match Register. MR can be enabled through the MCR to reset the
bogdanm	0:9b334a45a8ff	318	TC, stop both the TC and PC, and/or generate an interrupt every
bogdanm	0:9b334a45a8ff	319	time MR0 matches the TC. */
bogdanm	0:9b334a45a8ff	320	__IO uint32_t MR1; /*!< Match Register. MR can be enabled through the MCR to reset the
bogdanm	0:9b334a45a8ff	321	TC, stop both the TC and PC, and/or generate an interrupt every
bogdanm	0:9b334a45a8ff	322	time MR0 matches the TC. */
bogdanm	0:9b334a45a8ff	323	__IO uint32_t MR2; /*!< Match Register. MR can be enabled through the MCR to reset the
bogdanm	0:9b334a45a8ff	324	TC, stop both the TC and PC, and/or generate an interrupt every
bogdanm	0:9b334a45a8ff	325	time MR0 matches the TC. */
bogdanm	0:9b334a45a8ff	326	__IO uint32_t MR3; /*!< Match Register. MR can be enabled through the MCR to reset the
bogdanm	0:9b334a45a8ff	327	TC, stop both the TC and PC, and/or generate an interrupt every
bogdanm	0:9b334a45a8ff	328	time MR0 matches the TC. */
bogdanm	0:9b334a45a8ff	329	__IO uint32_t CCR; /*!< Capture Control Register. The CCR controls which edges of the
bogdanm	0:9b334a45a8ff	330	capture inputs are used to load the Capture Registers and whether
bogdanm	0:9b334a45a8ff	331	or not an interrupt is generated when a capture takes place. */
bogdanm	0:9b334a45a8ff	332	__I uint32_t CR0; /*!< Capture Register. CR is loaded with the value of TC when there
bogdanm	0:9b334a45a8ff	333	is an event on the CAP input. */
bogdanm	0:9b334a45a8ff	334	__I uint32_t CR1; /*!< Capture Register. CR is loaded with the value of TC when there
bogdanm	0:9b334a45a8ff	335	is an event on the CAP input. */
bogdanm	0:9b334a45a8ff	336	__I uint32_t CR2; /*!< Capture Register. CR is loaded with the value of TC when there
bogdanm	0:9b334a45a8ff	337	is an event on the CAP input. */
bogdanm	0:9b334a45a8ff	338	__I uint32_t RESERVED0;
bogdanm	0:9b334a45a8ff	339	__IO uint32_t EMR; /*!< External Match Register. The EMR controls the match function
bogdanm	0:9b334a45a8ff	340	and the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
bogdanm	0:9b334a45a8ff	341	__I uint32_t RESERVED1[12];
bogdanm	0:9b334a45a8ff	342	__IO uint32_t CTCR; /*!< Count Control Register. The CTCR selects between Timer and Counter
bogdanm	0:9b334a45a8ff	343	mode, and in Counter mode selects the signal and edge(s) for
bogdanm	0:9b334a45a8ff	344	counting. */
bogdanm	0:9b334a45a8ff	345	__IO uint32_t PWMC; /*!< PWM Control Register. The PWMCON enables PWM mode for the external
bogdanm	0:9b334a45a8ff	346	match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
bogdanm	0:9b334a45a8ff	347	} LPC_CT16B0_Type;
bogdanm	0:9b334a45a8ff	348
bogdanm	0:9b334a45a8ff	349
bogdanm	0:9b334a45a8ff	350	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	351	/* ================ CT32B0 ================ */
bogdanm	0:9b334a45a8ff	352	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	353
bogdanm	0:9b334a45a8ff	354
bogdanm	0:9b334a45a8ff	355	/**
bogdanm	0:9b334a45a8ff	356	* @brief 32-bit counter/timers CT32B0 (CT32B0)
bogdanm	0:9b334a45a8ff	357	*/
bogdanm	0:9b334a45a8ff	358
bogdanm	0:9b334a45a8ff	359	typedef struct { /!< CT32B0 Structure /
bogdanm	0:9b334a45a8ff	360	__IO uint32_t IR; /*!< Interrupt Register. The IR can be written to clear interrupts.
bogdanm	0:9b334a45a8ff	361	The IR can be read to identify which of eight possible interrupt
bogdanm	0:9b334a45a8ff	362	sources are pending. */
bogdanm	0:9b334a45a8ff	363	__IO uint32_t TCR; /*!< Timer Control Register. The TCR is used to control the Timer
bogdanm	0:9b334a45a8ff	364	Counter functions. The Timer Counter can be disabled or reset
bogdanm	0:9b334a45a8ff	365	through the TCR. */
bogdanm	0:9b334a45a8ff	366	__IO uint32_t TC; /*!< Timer Counter. The 32-bit TC is incremented every PR+1 cycles
bogdanm	0:9b334a45a8ff	367	of PCLK. The TC is controlled through the TCR. */
bogdanm	0:9b334a45a8ff	368	__IO uint32_t PR; /*!< Prescale Register. When the Prescale Counter (below) is equal
bogdanm	0:9b334a45a8ff	369	to this value, the next clock increments the TC and clears the
bogdanm	0:9b334a45a8ff	370	PC. */
bogdanm	0:9b334a45a8ff	371	__IO uint32_t PC; /*!< Prescale Counter. The 32-bit PC is a counter which is incremented
bogdanm	0:9b334a45a8ff	372	to the value stored in PR. When the value in PR is reached,
bogdanm	0:9b334a45a8ff	373	the TC is incremented and the PC is cleared. The PC is observable
bogdanm	0:9b334a45a8ff	374	and controllable through the bus interface. */
bogdanm	0:9b334a45a8ff	375	__IO uint32_t MCR; /*!< Match Control Register. The MCR is used to control if an interrupt
bogdanm	0:9b334a45a8ff	376	is generated and if the TC is reset when a Match occurs. */
bogdanm	0:9b334a45a8ff	377	__IO uint32_t MR0; /*!< Match Register. MR can be enabled through the MCR to reset the
bogdanm	0:9b334a45a8ff	378	TC, stop both the TC and PC, and/or generate an interrupt every
bogdanm	0:9b334a45a8ff	379	time MR0 matches the TC. */
bogdanm	0:9b334a45a8ff	380	__IO uint32_t MR1; /*!< Match Register. MR can be enabled through the MCR to reset the
bogdanm	0:9b334a45a8ff	381	TC, stop both the TC and PC, and/or generate an interrupt every
bogdanm	0:9b334a45a8ff	382	time MR0 matches the TC. */
bogdanm	0:9b334a45a8ff	383	__IO uint32_t MR2; /*!< Match Register. MR can be enabled through the MCR to reset the
bogdanm	0:9b334a45a8ff	384	TC, stop both the TC and PC, and/or generate an interrupt every
bogdanm	0:9b334a45a8ff	385	time MR0 matches the TC. */
bogdanm	0:9b334a45a8ff	386	__IO uint32_t MR3; /*!< Match Register. MR can be enabled through the MCR to reset the
bogdanm	0:9b334a45a8ff	387	TC, stop both the TC and PC, and/or generate an interrupt every
bogdanm	0:9b334a45a8ff	388	time MR0 matches the TC. */
bogdanm	0:9b334a45a8ff	389	__IO uint32_t CCR; /*!< Capture Control Register. The CCR controls which edges of the
bogdanm	0:9b334a45a8ff	390	capture inputs are used to load the Capture Registers and whether
bogdanm	0:9b334a45a8ff	391	or not an interrupt is generated when a capture takes place. */
bogdanm	0:9b334a45a8ff	392	__I uint32_t CR0; /*!< Capture Register. CR is loaded with the value of TC when there
bogdanm	0:9b334a45a8ff	393	is an event on the CAP input. */
bogdanm	0:9b334a45a8ff	394	__I uint32_t CR1; /*!< Capture Register. CR is loaded with the value of TC when there
bogdanm	0:9b334a45a8ff	395	is an event on the CAP input. */
bogdanm	0:9b334a45a8ff	396	__I uint32_t CR2; /*!< Capture Register. CR is loaded with the value of TC when there
bogdanm	0:9b334a45a8ff	397	is an event on the CAP input. */
bogdanm	0:9b334a45a8ff	398	__I uint32_t RESERVED0;
bogdanm	0:9b334a45a8ff	399	__IO uint32_t EMR; /*!< External Match Register. The EMR controls the match function
bogdanm	0:9b334a45a8ff	400	and the external match pins CT32Bn_MAT[3:0]. */
bogdanm	0:9b334a45a8ff	401	__I uint32_t RESERVED1[12];
bogdanm	0:9b334a45a8ff	402	__IO uint32_t CTCR; /*!< Count Control Register. The CTCR selects between Timer and Counter
bogdanm	0:9b334a45a8ff	403	mode, and in Counter mode selects the signal and edge(s) for
bogdanm	0:9b334a45a8ff	404	counting. */
bogdanm	0:9b334a45a8ff	405	__IO uint32_t PWMC; /*!< PWM Control Register. The PWMCON enables PWM mode for the external
bogdanm	0:9b334a45a8ff	406	match pins CT32Bn_MAT[3:0]. */
bogdanm	0:9b334a45a8ff	407	} LPC_CT32B0_Type;
bogdanm	0:9b334a45a8ff	408
bogdanm	0:9b334a45a8ff	409
bogdanm	0:9b334a45a8ff	410	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	411	/* ================ ADC ================ */
bogdanm	0:9b334a45a8ff	412	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	413
bogdanm	0:9b334a45a8ff	414
bogdanm	0:9b334a45a8ff	415	/**
bogdanm	0:9b334a45a8ff	416	* @brief Product name title=Kylin UM Chapter title=Kylin12-bit Analog-to-Digital Converter (ADC) Modification date=5/13/2013 Major revision=0 Minor revision=1 (ADC)
bogdanm	0:9b334a45a8ff	417	*/
bogdanm	0:9b334a45a8ff	418
bogdanm	0:9b334a45a8ff	419	typedef struct { /!< ADC Structure /
bogdanm	0:9b334a45a8ff	420	__IO uint32_t CTRL; /*!< A/D Control Register. Contains the clock divide value, enable
bogdanm	0:9b334a45a8ff	421	bits for each sequence and the A/D power-down bit. */
bogdanm	0:9b334a45a8ff	422	__I uint32_t RESERVED0;
bogdanm	0:9b334a45a8ff	423	__IO uint32_t SEQA_CTRL; /*!< A/D Conversion Sequence-A control Register: Controls triggering
bogdanm	0:9b334a45a8ff	424	and channel selection for conversion sequence-A. Also specifies
bogdanm	0:9b334a45a8ff	425	interrupt mode for sequence-A. */
bogdanm	0:9b334a45a8ff	426	__IO uint32_t SEQB_CTRL; /*!< A/D Conversion Sequence-B Control Register: Controls triggering
bogdanm	0:9b334a45a8ff	427	and channel selection for conversion sequence-B. Also specifies
bogdanm	0:9b334a45a8ff	428	interrupt mode for sequence-B. */
bogdanm	0:9b334a45a8ff	429	__IO uint32_t SEQA_GDAT; /*!< A/D Sequence-A Global Data Register. This register contains
bogdanm	0:9b334a45a8ff	430	the result of the most recent A/D conversion performed under
bogdanm	0:9b334a45a8ff	431	sequence-A */
bogdanm	0:9b334a45a8ff	432	__IO uint32_t SEQB_GDAT; /*!< A/D Sequence-B Global Data Register. This register contains
bogdanm	0:9b334a45a8ff	433	the result of the most recent A/D conversion performed under
bogdanm	0:9b334a45a8ff	434	sequence-B */
bogdanm	0:9b334a45a8ff	435	__I uint32_t RESERVED1[2];
bogdanm	0:9b334a45a8ff	436	__I uint32_t DAT[12]; /*!< A/D Channel 0 Data Register. This register contains the result
bogdanm	0:9b334a45a8ff	437	of the most recent conversion completed on channel 0. */
bogdanm	0:9b334a45a8ff	438	__IO uint32_t THR0_LOW; /*!< A/D Low Compare Threshold Register 0 : Contains the lower threshold
bogdanm	0:9b334a45a8ff	439	level for automatic threshold comparison for any channels linked
bogdanm	0:9b334a45a8ff	440	to threshold pair 0. */
bogdanm	0:9b334a45a8ff	441	__IO uint32_t THR1_LOW; /*!< A/D Low Compare Threshold Register 1: Contains the lower threshold
bogdanm	0:9b334a45a8ff	442	level for automatic threshold comparison for any channels linked
bogdanm	0:9b334a45a8ff	443	to threshold pair 1. */
bogdanm	0:9b334a45a8ff	444	__IO uint32_t THR0_HIGH; /*!< A/D High Compare Threshold Register 0: Contains the upper threshold
bogdanm	0:9b334a45a8ff	445	level for automatic threshold comparison for any channels linked
bogdanm	0:9b334a45a8ff	446	to threshold pair 0. */
bogdanm	0:9b334a45a8ff	447	__IO uint32_t THR1_HIGH; /*!< A/D High Compare Threshold Register 1: Contains the upper threshold
bogdanm	0:9b334a45a8ff	448	level for automatic threshold comparison for any channels linked
bogdanm	0:9b334a45a8ff	449	to threshold pair 1. */
bogdanm	0:9b334a45a8ff	450	__I uint32_t CHAN_THRSEL; /*!< A/D Channel-Threshold Select Register. Specifies which set of
bogdanm	0:9b334a45a8ff	451	threshold compare registers are to be used for each channel */
bogdanm	0:9b334a45a8ff	452	__IO uint32_t INTEN; /*!< A/D Interrupt Enable Register. This register contains enable
bogdanm	0:9b334a45a8ff	453	bits that enable the sequence-A, sequence-B, threshold compare
bogdanm	0:9b334a45a8ff	454	and data overrun interrupts to be generated. */
bogdanm	0:9b334a45a8ff	455	__I uint32_t FLAGS; /*!< A/D Flags Register. Contains the four interrupt request flags
bogdanm	0:9b334a45a8ff	456	and the individual component overrun and threshold-compare flags.
bogdanm	0:9b334a45a8ff	457	(The overrun bits replicate information stored in the result
bogdanm	0:9b334a45a8ff	458	registers). */
bogdanm	0:9b334a45a8ff	459	__IO uint32_t TRM; /!< ADC trim register. /
bogdanm	0:9b334a45a8ff	460	} LPC_ADC_Type;
bogdanm	0:9b334a45a8ff	461
bogdanm	0:9b334a45a8ff	462
bogdanm	0:9b334a45a8ff	463	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	464	/* ================ RTC ================ */
bogdanm	0:9b334a45a8ff	465	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	466
bogdanm	0:9b334a45a8ff	467
bogdanm	0:9b334a45a8ff	468	/**
bogdanm	0:9b334a45a8ff	469	* @brief Real-Time Clock (RTC) (RTC)
bogdanm	0:9b334a45a8ff	470	*/
bogdanm	0:9b334a45a8ff	471
bogdanm	0:9b334a45a8ff	472	typedef struct { /!< RTC Structure /
bogdanm	0:9b334a45a8ff	473	__IO uint32_t CTRL; /!< RTC control register /
bogdanm	0:9b334a45a8ff	474	__IO uint32_t MATCH; /!< RTC match register /
bogdanm	0:9b334a45a8ff	475	__IO uint32_t COUNT; /!< RTC counter register /
bogdanm	0:9b334a45a8ff	476	__IO uint32_t WAKE; /!< RTC high-resolution/wake-up timer control register /
bogdanm	0:9b334a45a8ff	477	} LPC_RTC_Type;
bogdanm	0:9b334a45a8ff	478
bogdanm	0:9b334a45a8ff	479
bogdanm	0:9b334a45a8ff	480	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	481	/* ================ DMATRIGMUX ================ */
bogdanm	0:9b334a45a8ff	482	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	483
bogdanm	0:9b334a45a8ff	484
bogdanm	0:9b334a45a8ff	485	/**
bogdanm	0:9b334a45a8ff	486	* @brief Product name title=Kylin UM Chapter title=KylinDMA controller Modification date=5/13/2013 Major revision=0 Minor revision=1 (DMATRIGMUX)
bogdanm	0:9b334a45a8ff	487	*/
bogdanm	0:9b334a45a8ff	488
bogdanm	0:9b334a45a8ff	489	typedef struct { /!< DMATRIGMUX Structure /
bogdanm	0:9b334a45a8ff	490	__IO uint32_t DMA_ITRIG_PINMUX[16]; /!< Trigger input select register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	491	} LPC_DMATRIGMUX_Type;
bogdanm	0:9b334a45a8ff	492
bogdanm	0:9b334a45a8ff	493
bogdanm	0:9b334a45a8ff	494	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	495	/* ================ PMU ================ */
bogdanm	0:9b334a45a8ff	496	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	497
bogdanm	0:9b334a45a8ff	498
bogdanm	0:9b334a45a8ff	499	/**
bogdanm	0:9b334a45a8ff	500	* @brief Product name title=Kylin UM Chapter title=KylinPower Management Unit (PMU) Modification date=5/13/2013 Major revision=0 Minor revision=1 (PMU)
bogdanm	0:9b334a45a8ff	501	*/
bogdanm	0:9b334a45a8ff	502
bogdanm	0:9b334a45a8ff	503	typedef struct { /!< PMU Structure /
bogdanm	0:9b334a45a8ff	504	__IO uint32_t PCON; /!< Power control register /
bogdanm	0:9b334a45a8ff	505	__IO uint32_t GPREG0; /!< General purpose register 0 /
bogdanm	0:9b334a45a8ff	506	__IO uint32_t GPREG1; /!< General purpose register 0 /
bogdanm	0:9b334a45a8ff	507	__IO uint32_t GPREG2; /!< General purpose register 0 /
bogdanm	0:9b334a45a8ff	508	__IO uint32_t GPREG3; /!< General purpose register 0 /
bogdanm	0:9b334a45a8ff	509	__IO uint32_t DPDCTRL; /!< Deep power down control register /
bogdanm	0:9b334a45a8ff	510	} LPC_PMU_Type;
bogdanm	0:9b334a45a8ff	511
bogdanm	0:9b334a45a8ff	512
bogdanm	0:9b334a45a8ff	513	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	514	/* ================ FLASHCTRL ================ */
bogdanm	0:9b334a45a8ff	515	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	516
bogdanm	0:9b334a45a8ff	517
bogdanm	0:9b334a45a8ff	518	/**
bogdanm	0:9b334a45a8ff	519	* @brief Flash controller (FLASHCTRL)
bogdanm	0:9b334a45a8ff	520	*/
bogdanm	0:9b334a45a8ff	521
bogdanm	0:9b334a45a8ff	522	typedef struct { /!< FLASHCTRL Structure /
bogdanm	0:9b334a45a8ff	523	__I uint32_t RESERVED0[4];
bogdanm	0:9b334a45a8ff	524	__IO uint32_t FLASHCFG; /!< Flash configuration register /
bogdanm	0:9b334a45a8ff	525	__I uint32_t RESERVED1[3];
bogdanm	0:9b334a45a8ff	526	__IO uint32_t FMSSTART; /!< Signature start address register /
bogdanm	0:9b334a45a8ff	527	__IO uint32_t FMSSTOP; /!< Signature stop-address register /
bogdanm	0:9b334a45a8ff	528	__I uint32_t RESERVED2;
bogdanm	0:9b334a45a8ff	529	__I uint32_t FMSW0; /!< Signature Word /
bogdanm	0:9b334a45a8ff	530	} LPC_FLASHCTRL_Type;
bogdanm	0:9b334a45a8ff	531
bogdanm	0:9b334a45a8ff	532
bogdanm	0:9b334a45a8ff	533	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	534	/* ================ SSP0 ================ */
bogdanm	0:9b334a45a8ff	535	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	536
bogdanm	0:9b334a45a8ff	537
bogdanm	0:9b334a45a8ff	538	/**
bogdanm	0:9b334a45a8ff	539	* @brief SSP/SPI (SSP0)
bogdanm	0:9b334a45a8ff	540	*/
bogdanm	0:9b334a45a8ff	541
bogdanm	0:9b334a45a8ff	542	typedef struct { /!< SSP0 Structure /
bogdanm	0:9b334a45a8ff	543	__IO uint32_t CR0; /*!< Control Register 0. Selects the serial clock rate, bus type,
bogdanm	0:9b334a45a8ff	544	and data size. */
bogdanm	0:9b334a45a8ff	545	__IO uint32_t CR1; /!< Control Register 1. Selects master/slave and other modes. /
bogdanm	0:9b334a45a8ff	546	__IO uint32_t DR; /*!< Data Register. Writes fill the transmit FIFO, and reads empty
bogdanm	0:9b334a45a8ff	547	the receive FIFO. */
bogdanm	0:9b334a45a8ff	548	__I uint32_t SR; /!< Status Register /
bogdanm	0:9b334a45a8ff	549	__IO uint32_t CPSR; /!< Clock Prescale Register /
bogdanm	0:9b334a45a8ff	550	__IO uint32_t IMSC; /!< Interrupt Mask Set and Clear Register /
bogdanm	0:9b334a45a8ff	551	__I uint32_t RIS; /!< Raw Interrupt Status Register /
bogdanm	0:9b334a45a8ff	552	__I uint32_t MIS; /!< Masked Interrupt Status Register /
bogdanm	0:9b334a45a8ff	553	__O uint32_t ICR; /!< SSPICR Interrupt Clear Register /
bogdanm	0:9b334a45a8ff	554	} LPC_SSP0_Type;
bogdanm	0:9b334a45a8ff	555
bogdanm	0:9b334a45a8ff	556
bogdanm	0:9b334a45a8ff	557	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	558	/* ================ IOCON ================ */
bogdanm	0:9b334a45a8ff	559	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	560
bogdanm	0:9b334a45a8ff	561
bogdanm	0:9b334a45a8ff	562	/**
bogdanm	0:9b334a45a8ff	563	* @brief Product name title=Kylin UM Chapter title=KylinI/O control (IOCON) Modification date=5/13/2013 Major revision=0 Minor revision=1 (IOCON)
bogdanm	0:9b334a45a8ff	564	*/
bogdanm	0:9b334a45a8ff	565
bogdanm	0:9b334a45a8ff	566	typedef struct { /!< IOCON Structure /
bogdanm	0:9b334a45a8ff	567	__IO uint32_t PIO0_0; /!< I/O configuration for port PIO0 /
bogdanm	0:9b334a45a8ff	568	__IO uint32_t PIO0_1; /!< I/O configuration for port PIO0 /
bogdanm	0:9b334a45a8ff	569	__IO uint32_t PIO0_2; /!< I/O configuration for port PIO0 /
bogdanm	0:9b334a45a8ff	570	__IO uint32_t PIO0_3; /!< I/O configuration for port PIO0 /
bogdanm	0:9b334a45a8ff	571	__IO uint32_t PIO0_4; /!< I/O configuration for port PIO0 /
bogdanm	0:9b334a45a8ff	572	__IO uint32_t PIO0_5; /!< I/O configuration for port PIO0 /
bogdanm	0:9b334a45a8ff	573	__IO uint32_t PIO0_6; /!< I/O configuration for port PIO0 /
bogdanm	0:9b334a45a8ff	574	__IO uint32_t PIO0_7; /!< I/O configuration for port PIO0 /
bogdanm	0:9b334a45a8ff	575	__IO uint32_t PIO0_8; /!< I/O configuration for port PIO0 /
bogdanm	0:9b334a45a8ff	576	__IO uint32_t PIO0_9; /!< I/O configuration for port PIO0 /
bogdanm	0:9b334a45a8ff	577	__IO uint32_t PIO0_10; /!< I/O configuration for port PIO0 /
bogdanm	0:9b334a45a8ff	578	__IO uint32_t PIO0_11; /!< I/O configuration for port PIO0 /
bogdanm	0:9b334a45a8ff	579	__IO uint32_t PIO0_12; /!< I/O configuration for port PIO0 /
bogdanm	0:9b334a45a8ff	580	__IO uint32_t PIO0_13; /!< I/O configuration for port PIO0 /
bogdanm	0:9b334a45a8ff	581	__IO uint32_t PIO0_14; /!< I/O configuration for port PIO0 /
bogdanm	0:9b334a45a8ff	582	__IO uint32_t PIO0_15; /!< I/O configuration for port PIO0 /
bogdanm	0:9b334a45a8ff	583	__IO uint32_t PIO0_16; /!< I/O configuration for port PIO0 /
bogdanm	0:9b334a45a8ff	584	__IO uint32_t PIO0_17; /!< I/O configuration for port PIO0 /
bogdanm	0:9b334a45a8ff	585	__IO uint32_t PIO0_18; /!< I/O configuration for port PIO0 /
bogdanm	0:9b334a45a8ff	586	__IO uint32_t PIO0_19; /!< I/O configuration for port PIO0 /
bogdanm	0:9b334a45a8ff	587	__IO uint32_t PIO0_20; /!< I/O configuration for port PIO0 /
bogdanm	0:9b334a45a8ff	588	__IO uint32_t PIO0_21; /!< I/O configuration for port PIO0 /
bogdanm	0:9b334a45a8ff	589	__IO uint32_t PIO0_22; /!< I/O configuration for port PIO0 /
bogdanm	0:9b334a45a8ff	590	__IO uint32_t PIO0_23; /!< I/O configuration for port PIO0 /
bogdanm	0:9b334a45a8ff	591	__IO uint32_t PIO1_0; /!< I/O configuration for port PIO1 /
bogdanm	0:9b334a45a8ff	592	__IO uint32_t PIO1_1; /!< I/O configuration for port PIO1 /
bogdanm	0:9b334a45a8ff	593	__IO uint32_t PIO1_2; /!< I/O configuration for port PIO1 /
bogdanm	0:9b334a45a8ff	594	__IO uint32_t PIO1_3; /!< I/O configuration for port PIO1 /
bogdanm	0:9b334a45a8ff	595	__IO uint32_t PIO1_4; /!< I/O configuration for port PIO1 /
bogdanm	0:9b334a45a8ff	596	__IO uint32_t PIO1_5; /!< I/O configuration for port PIO1 /
bogdanm	0:9b334a45a8ff	597	__IO uint32_t PIO1_6; /!< I/O configuration for port PIO1 /
bogdanm	0:9b334a45a8ff	598	__IO uint32_t PIO1_7; /!< I/O configuration for port PIO1 /
bogdanm	0:9b334a45a8ff	599	__IO uint32_t PIO1_8; /!< I/O configuration for port PIO1 /
bogdanm	0:9b334a45a8ff	600	__IO uint32_t PIO1_9; /!< I/O configuration for port PIO1 /
bogdanm	0:9b334a45a8ff	601	__IO uint32_t PIO1_10; /!< I/O configuration for port PIO1 /
bogdanm	0:9b334a45a8ff	602	__IO uint32_t PIO1_11; /!< I/O configuration for port PIO1 /
bogdanm	0:9b334a45a8ff	603	__IO uint32_t PIO1_12; /!< I/O configuration for port PIO1 /
bogdanm	0:9b334a45a8ff	604	__IO uint32_t PIO1_13; /!< I/O configuration for port PIO1 /
bogdanm	0:9b334a45a8ff	605	__IO uint32_t PIO1_14; /!< I/O configuration for port PIO1 /
bogdanm	0:9b334a45a8ff	606	__IO uint32_t PIO1_15; /!< I/O configuration for port PIO1 /
bogdanm	0:9b334a45a8ff	607	__IO uint32_t PIO1_16; /!< I/O configuration for port PIO1 /
bogdanm	0:9b334a45a8ff	608	__IO uint32_t PIO1_17; /!< I/O configuration for port PIO1 /
bogdanm	0:9b334a45a8ff	609	__IO uint32_t PIO1_18; /!< I/O configuration for port PIO1 /
bogdanm	0:9b334a45a8ff	610	__IO uint32_t PIO1_19; /!< I/O configuration for port PIO1 /
bogdanm	0:9b334a45a8ff	611	__IO uint32_t PIO1_20; /!< I/O configuration for port PIO1 /
bogdanm	0:9b334a45a8ff	612	__IO uint32_t PIO1_21; /!< I/O configuration for port PIO1 /
bogdanm	0:9b334a45a8ff	613	__IO uint32_t PIO1_22; /!< I/O configuration for port PIO1 /
bogdanm	0:9b334a45a8ff	614	__IO uint32_t PIO1_23; /!< I/O configuration for port PIO1 /
bogdanm	0:9b334a45a8ff	615	__IO uint32_t PIO1_24; /!< I/O configuration for port PIO1 /
bogdanm	0:9b334a45a8ff	616	__IO uint32_t PIO1_25; /!< I/O configuration for port PIO1 /
bogdanm	0:9b334a45a8ff	617	__IO uint32_t PIO1_26; /!< I/O configuration for port PIO1 /
bogdanm	0:9b334a45a8ff	618	__IO uint32_t PIO1_27; /!< I/O configuration for port PIO1 /
bogdanm	0:9b334a45a8ff	619	__IO uint32_t PIO1_28; /!< I/O configuration for port PIO1 /
bogdanm	0:9b334a45a8ff	620	__IO uint32_t PIO1_29; /!< I/O configuration for port PIO1 /
bogdanm	0:9b334a45a8ff	621	__IO uint32_t PIO1_30; /!< I/O configuration for port PIO1 /
bogdanm	0:9b334a45a8ff	622	__IO uint32_t PIO1_31; /!< I/O configuration for port PIO1 /
bogdanm	0:9b334a45a8ff	623	__I uint32_t RESERVED0[4];
bogdanm	0:9b334a45a8ff	624	__IO uint32_t PIO2_0; /!< I/O configuration for port PIO2 /
bogdanm	0:9b334a45a8ff	625	__IO uint32_t PIO2_1; /!< I/O configuration for port PIO2 /
bogdanm	0:9b334a45a8ff	626	__I uint32_t RESERVED1;
bogdanm	0:9b334a45a8ff	627	__IO uint32_t PIO2_2; /!< I/O configuration for port PIO2 /
bogdanm	0:9b334a45a8ff	628	__IO uint32_t PIO2_3; /!< I/O configuration for port PIO2 /
bogdanm	0:9b334a45a8ff	629	__IO uint32_t PIO2_4; /!< I/O configuration for port PIO2 /
bogdanm	0:9b334a45a8ff	630	__IO uint32_t PIO2_5; /!< I/O configuration for port PIO2 /
bogdanm	0:9b334a45a8ff	631	__IO uint32_t PIO2_6; /!< I/O configuration for port PIO2 /
bogdanm	0:9b334a45a8ff	632	__IO uint32_t PIO2_7; /!< I/O configuration for port PIO2 /
bogdanm	0:9b334a45a8ff	633	__IO uint32_t PIO2_8; /!< I/O configuration for port PIO2 /
bogdanm	0:9b334a45a8ff	634	__IO uint32_t PIO2_9; /!< I/O configuration for port PIO2 /
bogdanm	0:9b334a45a8ff	635	__IO uint32_t PIO2_10; /!< I/O configuration for port PIO2 /
bogdanm	0:9b334a45a8ff	636	__IO uint32_t PIO2_11; /!< I/O configuration for port PIO2 /
bogdanm	0:9b334a45a8ff	637	__IO uint32_t PIO2_12; /!< I/O configuration for port PIO2 /
bogdanm	0:9b334a45a8ff	638	__IO uint32_t PIO2_13; /!< I/O configuration for port PIO2 /
bogdanm	0:9b334a45a8ff	639	__IO uint32_t PIO2_14; /!< I/O configuration for port PIO2 /
bogdanm	0:9b334a45a8ff	640	__IO uint32_t PIO2_15; /!< I/O configuration for port PIO2 /
bogdanm	0:9b334a45a8ff	641	__IO uint32_t PIO2_16; /!< I/O configuration for port PIO2 /
bogdanm	0:9b334a45a8ff	642	__IO uint32_t PIO2_17; /!< I/O configuration for port PIO2 /
bogdanm	0:9b334a45a8ff	643	__IO uint32_t PIO2_18; /!< I/O configuration for port PIO2 /
bogdanm	0:9b334a45a8ff	644	__IO uint32_t PIO2_19; /!< I/O configuration for port PIO2 /
bogdanm	0:9b334a45a8ff	645	__IO uint32_t PIO2_20; /!< I/O configuration for port PIO2 /
bogdanm	0:9b334a45a8ff	646	__IO uint32_t PIO2_21; /!< I/O configuration for port PIO2 /
bogdanm	0:9b334a45a8ff	647	__IO uint32_t PIO2_22; /!< I/O configuration for port PIO2 /
bogdanm	0:9b334a45a8ff	648	__IO uint32_t PIO2_23; /!< I/O configuration for port PIO2 /
bogdanm	0:9b334a45a8ff	649	} LPC_IOCON_Type;
bogdanm	0:9b334a45a8ff	650
bogdanm	0:9b334a45a8ff	651
bogdanm	0:9b334a45a8ff	652	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	653	/* ================ SYSCON ================ */
bogdanm	0:9b334a45a8ff	654	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	655
bogdanm	0:9b334a45a8ff	656
bogdanm	0:9b334a45a8ff	657	/**
bogdanm	0:9b334a45a8ff	658	* @brief Product name title=Kylin UM Chapter title=KylinSystem configuration (SYSCON) Modification date=5/13/2013 Major revision=0 Minor revision=1 (SYSCON)
bogdanm	0:9b334a45a8ff	659	*/
bogdanm	0:9b334a45a8ff	660
bogdanm	0:9b334a45a8ff	661	typedef struct { /!< SYSCON Structure /
bogdanm	0:9b334a45a8ff	662	__IO uint32_t SYSMEMREMAP; /!< System memory remap /
bogdanm	0:9b334a45a8ff	663	__IO uint32_t PRESETCTRL; /!< Peripheral reset control /
bogdanm	0:9b334a45a8ff	664	__IO uint32_t SYSPLLCTRL; /!< System PLL control /
bogdanm	0:9b334a45a8ff	665	__I uint32_t SYSPLLSTAT; /!< System PLL status /
bogdanm	0:9b334a45a8ff	666	__IO uint32_t USBPLLCTRL; /!< USB PLL control /
bogdanm	0:9b334a45a8ff	667	__I uint32_t USBPLLSTAT; /!< USB PLL status /
bogdanm	0:9b334a45a8ff	668	__I uint32_t RESERVED0;
bogdanm	0:9b334a45a8ff	669	__IO uint32_t RTCOSCCTRL; /!< RTC oscillator 32 kHz output control /
bogdanm	0:9b334a45a8ff	670	__IO uint32_t SYSOSCCTRL; /!< System oscillator control /
bogdanm	0:9b334a45a8ff	671	__IO uint32_t WDTOSCCTRL; /!< Watchdog oscillator control /
bogdanm	0:9b334a45a8ff	672	__I uint32_t RESERVED1[2];
bogdanm	0:9b334a45a8ff	673	__IO uint32_t SYSRSTSTAT; /!< System reset status register /
bogdanm	0:9b334a45a8ff	674	__I uint32_t RESERVED2[3];
bogdanm	0:9b334a45a8ff	675	__IO uint32_t SYSPLLCLKSEL; /!< System PLL clock source select /
bogdanm	0:9b334a45a8ff	676	__IO uint32_t SYSPLLCLKUEN; /!< System PLL clock source update enable /
bogdanm	0:9b334a45a8ff	677	__IO uint32_t USBPLLCLKSEL; /!< USB PLL clock source select /
bogdanm	0:9b334a45a8ff	678	__IO uint32_t USBPLLCLKUEN; /!< USB PLL clock source update enable /
bogdanm	0:9b334a45a8ff	679	__I uint32_t RESERVED3[8];
bogdanm	0:9b334a45a8ff	680	__IO uint32_t MAINCLKSEL; /!< Main clock source select /
bogdanm	0:9b334a45a8ff	681	__IO uint32_t MAINCLKUEN; /!< Main clock source update enable /
bogdanm	0:9b334a45a8ff	682	__IO uint32_t SYSAHBCLKDIV; /!< System clock divider /
bogdanm	0:9b334a45a8ff	683	__I uint32_t RESERVED4;
bogdanm	0:9b334a45a8ff	684	__IO uint32_t SYSAHBCLKCTRL; /!< System clock control /
bogdanm	0:9b334a45a8ff	685	__I uint32_t RESERVED5[4];
bogdanm	0:9b334a45a8ff	686	__IO uint32_t SSP0CLKDIV; /!< SSP0 clock divider /
bogdanm	0:9b334a45a8ff	687	__IO uint32_t USART0CLKDIV; /!< USART0 clock divider /
bogdanm	0:9b334a45a8ff	688	__IO uint32_t SSP1CLKDIV; /!< SSP1 clock divider /
bogdanm	0:9b334a45a8ff	689	__IO uint32_t FRGCLKDIV; /*!< Clock divider for the common fractional baud rate generator
bogdanm	0:9b334a45a8ff	690	of USART1 to USART4 */
bogdanm	0:9b334a45a8ff	691	__I uint32_t RESERVED6[7];
bogdanm	0:9b334a45a8ff	692	__IO uint32_t USBCLKSEL; /!< USB clock source select /
bogdanm	0:9b334a45a8ff	693	__IO uint32_t USBCLKUEN; /!< USB clock source update enable /
bogdanm	0:9b334a45a8ff	694	__IO uint32_t USBCLKDIV; /!< USB clock source divider /
bogdanm	0:9b334a45a8ff	695	__I uint32_t RESERVED7[5];
bogdanm	0:9b334a45a8ff	696	__IO uint32_t CLKOUTSEL; /!< CLKOUT clock source select /
bogdanm	0:9b334a45a8ff	697	__IO uint32_t CLKOUTUEN; /!< CLKOUT clock source update enable /
bogdanm	0:9b334a45a8ff	698	__IO uint32_t CLKOUTDIV; /!< CLKOUT clock divider /
bogdanm	0:9b334a45a8ff	699	__I uint32_t RESERVED8;
bogdanm	0:9b334a45a8ff	700	__IO uint32_t UARTFRGDIV; /!< USART fractional generator divider value /
bogdanm	0:9b334a45a8ff	701	__IO uint32_t UARTFRGMULT; /!< USART fractional generator multiplier value /
bogdanm	0:9b334a45a8ff	702	__I uint32_t RESERVED9;
bogdanm	0:9b334a45a8ff	703	__IO uint32_t EXTTRACECMD; /!< External trace buffer command register /
bogdanm	0:9b334a45a8ff	704	__I uint32_t PIOPORCAP0; /!< POR captured PIO status 0 /
bogdanm	0:9b334a45a8ff	705	__I uint32_t PIOPORCAP1; /!< POR captured PIO status 1 /
bogdanm	0:9b334a45a8ff	706	__I uint32_t PIOPORCAP2; /!< POR captured PIO status 1 /
bogdanm	0:9b334a45a8ff	707	__I uint32_t RESERVED10[10];
bogdanm	0:9b334a45a8ff	708	__IO uint32_t IOCONCLKDIV6; /*!< Peripheral clock 6 to the IOCON block for programmable glitch
bogdanm	0:9b334a45a8ff	709	filter */
bogdanm	0:9b334a45a8ff	710	__IO uint32_t IOCONCLKDIV5; /*!< Peripheral clock 5 to the IOCON block for programmable glitch
bogdanm	0:9b334a45a8ff	711	filter */
bogdanm	0:9b334a45a8ff	712	__IO uint32_t IOCONCLKDIV4; /*!< Peripheral clock 4 to the IOCON block for programmable glitch
bogdanm	0:9b334a45a8ff	713	filter */
bogdanm	0:9b334a45a8ff	714	__IO uint32_t IOCONCLKDIV3; /*!< Peripheral clock 3 to the IOCON block for programmable glitch
bogdanm	0:9b334a45a8ff	715	filter */
bogdanm	0:9b334a45a8ff	716	__IO uint32_t IOCONCLKDIV2; /*!< Peripheral clock 2 to the IOCON block for programmable glitch
bogdanm	0:9b334a45a8ff	717	filter */
bogdanm	0:9b334a45a8ff	718	__IO uint32_t IOCONCLKDIV1; /*!< Peripheral clock 1 to the IOCON block for programmable glitch
bogdanm	0:9b334a45a8ff	719	filter */
bogdanm	0:9b334a45a8ff	720	__IO uint32_t IOCONCLKDIV0; /*!< Peripheral clock 0 to the IOCON block for programmable glitch
bogdanm	0:9b334a45a8ff	721	filter */
bogdanm	0:9b334a45a8ff	722	__IO uint32_t BODCTRL; /!< Brown-Out Detect /
bogdanm	0:9b334a45a8ff	723	__IO uint32_t SYSTCKCAL; /!< System tick counter calibration /
bogdanm	0:9b334a45a8ff	724	__IO uint32_t AHBMATRIXPRIO; /!< AHB matrix priority configuration /
bogdanm	0:9b334a45a8ff	725	__I uint32_t RESERVED11[5];
bogdanm	0:9b334a45a8ff	726	__IO uint32_t IRQLATENCY; /!< IRQ delay. Allows trade-off between interrupt latency and determinism. /
bogdanm	0:9b334a45a8ff	727	__IO uint32_t NMISRC; /!< NMI Source Control /
bogdanm	0:9b334a45a8ff	728	union {
bogdanm	0:9b334a45a8ff	729	__IO uint32_t PINTSEL[8];
bogdanm	0:9b334a45a8ff	730	struct {
bogdanm	0:9b334a45a8ff	731	__IO uint32_t PINTSEL0; /!< GPIO Pin Interrupt Select register 0 /
bogdanm	0:9b334a45a8ff	732	__IO uint32_t PINTSEL1; /!< GPIO Pin Interrupt Select register 0 /
bogdanm	0:9b334a45a8ff	733	__IO uint32_t PINTSEL2; /!< GPIO Pin Interrupt Select register 0 /
bogdanm	0:9b334a45a8ff	734	__IO uint32_t PINTSEL3; /!< GPIO Pin Interrupt Select register 0 /
bogdanm	0:9b334a45a8ff	735	__IO uint32_t PINTSEL4; /!< GPIO Pin Interrupt Select register 0 /
bogdanm	0:9b334a45a8ff	736	__IO uint32_t PINTSEL5; /!< GPIO Pin Interrupt Select register 0 /
bogdanm	0:9b334a45a8ff	737	__IO uint32_t PINTSEL6; /!< GPIO Pin Interrupt Select register 0 /
bogdanm	0:9b334a45a8ff	738	__IO uint32_t PINTSEL7; /!< GPIO Pin Interrupt Select register 0 /
bogdanm	0:9b334a45a8ff	739	};
bogdanm	0:9b334a45a8ff	740	};
bogdanm	0:9b334a45a8ff	741	__IO uint32_t USBCLKCTRL; /!< USB clock control /
bogdanm	0:9b334a45a8ff	742	__I uint32_t USBCLKST; /!< USB clock status /
bogdanm	0:9b334a45a8ff	743	__I uint32_t RESERVED12[25];
bogdanm	0:9b334a45a8ff	744	__IO uint32_t STARTERP0; /!< Start logic 0 interrupt wake-up enable register 0 /
bogdanm	0:9b334a45a8ff	745	__I uint32_t RESERVED13[3];
bogdanm	0:9b334a45a8ff	746	__IO uint32_t STARTERP1; /!< Start logic 1 interrupt wake-up enable register 1 /
bogdanm	0:9b334a45a8ff	747	__I uint32_t RESERVED14[6];
bogdanm	0:9b334a45a8ff	748	__IO uint32_t PDSLEEPCFG; /!< Power-down states in deep-sleep mode /
bogdanm	0:9b334a45a8ff	749	__IO uint32_t PDAWAKECFG; /!< Power-down states for wake-up from deep-sleep /
bogdanm	0:9b334a45a8ff	750	__IO uint32_t PDRUNCFG; /!< Power configuration register /
bogdanm	0:9b334a45a8ff	751	__I uint32_t RESERVED15[110];
bogdanm	0:9b334a45a8ff	752	__I uint32_t DEVICE_ID; /!< Device ID /
bogdanm	0:9b334a45a8ff	753	} LPC_SYSCON_Type;
bogdanm	0:9b334a45a8ff	754
bogdanm	0:9b334a45a8ff	755
bogdanm	0:9b334a45a8ff	756	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	757	/* ================ USART4 ================ */
bogdanm	0:9b334a45a8ff	758	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	759
bogdanm	0:9b334a45a8ff	760
bogdanm	0:9b334a45a8ff	761	/**
bogdanm	0:9b334a45a8ff	762	* @brief USART4 (USART4)
bogdanm	0:9b334a45a8ff	763	*/
bogdanm	0:9b334a45a8ff	764
bogdanm	0:9b334a45a8ff	765	typedef struct { /!< USART4 Structure /
bogdanm	0:9b334a45a8ff	766	__IO uint32_t CFG; /*!< USART Configuration register. Basic USART configuration settings
bogdanm	0:9b334a45a8ff	767	that typically are not changed during operation. */
bogdanm	0:9b334a45a8ff	768	__IO uint32_t CTL; /*!< USART Control register. USART control settings that are more
bogdanm	0:9b334a45a8ff	769	likely to change during operation. */
bogdanm	0:9b334a45a8ff	770	__IO uint32_t STAT; /*!< USART Status register. The complete status value can be read
bogdanm	0:9b334a45a8ff	771	here. Writing ones clears some bits in the register. Some bits
bogdanm	0:9b334a45a8ff	772	can be cleared by writing a 1 to them. */
bogdanm	0:9b334a45a8ff	773	__IO uint32_t INTENSET; /*!< Interrupt Enable read and Set register. Contains an individual
bogdanm	0:9b334a45a8ff	774	interrupt enable bit for each potential USART interrupt. A complete
bogdanm	0:9b334a45a8ff	775	value may be read from this register. Writing a 1 to any implemented
bogdanm	0:9b334a45a8ff	776	bit position causes that bit to be set. */
bogdanm	0:9b334a45a8ff	777	__O uint32_t INTENCLR; /*!< Interrupt Enable Clear register. Allows clearing any combination
bogdanm	0:9b334a45a8ff	778	of bits in the INTENSET register. Writing a 1 to any implemented
bogdanm	0:9b334a45a8ff	779	bit position causes the corresponding bit to be cleared. */
bogdanm	0:9b334a45a8ff	780	__I uint32_t RXDAT; /!< Receiver Data register. Contains the last character received. /
bogdanm	0:9b334a45a8ff	781	__I uint32_t RXDATSTAT; /*!< Receiver Data with Status register. Combines the last character
bogdanm	0:9b334a45a8ff	782	received with the current USART receive status. Allows DMA or
bogdanm	0:9b334a45a8ff	783	software to recover incoming data and status together. */
bogdanm	0:9b334a45a8ff	784	__IO uint32_t TXDAT; /!< Transmit Data register. Data to be transmitted is written here. /
bogdanm	0:9b334a45a8ff	785	__IO uint32_t BRG; /*!< Baud Rate Generator register. 16-bit integer baud rate divisor
bogdanm	0:9b334a45a8ff	786	value. */
bogdanm	0:9b334a45a8ff	787	__I uint32_t INTSTAT; /*!< Interrupt status register. Reflects interrupts that are currently
bogdanm	0:9b334a45a8ff	788	enabled. */
bogdanm	0:9b334a45a8ff	789	__IO uint32_t OSR; /!< Oversample selection register for asynchronous communication. /
bogdanm	0:9b334a45a8ff	790	__IO uint32_t ADDR; /!< Address register for automatic address matching. /
bogdanm	0:9b334a45a8ff	791	} LPC_USART4_Type;
bogdanm	0:9b334a45a8ff	792
bogdanm	0:9b334a45a8ff	793
bogdanm	0:9b334a45a8ff	794	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	795	/* ================ GINT0 ================ */
bogdanm	0:9b334a45a8ff	796	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	797
bogdanm	0:9b334a45a8ff	798
bogdanm	0:9b334a45a8ff	799	/**
bogdanm	0:9b334a45a8ff	800	* @brief GPIO group interrupt 0 (GINT0)
bogdanm	0:9b334a45a8ff	801	*/
bogdanm	0:9b334a45a8ff	802
bogdanm	0:9b334a45a8ff	803	typedef struct { /!< GINT0 Structure /
bogdanm	0:9b334a45a8ff	804	__IO uint32_t CTRL; /!< GPIO grouped interrupt control register /
bogdanm	0:9b334a45a8ff	805	__I uint32_t RESERVED0[7];
bogdanm	0:9b334a45a8ff	806	__IO uint32_t PORT_POL[3]; /!< GPIO grouped interrupt port 0 polarity register /
bogdanm	0:9b334a45a8ff	807	__I uint32_t RESERVED1[5];
bogdanm	0:9b334a45a8ff	808	__IO uint32_t PORT_ENA[3]; /!< GPIO grouped interrupt port enable register /
bogdanm	0:9b334a45a8ff	809	} LPC_GINT0_Type;
bogdanm	0:9b334a45a8ff	810
bogdanm	0:9b334a45a8ff	811
bogdanm	0:9b334a45a8ff	812	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	813	/* ================ USB ================ */
bogdanm	0:9b334a45a8ff	814	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	815
bogdanm	0:9b334a45a8ff	816
bogdanm	0:9b334a45a8ff	817	/**
bogdanm	0:9b334a45a8ff	818	* @brief USB device controller (USB)
bogdanm	0:9b334a45a8ff	819	*/
bogdanm	0:9b334a45a8ff	820
bogdanm	0:9b334a45a8ff	821	typedef struct { /!< USB Structure /
bogdanm	0:9b334a45a8ff	822	__IO uint32_t DEVCMDSTAT; /!< USB Device Command/Status register /
bogdanm	0:9b334a45a8ff	823	__IO uint32_t INFO; /!< USB Info register /
bogdanm	0:9b334a45a8ff	824	__IO uint32_t EPLISTSTART; /!< USB EP Command/Status List start address /
bogdanm	0:9b334a45a8ff	825	__IO uint32_t DATABUFSTART; /!< USB Data buffer start address /
bogdanm	0:9b334a45a8ff	826	__IO uint32_t LPM; /!< Link Power Management register /
bogdanm	0:9b334a45a8ff	827	__IO uint32_t EPSKIP; /!< USB Endpoint skip /
bogdanm	0:9b334a45a8ff	828	__IO uint32_t EPINUSE; /!< USB Endpoint Buffer in use /
bogdanm	0:9b334a45a8ff	829	__IO uint32_t EPBUFCFG; /!< USB Endpoint Buffer Configuration register /
bogdanm	0:9b334a45a8ff	830	__IO uint32_t INTSTAT; /!< USB interrupt status register /
bogdanm	0:9b334a45a8ff	831	__IO uint32_t INTEN; /!< USB interrupt enable register /
bogdanm	0:9b334a45a8ff	832	__IO uint32_t INTSETSTAT; /!< USB set interrupt status register /
bogdanm	0:9b334a45a8ff	833	__IO uint32_t INTROUTING; /!< USB interrupt routing register /
bogdanm	0:9b334a45a8ff	834	__I uint32_t RESERVED0;
bogdanm	0:9b334a45a8ff	835	__I uint32_t EPTOGGLE; /!< USB Endpoint toggle register /
bogdanm	0:9b334a45a8ff	836	} LPC_USB_Type;
bogdanm	0:9b334a45a8ff	837
bogdanm	0:9b334a45a8ff	838
bogdanm	0:9b334a45a8ff	839	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	840	/* ================ CRC ================ */
bogdanm	0:9b334a45a8ff	841	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	842
bogdanm	0:9b334a45a8ff	843
bogdanm	0:9b334a45a8ff	844	/**
bogdanm	0:9b334a45a8ff	845	* @brief Cyclic Redundancy Check (CRC) engine (CRC)
bogdanm	0:9b334a45a8ff	846	*/
bogdanm	0:9b334a45a8ff	847
bogdanm	0:9b334a45a8ff	848	typedef struct { /!< CRC Structure /
bogdanm	0:9b334a45a8ff	849	__IO uint32_t MODE; /!< CRC mode register /
bogdanm	0:9b334a45a8ff	850	__IO uint32_t SEED; /!< CRC seed register /
bogdanm	0:9b334a45a8ff	851
bogdanm	0:9b334a45a8ff	852	union {
bogdanm	0:9b334a45a8ff	853	__O uint32_t WR_DATA; /!< CRC data register /
bogdanm	0:9b334a45a8ff	854	__I uint32_t SUM; /!< CRC checksum register /
bogdanm	0:9b334a45a8ff	855	};
bogdanm	0:9b334a45a8ff	856	} LPC_CRC_Type;
bogdanm	0:9b334a45a8ff	857
bogdanm	0:9b334a45a8ff	858
bogdanm	0:9b334a45a8ff	859	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	860	/* ================ DMA ================ */
bogdanm	0:9b334a45a8ff	861	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	862
bogdanm	0:9b334a45a8ff	863
bogdanm	0:9b334a45a8ff	864	/**
bogdanm	0:9b334a45a8ff	865	* @brief Product name title=Kylin UM Chapter title=KylinDMA controller Modification date=5/13/2013 Major revision=0 Minor revision=1 (DMA)
bogdanm	0:9b334a45a8ff	866	*/
bogdanm	0:9b334a45a8ff	867
bogdanm	0:9b334a45a8ff	868	typedef struct { /!< DMA Structure /
bogdanm	0:9b334a45a8ff	869	__IO uint32_t CTRL; /!< DMA control. /
bogdanm	0:9b334a45a8ff	870	__I uint32_t INTSTAT; /!< Interrupt status. /
bogdanm	0:9b334a45a8ff	871	__IO uint32_t SRAMBASE; /!< SRAM address of the channel configuration table. /
bogdanm	0:9b334a45a8ff	872	__I uint32_t RESERVED0[5];
bogdanm	0:9b334a45a8ff	873	__IO uint32_t ENABLESET0; /!< Channel Enable read and Set for all DMA channels. /
bogdanm	0:9b334a45a8ff	874	__I uint32_t RESERVED1;
bogdanm	0:9b334a45a8ff	875	__O uint32_t ENABLECLR0; /!< Channel Enable Clear for all DMA channels. /
bogdanm	0:9b334a45a8ff	876	__I uint32_t RESERVED2;
bogdanm	0:9b334a45a8ff	877	__I uint32_t ACTIVE0; /!< Channel Active status for all DMA channels. /
bogdanm	0:9b334a45a8ff	878	__I uint32_t RESERVED3;
bogdanm	0:9b334a45a8ff	879	__I uint32_t BUSY0; /!< Channel Busy status for all DMA channels. /
bogdanm	0:9b334a45a8ff	880	__I uint32_t RESERVED4;
bogdanm	0:9b334a45a8ff	881	__IO uint32_t ERRINT0; /!< Error Interrupt status for all DMA channels. /
bogdanm	0:9b334a45a8ff	882	__I uint32_t RESERVED5;
bogdanm	0:9b334a45a8ff	883	__IO uint32_t INTENSET0; /!< Interrupt Enable read and Set for all DMA channels. /
bogdanm	0:9b334a45a8ff	884	__I uint32_t RESERVED6;
bogdanm	0:9b334a45a8ff	885	__O uint32_t INTENCLR0; /!< Interrupt Enable Clear for all DMA channels. /
bogdanm	0:9b334a45a8ff	886	__I uint32_t RESERVED7;
bogdanm	0:9b334a45a8ff	887	__IO uint32_t INTA0; /!< Interrupt A status for all DMA channels. /
bogdanm	0:9b334a45a8ff	888	__I uint32_t RESERVED8;
bogdanm	0:9b334a45a8ff	889	__IO uint32_t INTB0; /!< Interrupt B status for all DMA channels. /
bogdanm	0:9b334a45a8ff	890	__I uint32_t RESERVED9;
bogdanm	0:9b334a45a8ff	891	__O uint32_t SETVALID0; /!< Set ValidPending control bits for all DMA channels. /
bogdanm	0:9b334a45a8ff	892	__I uint32_t RESERVED10;
bogdanm	0:9b334a45a8ff	893	__O uint32_t SETTRIG0; /!< Set Trigger control bits for all DMA channels. /
bogdanm	0:9b334a45a8ff	894	__I uint32_t RESERVED11;
bogdanm	0:9b334a45a8ff	895	__O uint32_t ABORT0; /!< Channel Abort control for all DMA channels. /
bogdanm	0:9b334a45a8ff	896	__I uint32_t RESERVED12[225];
bogdanm	0:9b334a45a8ff	897	__IO uint32_t CFG0; /!< Configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	898	__I uint32_t CTLSTAT0; /!< Control and status register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	899	__IO uint32_t XFERCFG0; /!< Transfer configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	900	__I uint32_t RESERVED13;
bogdanm	0:9b334a45a8ff	901	__IO uint32_t CFG1; /!< Configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	902	__I uint32_t CTLSTAT1; /!< Control and status register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	903	__IO uint32_t XFERCFG1; /!< Transfer configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	904	__I uint32_t RESERVED14;
bogdanm	0:9b334a45a8ff	905	__IO uint32_t CFG2; /!< Configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	906	__I uint32_t CTLSTAT2; /!< Control and status register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	907	__IO uint32_t XFERCFG2; /!< Transfer configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	908	__I uint32_t RESERVED15;
bogdanm	0:9b334a45a8ff	909	__IO uint32_t CFG3; /!< Configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	910	__I uint32_t CTLSTAT3; /!< Control and status register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	911	__IO uint32_t XFERCFG3; /!< Transfer configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	912	__I uint32_t RESERVED16;
bogdanm	0:9b334a45a8ff	913	__IO uint32_t CFG4; /!< Configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	914	__I uint32_t CTLSTAT4; /!< Control and status register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	915	__IO uint32_t XFERCFG4; /!< Transfer configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	916	__I uint32_t RESERVED17;
bogdanm	0:9b334a45a8ff	917	__IO uint32_t CFG5; /!< Configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	918	__I uint32_t CTLSTAT5; /!< Control and status register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	919	__IO uint32_t XFERCFG5; /!< Transfer configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	920	__I uint32_t RESERVED18;
bogdanm	0:9b334a45a8ff	921	__IO uint32_t CFG6; /!< Configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	922	__I uint32_t CTLSTAT6; /!< Control and status register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	923	__IO uint32_t XFERCFG6; /!< Transfer configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	924	__I uint32_t RESERVED19;
bogdanm	0:9b334a45a8ff	925	__IO uint32_t CFG7; /!< Configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	926	__I uint32_t CTLSTAT7; /!< Control and status register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	927	__IO uint32_t XFERCFG7; /!< Transfer configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	928	__I uint32_t RESERVED20;
bogdanm	0:9b334a45a8ff	929	__IO uint32_t CFG8; /!< Configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	930	__I uint32_t CTLSTAT8; /!< Control and status register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	931	__IO uint32_t XFERCFG8; /!< Transfer configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	932	__I uint32_t RESERVED21;
bogdanm	0:9b334a45a8ff	933	__IO uint32_t CFG9; /!< Configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	934	__I uint32_t CTLSTAT9; /!< Control and status register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	935	__IO uint32_t XFERCFG9; /!< Transfer configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	936	__I uint32_t RESERVED22;
bogdanm	0:9b334a45a8ff	937	__IO uint32_t CFG10; /!< Configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	938	__I uint32_t CTLSTAT10; /!< Control and status register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	939	__IO uint32_t XFERCFG10; /!< Transfer configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	940	__I uint32_t RESERVED23;
bogdanm	0:9b334a45a8ff	941	__IO uint32_t CFG11; /!< Configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	942	__I uint32_t CTLSTAT11; /!< Control and status register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	943	__IO uint32_t XFERCFG11; /!< Transfer configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	944	__I uint32_t RESERVED24;
bogdanm	0:9b334a45a8ff	945	__IO uint32_t CFG12; /!< Configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	946	__I uint32_t CTLSTAT12; /!< Control and status register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	947	__IO uint32_t XFERCFG12; /!< Transfer configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	948	__I uint32_t RESERVED25;
bogdanm	0:9b334a45a8ff	949	__IO uint32_t CFG13; /!< Configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	950	__I uint32_t CTLSTAT13; /!< Control and status register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	951	__IO uint32_t XFERCFG13; /!< Transfer configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	952	__I uint32_t RESERVED26;
bogdanm	0:9b334a45a8ff	953	__IO uint32_t CFG14; /!< Configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	954	__I uint32_t CTLSTAT14; /!< Control and status register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	955	__IO uint32_t XFERCFG14; /!< Transfer configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	956	__I uint32_t RESERVED27;
bogdanm	0:9b334a45a8ff	957	__IO uint32_t CFG15; /!< Configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	958	__I uint32_t CTLSTAT15; /!< Control and status register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	959	__IO uint32_t XFERCFG15; /!< Transfer configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	960	} LPC_DMA_Type;
bogdanm	0:9b334a45a8ff	961
bogdanm	0:9b334a45a8ff	962
bogdanm	0:9b334a45a8ff	963	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	964	/* ================ SCT0 ================ */
bogdanm	0:9b334a45a8ff	965	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	966
bogdanm	0:9b334a45a8ff	967
bogdanm	0:9b334a45a8ff	968	/**
bogdanm	0:9b334a45a8ff	969	* @brief Product name title=Kylin UM Chapter title=KylinState Configurable Timers (SCT0/1) Modification date=5/14/2013 Major revision=0 Minor revision=1 (SCT0)
bogdanm	0:9b334a45a8ff	970	*/
bogdanm	0:9b334a45a8ff	971
bogdanm	0:9b334a45a8ff	972	typedef struct { /!< SCT0 Structure /
bogdanm	0:9b334a45a8ff	973	__IO uint32_t CONFIG; /!< SCT configuration register /
bogdanm	0:9b334a45a8ff	974	__IO uint32_t CTRL; /!< SCT control register /
bogdanm	0:9b334a45a8ff	975	__IO uint32_t LIMIT; /!< SCT limit register /
bogdanm	0:9b334a45a8ff	976	__IO uint32_t HALT; /!< SCT halt condition register /
bogdanm	0:9b334a45a8ff	977	__IO uint32_t STOP; /!< SCT stop condition register /
bogdanm	0:9b334a45a8ff	978	__IO uint32_t START; /!< SCT start condition register /
bogdanm	0:9b334a45a8ff	979	__I uint32_t RESERVED0[10];
bogdanm	0:9b334a45a8ff	980	__IO uint32_t COUNT; /!< SCT counter register /
bogdanm	0:9b334a45a8ff	981	__IO uint32_t STATE; /!< SCT state register /
bogdanm	0:9b334a45a8ff	982	__I uint32_t INPUT; /!< SCT input register /
bogdanm	0:9b334a45a8ff	983	__IO uint32_t REGMODE; /!< SCT match/capture registers mode register /
bogdanm	0:9b334a45a8ff	984	__IO uint32_t OUTPUT; /!< SCT output register /
bogdanm	0:9b334a45a8ff	985	__IO uint32_t OUTPUTDIRCTRL; /!< SCT output counter direction control register /
bogdanm	0:9b334a45a8ff	986	__IO uint32_t RES; /!< SCT conflict resolution register /
bogdanm	0:9b334a45a8ff	987	__IO uint32_t DMAREQ0; /!< SCT DMA request 0 register /
bogdanm	0:9b334a45a8ff	988	__IO uint32_t DMAREQ1; /!< SCT DMA request 1 register /
bogdanm	0:9b334a45a8ff	989	__I uint32_t RESERVED1[35];
bogdanm	0:9b334a45a8ff	990	__IO uint32_t EVEN; /!< SCT event enable register /
bogdanm	0:9b334a45a8ff	991	__IO uint32_t EVFLAG; /!< SCT event flag register /
bogdanm	0:9b334a45a8ff	992	__IO uint32_t CONEN; /!< SCT conflict enable register /
bogdanm	0:9b334a45a8ff	993	__IO uint32_t CONFLAG; /!< SCT conflict flag register /
bogdanm	0:9b334a45a8ff	994
bogdanm	0:9b334a45a8ff	995	union {
bogdanm	0:9b334a45a8ff	996	__IO uint32_t CAP0; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
bogdanm	0:9b334a45a8ff	997	= 1 */
bogdanm	0:9b334a45a8ff	998	__IO uint32_t MATCH0; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
bogdanm	0:9b334a45a8ff	999	REGMODE4 = 0 */
bogdanm	0:9b334a45a8ff	1000	};
bogdanm	0:9b334a45a8ff	1001
bogdanm	0:9b334a45a8ff	1002	union {
bogdanm	0:9b334a45a8ff	1003	__IO uint32_t CAP1; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
bogdanm	0:9b334a45a8ff	1004	= 1 */
bogdanm	0:9b334a45a8ff	1005	__IO uint32_t MATCH1; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
bogdanm	0:9b334a45a8ff	1006	REGMODE4 = 0 */
bogdanm	0:9b334a45a8ff	1007	};
bogdanm	0:9b334a45a8ff	1008
bogdanm	0:9b334a45a8ff	1009	union {
bogdanm	0:9b334a45a8ff	1010	__IO uint32_t MATCH2; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
bogdanm	0:9b334a45a8ff	1011	REGMODE4 = 0 */
bogdanm	0:9b334a45a8ff	1012	__IO uint32_t CAP2; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
bogdanm	0:9b334a45a8ff	1013	= 1 */
bogdanm	0:9b334a45a8ff	1014	};
bogdanm	0:9b334a45a8ff	1015
bogdanm	0:9b334a45a8ff	1016	union {
bogdanm	0:9b334a45a8ff	1017	__IO uint32_t CAP3; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
bogdanm	0:9b334a45a8ff	1018	= 1 */
bogdanm	0:9b334a45a8ff	1019	__IO uint32_t MATCH3; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
bogdanm	0:9b334a45a8ff	1020	REGMODE4 = 0 */
bogdanm	0:9b334a45a8ff	1021	};
bogdanm	0:9b334a45a8ff	1022
bogdanm	0:9b334a45a8ff	1023	union {
bogdanm	0:9b334a45a8ff	1024	__IO uint32_t CAP4; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
bogdanm	0:9b334a45a8ff	1025	= 1 */
bogdanm	0:9b334a45a8ff	1026	__IO uint32_t MATCH4; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
bogdanm	0:9b334a45a8ff	1027	REGMODE4 = 0 */
bogdanm	0:9b334a45a8ff	1028	};
bogdanm	0:9b334a45a8ff	1029	__I uint32_t RESERVED2[59];
bogdanm	0:9b334a45a8ff	1030
bogdanm	0:9b334a45a8ff	1031	union {
bogdanm	0:9b334a45a8ff	1032	__IO uint32_t CAPCTRL0; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
bogdanm	0:9b334a45a8ff	1033	= 1 */
bogdanm	0:9b334a45a8ff	1034	__IO uint32_t MATCHREL0; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
bogdanm	0:9b334a45a8ff	1035	= 0 */
bogdanm	0:9b334a45a8ff	1036	};
bogdanm	0:9b334a45a8ff	1037
bogdanm	0:9b334a45a8ff	1038	union {
bogdanm	0:9b334a45a8ff	1039	__IO uint32_t MATCHREL1; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
bogdanm	0:9b334a45a8ff	1040	= 0 */
bogdanm	0:9b334a45a8ff	1041	__IO uint32_t CAPCTRL1; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
bogdanm	0:9b334a45a8ff	1042	= 1 */
bogdanm	0:9b334a45a8ff	1043	};
bogdanm	0:9b334a45a8ff	1044
bogdanm	0:9b334a45a8ff	1045	union {
bogdanm	0:9b334a45a8ff	1046	__IO uint32_t MATCHREL2; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
bogdanm	0:9b334a45a8ff	1047	= 0 */
bogdanm	0:9b334a45a8ff	1048	__IO uint32_t CAPCTRL2; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
bogdanm	0:9b334a45a8ff	1049	= 1 */
bogdanm	0:9b334a45a8ff	1050	};
bogdanm	0:9b334a45a8ff	1051
bogdanm	0:9b334a45a8ff	1052	union {
bogdanm	0:9b334a45a8ff	1053	__IO uint32_t CAPCTRL3; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
bogdanm	0:9b334a45a8ff	1054	= 1 */
bogdanm	0:9b334a45a8ff	1055	__IO uint32_t MATCHREL3; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
bogdanm	0:9b334a45a8ff	1056	= 0 */
bogdanm	0:9b334a45a8ff	1057	};
bogdanm	0:9b334a45a8ff	1058
bogdanm	0:9b334a45a8ff	1059	union {
bogdanm	0:9b334a45a8ff	1060	__IO uint32_t CAPCTRL4; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
bogdanm	0:9b334a45a8ff	1061	= 1 */
bogdanm	0:9b334a45a8ff	1062	__IO uint32_t MATCHREL4; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
bogdanm	0:9b334a45a8ff	1063	= 0 */
bogdanm	0:9b334a45a8ff	1064	};
bogdanm	0:9b334a45a8ff	1065	__I uint32_t RESERVED3[59];
bogdanm	0:9b334a45a8ff	1066	__IO uint32_t EV0_STATE; /!< SCT event state register 0 /
bogdanm	0:9b334a45a8ff	1067	__IO uint32_t EV0_CTRL; /!< SCT event control register 0 /
bogdanm	0:9b334a45a8ff	1068	__IO uint32_t EV1_STATE; /!< SCT event state register 0 /
bogdanm	0:9b334a45a8ff	1069	__IO uint32_t EV1_CTRL; /!< SCT event control register 0 /
bogdanm	0:9b334a45a8ff	1070	__IO uint32_t EV2_STATE; /!< SCT event state register 0 /
bogdanm	0:9b334a45a8ff	1071	__IO uint32_t EV2_CTRL; /!< SCT event control register 0 /
bogdanm	0:9b334a45a8ff	1072	__IO uint32_t EV3_STATE; /!< SCT event state register 0 /
bogdanm	0:9b334a45a8ff	1073	__IO uint32_t EV3_CTRL; /!< SCT event control register 0 /
bogdanm	0:9b334a45a8ff	1074	__IO uint32_t EV4_STATE; /!< SCT event state register 0 /
bogdanm	0:9b334a45a8ff	1075	__IO uint32_t EV4_CTRL; /!< SCT event control register 0 /
bogdanm	0:9b334a45a8ff	1076	__IO uint32_t EV5_STATE; /!< SCT event state register 0 /
bogdanm	0:9b334a45a8ff	1077	__IO uint32_t EV5_CTRL; /!< SCT event control register 0 /
bogdanm	0:9b334a45a8ff	1078	__I uint32_t RESERVED4[116];
bogdanm	0:9b334a45a8ff	1079	__IO uint32_t OUT0_SET; /!< SCT output 0 set register /
bogdanm	0:9b334a45a8ff	1080	__IO uint32_t OUT0_CLR; /!< SCT output 0 clear register /
bogdanm	0:9b334a45a8ff	1081	__IO uint32_t OUT1_SET; /!< SCT output 0 set register /
bogdanm	0:9b334a45a8ff	1082	__IO uint32_t OUT1_CLR; /!< SCT output 0 clear register /
bogdanm	0:9b334a45a8ff	1083	__IO uint32_t OUT2_SET; /!< SCT output 0 set register /
bogdanm	0:9b334a45a8ff	1084	__IO uint32_t OUT2_CLR; /!< SCT output 0 clear register /
bogdanm	0:9b334a45a8ff	1085	__IO uint32_t OUT3_SET; /!< SCT output 0 set register /
bogdanm	0:9b334a45a8ff	1086	__IO uint32_t OUT3_CLR; /!< SCT output 0 clear register /
bogdanm	0:9b334a45a8ff	1087	} LPC_SCT0_Type;
bogdanm	0:9b334a45a8ff	1088
bogdanm	0:9b334a45a8ff	1089
bogdanm	0:9b334a45a8ff	1090	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	1091	/* ================ GPIO_PORT ================ */
bogdanm	0:9b334a45a8ff	1092	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	1093
bogdanm	0:9b334a45a8ff	1094
bogdanm	0:9b334a45a8ff	1095	/**
bogdanm	0:9b334a45a8ff	1096	* @brief General Purpose I/O (GPIO) (GPIO_PORT)
bogdanm	0:9b334a45a8ff	1097	*/
bogdanm	0:9b334a45a8ff	1098
bogdanm	0:9b334a45a8ff	1099	typedef struct { /!< GPIO_PORT Structure /
bogdanm	0:9b334a45a8ff	1100	__IO uint8_t B[88]; /!< Byte pin registers /
bogdanm	0:9b334a45a8ff	1101	__I uint32_t RESERVED0[42];
bogdanm	0:9b334a45a8ff	1102	__IO uint32_t W[88]; /!< Word pin registers /
bogdanm	0:9b334a45a8ff	1103	__I uint32_t RESERVED1[1896];
bogdanm	0:9b334a45a8ff	1104	__IO uint32_t DIR[3]; /!< Port Direction registers /
bogdanm	0:9b334a45a8ff	1105	__I uint32_t RESERVED2[29];
bogdanm	0:9b334a45a8ff	1106	__IO uint32_t MASK[3]; /!< Port Mask register /
bogdanm	0:9b334a45a8ff	1107	__I uint32_t RESERVED3[29];
bogdanm	0:9b334a45a8ff	1108	__IO uint32_t PIN[3]; /!< Port pin register /
bogdanm	0:9b334a45a8ff	1109	__I uint32_t RESERVED4[29];
bogdanm	0:9b334a45a8ff	1110	__IO uint32_t MPIN[3]; /!< Masked port register /
bogdanm	0:9b334a45a8ff	1111	__I uint32_t RESERVED5[29];
bogdanm	0:9b334a45a8ff	1112	__IO uint32_t SET[3]; /!< Write: Set port register Read: port output bits /
bogdanm	0:9b334a45a8ff	1113	__I uint32_t RESERVED6[29];
bogdanm	0:9b334a45a8ff	1114	__O uint32_t CLR[3]; /!< Clear port /
bogdanm	0:9b334a45a8ff	1115	__I uint32_t RESERVED7[29];
bogdanm	0:9b334a45a8ff	1116	__O uint32_t NOT[3]; /!< Toggle port /
bogdanm	0:9b334a45a8ff	1117	} LPC_GPIO_PORT_Type;
bogdanm	0:9b334a45a8ff	1118
bogdanm	0:9b334a45a8ff	1119
bogdanm	0:9b334a45a8ff	1120	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	1121	/* ================ PINT ================ */
bogdanm	0:9b334a45a8ff	1122	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	1123
bogdanm	0:9b334a45a8ff	1124
bogdanm	0:9b334a45a8ff	1125	/**
bogdanm	0:9b334a45a8ff	1126	* @brief Pin interruptand pattern match (PINT) (PINT)
bogdanm	0:9b334a45a8ff	1127	*/
bogdanm	0:9b334a45a8ff	1128
bogdanm	0:9b334a45a8ff	1129	typedef struct { /!< PINT Structure /
bogdanm	0:9b334a45a8ff	1130	__IO uint32_t ISEL; /!< Pin Interrupt Mode register /
bogdanm	0:9b334a45a8ff	1131	__IO uint32_t IENR; /!< Pin interrupt level or rising edge interrupt enable register /
bogdanm	0:9b334a45a8ff	1132	__O uint32_t SIENR; /!< Pin interrupt level or rising edge interrupt set register /
bogdanm	0:9b334a45a8ff	1133	__O uint32_t CIENR; /!< Pin interrupt level (rising edge interrupt) clear register /
bogdanm	0:9b334a45a8ff	1134	__IO uint32_t IENF; /*!< Pin interrupt active level or falling edge interrupt enable
bogdanm	0:9b334a45a8ff	1135	register */
bogdanm	0:9b334a45a8ff	1136	__O uint32_t SIENF; /!< Pin interrupt active level or falling edge interrupt set register /
bogdanm	0:9b334a45a8ff	1137	__O uint32_t CIENF; /!< Pin interrupt active level or falling edge interrupt clear register /
bogdanm	0:9b334a45a8ff	1138	__IO uint32_t RISE; /!< Pin interrupt rising edge register /
bogdanm	0:9b334a45a8ff	1139	__IO uint32_t FALL; /!< Pin interrupt falling edge register /
bogdanm	0:9b334a45a8ff	1140	__IO uint32_t IST; /!< Pin interrupt status register /
bogdanm	0:9b334a45a8ff	1141	__IO uint32_t PMCTRL; /!< Pattern match interrupt control register /
bogdanm	0:9b334a45a8ff	1142	__IO uint32_t PMSRC; /!< Pattern match interrupt bit-slice source register /
bogdanm	0:9b334a45a8ff	1143	__IO uint32_t PMCFG; /!< Pattern match interrupt bit slice configuration register /
bogdanm	0:9b334a45a8ff	1144	} LPC_PINT_Type;
bogdanm	0:9b334a45a8ff	1145
bogdanm	0:9b334a45a8ff	1146
bogdanm	0:9b334a45a8ff	1147	/* -------------------- End of section using anonymous unions ------------------- */
bogdanm	0:9b334a45a8ff	1148	#if defined(__CC_ARM)
bogdanm	0:9b334a45a8ff	1149	#pragma pop
bogdanm	0:9b334a45a8ff	1150	#elif defined(__ICCARM__)
bogdanm	0:9b334a45a8ff	1151	/* leave anonymous unions enabled */
bogdanm	0:9b334a45a8ff	1152	#elif defined(__GNUC__)
bogdanm	0:9b334a45a8ff	1153	/* anonymous unions are enabled by default */
bogdanm	0:9b334a45a8ff	1154	#elif defined(__TMS470__)
bogdanm	0:9b334a45a8ff	1155	/* anonymous unions are enabled by default */
bogdanm	0:9b334a45a8ff	1156	#elif defined(__TASKING__)
bogdanm	0:9b334a45a8ff	1157	#pragma warning restore
bogdanm	0:9b334a45a8ff	1158	#else
bogdanm	0:9b334a45a8ff	1159	#warning Not supported compiler type
bogdanm	0:9b334a45a8ff	1160	#endif
bogdanm	0:9b334a45a8ff	1161
bogdanm	0:9b334a45a8ff	1162
bogdanm	0:9b334a45a8ff	1163
bogdanm	0:9b334a45a8ff	1164
bogdanm	0:9b334a45a8ff	1165	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	1166	/* ================ Peripheral memory map ================ */
bogdanm	0:9b334a45a8ff	1167	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	1168
bogdanm	0:9b334a45a8ff	1169	#define LPC_I2C0_BASE 0x40000000UL
bogdanm	0:9b334a45a8ff	1170	#define LPC_WWDT_BASE 0x40004000UL
bogdanm	0:9b334a45a8ff	1171	#define LPC_USART0_BASE 0x40008000UL
bogdanm	0:9b334a45a8ff	1172	#define LPC_CT16B0_BASE 0x4000C000UL
bogdanm	0:9b334a45a8ff	1173	#define LPC_CT16B1_BASE 0x40010000UL
bogdanm	0:9b334a45a8ff	1174	#define LPC_CT32B0_BASE 0x40014000UL
bogdanm	0:9b334a45a8ff	1175	#define LPC_CT32B1_BASE 0x40018000UL
bogdanm	0:9b334a45a8ff	1176	#define LPC_ADC_BASE 0x4001C000UL
bogdanm	0:9b334a45a8ff	1177	#define LPC_I2C1_BASE 0x40020000UL
bogdanm	0:9b334a45a8ff	1178	#define LPC_RTC_BASE 0x40024000UL
bogdanm	0:9b334a45a8ff	1179	#define LPC_DMATRIGMUX_BASE 0x40028000UL
bogdanm	0:9b334a45a8ff	1180	#define LPC_PMU_BASE 0x40038000UL
bogdanm	0:9b334a45a8ff	1181	#define LPC_FLASHCTRL_BASE 0x4003C000UL
bogdanm	0:9b334a45a8ff	1182	#define LPC_SSP0_BASE 0x40040000UL
bogdanm	0:9b334a45a8ff	1183	#define LPC_IOCON_BASE 0x40044000UL
bogdanm	0:9b334a45a8ff	1184	#define LPC_SYSCON_BASE 0x40048000UL
bogdanm	0:9b334a45a8ff	1185	#define LPC_USART4_BASE 0x4004C000UL
bogdanm	0:9b334a45a8ff	1186	#define LPC_SSP1_BASE 0x40058000UL
bogdanm	0:9b334a45a8ff	1187	#define LPC_GINT0_BASE 0x4005C000UL
bogdanm	0:9b334a45a8ff	1188	#define LPC_GINT1_BASE 0x40060000UL
bogdanm	0:9b334a45a8ff	1189	#define LPC_USART1_BASE 0x4006C000UL
bogdanm	0:9b334a45a8ff	1190	#define LPC_USART2_BASE 0x40070000UL
bogdanm	0:9b334a45a8ff	1191	#define LPC_USART3_BASE 0x40074000UL
bogdanm	0:9b334a45a8ff	1192	#define LPC_USB_BASE 0x40080000UL
bogdanm	0:9b334a45a8ff	1193	#define LPC_CRC_BASE 0x50000000UL
bogdanm	0:9b334a45a8ff	1194	#define LPC_DMA_BASE 0x50004000UL
bogdanm	0:9b334a45a8ff	1195	#define LPC_SCT0_BASE 0x5000C000UL
bogdanm	0:9b334a45a8ff	1196	#define LPC_SCT1_BASE 0x5000E000UL
bogdanm	0:9b334a45a8ff	1197	#define LPC_GPIO_PORT_BASE 0xA0000000UL
bogdanm	0:9b334a45a8ff	1198	#define LPC_PINT_BASE 0xA0004000UL
bogdanm	0:9b334a45a8ff	1199
bogdanm	0:9b334a45a8ff	1200
bogdanm	0:9b334a45a8ff	1201	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	1202	/* ================ Peripheral declaration ================ */
bogdanm	0:9b334a45a8ff	1203	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	1204
bogdanm	0:9b334a45a8ff	1205	#define LPC_I2C0 ((LPC_I2C0_Type *) LPC_I2C0_BASE)
bogdanm	0:9b334a45a8ff	1206	#define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
bogdanm	0:9b334a45a8ff	1207	#define LPC_USART0 ((LPC_USART0_Type *) LPC_USART0_BASE)
bogdanm	0:9b334a45a8ff	1208	#define LPC_CT16B0 ((LPC_CT16B0_Type *) LPC_CT16B0_BASE)
bogdanm	0:9b334a45a8ff	1209	#define LPC_CT16B1 ((LPC_CT16B0_Type *) LPC_CT16B1_BASE)
bogdanm	0:9b334a45a8ff	1210	#define LPC_CT32B0 ((LPC_CT32B0_Type *) LPC_CT32B0_BASE)
bogdanm	0:9b334a45a8ff	1211	#define LPC_CT32B1 ((LPC_CT32B0_Type *) LPC_CT32B1_BASE)
bogdanm	0:9b334a45a8ff	1212	#define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE)
bogdanm	0:9b334a45a8ff	1213	#define LPC_I2C1 ((LPC_I2C0_Type *) LPC_I2C1_BASE)
bogdanm	0:9b334a45a8ff	1214	#define LPC_RTC ((LPC_RTC_Type *) LPC_RTC_BASE)
bogdanm	0:9b334a45a8ff	1215	#define LPC_DMATRIGMUX ((LPC_DMATRIGMUX_Type *) LPC_DMATRIGMUX_BASE)
bogdanm	0:9b334a45a8ff	1216	#define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
bogdanm	0:9b334a45a8ff	1217	#define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
bogdanm	0:9b334a45a8ff	1218	#define LPC_SSP0 ((LPC_SSP0_Type *) LPC_SSP0_BASE)
bogdanm	0:9b334a45a8ff	1219	#define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
bogdanm	0:9b334a45a8ff	1220	#define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
bogdanm	0:9b334a45a8ff	1221	#define LPC_USART4 ((LPC_USART4_Type *) LPC_USART4_BASE)
bogdanm	0:9b334a45a8ff	1222	#define LPC_SSP1 ((LPC_SSP0_Type *) LPC_SSP1_BASE)
bogdanm	0:9b334a45a8ff	1223	#define LPC_GINT0 ((LPC_GINT0_Type *) LPC_GINT0_BASE)
bogdanm	0:9b334a45a8ff	1224	#define LPC_GINT1 ((LPC_GINT0_Type *) LPC_GINT1_BASE)
bogdanm	0:9b334a45a8ff	1225	#define LPC_USART1 ((LPC_USART4_Type *) LPC_USART1_BASE)
bogdanm	0:9b334a45a8ff	1226	#define LPC_USART2 ((LPC_USART4_Type *) LPC_USART2_BASE)
bogdanm	0:9b334a45a8ff	1227	#define LPC_USART3 ((LPC_USART4_Type *) LPC_USART3_BASE)
bogdanm	0:9b334a45a8ff	1228	#define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE)
bogdanm	0:9b334a45a8ff	1229	#define LPC_CRC ((LPC_CRC_Type *) LPC_CRC_BASE)
bogdanm	0:9b334a45a8ff	1230	#define LPC_DMA ((LPC_DMA_Type *) LPC_DMA_BASE)
bogdanm	0:9b334a45a8ff	1231	#define LPC_SCT0 ((LPC_SCT0_Type *) LPC_SCT0_BASE)
bogdanm	0:9b334a45a8ff	1232	#define LPC_SCT1 ((LPC_SCT0_Type *) LPC_SCT1_BASE)
bogdanm	0:9b334a45a8ff	1233	#define LPC_GPIO_PORT ((LPC_GPIO_PORT_Type *) LPC_GPIO_PORT_BASE)
bogdanm	0:9b334a45a8ff	1234	#define LPC_PINT ((LPC_PINT_Type *) LPC_PINT_BASE)
bogdanm	0:9b334a45a8ff	1235
bogdanm	0:9b334a45a8ff	1236
bogdanm	0:9b334a45a8ff	1237	/** @} / / End of group Device_Peripheral_Registers */
bogdanm	0:9b334a45a8ff	1238	/** @} / / End of group LPC11U6x */
bogdanm	0:9b334a45a8ff	1239	/** @} / / End of group (null) */
bogdanm	0:9b334a45a8ff	1240
bogdanm	0:9b334a45a8ff	1241	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	1242	}
bogdanm	0:9b334a45a8ff	1243	#endif
bogdanm	0:9b334a45a8ff	1244
bogdanm	0:9b334a45a8ff	1245
bogdanm	0:9b334a45a8ff	1246	#endif /* LPC11U6x_H */
bogdanm	0:9b334a45a8ff	1247

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Type:	Library
Created:	23 Aug 2017
Imports:	7
Forks:	0
Commits:	167
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/LPC11U6x.h@0:9b334a45a8ff, 2015-10-01 (annotated)

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