Iftikhar Aziz / mbed-dev

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Dependents:   LSS_Rev_1

Fork of mbed-dev by Umar Naeem

targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/drivers/fsl_lpuart_dma.c@154:37f96f9d4de2, 2017-01-04 (annotated)

Committer:
<>
Date:
Wed Jan 04 16:58:05 2017 +0000
Revision:
154:37f96f9d4de2
This updates the lib to the mbed lib v133

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 154:37f96f9d4de2 1 /*
<> 154:37f96f9d4de2 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
<> 154:37f96f9d4de2 3 * All rights reserved.
<> 154:37f96f9d4de2 4 *
<> 154:37f96f9d4de2 5 * Redistribution and use in source and binary forms, with or without modification,
<> 154:37f96f9d4de2 6 * are permitted provided that the following conditions are met:
<> 154:37f96f9d4de2 7 *
<> 154:37f96f9d4de2 8 * o Redistributions of source code must retain the above copyright notice, this list
<> 154:37f96f9d4de2 9 * of conditions and the following disclaimer.
<> 154:37f96f9d4de2 10 *
<> 154:37f96f9d4de2 11 * o Redistributions in binary form must reproduce the above copyright notice, this
<> 154:37f96f9d4de2 12 * list of conditions and the following disclaimer in the documentation and/or
<> 154:37f96f9d4de2 13 * other materials provided with the distribution.
<> 154:37f96f9d4de2 14 *
<> 154:37f96f9d4de2 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 154:37f96f9d4de2 16 * contributors may be used to endorse or promote products derived from this
<> 154:37f96f9d4de2 17 * software without specific prior written permission.
<> 154:37f96f9d4de2 18 *
<> 154:37f96f9d4de2 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 154:37f96f9d4de2 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 154:37f96f9d4de2 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 154:37f96f9d4de2 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 154:37f96f9d4de2 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 154:37f96f9d4de2 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 154:37f96f9d4de2 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 154:37f96f9d4de2 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 154:37f96f9d4de2 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 154:37f96f9d4de2 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 154:37f96f9d4de2 29 */
<> 154:37f96f9d4de2 30 #include "fsl_lpuart_dma.h"
<> 154:37f96f9d4de2 31 #include "fsl_dmamux.h"
<> 154:37f96f9d4de2 32
<> 154:37f96f9d4de2 33 /*******************************************************************************
<> 154:37f96f9d4de2 34 * Definitions
<> 154:37f96f9d4de2 35 ******************************************************************************/
<> 154:37f96f9d4de2 36
<> 154:37f96f9d4de2 37 /*<! Structure definition for lpuart_dma_handle_t. The structure is private. */
<> 154:37f96f9d4de2 38 typedef struct _lpuart_dma_private_handle
<> 154:37f96f9d4de2 39 {
<> 154:37f96f9d4de2 40 LPUART_Type *base;
<> 154:37f96f9d4de2 41 lpuart_dma_handle_t *handle;
<> 154:37f96f9d4de2 42 } lpuart_dma_private_handle_t;
<> 154:37f96f9d4de2 43
<> 154:37f96f9d4de2 44 /* LPUART DMA transfer handle. */
<> 154:37f96f9d4de2 45 enum _uart_dma_tansfer_states
<> 154:37f96f9d4de2 46 {
<> 154:37f96f9d4de2 47 kLPUART_TxIdle, /* TX idle. */
<> 154:37f96f9d4de2 48 kLPUART_TxBusy, /* TX busy. */
<> 154:37f96f9d4de2 49 kLPUART_RxIdle, /* RX idle. */
<> 154:37f96f9d4de2 50 kLPUART_RxBusy /* RX busy. */
<> 154:37f96f9d4de2 51 };
<> 154:37f96f9d4de2 52
<> 154:37f96f9d4de2 53 /*******************************************************************************
<> 154:37f96f9d4de2 54 * Variables
<> 154:37f96f9d4de2 55 ******************************************************************************/
<> 154:37f96f9d4de2 56
<> 154:37f96f9d4de2 57 /*<! Private handle only used for internally. */
<> 154:37f96f9d4de2 58 static lpuart_dma_private_handle_t s_dmaPrivateHandle[FSL_FEATURE_SOC_LPUART_COUNT];
<> 154:37f96f9d4de2 59
<> 154:37f96f9d4de2 60 /*******************************************************************************
<> 154:37f96f9d4de2 61 * Prototypes
<> 154:37f96f9d4de2 62 ******************************************************************************/
<> 154:37f96f9d4de2 63
<> 154:37f96f9d4de2 64 /*!
<> 154:37f96f9d4de2 65 * @brief LPUART DMA send finished callback function.
<> 154:37f96f9d4de2 66 *
<> 154:37f96f9d4de2 67 * This function is called when LPUART DMA send finished. It disables the LPUART
<> 154:37f96f9d4de2 68 * TX DMA request and sends @ref kStatus_LPUART_TxIdle to LPUART callback.
<> 154:37f96f9d4de2 69 *
<> 154:37f96f9d4de2 70 * @param handle The DMA handle.
<> 154:37f96f9d4de2 71 * @param param Callback function parameter.
<> 154:37f96f9d4de2 72 */
<> 154:37f96f9d4de2 73 static void LPUART_TransferSendDMACallback(dma_handle_t *handle, void *param);
<> 154:37f96f9d4de2 74
<> 154:37f96f9d4de2 75 /*!
<> 154:37f96f9d4de2 76 * @brief LPUART DMA receive finished callback function.
<> 154:37f96f9d4de2 77 *
<> 154:37f96f9d4de2 78 * This function is called when LPUART DMA receive finished. It disables the LPUART
<> 154:37f96f9d4de2 79 * RX DMA request and sends @ref kStatus_LPUART_RxIdle to LPUART callback.
<> 154:37f96f9d4de2 80 *
<> 154:37f96f9d4de2 81 * @param handle The DMA handle.
<> 154:37f96f9d4de2 82 * @param param Callback function parameter.
<> 154:37f96f9d4de2 83 */
<> 154:37f96f9d4de2 84 static void LPUART_TransferReceiveDMACallback(dma_handle_t *handle, void *param);
<> 154:37f96f9d4de2 85
<> 154:37f96f9d4de2 86 /*!
<> 154:37f96f9d4de2 87 * @brief Get the LPUART instance from peripheral base address.
<> 154:37f96f9d4de2 88 *
<> 154:37f96f9d4de2 89 * @param base LPUART peripheral base address.
<> 154:37f96f9d4de2 90 * @return LPUART instance.
<> 154:37f96f9d4de2 91 */
<> 154:37f96f9d4de2 92 extern uint32_t LPUART_GetInstance(LPUART_Type *base);
<> 154:37f96f9d4de2 93
<> 154:37f96f9d4de2 94 /*******************************************************************************
<> 154:37f96f9d4de2 95 * Code
<> 154:37f96f9d4de2 96 ******************************************************************************/
<> 154:37f96f9d4de2 97
<> 154:37f96f9d4de2 98 static void LPUART_TransferSendDMACallback(dma_handle_t *handle, void *param)
<> 154:37f96f9d4de2 99 {
<> 154:37f96f9d4de2 100 lpuart_dma_private_handle_t *lpuartPrivateHandle = (lpuart_dma_private_handle_t *)param;
<> 154:37f96f9d4de2 101
<> 154:37f96f9d4de2 102 /* Disable LPUART TX DMA. */
<> 154:37f96f9d4de2 103 LPUART_EnableTxDMA(lpuartPrivateHandle->base, false);
<> 154:37f96f9d4de2 104
<> 154:37f96f9d4de2 105 /* Disable interrupt. */
<> 154:37f96f9d4de2 106 DMA_DisableInterrupts(lpuartPrivateHandle->handle->txDmaHandle->base,
<> 154:37f96f9d4de2 107 lpuartPrivateHandle->handle->txDmaHandle->channel);
<> 154:37f96f9d4de2 108
<> 154:37f96f9d4de2 109 lpuartPrivateHandle->handle->txState = kLPUART_TxIdle;
<> 154:37f96f9d4de2 110
<> 154:37f96f9d4de2 111 if (lpuartPrivateHandle->handle->callback)
<> 154:37f96f9d4de2 112 {
<> 154:37f96f9d4de2 113 lpuartPrivateHandle->handle->callback(lpuartPrivateHandle->base, lpuartPrivateHandle->handle,
<> 154:37f96f9d4de2 114 kStatus_LPUART_TxIdle, lpuartPrivateHandle->handle->userData);
<> 154:37f96f9d4de2 115 }
<> 154:37f96f9d4de2 116 }
<> 154:37f96f9d4de2 117
<> 154:37f96f9d4de2 118 static void LPUART_TransferReceiveDMACallback(dma_handle_t *handle, void *param)
<> 154:37f96f9d4de2 119 {
<> 154:37f96f9d4de2 120 lpuart_dma_private_handle_t *lpuartPrivateHandle = (lpuart_dma_private_handle_t *)param;
<> 154:37f96f9d4de2 121
<> 154:37f96f9d4de2 122 /* Disable LPUART RX DMA. */
<> 154:37f96f9d4de2 123 LPUART_EnableRxDMA(lpuartPrivateHandle->base, false);
<> 154:37f96f9d4de2 124
<> 154:37f96f9d4de2 125 /* Disable interrupt. */
<> 154:37f96f9d4de2 126 DMA_DisableInterrupts(lpuartPrivateHandle->handle->rxDmaHandle->base,
<> 154:37f96f9d4de2 127 lpuartPrivateHandle->handle->rxDmaHandle->channel);
<> 154:37f96f9d4de2 128
<> 154:37f96f9d4de2 129 lpuartPrivateHandle->handle->rxState = kLPUART_RxIdle;
<> 154:37f96f9d4de2 130
<> 154:37f96f9d4de2 131 if (lpuartPrivateHandle->handle->callback)
<> 154:37f96f9d4de2 132 {
<> 154:37f96f9d4de2 133 lpuartPrivateHandle->handle->callback(lpuartPrivateHandle->base, lpuartPrivateHandle->handle,
<> 154:37f96f9d4de2 134 kStatus_LPUART_RxIdle, lpuartPrivateHandle->handle->userData);
<> 154:37f96f9d4de2 135 }
<> 154:37f96f9d4de2 136 }
<> 154:37f96f9d4de2 137
<> 154:37f96f9d4de2 138 void LPUART_TransferCreateHandleDMA(LPUART_Type *base,
<> 154:37f96f9d4de2 139 lpuart_dma_handle_t *handle,
<> 154:37f96f9d4de2 140 lpuart_dma_transfer_callback_t callback,
<> 154:37f96f9d4de2 141 void *userData,
<> 154:37f96f9d4de2 142 dma_handle_t *txDmaHandle,
<> 154:37f96f9d4de2 143 dma_handle_t *rxDmaHandle)
<> 154:37f96f9d4de2 144 {
<> 154:37f96f9d4de2 145 assert(handle);
<> 154:37f96f9d4de2 146
<> 154:37f96f9d4de2 147 uint32_t instance = LPUART_GetInstance(base);
<> 154:37f96f9d4de2 148
<> 154:37f96f9d4de2 149 memset(handle, 0, sizeof(lpuart_dma_handle_t));
<> 154:37f96f9d4de2 150
<> 154:37f96f9d4de2 151 s_dmaPrivateHandle[instance].base = base;
<> 154:37f96f9d4de2 152 s_dmaPrivateHandle[instance].handle = handle;
<> 154:37f96f9d4de2 153
<> 154:37f96f9d4de2 154 handle->rxState = kLPUART_RxIdle;
<> 154:37f96f9d4de2 155 handle->txState = kLPUART_TxIdle;
<> 154:37f96f9d4de2 156
<> 154:37f96f9d4de2 157 handle->callback = callback;
<> 154:37f96f9d4de2 158 handle->userData = userData;
<> 154:37f96f9d4de2 159
<> 154:37f96f9d4de2 160 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
<> 154:37f96f9d4de2 161 /* Note:
<> 154:37f96f9d4de2 162 Take care of the RX FIFO, DMA request only assert when received bytes
<> 154:37f96f9d4de2 163 equal or more than RX water mark, there is potential issue if RX water
<> 154:37f96f9d4de2 164 mark larger than 1.
<> 154:37f96f9d4de2 165 For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and
<> 154:37f96f9d4de2 166 5 bytes are received. the last byte will be saved in FIFO but not trigger
<> 154:37f96f9d4de2 167 DMA transfer because the water mark is 2.
<> 154:37f96f9d4de2 168 */
<> 154:37f96f9d4de2 169 if (rxDmaHandle)
<> 154:37f96f9d4de2 170 {
<> 154:37f96f9d4de2 171 base->WATER &= (~LPUART_WATER_RXWATER_MASK);
<> 154:37f96f9d4de2 172 }
<> 154:37f96f9d4de2 173 #endif
<> 154:37f96f9d4de2 174
<> 154:37f96f9d4de2 175 handle->rxDmaHandle = rxDmaHandle;
<> 154:37f96f9d4de2 176 handle->txDmaHandle = txDmaHandle;
<> 154:37f96f9d4de2 177
<> 154:37f96f9d4de2 178 /* Configure TX. */
<> 154:37f96f9d4de2 179 if (txDmaHandle)
<> 154:37f96f9d4de2 180 {
<> 154:37f96f9d4de2 181 DMA_SetCallback(txDmaHandle, LPUART_TransferSendDMACallback, &s_dmaPrivateHandle[instance]);
<> 154:37f96f9d4de2 182 }
<> 154:37f96f9d4de2 183
<> 154:37f96f9d4de2 184 /* Configure RX. */
<> 154:37f96f9d4de2 185 if (rxDmaHandle)
<> 154:37f96f9d4de2 186 {
<> 154:37f96f9d4de2 187 DMA_SetCallback(rxDmaHandle, LPUART_TransferReceiveDMACallback, &s_dmaPrivateHandle[instance]);
<> 154:37f96f9d4de2 188 }
<> 154:37f96f9d4de2 189 }
<> 154:37f96f9d4de2 190
<> 154:37f96f9d4de2 191 status_t LPUART_TransferSendDMA(LPUART_Type *base, lpuart_dma_handle_t *handle, lpuart_transfer_t *xfer)
<> 154:37f96f9d4de2 192 {
<> 154:37f96f9d4de2 193 assert(handle->txDmaHandle);
<> 154:37f96f9d4de2 194
<> 154:37f96f9d4de2 195 status_t status;
<> 154:37f96f9d4de2 196 dma_transfer_config_t xferConfig;
<> 154:37f96f9d4de2 197
<> 154:37f96f9d4de2 198 /* Return error if xfer invalid. */
<> 154:37f96f9d4de2 199 if ((0U == xfer->dataSize) || (NULL == xfer->data))
<> 154:37f96f9d4de2 200 {
<> 154:37f96f9d4de2 201 return kStatus_InvalidArgument;
<> 154:37f96f9d4de2 202 }
<> 154:37f96f9d4de2 203
<> 154:37f96f9d4de2 204 /* If previous TX not finished. */
<> 154:37f96f9d4de2 205 if (kLPUART_TxBusy == handle->txState)
<> 154:37f96f9d4de2 206 {
<> 154:37f96f9d4de2 207 status = kStatus_LPUART_TxBusy;
<> 154:37f96f9d4de2 208 }
<> 154:37f96f9d4de2 209 else
<> 154:37f96f9d4de2 210 {
<> 154:37f96f9d4de2 211 handle->txState = kLPUART_TxBusy;
<> 154:37f96f9d4de2 212 handle->txDataSizeAll = xfer->dataSize;
<> 154:37f96f9d4de2 213
<> 154:37f96f9d4de2 214 /* Prepare transfer. */
<> 154:37f96f9d4de2 215 DMA_PrepareTransfer(&xferConfig, xfer->data, sizeof(uint8_t), (void *)LPUART_GetDataRegisterAddress(base),
<> 154:37f96f9d4de2 216 sizeof(uint8_t), xfer->dataSize, kDMA_MemoryToPeripheral);
<> 154:37f96f9d4de2 217
<> 154:37f96f9d4de2 218 /* Submit transfer. */
<> 154:37f96f9d4de2 219 DMA_SubmitTransfer(handle->txDmaHandle, &xferConfig, kDMA_EnableInterrupt);
<> 154:37f96f9d4de2 220 DMA_StartTransfer(handle->txDmaHandle);
<> 154:37f96f9d4de2 221
<> 154:37f96f9d4de2 222 /* Enable LPUART TX DMA. */
<> 154:37f96f9d4de2 223 LPUART_EnableTxDMA(base, true);
<> 154:37f96f9d4de2 224
<> 154:37f96f9d4de2 225 status = kStatus_Success;
<> 154:37f96f9d4de2 226 }
<> 154:37f96f9d4de2 227
<> 154:37f96f9d4de2 228 return status;
<> 154:37f96f9d4de2 229 }
<> 154:37f96f9d4de2 230
<> 154:37f96f9d4de2 231 status_t LPUART_TransferReceiveDMA(LPUART_Type *base, lpuart_dma_handle_t *handle, lpuart_transfer_t *xfer)
<> 154:37f96f9d4de2 232 {
<> 154:37f96f9d4de2 233 assert(handle->rxDmaHandle);
<> 154:37f96f9d4de2 234
<> 154:37f96f9d4de2 235 status_t status;
<> 154:37f96f9d4de2 236 dma_transfer_config_t xferConfig;
<> 154:37f96f9d4de2 237
<> 154:37f96f9d4de2 238 /* Return error if xfer invalid. */
<> 154:37f96f9d4de2 239 if ((0U == xfer->dataSize) || (NULL == xfer->data))
<> 154:37f96f9d4de2 240 {
<> 154:37f96f9d4de2 241 return kStatus_InvalidArgument;
<> 154:37f96f9d4de2 242 }
<> 154:37f96f9d4de2 243
<> 154:37f96f9d4de2 244 /* If previous RX not finished. */
<> 154:37f96f9d4de2 245 if (kLPUART_RxBusy == handle->rxState)
<> 154:37f96f9d4de2 246 {
<> 154:37f96f9d4de2 247 status = kStatus_LPUART_RxBusy;
<> 154:37f96f9d4de2 248 }
<> 154:37f96f9d4de2 249 else
<> 154:37f96f9d4de2 250 {
<> 154:37f96f9d4de2 251 handle->rxState = kLPUART_RxBusy;
<> 154:37f96f9d4de2 252 handle->rxDataSizeAll = xfer->dataSize;
<> 154:37f96f9d4de2 253
<> 154:37f96f9d4de2 254 /* Prepare transfer. */
<> 154:37f96f9d4de2 255 DMA_PrepareTransfer(&xferConfig, (void *)LPUART_GetDataRegisterAddress(base), sizeof(uint8_t), xfer->data,
<> 154:37f96f9d4de2 256 sizeof(uint8_t), xfer->dataSize, kDMA_PeripheralToMemory);
<> 154:37f96f9d4de2 257
<> 154:37f96f9d4de2 258 /* Submit transfer. */
<> 154:37f96f9d4de2 259 DMA_SubmitTransfer(handle->rxDmaHandle, &xferConfig, kDMA_EnableInterrupt);
<> 154:37f96f9d4de2 260 DMA_StartTransfer(handle->rxDmaHandle);
<> 154:37f96f9d4de2 261
<> 154:37f96f9d4de2 262 /* Enable LPUART RX DMA. */
<> 154:37f96f9d4de2 263 LPUART_EnableRxDMA(base, true);
<> 154:37f96f9d4de2 264
<> 154:37f96f9d4de2 265 status = kStatus_Success;
<> 154:37f96f9d4de2 266 }
<> 154:37f96f9d4de2 267
<> 154:37f96f9d4de2 268 return status;
<> 154:37f96f9d4de2 269 }
<> 154:37f96f9d4de2 270
<> 154:37f96f9d4de2 271 void LPUART_TransferAbortSendDMA(LPUART_Type *base, lpuart_dma_handle_t *handle)
<> 154:37f96f9d4de2 272 {
<> 154:37f96f9d4de2 273 assert(handle->txDmaHandle);
<> 154:37f96f9d4de2 274
<> 154:37f96f9d4de2 275 /* Disable LPUART TX DMA. */
<> 154:37f96f9d4de2 276 LPUART_EnableTxDMA(base, false);
<> 154:37f96f9d4de2 277
<> 154:37f96f9d4de2 278 /* Stop transfer. */
<> 154:37f96f9d4de2 279 DMA_AbortTransfer(handle->txDmaHandle);
<> 154:37f96f9d4de2 280
<> 154:37f96f9d4de2 281 /* Write DMA->DSR[DONE] to abort transfer and clear status. */
<> 154:37f96f9d4de2 282 DMA_ClearChannelStatusFlags(handle->txDmaHandle->base, handle->txDmaHandle->channel, kDMA_TransactionsDoneFlag);
<> 154:37f96f9d4de2 283
<> 154:37f96f9d4de2 284 handle->txState = kLPUART_TxIdle;
<> 154:37f96f9d4de2 285 }
<> 154:37f96f9d4de2 286
<> 154:37f96f9d4de2 287 void LPUART_TransferAbortReceiveDMA(LPUART_Type *base, lpuart_dma_handle_t *handle)
<> 154:37f96f9d4de2 288 {
<> 154:37f96f9d4de2 289 assert(handle->rxDmaHandle);
<> 154:37f96f9d4de2 290
<> 154:37f96f9d4de2 291 /* Disable LPUART RX DMA. */
<> 154:37f96f9d4de2 292 LPUART_EnableRxDMA(base, false);
<> 154:37f96f9d4de2 293
<> 154:37f96f9d4de2 294 /* Stop transfer. */
<> 154:37f96f9d4de2 295 DMA_AbortTransfer(handle->rxDmaHandle);
<> 154:37f96f9d4de2 296
<> 154:37f96f9d4de2 297 /* Write DMA->DSR[DONE] to abort transfer and clear status. */
<> 154:37f96f9d4de2 298 DMA_ClearChannelStatusFlags(handle->rxDmaHandle->base, handle->rxDmaHandle->channel, kDMA_TransactionsDoneFlag);
<> 154:37f96f9d4de2 299
<> 154:37f96f9d4de2 300 handle->rxState = kLPUART_RxIdle;
<> 154:37f96f9d4de2 301 }
<> 154:37f96f9d4de2 302
<> 154:37f96f9d4de2 303 status_t LPUART_TransferGetSendCountDMA(LPUART_Type *base, lpuart_dma_handle_t *handle, uint32_t *count)
<> 154:37f96f9d4de2 304 {
<> 154:37f96f9d4de2 305 assert(handle->txDmaHandle);
<> 154:37f96f9d4de2 306
<> 154:37f96f9d4de2 307 if (kLPUART_TxIdle == handle->txState)
<> 154:37f96f9d4de2 308 {
<> 154:37f96f9d4de2 309 return kStatus_NoTransferInProgress;
<> 154:37f96f9d4de2 310 }
<> 154:37f96f9d4de2 311
<> 154:37f96f9d4de2 312 if (!count)
<> 154:37f96f9d4de2 313 {
<> 154:37f96f9d4de2 314 return kStatus_InvalidArgument;
<> 154:37f96f9d4de2 315 }
<> 154:37f96f9d4de2 316
<> 154:37f96f9d4de2 317 *count = handle->txDataSizeAll - DMA_GetRemainingBytes(handle->txDmaHandle->base, handle->txDmaHandle->channel);
<> 154:37f96f9d4de2 318
<> 154:37f96f9d4de2 319 return kStatus_Success;
<> 154:37f96f9d4de2 320 }
<> 154:37f96f9d4de2 321
<> 154:37f96f9d4de2 322 status_t LPUART_TransferGetReceiveCountDMA(LPUART_Type *base, lpuart_dma_handle_t *handle, uint32_t *count)
<> 154:37f96f9d4de2 323 {
<> 154:37f96f9d4de2 324 assert(handle->rxDmaHandle);
<> 154:37f96f9d4de2 325
<> 154:37f96f9d4de2 326 if (kLPUART_RxIdle == handle->rxState)
<> 154:37f96f9d4de2 327 {
<> 154:37f96f9d4de2 328 return kStatus_NoTransferInProgress;
<> 154:37f96f9d4de2 329 }
<> 154:37f96f9d4de2 330
<> 154:37f96f9d4de2 331 if (!count)
<> 154:37f96f9d4de2 332 {
<> 154:37f96f9d4de2 333 return kStatus_InvalidArgument;
<> 154:37f96f9d4de2 334 }
<> 154:37f96f9d4de2 335
<> 154:37f96f9d4de2 336 *count = handle->rxDataSizeAll - DMA_GetRemainingBytes(handle->rxDmaHandle->base, handle->rxDmaHandle->channel);
<> 154:37f96f9d4de2 337
<> 154:37f96f9d4de2 338 return kStatus_Success;
<> 154:37f96f9d4de2 339 }