Iftikhar Aziz / mbed-dev

4545

Dependents:   LSS_Rev_1

Fork of mbed-dev by Umar Naeem

targets/TARGET_STM/TARGET_STM32L4/i2c_device.h@166:33361e55dd8c, 2017-08-23 (annotated)

Committer:
iftaziz
Date:
Wed Aug 23 10:32:38 2017 +0000
Revision:
166:33361e55dd8c
Parent:
156:95d6b41a828b 
r1

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 153:fa9ff456f731 1 /* mbed Microcontroller Library
<> 153:fa9ff456f731 2 *******************************************************************************
<> 153:fa9ff456f731 3 * Copyright (c) 2015, STMicroelectronics
<> 153:fa9ff456f731 4 * All rights reserved.
<> 153:fa9ff456f731 5 *
<> 153:fa9ff456f731 6 * Redistribution and use in source and binary forms, with or without
<> 153:fa9ff456f731 7 * modification, are permitted provided that the following conditions are met:
<> 153:fa9ff456f731 8 *
<> 153:fa9ff456f731 9 * 1. Redistributions of source code must retain the above copyright notice,
<> 153:fa9ff456f731 10 * this list of conditions and the following disclaimer.
<> 153:fa9ff456f731 11 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 153:fa9ff456f731 12 * this list of conditions and the following disclaimer in the documentation
<> 153:fa9ff456f731 13 * and/or other materials provided with the distribution.
<> 153:fa9ff456f731 14 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 153:fa9ff456f731 15 * may be used to endorse or promote products derived from this software
<> 153:fa9ff456f731 16 * without specific prior written permission.
<> 153:fa9ff456f731 17 *
<> 153:fa9ff456f731 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 153:fa9ff456f731 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 153:fa9ff456f731 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 153:fa9ff456f731 21 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 153:fa9ff456f731 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 153:fa9ff456f731 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 153:fa9ff456f731 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 153:fa9ff456f731 25 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 153:fa9ff456f731 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 153:fa9ff456f731 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 153:fa9ff456f731 28 *******************************************************************************
<> 153:fa9ff456f731 29 */
<> 153:fa9ff456f731 30 #ifndef MBED_I2C_DEVICE_H
<> 153:fa9ff456f731 31 #define MBED_I2C_DEVICE_H
<> 153:fa9ff456f731 32
<> 153:fa9ff456f731 33 #include "cmsis.h"
<> 153:fa9ff456f731 34
<> 153:fa9ff456f731 35 #ifdef __cplusplus
<> 153:fa9ff456f731 36 extern "C" {
<> 153:fa9ff456f731 37 #endif
<> 153:fa9ff456f731 38
<> 153:fa9ff456f731 39 #ifdef DEVICE_I2C
<> 153:fa9ff456f731 40
<> 153:fa9ff456f731 41 #define I2C_IP_VERSION_V2
<> 153:fa9ff456f731 42
<> 153:fa9ff456f731 43 #define I2C_IT_ALL (I2C_IT_ERRI|I2C_IT_TCI|I2C_IT_STOPI|I2C_IT_NACKI|I2C_IT_ADDRI|I2C_IT_RXI|I2C_IT_TXI)
<> 153:fa9ff456f731 44
<> 153:fa9ff456f731 45 /* Family specifc settings for clock source */
<> 153:fa9ff456f731 46 #define I2CAPI_I2C1_CLKSRC RCC_I2C1CLKSOURCE_SYSCLK
<> 153:fa9ff456f731 47 #define I2CAPI_I2C2_CLKSRC RCC_I2C2CLKSOURCE_SYSCLK
<> 153:fa9ff456f731 48 #define I2CAPI_I2C3_CLKSRC RCC_I2C3CLKSOURCE_SYSCLK
<> 153:fa9ff456f731 49 #define I2CAPI_I2C4_CLKSRC RCC_I2C4CLKSOURCE_SYSCLK
<> 153:fa9ff456f731 50
<> 153:fa9ff456f731 51 /* Provide the suitable timing depending on requested frequencie */
<> 156:95d6b41a828b 52 static inline uint32_t get_i2c_timing(int hz)
<> 153:fa9ff456f731 53 {
<> 153:fa9ff456f731 54 uint32_t tim = 0;
<> 153:fa9ff456f731 55 if (SystemCoreClock == 80000000) {
<> 153:fa9ff456f731 56 // Common settings: I2C clock = 80 MHz, Analog filter = ON, Digital filter coefficient = 0
<> 153:fa9ff456f731 57 switch (hz) {
<> 153:fa9ff456f731 58 case 100000:
<> 153:fa9ff456f731 59 tim = 0x30C14E6B; // Standard mode with Rise Time = 400ns and Fall Time = 100ns
<> 153:fa9ff456f731 60 break;
<> 153:fa9ff456f731 61 case 400000:
<> 153:fa9ff456f731 62 tim = 0x10D1143A; // Fast mode with Rise Time = 250ns and Fall Time = 100ns
<> 153:fa9ff456f731 63 break;
<> 153:fa9ff456f731 64 case 1000000:
<> 153:fa9ff456f731 65 tim = 0x00810E27; // Fast mode Plus with Rise Time = 60ns and Fall Time = 100ns
<> 153:fa9ff456f731 66 break;
<> 153:fa9ff456f731 67 default:
<> 153:fa9ff456f731 68 break;
<> 153:fa9ff456f731 69 }
<> 153:fa9ff456f731 70 } else if (SystemCoreClock == 48000000) {
<> 153:fa9ff456f731 71 // Common settings: I2C clock = 48 MHz, Analog filter = ON, Digital filter coefficient = 0
<> 153:fa9ff456f731 72 switch (hz) {
<> 153:fa9ff456f731 73 case 100000:
<> 153:fa9ff456f731 74 tim = 0x20A03E55; // Standard mode with Rise Time = 400ns and Fall Time = 100ns
<> 153:fa9ff456f731 75 break;
<> 153:fa9ff456f731 76 case 400000:
<> 153:fa9ff456f731 77 tim = 0x10800C21; // Fast mode with Rise Time = 250ns and Fall Time = 100ns
<> 153:fa9ff456f731 78 break;
<> 153:fa9ff456f731 79 case 1000000:
<> 153:fa9ff456f731 80 tim = 0x00500816; // Fast mode Plus with Rise Time = 60ns and Fall Time = 100ns
<> 153:fa9ff456f731 81 break;
<> 153:fa9ff456f731 82 default:
<> 153:fa9ff456f731 83 break;
<> 153:fa9ff456f731 84 }
<> 153:fa9ff456f731 85 }
<> 153:fa9ff456f731 86 return tim;
<> 153:fa9ff456f731 87 }
<> 153:fa9ff456f731 88
<> 153:fa9ff456f731 89 #ifdef __cplusplus
<> 153:fa9ff456f731 90 }
<> 153:fa9ff456f731 91 #endif
<> 153:fa9ff456f731 92
<> 153:fa9ff456f731 93 #endif // DEVICE_I2C
<> 153:fa9ff456f731 94
<> 153:fa9ff456f731 95 #endif