Iftikhar Aziz / mbed-dev

4545

Dependents:   LSS_Rev_1

Fork of mbed-dev by Umar Naeem

targets/TARGET_ONSEMI/TARGET_NCS36510/spi_api.c@166:33361e55dd8c, 2017-08-23 (annotated)

Committer:
iftaziz
Date:
Wed Aug 23 10:32:38 2017 +0000
Revision:
166:33361e55dd8c
Parent:
158:b23ee177fd68 
r1

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /**
<> 149:156823d33999 2 *******************************************************************************
<> 149:156823d33999 3 * @file spi_api.c
<> 149:156823d33999 4 * @brief Implementation of a sleep functionality
<> 149:156823d33999 5 * @internal
<> 149:156823d33999 6 * @author ON Semiconductor
<> 149:156823d33999 7 * $Rev: 0.1 $
<> 149:156823d33999 8 * $Date: 02-05-2016 $
<> 149:156823d33999 9 ******************************************************************************
<> 149:156823d33999 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
<> 149:156823d33999 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
<> 149:156823d33999 12 * under limited terms and conditions. The terms and conditions pertaining to the software
<> 149:156823d33999 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
<> 149:156823d33999 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
<> 149:156823d33999 15 * if applicable the software license agreement. Do not use this software and/or
<> 149:156823d33999 16 * documentation unless you have carefully read and you agree to the limited terms and
<> 149:156823d33999 17 * conditions. By using this software and/or documentation, you agree to the limited
<> 149:156823d33999 18 * terms and conditions.
<> 149:156823d33999 19 *
<> 149:156823d33999 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 149:156823d33999 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 149:156823d33999 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 149:156823d33999 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 149:156823d33999 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 149:156823d33999 25 * @endinternal
<> 149:156823d33999 26 *
<> 149:156823d33999 27 * @ingroup spi_api
<> 149:156823d33999 28 *
<> 149:156823d33999 29 * @details
<> 149:156823d33999 30 * SPI implementation
<> 149:156823d33999 31 *
<> 149:156823d33999 32 */
<> 149:156823d33999 33 #if DEVICE_SPI
<> 149:156823d33999 34 #include "spi.h"
<> 149:156823d33999 35 #include "PeripheralPins.h"
<> 149:156823d33999 36 #include "objects.h"
<> 149:156823d33999 37 #include "spi_api.h"
<> 149:156823d33999 38 #include "mbed_assert.h"
<> 149:156823d33999 39 #include "memory_map.h"
<> 149:156823d33999 40 #include "spi_ipc7207_map.h"
<> 149:156823d33999 41 #include "crossbar.h"
<> 149:156823d33999 42 #include "clock.h"
<> 149:156823d33999 43 #include "cmsis_nvic.h"
<> 149:156823d33999 44
<> 149:156823d33999 45
<> 149:156823d33999 46 #define SPI_FREQ_MAX 4000000
<> 149:156823d33999 47
<> 149:156823d33999 48 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
<> 149:156823d33999 49 {
<> 149:156823d33999 50 fSpiInit(obj, mosi, miso, sclk, ssel);
<> 149:156823d33999 51 }
<> 149:156823d33999 52 void spi_free(spi_t *obj)
<> 149:156823d33999 53 {
<> 149:156823d33999 54 fSpiClose(obj);
<> 149:156823d33999 55 }
<> 149:156823d33999 56
<> 149:156823d33999 57 void spi_format(spi_t *obj, int bits, int mode, int slave)
<> 149:156823d33999 58 {
<> 149:156823d33999 59 /* Clear word width | Slave/Master | CPOL | CPHA | MSB first bits in control register */
Kojto 158:b23ee177fd68 60 obj->membase->CONTROL.WORD &= ~(uint32_t)((True << SPI_WORD_WIDTH_BIT_POS) |
Kojto 158:b23ee177fd68 61 (True << SPI_SLAVE_MASTER_BIT_POS) |
Kojto 158:b23ee177fd68 62 (True << SPI_CPOL_BIT_POS) |
Kojto 158:b23ee177fd68 63 (True << SPI_CPHA_BIT_POS));
<> 149:156823d33999 64
<> 149:156823d33999 65 /* Configure word width | Slave/Master | CPOL | CPHA | MSB first bits in control register */
Kojto 158:b23ee177fd68 66 obj->membase->CONTROL.WORD |= (uint32_t)(((bits >> 0x4) << SPI_WORD_WIDTH_BIT_POS) |
Kojto 158:b23ee177fd68 67 (!slave << SPI_SLAVE_MASTER_BIT_POS) |
Kojto 158:b23ee177fd68 68 ((mode >> 0x1) << SPI_CPOL_BIT_POS) |
Kojto 158:b23ee177fd68 69 ((mode & 0x1) << SPI_CPHA_BIT_POS));
<> 149:156823d33999 70 }
<> 149:156823d33999 71
<> 149:156823d33999 72 void spi_frequency(spi_t *obj, int hz)
<> 149:156823d33999 73 {
<> 149:156823d33999 74 /* If the frequency is outside the allowable range, set it to the max */
<> 149:156823d33999 75 if(hz > SPI_FREQ_MAX) {
<> 149:156823d33999 76 hz = SPI_FREQ_MAX;
<> 149:156823d33999 77 }
<> 149:156823d33999 78 obj->membase->FDIV = ((fClockGetPeriphClockfrequency() / hz) >> 1) - 1;
<> 149:156823d33999 79 }
<> 149:156823d33999 80
<> 149:156823d33999 81 int spi_master_write(spi_t *obj, int value)
<> 149:156823d33999 82 {
<> 149:156823d33999 83 return(fSpiWriteB(obj, value));
<> 149:156823d33999 84 }
<> 149:156823d33999 85
<> 149:156823d33999 86 int spi_busy(spi_t *obj)
<> 149:156823d33999 87 {
<> 149:156823d33999 88 return(obj->membase->STATUS.BITS.XFER_IP);
<> 149:156823d33999 89 }
<> 149:156823d33999 90
<> 149:156823d33999 91 uint8_t spi_get_module(spi_t *obj)
<> 149:156823d33999 92 {
<> 149:156823d33999 93 if(obj->membase == SPI1REG) {
<> 149:156823d33999 94 return 0; /* UART #1 */
<> 149:156823d33999 95 } else if(obj->membase == SPI2REG) {
<> 149:156823d33999 96 return 1; /* UART #2 */
<> 149:156823d33999 97 } else {
<> 149:156823d33999 98 return 2; /* Invalid address */
<> 149:156823d33999 99 }
<> 149:156823d33999 100 }
<> 149:156823d33999 101
<> 149:156823d33999 102 int spi_slave_receive(spi_t *obj)
<> 149:156823d33999 103 {
<> 150:02e0a0aed4ec 104 if(obj->membase->STATUS.BITS.RX_EMPTY != True){ /* if receive status is not empty */
<> 150:02e0a0aed4ec 105 return True; /* Byte available to read */
<> 150:02e0a0aed4ec 106 }
<> 150:02e0a0aed4ec 107 return False; /* Byte not available to read */
<> 149:156823d33999 108 }
<> 149:156823d33999 109
<> 149:156823d33999 110 int spi_slave_read(spi_t *obj)
<> 149:156823d33999 111 {
<> 150:02e0a0aed4ec 112 int byte;
<> 150:02e0a0aed4ec 113
<> 150:02e0a0aed4ec 114 while (obj->membase->STATUS.BITS.RX_EMPTY == True); /* Wait till Receive status is empty */
<> 149:156823d33999 115 byte = obj->membase->RX_DATA;
<> 149:156823d33999 116 return byte;
<> 149:156823d33999 117 }
<> 149:156823d33999 118
<> 149:156823d33999 119 void spi_slave_write(spi_t *obj, int value)
<> 149:156823d33999 120 {
<> 150:02e0a0aed4ec 121 while((obj->membase->STATUS.BITS.TX_FULL == True) && (obj->membase->STATUS.BITS.RX_FULL == True)); /* Wait till Tx/Rx status is full */
<> 149:156823d33999 122 obj->membase->TX_DATA = value;
<> 149:156823d33999 123 }
<> 149:156823d33999 124
<> 150:02e0a0aed4ec 125 #if DEVICE_SPI_ASYNCH /* TODO Not yet implemented */
<> 149:156823d33999 126
<> 149:156823d33999 127 void spi_master_transfer(spi_t *obj, void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t handler, uint32_t event, DMAUsage hint)
<> 149:156823d33999 128 {
<> 149:156823d33999 129
<> 149:156823d33999 130 uint32_t i;
<> 149:156823d33999 131 int ndata = 0;
<> 149:156823d33999 132 uint16_t *tx_ptr = (uint16_t *) tx;
<> 149:156823d33999 133
<> 149:156823d33999 134 if(obj->spi->CONTROL.BITS.WORD_WIDTH == 0) {
<> 149:156823d33999 135 /* Word size 8 bits */
<> 149:156823d33999 136 WORD_WIDTH_MASK = 0xFF;
<> 149:156823d33999 137 } else if(obj->spi->CONTROL.BITS.WORD_WIDTH == 1) {
<> 149:156823d33999 138 /* Word size 16 bits */
<> 149:156823d33999 139 WORD_WIDTH_MASK = 0xFFFF;
<> 149:156823d33999 140 } else {
<> 149:156823d33999 141 /* Word size 32 bits */
<> 149:156823d33999 142 WORD_WIDTH_MASK = 0xFFFFFFFF;
<> 149:156823d33999 143 }
<> 149:156823d33999 144
<> 149:156823d33999 145 //frame size
<> 149:156823d33999 146 if(tx_length == 0) {
<> 149:156823d33999 147 tx_length = rx_length;
<> 149:156823d33999 148 tx = (void*) 0;
<> 149:156823d33999 149 }
<> 149:156823d33999 150 //set tx rx buffer
<> 149:156823d33999 151 obj->tx_buff.buffer = (void *)tx;
<> 149:156823d33999 152 obj->rx_buff.buffer = rx;
<> 149:156823d33999 153 obj->tx_buff.length = tx_length;
<> 149:156823d33999 154 obj->rx_buff.length = rx_length;
<> 149:156823d33999 155 obj->tx_buff.pos = 0;
<> 149:156823d33999 156 obj->rx_buff.pos = 0;
<> 149:156823d33999 157 obj->tx_buff.width = bit_width;
<> 149:156823d33999 158 obj->rx_buff.width = bit_width;
<> 149:156823d33999 159
<> 149:156823d33999 160
<> 149:156823d33999 161 if((obj->spi.bits == 9) && (tx != 0)) {
<> 149:156823d33999 162 // Make sure we don't have inadvertent non-zero bits outside 9-bit frames which could trigger unwanted operation
<> 149:156823d33999 163 for(i = 0; i < (tx_length / 2); i++) {
<> 149:156823d33999 164 tx_ptr[i] &= 0x1FF;
<> 149:156823d33999 165 }
<> 149:156823d33999 166 }
<> 149:156823d33999 167
<> 149:156823d33999 168
<> 149:156823d33999 169 // enable events
<> 149:156823d33999 170
<> 149:156823d33999 171 obj->spi.event |= event;
<> 149:156823d33999 172
<> 149:156823d33999 173
<> 149:156823d33999 174 // set sleep_level
<> 149:156823d33999 175 enable irq
<> 149:156823d33999 176
<> 149:156823d33999 177 //write async
<> 149:156823d33999 178
<> 149:156823d33999 179 if ( && ) {
<> 149:156823d33999 180
<> 149:156823d33999 181 }
<> 149:156823d33999 182 while ((obj->tx_buff.pos < obj->tx_buff.length) &&
<> 149:156823d33999 183 (obj->spi->STATUS.BITS.TX_FULL == False) &&
<> 149:156823d33999 184 (obj->spi->STATUS.BITS.RX_FULL == False)) {
<> 149:156823d33999 185 // spi_buffer_tx_write(obj);
<> 149:156823d33999 186
<> 149:156823d33999 187 if (obj->tx_buff.buffer == (void *)0) {
<> 149:156823d33999 188 data = SPI_FILL_WORD;
<> 149:156823d33999 189 } else {
<> 149:156823d33999 190 uint16_t *tx = (uint16_t *)(obj->tx_buff.buffer);
<> 149:156823d33999 191 data = tx[obj->tx_buff.pos] & 0xFF;
<> 149:156823d33999 192 }
<> 149:156823d33999 193 obj->spi->TX_DATA = data;
<> 149:156823d33999 194 }
<> 149:156823d33999 195
<> 149:156823d33999 196 ndata++;
<> 149:156823d33999 197 }
<> 149:156823d33999 198 return ndata;
<> 149:156823d33999 199
<> 149:156823d33999 200 }
<> 149:156823d33999 201
<> 149:156823d33999 202 uint32_t spi_irq_handler_asynch(spi_t *obj)
<> 149:156823d33999 203 {
<> 149:156823d33999 204 }
<> 149:156823d33999 205
<> 149:156823d33999 206 uint8_t spi_active(spi_t *obj)
<> 149:156823d33999 207 {
<> 149:156823d33999 208 }
<> 149:156823d33999 209
<> 149:156823d33999 210 void spi_abort_asynch(spi_t *obj)
<> 149:156823d33999 211 {
<> 149:156823d33999 212 }
<> 149:156823d33999 213
<> 149:156823d33999 214 #endif /* DEVICE_SPI_ASYNCH */
<> 149:156823d33999 215 #endif /* DEVICE_SPI */