Iftikhar Aziz / mbed-dev

4545

Dependents:   LSS_Rev_1

Fork of mbed-dev by Umar Naeem

targets/TARGET_ONSEMI/TARGET_NCS36510/rtc.c@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Child:
150:02e0a0aed4ec
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /**
<> 149:156823d33999 2 *******************************************************************************
<> 149:156823d33999 3 * @file rtc.c
<> 149:156823d33999 4 * @brief Implementation of a Rtc driver
<> 149:156823d33999 5 * @internal
<> 149:156823d33999 6 * @author ON Semiconductor
<> 149:156823d33999 7 * $Rev: 3525 $
<> 149:156823d33999 8 * $Date: 2015-07-20 15:24:25 +0530 (Mon, 20 Jul 2015) $
<> 149:156823d33999 9 ******************************************************************************
<> 149:156823d33999 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
<> 149:156823d33999 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
<> 149:156823d33999 12 * under limited terms and conditions. The terms and conditions pertaining to the software
<> 149:156823d33999 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
<> 149:156823d33999 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
<> 149:156823d33999 15 * if applicable the software license agreement. Do not use this software and/or
<> 149:156823d33999 16 * documentation unless you have carefully read and you agree to the limited terms and
<> 149:156823d33999 17 * conditions. By using this software and/or documentation, you agree to the limited
<> 149:156823d33999 18 * terms and conditions.
<> 149:156823d33999 19 *
<> 149:156823d33999 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 149:156823d33999 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 149:156823d33999 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 149:156823d33999 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 149:156823d33999 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 149:156823d33999 25 * @endinternal
<> 149:156823d33999 26 *
<> 149:156823d33999 27 * @ingroup rtc
<> 149:156823d33999 28 *
<> 149:156823d33999 29 * @details
<> 149:156823d33999 30 * A real-time clock (RTC) is a computer clock ,that keeps track of the current time. The heart of the RTC is a series of
<> 149:156823d33999 31 * freely running counters one for each time unit, The series of counters is linked as follows: a roll over event of
<> 149:156823d33999 32 * the seconds counter produces a minutes enable pulse; a roll over event of the minutes counter produces an hours
<> 149:156823d33999 33 * enable pulse, etc.Note that all Counter registers are in an undefined state on power-up.
<> 149:156823d33999 34 * Use the Reset bit in the Control Register to reset the counters to their default values.
<> 149:156823d33999 35 * DIVISOR is the register containing the value to divide the clock frequency to produce 1Hz strobe ; 1Hz strobe is used
<> 149:156823d33999 36 * internally to time the incrementing of the Seconds Counter.
<> 149:156823d33999 37 * There is a set of register to set the values in the counter for each time unit.from where time is start to increment.
<> 149:156823d33999 38 * There is another set of register to set the ALARM ...Each of the Alarm Registers can be programmed with a value that
<> 149:156823d33999 39 * is used to compare to a Counter Register in order to produce an alarm (an interrupt) when the values match.
<> 149:156823d33999 40 * There is a programmable bit in each Alarm Register that determines if the alarm occurs upon a value match, or
<> 149:156823d33999 41 * if the alarm occurs upon a Counter increment condition.
<> 149:156823d33999 42 *
<> 149:156823d33999 43 */
<> 149:156823d33999 44 #include "rtc.h"
<> 149:156823d33999 45 #include "mbed_assert.h"
<> 149:156823d33999 46
<> 149:156823d33999 47 static uint16_t SubSecond;
<> 149:156823d33999 48 static uint64_t LastRtcTimeus;
<> 149:156823d33999 49
<> 149:156823d33999 50 /* See rtc.h for details */
<> 149:156823d33999 51 void fRtcInit(void)
<> 149:156823d33999 52 {
<> 149:156823d33999 53 CLOCK_ENABLE(CLOCK_RTC); /* enable rtc peripheral */
<> 149:156823d33999 54 CLOCKREG->CCR.BITS.RTCEN = True; /* Enable RTC clock 32K */
<> 149:156823d33999 55
<> 149:156823d33999 56 /* Reset RTC control register */
<> 149:156823d33999 57 RTCREG->CONTROL.WORD = False;
<> 149:156823d33999 58
<> 149:156823d33999 59 /* Initialize all counters */
<> 149:156823d33999 60 RTCREG->SECOND_COUNTER = False;
<> 149:156823d33999 61 RTCREG->SUB_SECOND_COUNTER = False;
<> 149:156823d33999 62 RTCREG->SECOND_ALARM = False;
<> 149:156823d33999 63 RTCREG->SUB_SECOND_ALARM = False;
<> 149:156823d33999 64 LastRtcTimeus = 0;
<> 149:156823d33999 65
<> 149:156823d33999 66 /* Reset RTC Status register */
<> 149:156823d33999 67 RTCREG->STATUS.WORD = False;
<> 149:156823d33999 68
<> 149:156823d33999 69 /* Clear interrupt status */
<> 149:156823d33999 70 RTCREG->INT_CLEAR.WORD = False;
<> 149:156823d33999 71
<> 149:156823d33999 72 /* Start sec & sub_sec counter */
<> 149:156823d33999 73 while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True);/* Wait previous write to complete */
<> 149:156823d33999 74 RTCREG->CONTROL.WORD |= ((True << RTC_CONTROL_SUBSEC_CNT_START_BIT_POS) |
<> 149:156823d33999 75 (True << RTC_CONTROL_SEC_CNT_START_BIT_POS));
<> 149:156823d33999 76
<> 149:156823d33999 77 /* enable interruption associated with the rtc at NVIC level */
<> 149:156823d33999 78 NVIC_SetVector(Rtc_IRQn,(uint32_t)fRtcHandler); /* TODO define lp_ticker_isr */
<> 149:156823d33999 79 NVIC_ClearPendingIRQ(Rtc_IRQn);
<> 149:156823d33999 80 NVIC_EnableIRQ(Rtc_IRQn);
<> 149:156823d33999 81
<> 149:156823d33999 82 while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
<> 149:156823d33999 83
<> 149:156823d33999 84 return;
<> 149:156823d33999 85 }
<> 149:156823d33999 86
<> 149:156823d33999 87 /* See rtc.h for details */
<> 149:156823d33999 88 void fRtcFree(void)
<> 149:156823d33999 89 {
<> 149:156823d33999 90 /* Reset RTC control register */
<> 149:156823d33999 91 RTCREG->CONTROL.WORD = False;
<> 149:156823d33999 92
<> 149:156823d33999 93 /* disable interruption associated with the rtc */
<> 149:156823d33999 94 NVIC_DisableIRQ(Rtc_IRQn);
<> 149:156823d33999 95
<> 149:156823d33999 96 while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
<> 149:156823d33999 97 }
<> 149:156823d33999 98
<> 149:156823d33999 99 /* See rtc.h for details */
<> 149:156823d33999 100 void fRtcSetInterrupt(uint32_t timestamp)
<> 149:156823d33999 101 {
<> 149:156823d33999 102 SubSecond = False;
<> 149:156823d33999 103 uint32_t Second = False;
<> 149:156823d33999 104 uint8_t DividerAdjust = 1;
<> 149:156823d33999 105
<> 149:156823d33999 106 if(timestamp) {
<> 149:156823d33999 107 if(timestamp >= RTC_SEC_TO_US) {
<> 149:156823d33999 108 /* TimeStamp is big enough to set second alarm */
<> 149:156823d33999 109 Second = ((timestamp / RTC_SEC_TO_US) & RTC_SEC_MASK); /* Convert micro second to second */
<> 149:156823d33999 110 RTCREG->SECOND_ALARM = Second; /* Write to alarm register */
<> 149:156823d33999 111
<> 149:156823d33999 112 /* Enable second interrupt */
<> 149:156823d33999 113 RTCREG->CONTROL.WORD |= (True << RTC_CONTROL_SEC_CNT_INT_BIT_POS);
<> 149:156823d33999 114 }
<> 149:156823d33999 115 timestamp = timestamp - Second * RTC_SEC_TO_US; /* Take out micro second for sub second alarm */
<> 149:156823d33999 116 if(timestamp > False) {
<> 149:156823d33999 117 /* We have some thing for sub second */
<> 149:156823d33999 118
<> 149:156823d33999 119 /* Convert micro second to sub_seconds(each count = 30.5 us) */
<> 149:156823d33999 120 if(timestamp > 131000) {
<> 149:156823d33999 121 DividerAdjust = 100;
<> 149:156823d33999 122 }
<> 149:156823d33999 123
<> 149:156823d33999 124 volatile uint64_t Temp = (timestamp / DividerAdjust * RTC_CLOCK_HZ);
<> 149:156823d33999 125 Temp = (uint64_t)(Temp / RTC_SEC_TO_US * DividerAdjust);
<> 149:156823d33999 126 SubSecond = Temp & RTC_SUB_SEC_MASK;
<> 149:156823d33999 127
<> 149:156823d33999 128 if(SubSecond <= 5) {
<> 149:156823d33999 129 SubSecond = 0;
<> 149:156823d33999 130 }
<> 149:156823d33999 131
<> 149:156823d33999 132
<> 149:156823d33999 133 if(SubSecond > False) {
<> 149:156823d33999 134 /* Second interrupt not enabled */
<> 149:156823d33999 135
<> 149:156823d33999 136 /* Set SUB SEC_ALARM */
<> 149:156823d33999 137 RTCREG->SUB_SECOND_ALARM = SubSecond; /* Write to sub second alarm */
<> 149:156823d33999 138
<> 149:156823d33999 139 /* Enable sub second interrupt */
<> 149:156823d33999 140 while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True);
<> 149:156823d33999 141 RTCREG->CONTROL.WORD |= (True << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS);
<> 149:156823d33999 142 }
<> 149:156823d33999 143 }
<> 149:156823d33999 144
<> 149:156823d33999 145 while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
<> 149:156823d33999 146 }
<> 149:156823d33999 147 return;
<> 149:156823d33999 148 }
<> 149:156823d33999 149
<> 149:156823d33999 150 /* See rtc.h for details */
<> 149:156823d33999 151 void fRtcDisableInterrupt(void)
<> 149:156823d33999 152 {
<> 149:156823d33999 153 /* Disable subsec/sec interrupt */
<> 149:156823d33999 154 RTCREG->CONTROL.WORD &= ~((RTC_ALL_INTERRUPT_BIT_VAL) << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS);
<> 149:156823d33999 155 while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
<> 149:156823d33999 156 }
<> 149:156823d33999 157
<> 149:156823d33999 158 /* See rtc.h for details */
<> 149:156823d33999 159 void fRtcEnableInterrupt(void)
<> 149:156823d33999 160 {
<> 149:156823d33999 161 /* Disable subsec/sec interrupt */
<> 149:156823d33999 162 RTCREG->CONTROL.WORD |= ((RTC_ALL_INTERRUPT_BIT_VAL) << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS);
<> 149:156823d33999 163 while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
<> 149:156823d33999 164 }
<> 149:156823d33999 165
<> 149:156823d33999 166 /* See rtc.h for details */
<> 149:156823d33999 167 void fRtcClearInterrupt(void)
<> 149:156823d33999 168 {
<> 149:156823d33999 169 /* Disable subsec/sec interrupt */
<> 149:156823d33999 170 /* Clear sec & sub_sec interrupts */
<> 149:156823d33999 171 RTCREG->INT_CLEAR.WORD = ((True << RTC_INT_CLR_SUB_SEC_BIT_POS) |
<> 149:156823d33999 172 (True << RTC_INT_CLR_SEC_BIT_POS));
<> 149:156823d33999 173 while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
<> 149:156823d33999 174 }
<> 149:156823d33999 175
<> 149:156823d33999 176 /* See rtc.h for details */
<> 149:156823d33999 177 uint64_t fRtcRead(void)
<> 149:156823d33999 178 {
<> 149:156823d33999 179 uint32_t Second;
<> 149:156823d33999 180 uint16_t SubSecond;
<> 149:156823d33999 181
<> 149:156823d33999 182 /* Hardware Bug fix: The rollover of the sub-second counter initiates the increment of the second counter.
<> 149:156823d33999 183 * That means there is one cycle where the sub-second has rolled back to zero and the second counter has not incremented
<> 149:156823d33999 184 * and a read during that cycle will be incorrect. That will occur for one RTC cycle and that is about 31us of exposure.
<> 149:156823d33999 185 * If you read a zero in the sub-second counter then increment the second counter by 1.
<> 149:156823d33999 186 * Alternatively, subtract 1 from the Sub-seconds counter to align the Second and Sub-Second rollover.
<> 149:156823d33999 187 */
<> 149:156823d33999 188
<> 149:156823d33999 189 /* Read the Second and Sub-second counters, then read the Second counter again.
<> 149:156823d33999 190 * If it changed, then the Second rolled over while reading Sub-seconds, so go back and read them both again.
<> 149:156823d33999 191 */
<> 149:156823d33999 192
<> 149:156823d33999 193 do {
<> 149:156823d33999 194 Second = RTCREG->SECOND_COUNTER; /* Get SEC_COUNTER reg value */
<> 149:156823d33999 195 SubSecond = (RTCREG->SUB_SECOND_COUNTER - 1) & 0x7FFF; /* Get SUB_SEC_COUNTER reg value */
<> 149:156823d33999 196 } while (Second != RTCREG->SECOND_COUNTER); /* Repeat if the second has changed */
<> 149:156823d33999 197
<> 149:156823d33999 198 //note: casting to float removed to avoid reduction in resolution
<> 149:156823d33999 199 uint64_t RtcTimeus = ((uint64_t)SubSecond * RTC_SEC_TO_US / RTC_CLOCK_HZ) + ((uint64_t)Second * RTC_SEC_TO_US);
<> 149:156823d33999 200
<> 149:156823d33999 201 /*check that the time did not go backwards */
<> 149:156823d33999 202 MBED_ASSERT(RtcTimeus >= LastRtcTimeus);
<> 149:156823d33999 203 LastRtcTimeus = RtcTimeus;
<> 149:156823d33999 204
<> 149:156823d33999 205 return RtcTimeus;
<> 149:156823d33999 206 }
<> 149:156823d33999 207
<> 149:156823d33999 208 /* See rtc.h for details */
<> 149:156823d33999 209 void fRtcWrite(uint64_t RtcTimeus)
<> 149:156823d33999 210 {
<> 149:156823d33999 211 uint32_t Second = 0;
<> 149:156823d33999 212 uint16_t SubSecond = 0;
<> 149:156823d33999 213 /* Stop RTC */
<> 149:156823d33999 214 RTCREG->CONTROL.WORD &= ~((True << RTC_CONTROL_SUBSEC_CNT_START_BIT_POS) |
<> 149:156823d33999 215 (True << RTC_CONTROL_SEC_CNT_START_BIT_POS));
<> 149:156823d33999 216
<> 149:156823d33999 217 if(RtcTimeus > RTC_SEC_TO_US) {
<> 149:156823d33999 218 /* TimeStamp is big enough to set second counter */
<> 149:156823d33999 219 Second = ((RtcTimeus / RTC_SEC_TO_US) & RTC_SEC_MASK);
<> 149:156823d33999 220 }
<> 149:156823d33999 221 RTCREG->SECOND_COUNTER = Second;
<> 149:156823d33999 222 RtcTimeus = RtcTimeus - (Second * RTC_SEC_TO_US);
<> 149:156823d33999 223 if(RtcTimeus > False) {
<> 149:156823d33999 224 /* Convert TimeStamp to sub_seconds */
<> 149:156823d33999 225 SubSecond = (uint16_t)((float)(RtcTimeus * RTC_CLOCK_HZ / RTC_SEC_TO_US)) & RTC_SUB_SEC_MASK;
<> 149:156823d33999 226 }
<> 149:156823d33999 227 /* Set SUB_SEC_ALARM */
<> 149:156823d33999 228 RTCREG->SUB_SECOND_COUNTER = SubSecond;
<> 149:156823d33999 229
<> 149:156823d33999 230 while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
<> 149:156823d33999 231 /* Start RTC */
<> 149:156823d33999 232 RTCREG->CONTROL.WORD |= ((True << RTC_CONTROL_SUBSEC_CNT_START_BIT_POS) |
<> 149:156823d33999 233 (True << RTC_CONTROL_SEC_CNT_START_BIT_POS));
<> 149:156823d33999 234
<> 149:156823d33999 235 while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
<> 149:156823d33999 236 }
<> 149:156823d33999 237
<> 149:156823d33999 238 /* See rtc.h for details */
<> 149:156823d33999 239 void fRtcHandler(void)
<> 149:156823d33999 240 {
<> 149:156823d33999 241 /* SUB_SECOND/SECOND interrupt occured */
<> 149:156823d33999 242 volatile uint32_t TempStatus = RTCREG->STATUS.WORD;
<> 149:156823d33999 243
<> 149:156823d33999 244 /* Disable RTC interrupt */
<> 149:156823d33999 245 NVIC_DisableIRQ(Rtc_IRQn);
<> 149:156823d33999 246
<> 149:156823d33999 247 /* Clear sec & sub_sec interrupts */
<> 149:156823d33999 248 RTCREG->INT_CLEAR.WORD = ((True << RTC_INT_CLR_SUB_SEC_BIT_POS) |
<> 149:156823d33999 249 (True << RTC_INT_CLR_SEC_BIT_POS));
<> 149:156823d33999 250
<> 149:156823d33999 251 /* TODO ANDing SUB_SEC & SEC interrupt - work around for RTC issue - will be resolved in REV G */
<> 149:156823d33999 252 if(TempStatus & RTC_SEC_INT_STATUS_MASK) {
<> 149:156823d33999 253 /* Second interrupt occured */
<> 149:156823d33999 254 if(SubSecond > False) {
<> 149:156823d33999 255 /* Set SUB SEC_ALARM */
<> 149:156823d33999 256 RTCREG->SUB_SECOND_ALARM = SubSecond + RTCREG->SUB_SECOND_COUNTER;
<> 149:156823d33999 257 /* Enable sub second interrupt */
<> 149:156823d33999 258 RTCREG->CONTROL.WORD |= (True << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS);
<> 149:156823d33999 259 } else {
<> 149:156823d33999 260 /* We reach here after second interrupt is occured */
<> 149:156823d33999 261 RTCREG->CONTROL.WORD &= ~(True << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS) |
<> 149:156823d33999 262 (True << RTC_CONTROL_SEC_CNT_INT_BIT_POS);
<> 149:156823d33999 263 }
<> 149:156823d33999 264 } else {
<> 149:156823d33999 265 /* We reach here after sub_second or (Sub second + second) interrupt occured */
<> 149:156823d33999 266 /* Disable Second and sub_second interrupt */
<> 149:156823d33999 267 RTCREG->CONTROL.WORD &= ~(True << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS) |
<> 149:156823d33999 268 (True << RTC_CONTROL_SEC_CNT_INT_BIT_POS);
<> 149:156823d33999 269 }
<> 149:156823d33999 270
<> 149:156823d33999 271 NVIC_EnableIRQ(Rtc_IRQn);
<> 149:156823d33999 272
<> 149:156823d33999 273 while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
<> 149:156823d33999 274
<> 149:156823d33999 275 lp_ticker_irq_handler();
<> 149:156823d33999 276 }
<> 149:156823d33999 277
<> 149:156823d33999 278 boolean fIsRtcEnabled(void)
<> 149:156823d33999 279 {
<> 149:156823d33999 280 if(RTCREG->CONTROL.BITS.SUB_SEC_COUNTER_EN | RTCREG->CONTROL.BITS.SEC_COUNTER_EN) {
<> 149:156823d33999 281 return True;
<> 149:156823d33999 282 } else {
<> 149:156823d33999 283 return False;
<> 149:156823d33999 284 }
<> 149:156823d33999 285 }