Iftikhar Aziz / mbed-dev

4545

Dependents:   LSS_Rev_1

Fork of mbed-dev by Umar Naeem

targets/TARGET_Freescale/TARGET_K20XX/clk_freqs.h@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/hal/TARGET_Freescale/TARGET_K20XX/clk_freqs.h@144:ef7eb2e8f9f7 
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2006-2015 ARM Limited
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 */
<> 144:ef7eb2e8f9f7 16 #ifndef CLK_FREQS_H
<> 144:ef7eb2e8f9f7 17 #define CLK_FREQS_H
<> 144:ef7eb2e8f9f7 18
<> 144:ef7eb2e8f9f7 19 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 20 extern "C" {
<> 144:ef7eb2e8f9f7 21 #endif
<> 144:ef7eb2e8f9f7 22
<> 144:ef7eb2e8f9f7 23 /*!
<> 144:ef7eb2e8f9f7 24 * \brief Get the peripheral bus clock frequency
<> 144:ef7eb2e8f9f7 25 * \return Bus frequency
<> 144:ef7eb2e8f9f7 26 */
<> 144:ef7eb2e8f9f7 27 static inline uint32_t bus_frequency(void) {
<> 144:ef7eb2e8f9f7 28 return SystemCoreClock / (((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV2_MASK) >> SIM_CLKDIV1_OUTDIV2_SHIFT) + 1);
<> 144:ef7eb2e8f9f7 29 }
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 /*!
<> 144:ef7eb2e8f9f7 32 * \brief Get external oscillator (crystal) frequency
<> 144:ef7eb2e8f9f7 33 * \return External osc frequency
<> 144:ef7eb2e8f9f7 34 */
<> 144:ef7eb2e8f9f7 35 static uint32_t extosc_frequency(void) {
<> 144:ef7eb2e8f9f7 36 uint32_t MCGClock = SystemCoreClock * (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT));
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(2)) //MCG clock = external reference clock
<> 144:ef7eb2e8f9f7 39 return MCGClock;
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0)) { //PLL/FLL is selected
<> 144:ef7eb2e8f9f7 42 uint32_t divider, multiplier;
<> 144:ef7eb2e8f9f7 43 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { //FLL is selected
<> 144:ef7eb2e8f9f7 44 if ((MCG->S & MCG_S_IREFST_MASK) == 0x0u) { //FLL uses external reference
<> 144:ef7eb2e8f9f7 45 divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
<> 144:ef7eb2e8f9f7 46 if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u)
<> 144:ef7eb2e8f9f7 47 divider <<= 5u;
<> 144:ef7eb2e8f9f7 48 /* Select correct multiplier to calculate the MCG output clock */
<> 144:ef7eb2e8f9f7 49 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
<> 144:ef7eb2e8f9f7 50 case 0x0u:
<> 144:ef7eb2e8f9f7 51 multiplier = 640u;
<> 144:ef7eb2e8f9f7 52 break;
<> 144:ef7eb2e8f9f7 53 case 0x20u:
<> 144:ef7eb2e8f9f7 54 multiplier = 1280u;
<> 144:ef7eb2e8f9f7 55 break;
<> 144:ef7eb2e8f9f7 56 case 0x40u:
<> 144:ef7eb2e8f9f7 57 multiplier = 1920u;
<> 144:ef7eb2e8f9f7 58 break;
<> 144:ef7eb2e8f9f7 59 case 0x60u:
<> 144:ef7eb2e8f9f7 60 multiplier = 2560u;
<> 144:ef7eb2e8f9f7 61 break;
<> 144:ef7eb2e8f9f7 62 case 0x80u:
<> 144:ef7eb2e8f9f7 63 multiplier = 732u;
<> 144:ef7eb2e8f9f7 64 break;
<> 144:ef7eb2e8f9f7 65 case 0xA0u:
<> 144:ef7eb2e8f9f7 66 multiplier = 1464u;
<> 144:ef7eb2e8f9f7 67 break;
<> 144:ef7eb2e8f9f7 68 case 0xC0u:
<> 144:ef7eb2e8f9f7 69 multiplier = 2197u;
<> 144:ef7eb2e8f9f7 70 break;
<> 144:ef7eb2e8f9f7 71 case 0xE0u:
<> 144:ef7eb2e8f9f7 72 default:
<> 144:ef7eb2e8f9f7 73 multiplier = 2929u;
<> 144:ef7eb2e8f9f7 74 break;
<> 144:ef7eb2e8f9f7 75 }
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 return MCGClock * divider / multiplier;
<> 144:ef7eb2e8f9f7 78 }
<> 144:ef7eb2e8f9f7 79 } else { //PLL is selected
<> 144:ef7eb2e8f9f7 80 divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
<> 144:ef7eb2e8f9f7 81 multiplier = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
<> 144:ef7eb2e8f9f7 82 return MCGClock * divider / multiplier;
<> 144:ef7eb2e8f9f7 83 }
<> 144:ef7eb2e8f9f7 84 }
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 //In all other cases either there is no crystal or we cannot determine it
<> 144:ef7eb2e8f9f7 87 //For example when the FLL is running on the internal reference, and there is also an
<> 144:ef7eb2e8f9f7 88 //external crystal. However these are unlikely situations
<> 144:ef7eb2e8f9f7 89 return 0;
<> 144:ef7eb2e8f9f7 90 }
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 //Get MCG PLL/2 or FLL frequency, depending on which one is active, sets PLLFLLSEL bit
<> 144:ef7eb2e8f9f7 93 static uint32_t mcgpllfll_frequency(void) {
<> 144:ef7eb2e8f9f7 94 if ((MCG->C1 & MCG_C1_CLKS_MASK) != MCG_C1_CLKS(0)) //PLL/FLL is not selected
<> 144:ef7eb2e8f9f7 95 return 0;
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 uint32_t MCGClock = SystemCoreClock * (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT));
<> 144:ef7eb2e8f9f7 98 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { //FLL is selected
<> 144:ef7eb2e8f9f7 99 SIM->SOPT2 &= ~SIM_SOPT2_PLLFLLSEL_MASK; //MCG peripheral clock is FLL output
<> 144:ef7eb2e8f9f7 100 return MCGClock;
<> 144:ef7eb2e8f9f7 101 } else { //PLL is selected
<> 144:ef7eb2e8f9f7 102 SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; //MCG peripheral clock is PLL output
<> 144:ef7eb2e8f9f7 103 return MCGClock;
<> 144:ef7eb2e8f9f7 104 }
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 //It is possible the SystemCoreClock isn't running on the PLL, and the PLL is still active
<> 144:ef7eb2e8f9f7 107 //for the peripherals, this is however an unlikely setup
<> 144:ef7eb2e8f9f7 108 }
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 112 }
<> 144:ef7eb2e8f9f7 113 #endif
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 #endif