iforce2d Chris / Mbed 2 deprecated ubxDistanceMeter

Displays distance to start location on OLED screen.

Dependencies:   mbed

u8g_dev_st7920_192x32.c@0:972874f31c98, 2018-03-07 (annotated)

Committer:
iforce2d
Date:
Wed Mar 07 12:49:14 2018 +0000
Revision:
0:972874f31c98
First commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
iforce2d 0:972874f31c98 1 /*
iforce2d 0:972874f31c98 2
iforce2d 0:972874f31c98 3 u8g_dev_st7920_192x32.c
iforce2d 0:972874f31c98 4
iforce2d 0:972874f31c98 5 Universal 8bit Graphics Library
iforce2d 0:972874f31c98 6
iforce2d 0:972874f31c98 7 Copyright (c) 2011, olikraus@gmail.com
iforce2d 0:972874f31c98 8 All rights reserved.
iforce2d 0:972874f31c98 9
iforce2d 0:972874f31c98 10 Redistribution and use in source and binary forms, with or without modification,
iforce2d 0:972874f31c98 11 are permitted provided that the following conditions are met:
iforce2d 0:972874f31c98 12
iforce2d 0:972874f31c98 13 * Redistributions of source code must retain the above copyright notice, this list
iforce2d 0:972874f31c98 14 of conditions and the following disclaimer.
iforce2d 0:972874f31c98 15
iforce2d 0:972874f31c98 16 * Redistributions in binary form must reproduce the above copyright notice, this
iforce2d 0:972874f31c98 17 list of conditions and the following disclaimer in the documentation and/or other
iforce2d 0:972874f31c98 18 materials provided with the distribution.
iforce2d 0:972874f31c98 19
iforce2d 0:972874f31c98 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
iforce2d 0:972874f31c98 21 CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
iforce2d 0:972874f31c98 22 INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
iforce2d 0:972874f31c98 23 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
iforce2d 0:972874f31c98 24 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
iforce2d 0:972874f31c98 25 CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
iforce2d 0:972874f31c98 26 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
iforce2d 0:972874f31c98 27 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
iforce2d 0:972874f31c98 28 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
iforce2d 0:972874f31c98 29 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
iforce2d 0:972874f31c98 30 STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
iforce2d 0:972874f31c98 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
iforce2d 0:972874f31c98 32 ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
iforce2d 0:972874f31c98 33
iforce2d 0:972874f31c98 34
iforce2d 0:972874f31c98 35 */
iforce2d 0:972874f31c98 36
iforce2d 0:972874f31c98 37 #include "u8g.h"
iforce2d 0:972874f31c98 38
iforce2d 0:972874f31c98 39 #define WIDTH 192
iforce2d 0:972874f31c98 40 #define HEIGHT 32
iforce2d 0:972874f31c98 41
iforce2d 0:972874f31c98 42
iforce2d 0:972874f31c98 43 /* init sequence from https://github.com/adafruit/ST7565-LCD/blob/master/ST7565/ST7565.cpp */
iforce2d 0:972874f31c98 44 static const uint8_t u8g_dev_st7920_192x32_init_seq[] PROGMEM = {
iforce2d 0:972874f31c98 45 U8G_ESC_CS(0), /* disable chip */
iforce2d 0:972874f31c98 46 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 47 U8G_ESC_RST(15), /* do reset low pulse with (15*16)+2 milliseconds (=maximum delay)*/
iforce2d 0:972874f31c98 48 U8G_ESC_DLY(100), /* 8 Dez 2012: additional delay 100 ms because of reset*/
iforce2d 0:972874f31c98 49 U8G_ESC_CS(1), /* enable chip */
iforce2d 0:972874f31c98 50 U8G_ESC_DLY(50), /* delay 50 ms */
iforce2d 0:972874f31c98 51
iforce2d 0:972874f31c98 52 0x038, /* 8 Bit interface (DL=1), basic instruction set (RE=0) */
iforce2d 0:972874f31c98 53 0x00c, /* display on, cursor & blink off; 0x08: all off */
iforce2d 0:972874f31c98 54 0x006, /* Entry mode: Cursor move to right ,DDRAM address counter (AC) plus 1, no shift */
iforce2d 0:972874f31c98 55 0x002, /* disable scroll, enable CGRAM adress */
iforce2d 0:972874f31c98 56 0x001, /* clear RAM, needs 1.6 ms */
iforce2d 0:972874f31c98 57 U8G_ESC_DLY(100), /* delay 10 ms */
iforce2d 0:972874f31c98 58
iforce2d 0:972874f31c98 59 U8G_ESC_CS(0), /* disable chip */
iforce2d 0:972874f31c98 60 U8G_ESC_END /* end of sequence */
iforce2d 0:972874f31c98 61 };
iforce2d 0:972874f31c98 62
iforce2d 0:972874f31c98 63 uint8_t u8g_dev_st7920_192x32_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
iforce2d 0:972874f31c98 64 {
iforce2d 0:972874f31c98 65 switch(msg)
iforce2d 0:972874f31c98 66 {
iforce2d 0:972874f31c98 67 case U8G_DEV_MSG_INIT:
iforce2d 0:972874f31c98 68 u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_400NS);
iforce2d 0:972874f31c98 69 u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7920_192x32_init_seq);
iforce2d 0:972874f31c98 70 break;
iforce2d 0:972874f31c98 71 case U8G_DEV_MSG_STOP:
iforce2d 0:972874f31c98 72 break;
iforce2d 0:972874f31c98 73 case U8G_DEV_MSG_PAGE_NEXT:
iforce2d 0:972874f31c98 74 {
iforce2d 0:972874f31c98 75 uint8_t y, i;
iforce2d 0:972874f31c98 76 uint8_t *ptr;
iforce2d 0:972874f31c98 77 u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
iforce2d 0:972874f31c98 78
iforce2d 0:972874f31c98 79 u8g_SetAddress(u8g, dev, 0); /* cmd mode */
iforce2d 0:972874f31c98 80 u8g_SetChipSelect(u8g, dev, 1);
iforce2d 0:972874f31c98 81 y = pb->p.page_y0;
iforce2d 0:972874f31c98 82 ptr = pb->buf;
iforce2d 0:972874f31c98 83 for( i = 0; i < 8; i ++ )
iforce2d 0:972874f31c98 84 {
iforce2d 0:972874f31c98 85 u8g_SetAddress(u8g, dev, 0); /* cmd mode */
iforce2d 0:972874f31c98 86 u8g_WriteByte(u8g, dev, 0x03e ); /* enable extended mode */
iforce2d 0:972874f31c98 87 u8g_WriteByte(u8g, dev, 0x080 | y ); /* y pos */
iforce2d 0:972874f31c98 88 u8g_WriteByte(u8g, dev, 0x080 ); /* set x pos to 0*/
iforce2d 0:972874f31c98 89 u8g_SetAddress(u8g, dev, 1); /* data mode */
iforce2d 0:972874f31c98 90 u8g_WriteSequence(u8g, dev, WIDTH/8, ptr);
iforce2d 0:972874f31c98 91 ptr += WIDTH/8;
iforce2d 0:972874f31c98 92 y++;
iforce2d 0:972874f31c98 93 }
iforce2d 0:972874f31c98 94 u8g_SetChipSelect(u8g, dev, 0);
iforce2d 0:972874f31c98 95 }
iforce2d 0:972874f31c98 96 break;
iforce2d 0:972874f31c98 97 }
iforce2d 0:972874f31c98 98 return u8g_dev_pb8h1_base_fn(u8g, dev, msg, arg);
iforce2d 0:972874f31c98 99 }
iforce2d 0:972874f31c98 100
iforce2d 0:972874f31c98 101 uint8_t u8g_dev_st7920_192x32_4x_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
iforce2d 0:972874f31c98 102 {
iforce2d 0:972874f31c98 103 switch(msg)
iforce2d 0:972874f31c98 104 {
iforce2d 0:972874f31c98 105 case U8G_DEV_MSG_INIT:
iforce2d 0:972874f31c98 106 u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_400NS);
iforce2d 0:972874f31c98 107 u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7920_192x32_init_seq);
iforce2d 0:972874f31c98 108 break;
iforce2d 0:972874f31c98 109 case U8G_DEV_MSG_STOP:
iforce2d 0:972874f31c98 110 break;
iforce2d 0:972874f31c98 111 case U8G_DEV_MSG_PAGE_NEXT:
iforce2d 0:972874f31c98 112 {
iforce2d 0:972874f31c98 113 uint8_t y, i;
iforce2d 0:972874f31c98 114 uint8_t *ptr;
iforce2d 0:972874f31c98 115 u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
iforce2d 0:972874f31c98 116
iforce2d 0:972874f31c98 117 u8g_SetAddress(u8g, dev, 0); /* cmd mode */
iforce2d 0:972874f31c98 118 u8g_SetChipSelect(u8g, dev, 1);
iforce2d 0:972874f31c98 119 y = pb->p.page_y0;
iforce2d 0:972874f31c98 120 ptr = pb->buf;
iforce2d 0:972874f31c98 121 for( i = 0; i < 32; i ++ )
iforce2d 0:972874f31c98 122 {
iforce2d 0:972874f31c98 123 u8g_SetAddress(u8g, dev, 0); /* cmd mode */
iforce2d 0:972874f31c98 124 u8g_WriteByte(u8g, dev, 0x03e ); /* enable extended mode */
iforce2d 0:972874f31c98 125 u8g_WriteByte(u8g, dev, 0x080 | y ); /* y pos */
iforce2d 0:972874f31c98 126 u8g_WriteByte(u8g, dev, 0x080 ); /* set x pos to 0*/
iforce2d 0:972874f31c98 127 u8g_SetAddress(u8g, dev, 1); /* data mode */
iforce2d 0:972874f31c98 128 u8g_WriteSequence(u8g, dev, WIDTH/8, ptr);
iforce2d 0:972874f31c98 129 ptr += WIDTH/8;
iforce2d 0:972874f31c98 130 y++;
iforce2d 0:972874f31c98 131 }
iforce2d 0:972874f31c98 132 u8g_SetChipSelect(u8g, dev, 0);
iforce2d 0:972874f31c98 133 }
iforce2d 0:972874f31c98 134 break;
iforce2d 0:972874f31c98 135 }
iforce2d 0:972874f31c98 136 return u8g_dev_pb32h1_base_fn(u8g, dev, msg, arg);
iforce2d 0:972874f31c98 137 }
iforce2d 0:972874f31c98 138
iforce2d 0:972874f31c98 139
iforce2d 0:972874f31c98 140 U8G_PB_DEV(u8g_dev_st7920_192x32_sw_spi, WIDTH, HEIGHT, 8, u8g_dev_st7920_192x32_fn, U8G_COM_ST7920_SW_SPI);
iforce2d 0:972874f31c98 141 U8G_PB_DEV(u8g_dev_st7920_192x32_hw_spi, WIDTH, HEIGHT, 8, u8g_dev_st7920_192x32_fn, U8G_COM_ST7920_HW_SPI);
iforce2d 0:972874f31c98 142 U8G_PB_DEV(u8g_dev_st7920_192x32_8bit, WIDTH, HEIGHT, 8, u8g_dev_st7920_192x32_fn, U8G_COM_FAST_PARALLEL);
iforce2d 0:972874f31c98 143
iforce2d 0:972874f31c98 144
iforce2d 0:972874f31c98 145 #define QWIDTH (WIDTH*4)
iforce2d 0:972874f31c98 146 uint8_t u8g_dev_st7920_192x32_4x_buf[QWIDTH] U8G_NOCOMMON ;
iforce2d 0:972874f31c98 147 u8g_pb_t u8g_dev_st7920_192x32_4x_pb = { {32, HEIGHT, 0, 0, 0}, WIDTH, u8g_dev_st7920_192x32_4x_buf};
iforce2d 0:972874f31c98 148 u8g_dev_t u8g_dev_st7920_192x32_4x_sw_spi = { u8g_dev_st7920_192x32_4x_fn, &u8g_dev_st7920_192x32_4x_pb, U8G_COM_ST7920_SW_SPI };
iforce2d 0:972874f31c98 149 u8g_dev_t u8g_dev_st7920_192x32_4x_hw_spi = { u8g_dev_st7920_192x32_4x_fn, &u8g_dev_st7920_192x32_4x_pb, U8G_COM_ST7920_HW_SPI };
iforce2d 0:972874f31c98 150 u8g_dev_t u8g_dev_st7920_192x32_4x_8bit = { u8g_dev_st7920_192x32_4x_fn, &u8g_dev_st7920_192x32_4x_pb, U8G_COM_FAST_PARALLEL };
iforce2d 0:972874f31c98 151
iforce2d 0:972874f31c98 152