iforce2d Chris / Mbed 2 deprecated ubxDistanceMeter

Displays distance to start location on OLED screen.

Dependencies:   mbed

u8g_dev_st7687_c144mvgd.c@0:972874f31c98, 2018-03-07 (annotated)

Committer:
iforce2d
Date:
Wed Mar 07 12:49:14 2018 +0000
Revision:
0:972874f31c98
First commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
iforce2d 0:972874f31c98 1 /*
iforce2d 0:972874f31c98 2
iforce2d 0:972874f31c98 3 u8g_dev_st7687_c144mvgd.c (1.44" TFT)
iforce2d 0:972874f31c98 4
iforce2d 0:972874f31c98 5 Status: Started, but not finished
iforce2d 0:972874f31c98 6
iforce2d 0:972874f31c98 7 Universal 8bit Graphics Library
iforce2d 0:972874f31c98 8
iforce2d 0:972874f31c98 9 Copyright (c) 2012, olikraus@gmail.com
iforce2d 0:972874f31c98 10 All rights reserved.
iforce2d 0:972874f31c98 11
iforce2d 0:972874f31c98 12 Redistribution and use in source and binary forms, with or without modification,
iforce2d 0:972874f31c98 13 are permitted provided that the following conditions are met:
iforce2d 0:972874f31c98 14
iforce2d 0:972874f31c98 15 * Redistributions of source code must retain the above copyright notice, this list
iforce2d 0:972874f31c98 16 of conditions and the following disclaimer.
iforce2d 0:972874f31c98 17
iforce2d 0:972874f31c98 18 * Redistributions in binary form must reproduce the above copyright notice, this
iforce2d 0:972874f31c98 19 list of conditions and the following disclaimer in the documentation and/or other
iforce2d 0:972874f31c98 20 materials provided with the distribution.
iforce2d 0:972874f31c98 21
iforce2d 0:972874f31c98 22 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
iforce2d 0:972874f31c98 23 CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
iforce2d 0:972874f31c98 24 INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
iforce2d 0:972874f31c98 25 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
iforce2d 0:972874f31c98 26 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
iforce2d 0:972874f31c98 27 CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
iforce2d 0:972874f31c98 28 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
iforce2d 0:972874f31c98 29 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
iforce2d 0:972874f31c98 30 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
iforce2d 0:972874f31c98 31 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
iforce2d 0:972874f31c98 32 STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
iforce2d 0:972874f31c98 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
iforce2d 0:972874f31c98 34 ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
iforce2d 0:972874f31c98 35
iforce2d 0:972874f31c98 36
iforce2d 0:972874f31c98 37 */
iforce2d 0:972874f31c98 38
iforce2d 0:972874f31c98 39 #include "u8g.h"
iforce2d 0:972874f31c98 40
iforce2d 0:972874f31c98 41 #define WIDTH 128
iforce2d 0:972874f31c98 42 #define HEIGHT 128
iforce2d 0:972874f31c98 43 #define PAGE_HEIGHT 8
iforce2d 0:972874f31c98 44
iforce2d 0:972874f31c98 45
iforce2d 0:972874f31c98 46 #ifdef FIRST_VERSION
iforce2d 0:972874f31c98 47 /*
iforce2d 0:972874f31c98 48 see also: read.pudn.com/downloads115/sourcecode/app/484503/LCM_Display.c__.htm
iforce2d 0:972874f31c98 49 http://en.pudn.com/downloads115/sourcecode/app/detail484503_en.html
iforce2d 0:972874f31c98 50 */
iforce2d 0:972874f31c98 51
iforce2d 0:972874f31c98 52 static const uint8_t u8g_dev_st7687_c144mvgd_init_seq[] PROGMEM = {
iforce2d 0:972874f31c98 53 U8G_ESC_CS(0), /* disable chip */
iforce2d 0:972874f31c98 54 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 55 U8G_ESC_CS(1), /* enable chip */
iforce2d 0:972874f31c98 56 U8G_ESC_RST(15), /* do reset low pulse with (15*16)+2 milliseconds (=maximum delay)*/
iforce2d 0:972874f31c98 57
iforce2d 0:972874f31c98 58 0x001, /* A0=0, SW reset */
iforce2d 0:972874f31c98 59 U8G_ESC_DLY(200), /* delay 200 ms */
iforce2d 0:972874f31c98 60
iforce2d 0:972874f31c98 61 0x0d7, /* EEPROM data auto re-load control */
iforce2d 0:972874f31c98 62 U8G_ESC_ADR(1), /* data mode */
iforce2d 0:972874f31c98 63 0x09f, /* ARD = 1 */
iforce2d 0:972874f31c98 64 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 65 U8G_ESC_DLY(100), /* delay 100 ms */
iforce2d 0:972874f31c98 66
iforce2d 0:972874f31c98 67 0x0e0, /* EEPROM control in */
iforce2d 0:972874f31c98 68 U8G_ESC_ADR(1), /* data mode */
iforce2d 0:972874f31c98 69 0x000, /* */
iforce2d 0:972874f31c98 70 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 71 U8G_ESC_DLY(100), /* delay 100 ms */
iforce2d 0:972874f31c98 72
iforce2d 0:972874f31c98 73 #ifdef NOT_REQUIRED
iforce2d 0:972874f31c98 74 0x0fa, /* EEPROM function selection 8.1.66 */
iforce2d 0:972874f31c98 75 U8G_ESC_ADR(1), /* data mode */
iforce2d 0:972874f31c98 76 0x000, /* */
iforce2d 0:972874f31c98 77 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 78 U8G_ESC_DLY(100), /* delay 100 ms */
iforce2d 0:972874f31c98 79 #endif
iforce2d 0:972874f31c98 80
iforce2d 0:972874f31c98 81 0x0e3, /* Read from EEPROM, 8.1.55 */
iforce2d 0:972874f31c98 82 U8G_ESC_DLY(100), /* delay 100 ms */
iforce2d 0:972874f31c98 83
iforce2d 0:972874f31c98 84 0x0e1, /* EEPROM control out, 8.1.53 */
iforce2d 0:972874f31c98 85 U8G_ESC_DLY(100), /* delay 100 ms */
iforce2d 0:972874f31c98 86
iforce2d 0:972874f31c98 87 //0x028, /* display off */
iforce2d 0:972874f31c98 88 0x011, /* Sleep out & booster on */
iforce2d 0:972874f31c98 89 U8G_ESC_DLY(100), /* delay 100 ms */
iforce2d 0:972874f31c98 90
iforce2d 0:972874f31c98 91 0x0c0, /* Vop setting, 8.1.42 */
iforce2d 0:972874f31c98 92 U8G_ESC_ADR(1), /* data mode */
iforce2d 0:972874f31c98 93 0x000, /* */
iforce2d 0:972874f31c98 94 0x001, /* 3.6 + 256*0.04 = 13.84 Volt */
iforce2d 0:972874f31c98 95 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 96 U8G_ESC_DLY(100), /* delay 100 ms */
iforce2d 0:972874f31c98 97
iforce2d 0:972874f31c98 98 0x0c3, /* Bias selection, 8.1.45 */
iforce2d 0:972874f31c98 99 U8G_ESC_ADR(1), /* data mode */
iforce2d 0:972874f31c98 100 0x003,
iforce2d 0:972874f31c98 101 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 102
iforce2d 0:972874f31c98 103 0x0c4, /* Booster setting 8.1.46 */
iforce2d 0:972874f31c98 104 U8G_ESC_ADR(1), /* data mode */
iforce2d 0:972874f31c98 105 0x007,
iforce2d 0:972874f31c98 106 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 107
iforce2d 0:972874f31c98 108 0x0c5, /* ??? */
iforce2d 0:972874f31c98 109 U8G_ESC_ADR(1), /* data mode */
iforce2d 0:972874f31c98 110 0x001,
iforce2d 0:972874f31c98 111 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 112
iforce2d 0:972874f31c98 113 0x0cb, /* FV3 with Booster x2 control, 8.1.47 */
iforce2d 0:972874f31c98 114 U8G_ESC_ADR(1), /* data mode */
iforce2d 0:972874f31c98 115 0x001,
iforce2d 0:972874f31c98 116 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 117
iforce2d 0:972874f31c98 118 0x036, /* Memory data access control, 8.1.28 */
iforce2d 0:972874f31c98 119 U8G_ESC_ADR(1), /* data mode */
iforce2d 0:972874f31c98 120 0x080,
iforce2d 0:972874f31c98 121 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 122
iforce2d 0:972874f31c98 123 0x0b5, /* N-line control, 8.1.37 */
iforce2d 0:972874f31c98 124 U8G_ESC_ADR(1), /* data mode */
iforce2d 0:972874f31c98 125 0x089,
iforce2d 0:972874f31c98 126 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 127
iforce2d 0:972874f31c98 128
iforce2d 0:972874f31c98 129 0x0d0, /* Analog circuit setting, 8.1.49 */
iforce2d 0:972874f31c98 130 U8G_ESC_ADR(1), /* data mode */
iforce2d 0:972874f31c98 131 0x01d,
iforce2d 0:972874f31c98 132 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 133
iforce2d 0:972874f31c98 134 0x0b7, /* Com/Seg Scan Direction, 8.1.38 */
iforce2d 0:972874f31c98 135 U8G_ESC_ADR(1), /* data mode */
iforce2d 0:972874f31c98 136 0x040,
iforce2d 0:972874f31c98 137 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 138
iforce2d 0:972874f31c98 139 0x025, /* Write contrast, 8.1.17 */
iforce2d 0:972874f31c98 140 U8G_ESC_ADR(1), /* data mode */
iforce2d 0:972874f31c98 141 0x03f,
iforce2d 0:972874f31c98 142 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 143
iforce2d 0:972874f31c98 144 0x03a, /* Interface pixel format, 8.1.32 */
iforce2d 0:972874f31c98 145 U8G_ESC_ADR(1), /* data mode */
iforce2d 0:972874f31c98 146 0x004, /* 3: 12 bit per pixel Type A, 4: 12 bit Type B, 5: 16bit per pixel */
iforce2d 0:972874f31c98 147 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 148
iforce2d 0:972874f31c98 149 0x0b0, /* Display Duty setting, 8.1.34 */
iforce2d 0:972874f31c98 150 U8G_ESC_ADR(1), /* data mode */
iforce2d 0:972874f31c98 151 0x07f,
iforce2d 0:972874f31c98 152 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 153
iforce2d 0:972874f31c98 154 0x0f0, /* Frame Freq. in Temp range A,B,C and D, 8.1.59 */
iforce2d 0:972874f31c98 155 U8G_ESC_ADR(1), /* data mode */
iforce2d 0:972874f31c98 156 0x007,
iforce2d 0:972874f31c98 157 0x00c,
iforce2d 0:972874f31c98 158 0x00c,
iforce2d 0:972874f31c98 159 0x015,
iforce2d 0:972874f31c98 160 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 161
iforce2d 0:972874f31c98 162 0x0f9, /* Frame RGB Value, 8.1.65 */
iforce2d 0:972874f31c98 163 U8G_ESC_ADR(1), /* data mode */
iforce2d 0:972874f31c98 164 0x000,
iforce2d 0:972874f31c98 165 0x005,
iforce2d 0:972874f31c98 166 0x008,
iforce2d 0:972874f31c98 167 0x00a,
iforce2d 0:972874f31c98 168 0x00c,
iforce2d 0:972874f31c98 169 0x00e,
iforce2d 0:972874f31c98 170 0x010,
iforce2d 0:972874f31c98 171 0x011,
iforce2d 0:972874f31c98 172 0x012,
iforce2d 0:972874f31c98 173 0x013,
iforce2d 0:972874f31c98 174 0x014,
iforce2d 0:972874f31c98 175 0x015,
iforce2d 0:972874f31c98 176 0x016,
iforce2d 0:972874f31c98 177 0x018,
iforce2d 0:972874f31c98 178 0x01a,
iforce2d 0:972874f31c98 179 0x01b,
iforce2d 0:972874f31c98 180 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 181
iforce2d 0:972874f31c98 182 0x0f9, /* Frame RGB Value, 8.1.65 */
iforce2d 0:972874f31c98 183 U8G_ESC_ADR(1), /* data mode */
iforce2d 0:972874f31c98 184 0x000,
iforce2d 0:972874f31c98 185 0x000,
iforce2d 0:972874f31c98 186 0x000,
iforce2d 0:972874f31c98 187 0x000,
iforce2d 0:972874f31c98 188 0x033,
iforce2d 0:972874f31c98 189 0x055,
iforce2d 0:972874f31c98 190 0x055,
iforce2d 0:972874f31c98 191 0x055,
iforce2d 0:972874f31c98 192 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 193
iforce2d 0:972874f31c98 194 0x029, /* display on */
iforce2d 0:972874f31c98 195
iforce2d 0:972874f31c98 196 U8G_ESC_CS(0), /* disable chip */
iforce2d 0:972874f31c98 197 U8G_ESC_END /* end of sequence */
iforce2d 0:972874f31c98 198
iforce2d 0:972874f31c98 199 };
iforce2d 0:972874f31c98 200
iforce2d 0:972874f31c98 201 #else
iforce2d 0:972874f31c98 202
iforce2d 0:972874f31c98 203 /*
iforce2d 0:972874f31c98 204 http://www.waitingforfriday.com/images/e/e3/FTM144D01N_test.zip
iforce2d 0:972874f31c98 205 */
iforce2d 0:972874f31c98 206
iforce2d 0:972874f31c98 207 static const uint8_t u8g_dev_st7687_c144mvgd_init_seq[] PROGMEM = {
iforce2d 0:972874f31c98 208 U8G_ESC_CS(0), /* disable chip */
iforce2d 0:972874f31c98 209 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 210 U8G_ESC_CS(1), /* enable chip */
iforce2d 0:972874f31c98 211 U8G_ESC_RST(15), /* do reset low pulse with (15*16)+2 milliseconds (=maximum delay)*/
iforce2d 0:972874f31c98 212
iforce2d 0:972874f31c98 213 0x011, /* Sleep out & booster on */
iforce2d 0:972874f31c98 214 U8G_ESC_DLY(5), /* delay 5 ms */
iforce2d 0:972874f31c98 215
iforce2d 0:972874f31c98 216 0x03a, /* Interface pixel format, 8.1.32 */
iforce2d 0:972874f31c98 217 U8G_ESC_ADR(1), /* data mode */
iforce2d 0:972874f31c98 218 0x004, /* 3: 12 bit per pixel Type A, 4: 12 bit Type B, 5: 16bit per pixel */
iforce2d 0:972874f31c98 219 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 220
iforce2d 0:972874f31c98 221
iforce2d 0:972874f31c98 222 0x026, /* SET_GAMMA_CURVE */
iforce2d 0:972874f31c98 223 U8G_ESC_ADR(1), /* data mode */
iforce2d 0:972874f31c98 224 0x004,
iforce2d 0:972874f31c98 225 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 226
iforce2d 0:972874f31c98 227 0x0f2, /* GAM_R_SEL */
iforce2d 0:972874f31c98 228 U8G_ESC_ADR(1), /* data mode */
iforce2d 0:972874f31c98 229 0x001, /* enable gamma adj */
iforce2d 0:972874f31c98 230 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 231
iforce2d 0:972874f31c98 232
iforce2d 0:972874f31c98 233 0x0e0, /* POSITIVE_GAMMA_CORRECT */
iforce2d 0:972874f31c98 234 U8G_ESC_ADR(1), /* data mode */
iforce2d 0:972874f31c98 235 0x3f,
iforce2d 0:972874f31c98 236 0x25,
iforce2d 0:972874f31c98 237 0x1c,
iforce2d 0:972874f31c98 238 0x1e,
iforce2d 0:972874f31c98 239 0x20,
iforce2d 0:972874f31c98 240 0x12,
iforce2d 0:972874f31c98 241 0x2a,
iforce2d 0:972874f31c98 242 0x90,
iforce2d 0:972874f31c98 243 0x24,
iforce2d 0:972874f31c98 244 0x11,
iforce2d 0:972874f31c98 245 0x00,
iforce2d 0:972874f31c98 246 0x00,
iforce2d 0:972874f31c98 247 0x00,
iforce2d 0:972874f31c98 248 0x00,
iforce2d 0:972874f31c98 249 0x00,
iforce2d 0:972874f31c98 250 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 251
iforce2d 0:972874f31c98 252 0x0e1, /* NEGATIVE_GAMMA_CORRECT */
iforce2d 0:972874f31c98 253 U8G_ESC_ADR(1), /* data mode */
iforce2d 0:972874f31c98 254 0x20,
iforce2d 0:972874f31c98 255 0x20,
iforce2d 0:972874f31c98 256 0x20,
iforce2d 0:972874f31c98 257 0x20,
iforce2d 0:972874f31c98 258 0x05,
iforce2d 0:972874f31c98 259 0x00,
iforce2d 0:972874f31c98 260 0x15,
iforce2d 0:972874f31c98 261 0xa7,
iforce2d 0:972874f31c98 262 0x3d,
iforce2d 0:972874f31c98 263 0x18,
iforce2d 0:972874f31c98 264 0x25,
iforce2d 0:972874f31c98 265 0x2a,
iforce2d 0:972874f31c98 266 0x2b,
iforce2d 0:972874f31c98 267 0x2b,
iforce2d 0:972874f31c98 268 0x3a,
iforce2d 0:972874f31c98 269 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 270
iforce2d 0:972874f31c98 271 0x0b1, /* FRAME_RATE_CONTROL1 */
iforce2d 0:972874f31c98 272 U8G_ESC_ADR(1), /* data mode */
iforce2d 0:972874f31c98 273 0x008, /* DIVA = 8 */
iforce2d 0:972874f31c98 274 0x008, /* VPA = 8 */
iforce2d 0:972874f31c98 275 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 276
iforce2d 0:972874f31c98 277
iforce2d 0:972874f31c98 278 0x0b4, /* DISPLAY_INVERSION */
iforce2d 0:972874f31c98 279 U8G_ESC_ADR(1), /* data mode */
iforce2d 0:972874f31c98 280 0x007, /* NLA = 1, NLB = 1, NLC = 1 (all on Frame Inversion) */
iforce2d 0:972874f31c98 281 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 282
iforce2d 0:972874f31c98 283 0x0c0, /* POWER_CONTROL1 */
iforce2d 0:972874f31c98 284 U8G_ESC_ADR(1), /* data mode */
iforce2d 0:972874f31c98 285 0x00a, /* VRH = 10: GVDD = 4.30 */
iforce2d 0:972874f31c98 286 0x002, /* VC = 2: VCI1 = 2.65 */
iforce2d 0:972874f31c98 287 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 288
iforce2d 0:972874f31c98 289 0x0c1, /* POWER_CONTROL2 */
iforce2d 0:972874f31c98 290 U8G_ESC_ADR(1), /* data mode */
iforce2d 0:972874f31c98 291 0x002, /* BT = 2: AVDD = 2xVCI1, VCL = -1xVCI1, VGH = 5xVCI1, VGL = -2xVCI1 */
iforce2d 0:972874f31c98 292 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 293
iforce2d 0:972874f31c98 294 0x0c5, /* VCOM_CONTROL1 */
iforce2d 0:972874f31c98 295 U8G_ESC_ADR(1), /* data mode */
iforce2d 0:972874f31c98 296 0x050, /* VMH = 80: VCOMH voltage = 4.5 */
iforce2d 0:972874f31c98 297 0x05b, /* VML = 91: VCOML voltage = -0.225 */
iforce2d 0:972874f31c98 298 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 299
iforce2d 0:972874f31c98 300 0x0c7, /* VCOM_OFFSET_CONTROL */
iforce2d 0:972874f31c98 301 U8G_ESC_ADR(1), /* data mode */
iforce2d 0:972874f31c98 302 0x040, /* nVM = 0, VMF = 64: VCOMH output = VMH, VCOML output = VML */
iforce2d 0:972874f31c98 303 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 304
iforce2d 0:972874f31c98 305 0x02a, /* SET_COLUMN_ADDRESS */
iforce2d 0:972874f31c98 306 U8G_ESC_ADR(1), /* data mode */
iforce2d 0:972874f31c98 307 0x000, /* */
iforce2d 0:972874f31c98 308 0x000, /* */
iforce2d 0:972874f31c98 309 0x000, /* */
iforce2d 0:972874f31c98 310 0x07f, /* */
iforce2d 0:972874f31c98 311 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 312
iforce2d 0:972874f31c98 313 0x02b, /* SET_PAGE_ADDRESS */
iforce2d 0:972874f31c98 314 U8G_ESC_ADR(1), /* data mode */
iforce2d 0:972874f31c98 315 0x000, /* */
iforce2d 0:972874f31c98 316 0x000, /* */
iforce2d 0:972874f31c98 317 0x000, /* */
iforce2d 0:972874f31c98 318 0x07f, /* */
iforce2d 0:972874f31c98 319 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 320
iforce2d 0:972874f31c98 321 0x036, /* SET_ADDRESS_MODE */
iforce2d 0:972874f31c98 322 U8G_ESC_ADR(1), /* data mode */
iforce2d 0:972874f31c98 323 0x000, /* Select display orientation */
iforce2d 0:972874f31c98 324 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 325
iforce2d 0:972874f31c98 326
iforce2d 0:972874f31c98 327 0x029, /* display on */
iforce2d 0:972874f31c98 328
iforce2d 0:972874f31c98 329 0x02c, /* write start */
iforce2d 0:972874f31c98 330
iforce2d 0:972874f31c98 331 U8G_ESC_CS(0), /* disable chip */
iforce2d 0:972874f31c98 332 U8G_ESC_END /* end of sequence */
iforce2d 0:972874f31c98 333
iforce2d 0:972874f31c98 334 };
iforce2d 0:972874f31c98 335
iforce2d 0:972874f31c98 336 #endif
iforce2d 0:972874f31c98 337
iforce2d 0:972874f31c98 338
iforce2d 0:972874f31c98 339
iforce2d 0:972874f31c98 340
iforce2d 0:972874f31c98 341 /* calculate bytes for Type B 4096 color display */
iforce2d 0:972874f31c98 342 static uint8_t get_byte_1(uint8_t v)
iforce2d 0:972874f31c98 343 {
iforce2d 0:972874f31c98 344 v >>= 4;
iforce2d 0:972874f31c98 345 v &= 0x0e;
iforce2d 0:972874f31c98 346 return v;
iforce2d 0:972874f31c98 347 }
iforce2d 0:972874f31c98 348
iforce2d 0:972874f31c98 349 static uint8_t get_byte_2(uint8_t v)
iforce2d 0:972874f31c98 350 {
iforce2d 0:972874f31c98 351 uint8_t w;
iforce2d 0:972874f31c98 352 w = v;
iforce2d 0:972874f31c98 353 w &= 3;
iforce2d 0:972874f31c98 354 w = (w<<2) | w;
iforce2d 0:972874f31c98 355 v <<= 3;
iforce2d 0:972874f31c98 356 v &= 0x0e0;
iforce2d 0:972874f31c98 357 w |= v;
iforce2d 0:972874f31c98 358 return w;
iforce2d 0:972874f31c98 359 }
iforce2d 0:972874f31c98 360
iforce2d 0:972874f31c98 361 uint8_t u8g_dev_st7687_c144mvgd_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
iforce2d 0:972874f31c98 362 {
iforce2d 0:972874f31c98 363 switch(msg)
iforce2d 0:972874f31c98 364 {
iforce2d 0:972874f31c98 365 case U8G_DEV_MSG_INIT:
iforce2d 0:972874f31c98 366 u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_400NS);
iforce2d 0:972874f31c98 367 u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7687_c144mvgd_init_seq);
iforce2d 0:972874f31c98 368 break;
iforce2d 0:972874f31c98 369 case U8G_DEV_MSG_STOP:
iforce2d 0:972874f31c98 370 break;
iforce2d 0:972874f31c98 371 case U8G_DEV_MSG_PAGE_NEXT:
iforce2d 0:972874f31c98 372 {
iforce2d 0:972874f31c98 373 uint8_t y, i, j;
iforce2d 0:972874f31c98 374 uint8_t *ptr;
iforce2d 0:972874f31c98 375 u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
iforce2d 0:972874f31c98 376
iforce2d 0:972874f31c98 377 u8g_SetAddress(u8g, dev, 0); /* cmd mode */
iforce2d 0:972874f31c98 378 u8g_SetChipSelect(u8g, dev, 1);
iforce2d 0:972874f31c98 379 y = pb->p.page_y0;
iforce2d 0:972874f31c98 380 ptr = pb->buf;
iforce2d 0:972874f31c98 381
iforce2d 0:972874f31c98 382 u8g_SetAddress(u8g, dev, 0); /* cmd mode */
iforce2d 0:972874f31c98 383 u8g_WriteByte(u8g, dev, 0x02a ); /* Column address set 8.1.20 */
iforce2d 0:972874f31c98 384 u8g_SetAddress(u8g, dev, 1); /* data mode */
iforce2d 0:972874f31c98 385 u8g_WriteByte(u8g, dev, 0x000 ); /* x0 */
iforce2d 0:972874f31c98 386 u8g_WriteByte(u8g, dev, WIDTH-1 ); /* x1 */
iforce2d 0:972874f31c98 387 u8g_SetAddress(u8g, dev, 0); /* cmd mode */
iforce2d 0:972874f31c98 388 u8g_WriteByte(u8g, dev, 0x02b ); /* Row address set 8.1.21 */
iforce2d 0:972874f31c98 389 u8g_SetAddress(u8g, dev, 1); /* data mode */
iforce2d 0:972874f31c98 390 u8g_WriteByte(u8g, dev, y ); /* y0 */
iforce2d 0:972874f31c98 391 u8g_WriteByte(u8g, dev, y+PAGE_HEIGHT-1 ); /* y1 */
iforce2d 0:972874f31c98 392 u8g_SetAddress(u8g, dev, 0); /* cmd mode */
iforce2d 0:972874f31c98 393 u8g_WriteByte(u8g, dev, 0x02c ); /* Memory write 8.1.22 */
iforce2d 0:972874f31c98 394 u8g_SetAddress(u8g, dev, 1); /* data mode */
iforce2d 0:972874f31c98 395
iforce2d 0:972874f31c98 396 for( i = 0; i < PAGE_HEIGHT; i ++ )
iforce2d 0:972874f31c98 397 {
iforce2d 0:972874f31c98 398
iforce2d 0:972874f31c98 399 for( j = 0; j < WIDTH; j ++ )
iforce2d 0:972874f31c98 400 {
iforce2d 0:972874f31c98 401 u8g_WriteByte(u8g, dev, get_byte_1(*ptr) );
iforce2d 0:972874f31c98 402 u8g_WriteByte(u8g, dev, get_byte_2(*ptr) );
iforce2d 0:972874f31c98 403 ptr++;
iforce2d 0:972874f31c98 404 }
iforce2d 0:972874f31c98 405 }
iforce2d 0:972874f31c98 406 u8g_SetAddress(u8g, dev, 0); /* cmd mode */
iforce2d 0:972874f31c98 407 u8g_SetChipSelect(u8g, dev, 0);
iforce2d 0:972874f31c98 408 }
iforce2d 0:972874f31c98 409 break;
iforce2d 0:972874f31c98 410 }
iforce2d 0:972874f31c98 411 return u8g_dev_pb8h8_base_fn(u8g, dev, msg, arg);
iforce2d 0:972874f31c98 412 }
iforce2d 0:972874f31c98 413
iforce2d 0:972874f31c98 414
iforce2d 0:972874f31c98 415 uint8_t u8g_st7687_c144mvgd_8h8_buf[WIDTH*8] U8G_NOCOMMON ;
iforce2d 0:972874f31c98 416 u8g_pb_t u8g_st7687_c144mvgd_8h8_pb = { {8, HEIGHT, 0, 0, 0}, WIDTH, u8g_st7687_c144mvgd_8h8_buf};
iforce2d 0:972874f31c98 417
iforce2d 0:972874f31c98 418 u8g_dev_t u8g_dev_st7687_c144mvgd_sw_spi = { u8g_dev_st7687_c144mvgd_fn, &u8g_st7687_c144mvgd_8h8_pb, u8g_com_arduino_sw_spi_fn };
iforce2d 0:972874f31c98 419
iforce2d 0:972874f31c98 420 u8g_dev_t u8g_dev_st7687_c144mvgd_8bit = { u8g_dev_st7687_c144mvgd_fn, &u8g_st7687_c144mvgd_8h8_pb, U8G_COM_PARALLEL };
iforce2d 0:972874f31c98 421