iforce2d Chris / Mbed 2 deprecated ubxDistanceMeter

Displays distance to start location on OLED screen.

Dependencies:   mbed

u8g_dev_ssd1327_96x96_gr.c@0:972874f31c98, 2018-03-07 (annotated)

Committer:
iforce2d
Date:
Wed Mar 07 12:49:14 2018 +0000
Revision:
0:972874f31c98
First commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
iforce2d 0:972874f31c98 1 /*
iforce2d 0:972874f31c98 2
iforce2d 0:972874f31c98 3 u8g_dev_ssd1327_96x96_gr.c
iforce2d 0:972874f31c98 4
iforce2d 0:972874f31c98 5 2-Bit (graylevel) Driver for SSD1327 Controller (OLED Display)
iforce2d 0:972874f31c98 6 Tested with Seedstudio 96x96 Oled (LY120)
iforce2d 0:972874f31c98 7 http://www.seeedstudio.com/wiki/index.php?title=Twig_-_OLED_96x96
iforce2d 0:972874f31c98 8
iforce2d 0:972874f31c98 9 Universal 8bit Graphics Library
iforce2d 0:972874f31c98 10
iforce2d 0:972874f31c98 11 Copyright (c) 2012, olikraus@gmail.com
iforce2d 0:972874f31c98 12 All rights reserved.
iforce2d 0:972874f31c98 13
iforce2d 0:972874f31c98 14 Redistribution and use in source and binary forms, with or without modification,
iforce2d 0:972874f31c98 15 are permitted provided that the following conditions are met:
iforce2d 0:972874f31c98 16
iforce2d 0:972874f31c98 17 * Redistributions of source code must retain the above copyright notice, this list
iforce2d 0:972874f31c98 18 of conditions and the following disclaimer.
iforce2d 0:972874f31c98 19
iforce2d 0:972874f31c98 20 * Redistributions in binary form must reproduce the above copyright notice, this
iforce2d 0:972874f31c98 21 list of conditions and the following disclaimer in the documentation and/or other
iforce2d 0:972874f31c98 22 materials provided with the distribution.
iforce2d 0:972874f31c98 23
iforce2d 0:972874f31c98 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
iforce2d 0:972874f31c98 25 CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
iforce2d 0:972874f31c98 26 INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
iforce2d 0:972874f31c98 27 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
iforce2d 0:972874f31c98 28 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
iforce2d 0:972874f31c98 29 CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
iforce2d 0:972874f31c98 30 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
iforce2d 0:972874f31c98 31 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
iforce2d 0:972874f31c98 32 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
iforce2d 0:972874f31c98 33 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
iforce2d 0:972874f31c98 34 STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
iforce2d 0:972874f31c98 35 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
iforce2d 0:972874f31c98 36 ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
iforce2d 0:972874f31c98 37
iforce2d 0:972874f31c98 38 SSD130x Monochrom OLED Controller
iforce2d 0:972874f31c98 39 SSD131x Character OLED Controller
iforce2d 0:972874f31c98 40 SSD132x Graylevel OLED Controller
iforce2d 0:972874f31c98 41 SSD1331 Color OLED Controller
iforce2d 0:972874f31c98 42
iforce2d 0:972874f31c98 43 */
iforce2d 0:972874f31c98 44
iforce2d 0:972874f31c98 45 #include "u8g.h"
iforce2d 0:972874f31c98 46
iforce2d 0:972874f31c98 47 #define WIDTH 96
iforce2d 0:972874f31c98 48 #define HEIGHT 96
iforce2d 0:972874f31c98 49 #define XOFFSET 8
iforce2d 0:972874f31c98 50
iforce2d 0:972874f31c98 51 /*
iforce2d 0:972874f31c98 52 http://www.seeedstudio.com/wiki/index.php?title=Twig_-_OLED_96x96
iforce2d 0:972874f31c98 53 */
iforce2d 0:972874f31c98 54 static const uint8_t u8g_dev_ssd1327_2bit_96x96_init_seq[] PROGMEM = {
iforce2d 0:972874f31c98 55 U8G_ESC_DLY(10), /* delay 10 ms */
iforce2d 0:972874f31c98 56 U8G_ESC_CS(0), /* disable chip */
iforce2d 0:972874f31c98 57 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 58 U8G_ESC_RST(1), /* do reset low pulse with (1*16)+2 milliseconds */
iforce2d 0:972874f31c98 59 U8G_ESC_CS(1), /* enable chip */
iforce2d 0:972874f31c98 60 0x0fd, 0x012, /* unlock display, usually not required because the display is unlocked after reset */
iforce2d 0:972874f31c98 61 0x0ae, /* display off, sleep mode */
iforce2d 0:972874f31c98 62 0x0a8, 0x05f, /* multiplex ratio: 0x05f * 1/64 duty */
iforce2d 0:972874f31c98 63 0x0a1, 0x000, /* display start line */
iforce2d 0:972874f31c98 64 0x0a2, 0x060, /* display offset, shift mapping ram counter */
iforce2d 0:972874f31c98 65 //0x0a2, 0x04c, /* NHD: display offset, shift mapping ram counter */
iforce2d 0:972874f31c98 66 0x0a0, 0x046, /* remap configuration, vertical address increment, enable nibble remap (upper nibble is left) */
iforce2d 0:972874f31c98 67 //0x0a0, 0x056, /* NHD: remap configuration, vertical address increment, enable nibble remap (upper nibble is left) */
iforce2d 0:972874f31c98 68 0x0ab, 0x001, /* Enable internal VDD regulator (RESET) */
iforce2d 0:972874f31c98 69 0x081, 0x053, /* contrast, brightness, 0..128, Newhaven: 0x040, LY120 0x053, 0x070 seems also ok */
iforce2d 0:972874f31c98 70 0x0b1, 0x051, /* phase length */
iforce2d 0:972874f31c98 71 0x0b3, 0x001, /* set display clock divide ratio/oscillator frequency */
iforce2d 0:972874f31c98 72 0x0b9, /* use linear lookup table */
iforce2d 0:972874f31c98 73 #if 0
iforce2d 0:972874f31c98 74 0x0b8, /* set gray scale table */
iforce2d 0:972874f31c98 75 //0x01, 0x011, 0x022, 0x032, 0x043, 0x054, 0x065, 0x076,
iforce2d 0:972874f31c98 76 0x01, 0x011, 0x022, 0x032, 0x043, 0x054, 0x077, 0x077, // 4L mode uses 0, 2, 4, 7
iforce2d 0:972874f31c98 77 #endif
iforce2d 0:972874f31c98 78 0x0bc, 0x008, /* pre-charge voltage level */
iforce2d 0:972874f31c98 79 0x0be, 0x007, /* VCOMH voltage */
iforce2d 0:972874f31c98 80 0x0b6, 0x001, /* second precharge */
iforce2d 0:972874f31c98 81 0x0d5, 0x062, /* enable second precharge, internal vsl (bit0 = 0) */
iforce2d 0:972874f31c98 82
iforce2d 0:972874f31c98 83 #if 0
iforce2d 0:972874f31c98 84 // the following commands are not used by the SeeedGrayOLED sequence */
iforce2d 0:972874f31c98 85 0x0ad, 0x002, /* master configuration: disable embedded DC-DC, enable internal VCOMH */
iforce2d 0:972874f31c98 86 0x086, /* full current range (0x084, 0x085, 0x086) */
iforce2d 0:972874f31c98 87 0x0b2, 0x051, /* frame frequency (row period) */
iforce2d 0:972874f31c98 88 0x0b4, 0x002, /* set pre-charge compensation level (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
iforce2d 0:972874f31c98 89 0x0b0, 0x028, /* enable pre-charge compensation (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
iforce2d 0:972874f31c98 90 0x0bf, 0x002|0x00d, /* VSL voltage level (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
iforce2d 0:972874f31c98 91 #endif
iforce2d 0:972874f31c98 92
iforce2d 0:972874f31c98 93 0x0a5, /* all pixel on */
iforce2d 0:972874f31c98 94 //0x02e, /* no scroll (according to SeeedGrayOLED sequence) */
iforce2d 0:972874f31c98 95 0x0af, /* display on */
iforce2d 0:972874f31c98 96 U8G_ESC_DLY(100), /* delay 100 ms */
iforce2d 0:972874f31c98 97 0x0a4, /* normal display mode */
iforce2d 0:972874f31c98 98 U8G_ESC_DLY(100), /* delay 100 ms */
iforce2d 0:972874f31c98 99 0x0a5, /* all pixel on */
iforce2d 0:972874f31c98 100 0x0af, /* display on */
iforce2d 0:972874f31c98 101 U8G_ESC_DLY(100), /* delay 100 ms */
iforce2d 0:972874f31c98 102 0x0a4, /* normal display mode */
iforce2d 0:972874f31c98 103
iforce2d 0:972874f31c98 104 0x015, /* column address... */
iforce2d 0:972874f31c98 105 0x008, /* start at column 8, special for the LY120 ??? */
iforce2d 0:972874f31c98 106 0x037, /* end at column 55, note: there are two pixel in one column */
iforce2d 0:972874f31c98 107
iforce2d 0:972874f31c98 108 0x075, /* row address... */
iforce2d 0:972874f31c98 109 0x008,
iforce2d 0:972874f31c98 110 0x05f,
iforce2d 0:972874f31c98 111
iforce2d 0:972874f31c98 112 U8G_ESC_ADR(1), /* data mode */
iforce2d 0:972874f31c98 113 0x000f, 0x000f, 0x0000, 0x0000, 0x000f,0x000f,0x0000,0x0000,
iforce2d 0:972874f31c98 114 0x000f, 0x000f, 0x0000, 0x0000, 0x000f,0x000f,0x0000,0x0000,
iforce2d 0:972874f31c98 115 0x000f, 0x000f, 0x0000, 0x0000, 0x000f,0x000f,0x0000,0x0000,
iforce2d 0:972874f31c98 116 0x000f, 0x000f, 0x0000, 0x0000, 0x000f,0x000f,0x0000,0x0000,
iforce2d 0:972874f31c98 117
iforce2d 0:972874f31c98 118 U8G_ESC_CS(0), /* disable chip */
iforce2d 0:972874f31c98 119 U8G_ESC_END /* end of sequence */
iforce2d 0:972874f31c98 120 };
iforce2d 0:972874f31c98 121
iforce2d 0:972874f31c98 122 static const uint8_t u8g_dev_ssd1327_2bit_96x96_prepare_page_seq[] PROGMEM = {
iforce2d 0:972874f31c98 123 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 124 U8G_ESC_CS(1), /* enable chip */
iforce2d 0:972874f31c98 125 0x015, /* column address... */
iforce2d 0:972874f31c98 126 XOFFSET, /* start at column 8, special for the LY120 ??? */
iforce2d 0:972874f31c98 127 0x037, /* end at column 55, note: there are two pixel in one column */
iforce2d 0:972874f31c98 128 0x075, /* row address... */
iforce2d 0:972874f31c98 129 U8G_ESC_END /* end of sequence */
iforce2d 0:972874f31c98 130 };
iforce2d 0:972874f31c98 131
iforce2d 0:972874f31c98 132
iforce2d 0:972874f31c98 133 static void u8g_dev_ssd1327_2bit_prepare_page(u8g_t *u8g, u8g_dev_t *dev)
iforce2d 0:972874f31c98 134 {
iforce2d 0:972874f31c98 135 uint8_t page = ((u8g_pb_t *)(dev->dev_mem))->p.page;
iforce2d 0:972874f31c98 136
iforce2d 0:972874f31c98 137 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1327_2bit_96x96_prepare_page_seq);
iforce2d 0:972874f31c98 138
iforce2d 0:972874f31c98 139 page <<= 2;
iforce2d 0:972874f31c98 140 u8g_WriteByte(u8g, dev, page); /* start at the selected page */
iforce2d 0:972874f31c98 141 page += 3;
iforce2d 0:972874f31c98 142 u8g_WriteByte(u8g, dev, page); /* end within the selected page */
iforce2d 0:972874f31c98 143
iforce2d 0:972874f31c98 144 u8g_SetAddress(u8g, dev, 1); /* data mode */
iforce2d 0:972874f31c98 145 }
iforce2d 0:972874f31c98 146
iforce2d 0:972874f31c98 147 static void u8g_dev_ssd1327_2bit_2x_prepare_page(u8g_t *u8g, u8g_dev_t *dev, uint8_t is_odd)
iforce2d 0:972874f31c98 148 {
iforce2d 0:972874f31c98 149 uint8_t page = ((u8g_pb_t *)(dev->dev_mem))->p.page;
iforce2d 0:972874f31c98 150
iforce2d 0:972874f31c98 151 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1327_2bit_96x96_prepare_page_seq);
iforce2d 0:972874f31c98 152
iforce2d 0:972874f31c98 153 page <<= 1;
iforce2d 0:972874f31c98 154 page += is_odd;
iforce2d 0:972874f31c98 155
iforce2d 0:972874f31c98 156 page <<= 2;
iforce2d 0:972874f31c98 157 u8g_WriteByte(u8g, dev, page); /* start at the selected page */
iforce2d 0:972874f31c98 158 page += 3;
iforce2d 0:972874f31c98 159 u8g_WriteByte(u8g, dev, page); /* end within the selected page */
iforce2d 0:972874f31c98 160
iforce2d 0:972874f31c98 161 u8g_SetAddress(u8g, dev, 1); /* data mode */
iforce2d 0:972874f31c98 162 }
iforce2d 0:972874f31c98 163
iforce2d 0:972874f31c98 164 /* assumes row autoincrement and activated nibble remap */
iforce2d 0:972874f31c98 165 static void u8g_dev_ssd1327_2bit_write_4_pixel(u8g_t *u8g, u8g_dev_t *dev, uint8_t left, uint8_t right)
iforce2d 0:972874f31c98 166 {
iforce2d 0:972874f31c98 167 uint8_t d, tmp, cnt;
iforce2d 0:972874f31c98 168 static uint8_t buf[4];
iforce2d 0:972874f31c98 169 buf[0] = 0;
iforce2d 0:972874f31c98 170 buf[1] = 0;
iforce2d 0:972874f31c98 171 buf[2] = 0;
iforce2d 0:972874f31c98 172 buf[3] = 0;
iforce2d 0:972874f31c98 173 cnt = 0;
iforce2d 0:972874f31c98 174 do
iforce2d 0:972874f31c98 175 {
iforce2d 0:972874f31c98 176 if ( left == 0 && right == 0 )
iforce2d 0:972874f31c98 177 break;
iforce2d 0:972874f31c98 178 d = left;
iforce2d 0:972874f31c98 179 d &= 3;
iforce2d 0:972874f31c98 180 d <<= 4;
iforce2d 0:972874f31c98 181 tmp = right;
iforce2d 0:972874f31c98 182 tmp &= 3;
iforce2d 0:972874f31c98 183 d |= tmp;
iforce2d 0:972874f31c98 184 d <<= 2;
iforce2d 0:972874f31c98 185 buf[cnt] = d;
iforce2d 0:972874f31c98 186 left >>= 2;
iforce2d 0:972874f31c98 187 right >>= 2;
iforce2d 0:972874f31c98 188 cnt++;
iforce2d 0:972874f31c98 189 }while ( cnt < 4 );
iforce2d 0:972874f31c98 190 u8g_WriteSequence(u8g, dev, 4, buf);
iforce2d 0:972874f31c98 191 }
iforce2d 0:972874f31c98 192
iforce2d 0:972874f31c98 193 static void u8g_dev_ssd1327_2bit_write_buffer(u8g_t *u8g, u8g_dev_t *dev)
iforce2d 0:972874f31c98 194 {
iforce2d 0:972874f31c98 195 uint8_t cnt, left, right;
iforce2d 0:972874f31c98 196 uint8_t *ptr;
iforce2d 0:972874f31c98 197 u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
iforce2d 0:972874f31c98 198
iforce2d 0:972874f31c98 199 cnt = pb->width;
iforce2d 0:972874f31c98 200 cnt >>= 1;
iforce2d 0:972874f31c98 201 ptr = pb->buf;
iforce2d 0:972874f31c98 202 do
iforce2d 0:972874f31c98 203 {
iforce2d 0:972874f31c98 204 left = *ptr++;
iforce2d 0:972874f31c98 205 right = *ptr++;
iforce2d 0:972874f31c98 206 u8g_dev_ssd1327_2bit_write_4_pixel(u8g, dev, left, right);
iforce2d 0:972874f31c98 207 cnt--;
iforce2d 0:972874f31c98 208 } while( cnt > 0 );
iforce2d 0:972874f31c98 209 }
iforce2d 0:972874f31c98 210
iforce2d 0:972874f31c98 211 static void u8g_dev_ssd1327_2bit_2x_write_buffer(u8g_t *u8g, u8g_dev_t *dev, uint8_t is_odd)
iforce2d 0:972874f31c98 212 {
iforce2d 0:972874f31c98 213 uint8_t cnt, left, right;
iforce2d 0:972874f31c98 214 uint8_t *ptr;
iforce2d 0:972874f31c98 215 u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
iforce2d 0:972874f31c98 216
iforce2d 0:972874f31c98 217 ptr = pb->buf;
iforce2d 0:972874f31c98 218 cnt = pb->width;
iforce2d 0:972874f31c98 219 if ( is_odd )
iforce2d 0:972874f31c98 220 ptr += cnt;
iforce2d 0:972874f31c98 221 cnt >>= 1;
iforce2d 0:972874f31c98 222 do
iforce2d 0:972874f31c98 223 {
iforce2d 0:972874f31c98 224 left = *ptr++;
iforce2d 0:972874f31c98 225 right = *ptr++;
iforce2d 0:972874f31c98 226 u8g_dev_ssd1327_2bit_write_4_pixel(u8g, dev, left, right);
iforce2d 0:972874f31c98 227 cnt--;
iforce2d 0:972874f31c98 228 } while( cnt > 0 );
iforce2d 0:972874f31c98 229 }
iforce2d 0:972874f31c98 230
iforce2d 0:972874f31c98 231 uint8_t u8g_dev_ssd1327_96x96_gr_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
iforce2d 0:972874f31c98 232 {
iforce2d 0:972874f31c98 233 switch(msg)
iforce2d 0:972874f31c98 234 {
iforce2d 0:972874f31c98 235 case U8G_DEV_MSG_INIT:
iforce2d 0:972874f31c98 236 u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
iforce2d 0:972874f31c98 237 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1327_2bit_96x96_init_seq);
iforce2d 0:972874f31c98 238 break;
iforce2d 0:972874f31c98 239 case U8G_DEV_MSG_STOP:
iforce2d 0:972874f31c98 240 break;
iforce2d 0:972874f31c98 241 case U8G_DEV_MSG_PAGE_NEXT:
iforce2d 0:972874f31c98 242 {
iforce2d 0:972874f31c98 243 u8g_dev_ssd1327_2bit_prepare_page(u8g, dev);
iforce2d 0:972874f31c98 244 u8g_dev_ssd1327_2bit_write_buffer(u8g, dev);
iforce2d 0:972874f31c98 245 u8g_SetChipSelect(u8g, dev, 0);
iforce2d 0:972874f31c98 246 }
iforce2d 0:972874f31c98 247 break;
iforce2d 0:972874f31c98 248 case U8G_DEV_MSG_CONTRAST:
iforce2d 0:972874f31c98 249 u8g_SetChipSelect(u8g, dev, 1);
iforce2d 0:972874f31c98 250 u8g_SetAddress(u8g, dev, 0); /* instruction mode */
iforce2d 0:972874f31c98 251 u8g_WriteByte(u8g, dev, 0x081);
iforce2d 0:972874f31c98 252 u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 1);
iforce2d 0:972874f31c98 253 u8g_SetChipSelect(u8g, dev, 0);
iforce2d 0:972874f31c98 254 return 1;
iforce2d 0:972874f31c98 255 }
iforce2d 0:972874f31c98 256 return u8g_dev_pb8v2_base_fn(u8g, dev, msg, arg);
iforce2d 0:972874f31c98 257 }
iforce2d 0:972874f31c98 258
iforce2d 0:972874f31c98 259 uint8_t u8g_dev_ssd1327_96x96_2x_gr_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
iforce2d 0:972874f31c98 260 {
iforce2d 0:972874f31c98 261 switch(msg)
iforce2d 0:972874f31c98 262 {
iforce2d 0:972874f31c98 263 case U8G_DEV_MSG_INIT:
iforce2d 0:972874f31c98 264 u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
iforce2d 0:972874f31c98 265 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1327_2bit_96x96_init_seq);
iforce2d 0:972874f31c98 266 break;
iforce2d 0:972874f31c98 267 case U8G_DEV_MSG_STOP:
iforce2d 0:972874f31c98 268 break;
iforce2d 0:972874f31c98 269 case U8G_DEV_MSG_PAGE_NEXT:
iforce2d 0:972874f31c98 270 {
iforce2d 0:972874f31c98 271 u8g_dev_ssd1327_2bit_2x_prepare_page(u8g, dev, 0);
iforce2d 0:972874f31c98 272 u8g_dev_ssd1327_2bit_2x_write_buffer(u8g, dev, 0);
iforce2d 0:972874f31c98 273 u8g_dev_ssd1327_2bit_2x_prepare_page(u8g, dev, 1);
iforce2d 0:972874f31c98 274 u8g_dev_ssd1327_2bit_2x_write_buffer(u8g, dev, 1);
iforce2d 0:972874f31c98 275 u8g_SetChipSelect(u8g, dev, 0);
iforce2d 0:972874f31c98 276 }
iforce2d 0:972874f31c98 277 break;
iforce2d 0:972874f31c98 278 case U8G_DEV_MSG_CONTRAST:
iforce2d 0:972874f31c98 279 u8g_SetChipSelect(u8g, dev, 1);
iforce2d 0:972874f31c98 280 u8g_SetAddress(u8g, dev, 0); /* instruction mode */
iforce2d 0:972874f31c98 281 u8g_WriteByte(u8g, dev, 0x081);
iforce2d 0:972874f31c98 282 u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 1);
iforce2d 0:972874f31c98 283 u8g_SetChipSelect(u8g, dev, 0);
iforce2d 0:972874f31c98 284 return 1;
iforce2d 0:972874f31c98 285 }
iforce2d 0:972874f31c98 286 return u8g_dev_pb16v2_base_fn(u8g, dev, msg, arg);
iforce2d 0:972874f31c98 287 }
iforce2d 0:972874f31c98 288
iforce2d 0:972874f31c98 289 U8G_PB_DEV(u8g_dev_ssd1327_96x96_gr_sw_spi , WIDTH, HEIGHT, 4, u8g_dev_ssd1327_96x96_gr_fn, U8G_COM_SW_SPI);
iforce2d 0:972874f31c98 290 U8G_PB_DEV(u8g_dev_ssd1327_96x96_gr_hw_spi , WIDTH, HEIGHT, 4, u8g_dev_ssd1327_96x96_gr_fn, U8G_COM_HW_SPI);
iforce2d 0:972874f31c98 291 U8G_PB_DEV(u8g_dev_ssd1327_96x96_gr_i2c , WIDTH, HEIGHT, 4, u8g_dev_ssd1327_96x96_gr_fn, U8G_COM_SSD_I2C);
iforce2d 0:972874f31c98 292
iforce2d 0:972874f31c98 293 #define DWIDTH (2*WIDTH)
iforce2d 0:972874f31c98 294 uint8_t u8g_dev_ssd1327_96x96_2x_buf[DWIDTH] U8G_NOCOMMON ;
iforce2d 0:972874f31c98 295 u8g_pb_t u8g_dev_ssd1327_96x96_2x_pb = { {8, HEIGHT, 0, 0, 0}, WIDTH, u8g_dev_ssd1327_96x96_2x_buf};
iforce2d 0:972874f31c98 296 u8g_dev_t u8g_dev_ssd1327_96x96_2x_gr_sw_spi = { u8g_dev_ssd1327_96x96_2x_gr_fn, &u8g_dev_ssd1327_96x96_2x_pb, U8G_COM_SW_SPI };
iforce2d 0:972874f31c98 297 u8g_dev_t u8g_dev_ssd1327_96x96_2x_gr_hw_spi = { u8g_dev_ssd1327_96x96_2x_gr_fn, &u8g_dev_ssd1327_96x96_2x_pb, U8G_COM_HW_SPI };
iforce2d 0:972874f31c98 298 u8g_dev_t u8g_dev_ssd1327_96x96_2x_gr_i2c = { u8g_dev_ssd1327_96x96_2x_gr_fn, &u8g_dev_ssd1327_96x96_2x_pb, U8G_COM_SSD_I2C };
iforce2d 0:972874f31c98 299
iforce2d 0:972874f31c98 300