iforce2d Chris / Mbed 2 deprecated ubxDistanceMeter

Displays distance to start location on OLED screen.

Dependencies:   mbed

u8g_dev_ssd1325_nhd27oled_gr_new.c@0:972874f31c98, 2018-03-07 (annotated)

Committer:
iforce2d
Date:
Wed Mar 07 12:49:14 2018 +0000
Revision:
0:972874f31c98
First commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
iforce2d 0:972874f31c98 1 /*
iforce2d 0:972874f31c98 2
iforce2d 0:972874f31c98 3 u8g_dev_ssd1325_nhd27oled_gr.c
iforce2d 0:972874f31c98 4
iforce2d 0:972874f31c98 5 2-Bit (gray level) Driver for SSD1325 Controller (OLED Display)
iforce2d 0:972874f31c98 6 Rewritten with new architecture
iforce2d 0:972874f31c98 7 Tested with NHD-2.7-12864UCY3
iforce2d 0:972874f31c98 8
iforce2d 0:972874f31c98 9 Universal 8bit Graphics Library
iforce2d 0:972874f31c98 10
iforce2d 0:972874f31c98 11 Copyright (c) 2011, olikraus@gmail.com
iforce2d 0:972874f31c98 12 All rights reserved.
iforce2d 0:972874f31c98 13
iforce2d 0:972874f31c98 14 Redistribution and use in source and binary forms, with or without modification,
iforce2d 0:972874f31c98 15 are permitted provided that the following conditions are met:
iforce2d 0:972874f31c98 16
iforce2d 0:972874f31c98 17 * Redistributions of source code must retain the above copyright notice, this list
iforce2d 0:972874f31c98 18 of conditions and the following disclaimer.
iforce2d 0:972874f31c98 19
iforce2d 0:972874f31c98 20 * Redistributions in binary form must reproduce the above copyright notice, this
iforce2d 0:972874f31c98 21 list of conditions and the following disclaimer in the documentation and/or other
iforce2d 0:972874f31c98 22 materials provided with the distribution.
iforce2d 0:972874f31c98 23
iforce2d 0:972874f31c98 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
iforce2d 0:972874f31c98 25 CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
iforce2d 0:972874f31c98 26 INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
iforce2d 0:972874f31c98 27 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
iforce2d 0:972874f31c98 28 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
iforce2d 0:972874f31c98 29 CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
iforce2d 0:972874f31c98 30 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
iforce2d 0:972874f31c98 31 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
iforce2d 0:972874f31c98 32 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
iforce2d 0:972874f31c98 33 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
iforce2d 0:972874f31c98 34 STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
iforce2d 0:972874f31c98 35 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
iforce2d 0:972874f31c98 36 ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
iforce2d 0:972874f31c98 37
iforce2d 0:972874f31c98 38 SSD130x Monochrom OLED Controller
iforce2d 0:972874f31c98 39 SSD131x Character OLED Controller
iforce2d 0:972874f31c98 40 SSD132x Graylevel OLED Controller
iforce2d 0:972874f31c98 41 SSD1331 Color OLED Controller
iforce2d 0:972874f31c98 42
iforce2d 0:972874f31c98 43 */
iforce2d 0:972874f31c98 44
iforce2d 0:972874f31c98 45 #include "u8g.h"
iforce2d 0:972874f31c98 46
iforce2d 0:972874f31c98 47 #define WIDTH 128
iforce2d 0:972874f31c98 48 #define HEIGHT 64
iforce2d 0:972874f31c98 49
iforce2d 0:972874f31c98 50 /* http://www.newhavendisplay.com/app_notes/OLED_2_7_12864.txt */
iforce2d 0:972874f31c98 51 static const uint8_t u8g_dev_ssd1325_2bit_nhd_27_12864ucy3_init_seq[] PROGMEM = {
iforce2d 0:972874f31c98 52 U8G_ESC_DLY(10), /* delay 10 ms */
iforce2d 0:972874f31c98 53 U8G_ESC_CS(0), /* disable chip */
iforce2d 0:972874f31c98 54 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 55 U8G_ESC_RST(1), /* do reset low pulse with (1*16)+2 milliseconds */
iforce2d 0:972874f31c98 56 U8G_ESC_CS(1), /* enable chip */
iforce2d 0:972874f31c98 57 0x0ae, /* display off, sleep mode */
iforce2d 0:972874f31c98 58 0x0b3, 0x091, /* set display clock divide ratio/oscillator frequency (set clock as 135 frames/sec) */
iforce2d 0:972874f31c98 59 0x0a8, 0x03f, /* multiplex ratio: 0x03f * 1/64 duty */
iforce2d 0:972874f31c98 60 0x0a2, 0x04c, /* display offset, shift mapping ram counter */
iforce2d 0:972874f31c98 61 0x0a1, 0x000, /* display start line */
iforce2d 0:972874f31c98 62 0x0ad, 0x002, /* master configuration: disable embedded DC-DC, enable internal VCOMH */
iforce2d 0:972874f31c98 63 0x0a0, 0x052, /* remap configuration, horizontal address increment (bit 2 = 0), enable nibble remap (upper nibble is left, bit 1 = 1), old values: 0x0a0 0x0a6 */
iforce2d 0:972874f31c98 64 0x086, /* full current range (0x084, 0x085, 0x086) */
iforce2d 0:972874f31c98 65 0x0b8, /* set gray scale table */
iforce2d 0:972874f31c98 66 //0x01, 0x011, 0x022, 0x032, 0x043, 0x054, 0x065, 0x076,
iforce2d 0:972874f31c98 67 0x01, 0x011, 0x022, 0x032, 0x043, 0x054, 0x077, 0x077, // 4L mode uses 0, 2, 4, 7
iforce2d 0:972874f31c98 68 0x081, 0x070, /* contrast, brightness, 0..128, Newhaven: 0x040 */
iforce2d 0:972874f31c98 69 0x0b2, 0x051, /* frame frequency (row period) */
iforce2d 0:972874f31c98 70 0x0b1, 0x055, /* phase length */
iforce2d 0:972874f31c98 71 0x0bc, 0x010, /* pre-charge voltage level */
iforce2d 0:972874f31c98 72 0x0b4, 0x002, /* set pre-charge compensation level (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
iforce2d 0:972874f31c98 73 0x0b0, 0x028, /* enable pre-charge compensation (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
iforce2d 0:972874f31c98 74 0x0be, 0x01c, /* VCOMH voltage */
iforce2d 0:972874f31c98 75 0x0bf, 0x002|0x00d, /* VSL voltage level (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
iforce2d 0:972874f31c98 76 0x0a4, /* normal display mode */
iforce2d 0:972874f31c98 77 0x0af, /* display on */
iforce2d 0:972874f31c98 78 U8G_ESC_DLY(50), /* delay 50 ms */
iforce2d 0:972874f31c98 79 U8G_ESC_CS(0), /* disable chip */
iforce2d 0:972874f31c98 80 U8G_ESC_END /* end of sequence */
iforce2d 0:972874f31c98 81 };
iforce2d 0:972874f31c98 82
iforce2d 0:972874f31c98 83 static const uint8_t u8g_dev_ssd1325_2bit_nhd_27_12864ucy3_prepare_page_seq[] PROGMEM = {
iforce2d 0:972874f31c98 84 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 85 U8G_ESC_CS(1), /* enable chip */
iforce2d 0:972874f31c98 86 0x015, /* column address... */
iforce2d 0:972874f31c98 87 0x000, /* start at column 0 */
iforce2d 0:972874f31c98 88 0x03f, /* end at column 63 (which is y == 127), because there are two pixel in one column */
iforce2d 0:972874f31c98 89 0x075, /* row address... */
iforce2d 0:972874f31c98 90 U8G_ESC_END /* end of sequence */
iforce2d 0:972874f31c98 91 };
iforce2d 0:972874f31c98 92
iforce2d 0:972874f31c98 93 static void u8g_dev_ssd1325_gr_prepare_row(u8g_t *u8g, u8g_dev_t *dev, uint8_t delta_row)
iforce2d 0:972874f31c98 94 {
iforce2d 0:972874f31c98 95 uint8_t row = ((u8g_pb_t *)(dev->dev_mem))->p.page;
iforce2d 0:972874f31c98 96
iforce2d 0:972874f31c98 97 row *= ((u8g_pb_t *)(dev->dev_mem))->p.page_height;
iforce2d 0:972874f31c98 98 row += delta_row;
iforce2d 0:972874f31c98 99
iforce2d 0:972874f31c98 100 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1325_2bit_nhd_27_12864ucy3_prepare_page_seq);
iforce2d 0:972874f31c98 101
iforce2d 0:972874f31c98 102 u8g_WriteByte(u8g, dev, row); /* start at the selected row */
iforce2d 0:972874f31c98 103 u8g_WriteByte(u8g, dev, row+1); /* end within the selected row */
iforce2d 0:972874f31c98 104
iforce2d 0:972874f31c98 105 //u8g_SetAddress(u8g, dev, 0); /* instruction mode mode */
iforce2d 0:972874f31c98 106 //u8g_WriteByte(u8g, dev, 0x05c); /* write to ram */
iforce2d 0:972874f31c98 107 u8g_SetAddress(u8g, dev, 1); /* data mode */
iforce2d 0:972874f31c98 108 }
iforce2d 0:972874f31c98 109
iforce2d 0:972874f31c98 110 static const uint8_t u8g_dev_ssd13xx_sleep_on[] PROGMEM = {
iforce2d 0:972874f31c98 111 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 112 U8G_ESC_CS(1), /* enable chip */
iforce2d 0:972874f31c98 113 0x0ae, /* display off */
iforce2d 0:972874f31c98 114 U8G_ESC_CS(1), /* disable chip */
iforce2d 0:972874f31c98 115 U8G_ESC_END /* end of sequence */
iforce2d 0:972874f31c98 116 };
iforce2d 0:972874f31c98 117
iforce2d 0:972874f31c98 118 static const uint8_t u8g_dev_ssd13xx_sleep_off[] PROGMEM = {
iforce2d 0:972874f31c98 119 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 120 U8G_ESC_CS(1), /* enable chip */
iforce2d 0:972874f31c98 121 0x0af, /* display on */
iforce2d 0:972874f31c98 122 U8G_ESC_DLY(50), /* delay 50 ms */
iforce2d 0:972874f31c98 123 U8G_ESC_CS(1), /* disable chip */
iforce2d 0:972874f31c98 124 U8G_ESC_END /* end of sequence */
iforce2d 0:972874f31c98 125 };
iforce2d 0:972874f31c98 126
iforce2d 0:972874f31c98 127
iforce2d 0:972874f31c98 128
iforce2d 0:972874f31c98 129 static uint8_t u8g_dev_ssd1325_nhd27oled_gr_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
iforce2d 0:972874f31c98 130 {
iforce2d 0:972874f31c98 131 switch(msg)
iforce2d 0:972874f31c98 132 {
iforce2d 0:972874f31c98 133 case U8G_DEV_MSG_INIT:
iforce2d 0:972874f31c98 134 u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
iforce2d 0:972874f31c98 135 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1325_2bit_nhd_27_12864ucy3_init_seq);
iforce2d 0:972874f31c98 136 break;
iforce2d 0:972874f31c98 137 case U8G_DEV_MSG_STOP:
iforce2d 0:972874f31c98 138 break;
iforce2d 0:972874f31c98 139 case U8G_DEV_MSG_PAGE_NEXT:
iforce2d 0:972874f31c98 140 {
iforce2d 0:972874f31c98 141 uint8_t i;
iforce2d 0:972874f31c98 142 u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
iforce2d 0:972874f31c98 143 uint8_t *p = pb->buf;
iforce2d 0:972874f31c98 144 u8g_uint_t cnt;
iforce2d 0:972874f31c98 145 cnt = pb->width;
iforce2d 0:972874f31c98 146 cnt >>= 2;
iforce2d 0:972874f31c98 147
iforce2d 0:972874f31c98 148 for( i = 0; i < pb->p.page_height; i++ )
iforce2d 0:972874f31c98 149 {
iforce2d 0:972874f31c98 150 u8g_dev_ssd1325_gr_prepare_row(u8g, dev, i); /* this will also enable chip select */
iforce2d 0:972874f31c98 151 u8g_WriteSequence4LTo16GrDevice(u8g, dev, cnt, p);
iforce2d 0:972874f31c98 152 u8g_SetChipSelect(u8g, dev, 0);
iforce2d 0:972874f31c98 153 p+=cnt;
iforce2d 0:972874f31c98 154 }
iforce2d 0:972874f31c98 155 }
iforce2d 0:972874f31c98 156 break;
iforce2d 0:972874f31c98 157 case U8G_DEV_MSG_CONTRAST:
iforce2d 0:972874f31c98 158 u8g_SetChipSelect(u8g, dev, 1);
iforce2d 0:972874f31c98 159 u8g_SetAddress(u8g, dev, 0); /* instruction mode */
iforce2d 0:972874f31c98 160 u8g_WriteByte(u8g, dev, 0x081);
iforce2d 0:972874f31c98 161 u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 1);
iforce2d 0:972874f31c98 162 u8g_SetChipSelect(u8g, dev, 0);
iforce2d 0:972874f31c98 163 return 1;
iforce2d 0:972874f31c98 164 case U8G_DEV_MSG_SLEEP_ON:
iforce2d 0:972874f31c98 165 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_on);
iforce2d 0:972874f31c98 166 return 1;
iforce2d 0:972874f31c98 167 case U8G_DEV_MSG_SLEEP_OFF:
iforce2d 0:972874f31c98 168 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_off);
iforce2d 0:972874f31c98 169 return 1;
iforce2d 0:972874f31c98 170 }
iforce2d 0:972874f31c98 171 return u8g_dev_pb8h2_base_fn(u8g, dev, msg, arg);
iforce2d 0:972874f31c98 172 }
iforce2d 0:972874f31c98 173
iforce2d 0:972874f31c98 174
iforce2d 0:972874f31c98 175
iforce2d 0:972874f31c98 176 static uint8_t u8g_dev_ssd1325_nhd27oled_2x_gr_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
iforce2d 0:972874f31c98 177 {
iforce2d 0:972874f31c98 178 switch(msg)
iforce2d 0:972874f31c98 179 {
iforce2d 0:972874f31c98 180 case U8G_DEV_MSG_INIT:
iforce2d 0:972874f31c98 181 u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
iforce2d 0:972874f31c98 182 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1325_2bit_nhd_27_12864ucy3_init_seq);
iforce2d 0:972874f31c98 183 break;
iforce2d 0:972874f31c98 184 case U8G_DEV_MSG_STOP:
iforce2d 0:972874f31c98 185 break;
iforce2d 0:972874f31c98 186 case U8G_DEV_MSG_PAGE_NEXT:
iforce2d 0:972874f31c98 187 {
iforce2d 0:972874f31c98 188 uint8_t i;
iforce2d 0:972874f31c98 189 u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
iforce2d 0:972874f31c98 190 uint8_t *p = pb->buf;
iforce2d 0:972874f31c98 191 u8g_uint_t cnt;
iforce2d 0:972874f31c98 192 cnt = pb->width;
iforce2d 0:972874f31c98 193 cnt >>= 2;
iforce2d 0:972874f31c98 194
iforce2d 0:972874f31c98 195 for( i = 0; i < pb->p.page_height; i++ )
iforce2d 0:972874f31c98 196 {
iforce2d 0:972874f31c98 197 u8g_dev_ssd1325_gr_prepare_row(u8g, dev, i); /* this will also enable chip select */
iforce2d 0:972874f31c98 198 u8g_WriteSequence4LTo16GrDevice(u8g, dev, cnt, p);
iforce2d 0:972874f31c98 199 u8g_SetChipSelect(u8g, dev, 0);
iforce2d 0:972874f31c98 200 p+=cnt;
iforce2d 0:972874f31c98 201 }
iforce2d 0:972874f31c98 202 }
iforce2d 0:972874f31c98 203 break;
iforce2d 0:972874f31c98 204 case U8G_DEV_MSG_CONTRAST:
iforce2d 0:972874f31c98 205 u8g_SetChipSelect(u8g, dev, 1);
iforce2d 0:972874f31c98 206 u8g_SetAddress(u8g, dev, 0); /* instruction mode */
iforce2d 0:972874f31c98 207 u8g_WriteByte(u8g, dev, 0x081);
iforce2d 0:972874f31c98 208 u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 1);
iforce2d 0:972874f31c98 209 u8g_SetChipSelect(u8g, dev, 0);
iforce2d 0:972874f31c98 210 return 1;
iforce2d 0:972874f31c98 211 case U8G_DEV_MSG_SLEEP_ON:
iforce2d 0:972874f31c98 212 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_on);
iforce2d 0:972874f31c98 213 return 1;
iforce2d 0:972874f31c98 214 case U8G_DEV_MSG_SLEEP_OFF:
iforce2d 0:972874f31c98 215 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_off);
iforce2d 0:972874f31c98 216 return 1;
iforce2d 0:972874f31c98 217 }
iforce2d 0:972874f31c98 218 return u8g_dev_pb16h2_base_fn(u8g, dev, msg, arg);
iforce2d 0:972874f31c98 219 }
iforce2d 0:972874f31c98 220
iforce2d 0:972874f31c98 221 U8G_PB_DEV(u8g_dev_ssd1325_nhd27oled_gr_sw_spi , WIDTH, HEIGHT, 4, u8g_dev_ssd1325_nhd27oled_gr_fn, U8G_COM_SW_SPI);
iforce2d 0:972874f31c98 222 U8G_PB_DEV(u8g_dev_ssd1325_nhd27oled_gr_hw_spi , WIDTH, HEIGHT, 4, u8g_dev_ssd1325_nhd27oled_gr_fn, U8G_COM_HW_SPI);
iforce2d 0:972874f31c98 223
iforce2d 0:972874f31c98 224 uint8_t u8g_dev_ssd1325_nhd27oled_2x_buf[WIDTH*2] U8G_NOCOMMON ;
iforce2d 0:972874f31c98 225 u8g_pb_t u8g_dev_ssd1325_nhd27oled_2x_pb = { {8, HEIGHT, 0, 0, 0}, WIDTH, u8g_dev_ssd1325_nhd27oled_2x_buf};
iforce2d 0:972874f31c98 226 u8g_dev_t u8g_dev_ssd1325_nhd27oled_2x_gr_sw_spi = { u8g_dev_ssd1325_nhd27oled_2x_gr_fn, &u8g_dev_ssd1325_nhd27oled_2x_pb, U8G_COM_SW_SPI };
iforce2d 0:972874f31c98 227 u8g_dev_t u8g_dev_ssd1325_nhd27oled_2x_gr_hw_spi = { u8g_dev_ssd1325_nhd27oled_2x_gr_fn, &u8g_dev_ssd1325_nhd27oled_2x_pb, U8G_COM_HW_SPI };
iforce2d 0:972874f31c98 228