iforce2d Chris / Mbed 2 deprecated ubxDistanceMeter

Displays distance to start location on OLED screen.

Dependencies:   mbed

u8g_dev_ssd1325_nhd27oled_gr.c@0:972874f31c98, 2018-03-07 (annotated)

Committer:
iforce2d
Date:
Wed Mar 07 12:49:14 2018 +0000
Revision:
0:972874f31c98
First commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
iforce2d 0:972874f31c98 1 /*
iforce2d 0:972874f31c98 2
iforce2d 0:972874f31c98 3 u8g_dev_ssd1325_nhd27oled_gr.c
iforce2d 0:972874f31c98 4
iforce2d 0:972874f31c98 5 2-Bit (gray level) Driver for SSD1325 Controller (OLED Display)
iforce2d 0:972874f31c98 6 Tested with NHD-2.7-12864UCY3
iforce2d 0:972874f31c98 7
iforce2d 0:972874f31c98 8 Universal 8bit Graphics Library
iforce2d 0:972874f31c98 9
iforce2d 0:972874f31c98 10 Copyright (c) 2011, olikraus@gmail.com
iforce2d 0:972874f31c98 11 All rights reserved.
iforce2d 0:972874f31c98 12
iforce2d 0:972874f31c98 13 Redistribution and use in source and binary forms, with or without modification,
iforce2d 0:972874f31c98 14 are permitted provided that the following conditions are met:
iforce2d 0:972874f31c98 15
iforce2d 0:972874f31c98 16 * Redistributions of source code must retain the above copyright notice, this list
iforce2d 0:972874f31c98 17 of conditions and the following disclaimer.
iforce2d 0:972874f31c98 18
iforce2d 0:972874f31c98 19 * Redistributions in binary form must reproduce the above copyright notice, this
iforce2d 0:972874f31c98 20 list of conditions and the following disclaimer in the documentation and/or other
iforce2d 0:972874f31c98 21 materials provided with the distribution.
iforce2d 0:972874f31c98 22
iforce2d 0:972874f31c98 23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
iforce2d 0:972874f31c98 24 CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
iforce2d 0:972874f31c98 25 INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
iforce2d 0:972874f31c98 26 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
iforce2d 0:972874f31c98 27 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
iforce2d 0:972874f31c98 28 CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
iforce2d 0:972874f31c98 29 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
iforce2d 0:972874f31c98 30 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
iforce2d 0:972874f31c98 31 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
iforce2d 0:972874f31c98 32 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
iforce2d 0:972874f31c98 33 STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
iforce2d 0:972874f31c98 34 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
iforce2d 0:972874f31c98 35 ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
iforce2d 0:972874f31c98 36
iforce2d 0:972874f31c98 37 SSD130x Monochrom OLED Controller
iforce2d 0:972874f31c98 38 SSD131x Character OLED Controller
iforce2d 0:972874f31c98 39 SSD132x Graylevel OLED Controller
iforce2d 0:972874f31c98 40 SSD1331 Color OLED Controller
iforce2d 0:972874f31c98 41
iforce2d 0:972874f31c98 42 */
iforce2d 0:972874f31c98 43
iforce2d 0:972874f31c98 44 #ifdef OBSOLETE_CODE
iforce2d 0:972874f31c98 45
iforce2d 0:972874f31c98 46 #include "u8g.h"
iforce2d 0:972874f31c98 47
iforce2d 0:972874f31c98 48 #define WIDTH 128
iforce2d 0:972874f31c98 49 #define HEIGHT 64
iforce2d 0:972874f31c98 50
iforce2d 0:972874f31c98 51 /* http://www.newhavendisplay.com/app_notes/OLED_2_7_12864.txt */
iforce2d 0:972874f31c98 52 static const uint8_t u8g_dev_ssd1325_2bit_nhd_27_12864ucy3_init_seq[] PROGMEM = {
iforce2d 0:972874f31c98 53 U8G_ESC_DLY(10), /* delay 10 ms */
iforce2d 0:972874f31c98 54 U8G_ESC_CS(0), /* disable chip */
iforce2d 0:972874f31c98 55 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 56 U8G_ESC_RST(1), /* do reset low pulse with (1*16)+2 milliseconds */
iforce2d 0:972874f31c98 57 U8G_ESC_CS(1), /* enable chip */
iforce2d 0:972874f31c98 58 0x0ae, /* display off, sleep mode */
iforce2d 0:972874f31c98 59 0x0b3, 0x091, /* set display clock divide ratio/oscillator frequency (set clock as 135 frames/sec) */
iforce2d 0:972874f31c98 60 0x0a8, 0x03f, /* multiplex ratio: 0x03f * 1/64 duty */
iforce2d 0:972874f31c98 61 0x0a2, 0x04c, /* display offset, shift mapping ram counter */
iforce2d 0:972874f31c98 62 0x0a1, 0x000, /* display start line */
iforce2d 0:972874f31c98 63 0x0ad, 0x002, /* master configuration: disable embedded DC-DC, enable internal VCOMH */
iforce2d 0:972874f31c98 64 0x0a0, 0x056, /* remap configuration, vertical address increment, enable nibble remap (upper nibble is left) */
iforce2d 0:972874f31c98 65 0x086, /* full current range (0x084, 0x085, 0x086) */
iforce2d 0:972874f31c98 66 0x0b8, /* set gray scale table */
iforce2d 0:972874f31c98 67 //0x01, 0x011, 0x022, 0x032, 0x043, 0x054, 0x065, 0x076,
iforce2d 0:972874f31c98 68 0x01, 0x011, 0x022, 0x032, 0x043, 0x054, 0x077, 0x077, // 4L mode uses 0, 2, 4, 7
iforce2d 0:972874f31c98 69 0x081, 0x070, /* contrast, brightness, 0..128, Newhaven: 0x040 */
iforce2d 0:972874f31c98 70 0x0b2, 0x051, /* frame frequency (row period) */
iforce2d 0:972874f31c98 71 0x0b1, 0x055, /* phase length */
iforce2d 0:972874f31c98 72 0x0bc, 0x010, /* pre-charge voltage level */
iforce2d 0:972874f31c98 73 0x0b4, 0x002, /* set pre-charge compensation level (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
iforce2d 0:972874f31c98 74 0x0b0, 0x028, /* enable pre-charge compensation (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
iforce2d 0:972874f31c98 75 0x0be, 0x01c, /* VCOMH voltage */
iforce2d 0:972874f31c98 76 0x0bf, 0x002|0x00d, /* VSL voltage level (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
iforce2d 0:972874f31c98 77 0x0a5, /* all pixel on */
iforce2d 0:972874f31c98 78 0x0af, /* display on */
iforce2d 0:972874f31c98 79 U8G_ESC_DLY(100), /* delay 100 ms */
iforce2d 0:972874f31c98 80 U8G_ESC_DLY(100), /* delay 100 ms */
iforce2d 0:972874f31c98 81 0x0a4, /* normal display mode */
iforce2d 0:972874f31c98 82 U8G_ESC_CS(0), /* disable chip */
iforce2d 0:972874f31c98 83 U8G_ESC_END /* end of sequence */
iforce2d 0:972874f31c98 84 };
iforce2d 0:972874f31c98 85
iforce2d 0:972874f31c98 86 static const uint8_t u8g_dev_ssd1325_2bit_nhd_27_12864ucy3_prepare_page_seq[] PROGMEM = {
iforce2d 0:972874f31c98 87 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 88 U8G_ESC_CS(1), /* enable chip */
iforce2d 0:972874f31c98 89 0x015, /* column address... */
iforce2d 0:972874f31c98 90 0x000, /* start at column 0 */
iforce2d 0:972874f31c98 91 0x03f, /* end at column 63 (which is y == 127), because there are two pixel in one column */
iforce2d 0:972874f31c98 92 0x075, /* row address... */
iforce2d 0:972874f31c98 93 U8G_ESC_END /* end of sequence */
iforce2d 0:972874f31c98 94 };
iforce2d 0:972874f31c98 95
iforce2d 0:972874f31c98 96
iforce2d 0:972874f31c98 97 static void u8g_dev_ssd1325_2bit_prepare_page(u8g_t *u8g, u8g_dev_t *dev)
iforce2d 0:972874f31c98 98 {
iforce2d 0:972874f31c98 99 uint8_t page = ((u8g_pb_t *)(dev->dev_mem))->p.page;
iforce2d 0:972874f31c98 100
iforce2d 0:972874f31c98 101 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1325_2bit_nhd_27_12864ucy3_prepare_page_seq);
iforce2d 0:972874f31c98 102
iforce2d 0:972874f31c98 103 page <<= 2;
iforce2d 0:972874f31c98 104 u8g_WriteByte(u8g, dev, page); /* start at the selected page */
iforce2d 0:972874f31c98 105 page += 3;
iforce2d 0:972874f31c98 106 u8g_WriteByte(u8g, dev, page); /* end within the selected page */
iforce2d 0:972874f31c98 107
iforce2d 0:972874f31c98 108 u8g_SetAddress(u8g, dev, 1); /* data mode */
iforce2d 0:972874f31c98 109 }
iforce2d 0:972874f31c98 110
iforce2d 0:972874f31c98 111 static void u8g_dev_ssd1325_2bit_2x_prepare_page(u8g_t *u8g, u8g_dev_t *dev, uint8_t is_odd)
iforce2d 0:972874f31c98 112 {
iforce2d 0:972874f31c98 113 uint8_t page = ((u8g_pb_t *)(dev->dev_mem))->p.page;
iforce2d 0:972874f31c98 114
iforce2d 0:972874f31c98 115 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1325_2bit_nhd_27_12864ucy3_prepare_page_seq);
iforce2d 0:972874f31c98 116
iforce2d 0:972874f31c98 117 page <<= 1;
iforce2d 0:972874f31c98 118 page += is_odd;
iforce2d 0:972874f31c98 119
iforce2d 0:972874f31c98 120
iforce2d 0:972874f31c98 121 page <<= 2;
iforce2d 0:972874f31c98 122 u8g_WriteByte(u8g, dev, page); /* start at the selected page */
iforce2d 0:972874f31c98 123 page += 3;
iforce2d 0:972874f31c98 124 u8g_WriteByte(u8g, dev, page); /* end within the selected page */
iforce2d 0:972874f31c98 125
iforce2d 0:972874f31c98 126 u8g_SetAddress(u8g, dev, 1); /* data mode */
iforce2d 0:972874f31c98 127 }
iforce2d 0:972874f31c98 128
iforce2d 0:972874f31c98 129 /* assumes row autoincrement and activated nibble remap */
iforce2d 0:972874f31c98 130 static void u8g_dev_ssd1325_2bit_write_4_pixel(u8g_t *u8g, u8g_dev_t *dev, uint8_t left, uint8_t right)
iforce2d 0:972874f31c98 131 {
iforce2d 0:972874f31c98 132 uint8_t d, tmp, cnt;
iforce2d 0:972874f31c98 133 cnt = 4;
iforce2d 0:972874f31c98 134 do
iforce2d 0:972874f31c98 135 {
iforce2d 0:972874f31c98 136 d = left;
iforce2d 0:972874f31c98 137 d &= 3;
iforce2d 0:972874f31c98 138 d <<= 4;
iforce2d 0:972874f31c98 139 tmp = right;
iforce2d 0:972874f31c98 140 tmp &= 3;
iforce2d 0:972874f31c98 141 d |= tmp;
iforce2d 0:972874f31c98 142 d <<= 2;
iforce2d 0:972874f31c98 143 u8g_WriteByte(u8g, dev, d);
iforce2d 0:972874f31c98 144 left >>= 2;
iforce2d 0:972874f31c98 145 right >>= 2;
iforce2d 0:972874f31c98 146 cnt--;
iforce2d 0:972874f31c98 147 }while ( cnt > 0 );
iforce2d 0:972874f31c98 148 }
iforce2d 0:972874f31c98 149
iforce2d 0:972874f31c98 150 static void u8g_dev_ssd1325_2bit_write_buffer(u8g_t *u8g, u8g_dev_t *dev)
iforce2d 0:972874f31c98 151 {
iforce2d 0:972874f31c98 152 uint8_t cnt, left, right;
iforce2d 0:972874f31c98 153 uint8_t *ptr;
iforce2d 0:972874f31c98 154 u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
iforce2d 0:972874f31c98 155
iforce2d 0:972874f31c98 156 cnt = pb->width;
iforce2d 0:972874f31c98 157 cnt >>= 1;
iforce2d 0:972874f31c98 158 ptr = pb->buf;
iforce2d 0:972874f31c98 159 do
iforce2d 0:972874f31c98 160 {
iforce2d 0:972874f31c98 161 left = *ptr++;
iforce2d 0:972874f31c98 162 right = *ptr++;
iforce2d 0:972874f31c98 163 u8g_dev_ssd1325_2bit_write_4_pixel(u8g, dev, left, right);
iforce2d 0:972874f31c98 164 cnt--;
iforce2d 0:972874f31c98 165 } while( cnt > 0 );
iforce2d 0:972874f31c98 166 }
iforce2d 0:972874f31c98 167
iforce2d 0:972874f31c98 168 static void u8g_dev_ssd1325_2bit_2x_write_buffer(u8g_t *u8g, u8g_dev_t *dev, uint8_t is_odd)
iforce2d 0:972874f31c98 169 {
iforce2d 0:972874f31c98 170 uint8_t cnt, left, right;
iforce2d 0:972874f31c98 171 uint8_t *ptr;
iforce2d 0:972874f31c98 172 u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
iforce2d 0:972874f31c98 173
iforce2d 0:972874f31c98 174 ptr = pb->buf;
iforce2d 0:972874f31c98 175 cnt = pb->width;
iforce2d 0:972874f31c98 176 if ( is_odd )
iforce2d 0:972874f31c98 177 ptr += cnt;
iforce2d 0:972874f31c98 178 cnt >>= 1;
iforce2d 0:972874f31c98 179 do
iforce2d 0:972874f31c98 180 {
iforce2d 0:972874f31c98 181 left = *ptr++;
iforce2d 0:972874f31c98 182 right = *ptr++;
iforce2d 0:972874f31c98 183 u8g_dev_ssd1325_2bit_write_4_pixel(u8g, dev, left, right);
iforce2d 0:972874f31c98 184 cnt--;
iforce2d 0:972874f31c98 185 } while( cnt > 0 );
iforce2d 0:972874f31c98 186 }
iforce2d 0:972874f31c98 187
iforce2d 0:972874f31c98 188 static uint8_t u8g_dev_ssd1325_nhd27oled_gr_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
iforce2d 0:972874f31c98 189 {
iforce2d 0:972874f31c98 190 switch(msg)
iforce2d 0:972874f31c98 191 {
iforce2d 0:972874f31c98 192 case U8G_DEV_MSG_INIT:
iforce2d 0:972874f31c98 193 u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
iforce2d 0:972874f31c98 194 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1325_2bit_nhd_27_12864ucy3_init_seq);
iforce2d 0:972874f31c98 195 break;
iforce2d 0:972874f31c98 196 case U8G_DEV_MSG_STOP:
iforce2d 0:972874f31c98 197 break;
iforce2d 0:972874f31c98 198 case U8G_DEV_MSG_PAGE_NEXT:
iforce2d 0:972874f31c98 199 {
iforce2d 0:972874f31c98 200 u8g_dev_ssd1325_2bit_prepare_page(u8g, dev);
iforce2d 0:972874f31c98 201 u8g_dev_ssd1325_2bit_write_buffer(u8g, dev);
iforce2d 0:972874f31c98 202 u8g_SetChipSelect(u8g, dev, 0);
iforce2d 0:972874f31c98 203 }
iforce2d 0:972874f31c98 204 break;
iforce2d 0:972874f31c98 205 case U8G_DEV_MSG_CONTRAST:
iforce2d 0:972874f31c98 206 u8g_SetChipSelect(u8g, dev, 1);
iforce2d 0:972874f31c98 207 u8g_SetAddress(u8g, dev, 0); /* instruction mode */
iforce2d 0:972874f31c98 208 u8g_WriteByte(u8g, dev, 0x081);
iforce2d 0:972874f31c98 209 u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 1);
iforce2d 0:972874f31c98 210 u8g_SetChipSelect(u8g, dev, 0);
iforce2d 0:972874f31c98 211 return 1;
iforce2d 0:972874f31c98 212 }
iforce2d 0:972874f31c98 213 return u8g_dev_pb8v2_base_fn(u8g, dev, msg, arg);
iforce2d 0:972874f31c98 214 }
iforce2d 0:972874f31c98 215
iforce2d 0:972874f31c98 216 static uint8_t u8g_dev_ssd1325_nhd27oled_2x_gr_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
iforce2d 0:972874f31c98 217 {
iforce2d 0:972874f31c98 218 switch(msg)
iforce2d 0:972874f31c98 219 {
iforce2d 0:972874f31c98 220 case U8G_DEV_MSG_INIT:
iforce2d 0:972874f31c98 221 u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
iforce2d 0:972874f31c98 222 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1325_2bit_nhd_27_12864ucy3_init_seq);
iforce2d 0:972874f31c98 223 break;
iforce2d 0:972874f31c98 224 case U8G_DEV_MSG_STOP:
iforce2d 0:972874f31c98 225 break;
iforce2d 0:972874f31c98 226 case U8G_DEV_MSG_PAGE_NEXT:
iforce2d 0:972874f31c98 227 {
iforce2d 0:972874f31c98 228 u8g_dev_ssd1325_2bit_2x_prepare_page(u8g, dev, 0);
iforce2d 0:972874f31c98 229 u8g_dev_ssd1325_2bit_2x_write_buffer(u8g, dev, 0);
iforce2d 0:972874f31c98 230 u8g_dev_ssd1325_2bit_2x_prepare_page(u8g, dev, 1);
iforce2d 0:972874f31c98 231 u8g_dev_ssd1325_2bit_2x_write_buffer(u8g, dev, 1);
iforce2d 0:972874f31c98 232 u8g_SetChipSelect(u8g, dev, 0);
iforce2d 0:972874f31c98 233 }
iforce2d 0:972874f31c98 234 break;
iforce2d 0:972874f31c98 235 case U8G_DEV_MSG_CONTRAST:
iforce2d 0:972874f31c98 236 u8g_SetChipSelect(u8g, dev, 1);
iforce2d 0:972874f31c98 237 u8g_SetAddress(u8g, dev, 0); /* instruction mode */
iforce2d 0:972874f31c98 238 u8g_WriteByte(u8g, dev, 0x081);
iforce2d 0:972874f31c98 239 u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 1);
iforce2d 0:972874f31c98 240 u8g_SetChipSelect(u8g, dev, 0);
iforce2d 0:972874f31c98 241 return 1;
iforce2d 0:972874f31c98 242 }
iforce2d 0:972874f31c98 243 return u8g_dev_pb16v2_base_fn(u8g, dev, msg, arg);
iforce2d 0:972874f31c98 244 }
iforce2d 0:972874f31c98 245
iforce2d 0:972874f31c98 246 //U8G_PB_DEV(u8g_dev_ssd1325_nhd27oled_gr_sw_spi , WIDTH, HEIGHT, 4, u8g_dev_ssd1325_nhd27oled_gr_fn, U8G_COM_SW_SPI);
iforce2d 0:972874f31c98 247 //U8G_PB_DEV(u8g_dev_ssd1325_nhd27oled_gr_hw_spi , WIDTH, HEIGHT, 4, u8g_dev_ssd1325_nhd27oled_gr_fn, U8G_COM_HW_SPI);
iforce2d 0:972874f31c98 248
iforce2d 0:972874f31c98 249 //uint8_t u8g_dev_ssd1325_nhd27oled_2x_buf[WIDTH*2] U8G_NOCOMMON ;
iforce2d 0:972874f31c98 250 //u8g_pb_t u8g_dev_ssd1325_nhd27oled_2x_pb = { {8, HEIGHT, 0, 0, 0}, WIDTH, u8g_dev_ssd1325_nhd27oled_2x_buf};
iforce2d 0:972874f31c98 251 //u8g_dev_t u8g_dev_ssd1325_nhd27oled_2x_gr_sw_spi = { u8g_dev_ssd1325_nhd27oled_2x_gr_fn, &u8g_dev_ssd1325_nhd27oled_2x_pb, U8G_COM_SW_SPI };
iforce2d 0:972874f31c98 252 //u8g_dev_t u8g_dev_ssd1325_nhd27oled_2x_gr_hw_spi = { u8g_dev_ssd1325_nhd27oled_2x_gr_fn, &u8g_dev_ssd1325_nhd27oled_2x_pb, U8G_COM_HW_SPI };
iforce2d 0:972874f31c98 253
iforce2d 0:972874f31c98 254
iforce2d 0:972874f31c98 255 #endif /* OBSOLETE_CODE */
iforce2d 0:972874f31c98 256