iforce2d Chris / Mbed 2 deprecated ubxDistanceMeter

Displays distance to start location on OLED screen.

Dependencies:   mbed

u8g_dev_ssd1306_128x32.c@0:972874f31c98, 2018-03-07 (annotated)

Committer:
iforce2d
Date:
Wed Mar 07 12:49:14 2018 +0000
Revision:
0:972874f31c98
First commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
iforce2d 0:972874f31c98 1 /*
iforce2d 0:972874f31c98 2
iforce2d 0:972874f31c98 3 u8g_dev_ssd1306_128x32.c
iforce2d 0:972874f31c98 4
iforce2d 0:972874f31c98 5 Universal 8bit Graphics Library
iforce2d 0:972874f31c98 6
iforce2d 0:972874f31c98 7 Copyright (c) 2011, olikraus@gmail.com
iforce2d 0:972874f31c98 8 All rights reserved.
iforce2d 0:972874f31c98 9
iforce2d 0:972874f31c98 10 Redistribution and use in source and binary forms, with or without modification,
iforce2d 0:972874f31c98 11 are permitted provided that the following conditions are met:
iforce2d 0:972874f31c98 12
iforce2d 0:972874f31c98 13 * Redistributions of source code must retain the above copyright notice, this list
iforce2d 0:972874f31c98 14 of conditions and the following disclaimer.
iforce2d 0:972874f31c98 15
iforce2d 0:972874f31c98 16 * Redistributions in binary form must reproduce the above copyright notice, this
iforce2d 0:972874f31c98 17 list of conditions and the following disclaimer in the documentation and/or other
iforce2d 0:972874f31c98 18 materials provided with the distribution.
iforce2d 0:972874f31c98 19
iforce2d 0:972874f31c98 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
iforce2d 0:972874f31c98 21 CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
iforce2d 0:972874f31c98 22 INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
iforce2d 0:972874f31c98 23 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
iforce2d 0:972874f31c98 24 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
iforce2d 0:972874f31c98 25 CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
iforce2d 0:972874f31c98 26 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
iforce2d 0:972874f31c98 27 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
iforce2d 0:972874f31c98 28 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
iforce2d 0:972874f31c98 29 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
iforce2d 0:972874f31c98 30 STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
iforce2d 0:972874f31c98 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
iforce2d 0:972874f31c98 32 ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
iforce2d 0:972874f31c98 33
iforce2d 0:972874f31c98 34
iforce2d 0:972874f31c98 35 23 Feb 2013: Fixed, Issue 147
iforce2d 0:972874f31c98 36
iforce2d 0:972874f31c98 37 */
iforce2d 0:972874f31c98 38
iforce2d 0:972874f31c98 39
iforce2d 0:972874f31c98 40 #include "u8g.h"
iforce2d 0:972874f31c98 41
iforce2d 0:972874f31c98 42 #define WIDTH 128
iforce2d 0:972874f31c98 43 #define HEIGHT 32
iforce2d 0:972874f31c98 44 #define PAGE_HEIGHT 8
iforce2d 0:972874f31c98 45
iforce2d 0:972874f31c98 46
iforce2d 0:972874f31c98 47 /* init sequence adafruit 128x32 OLED (NOT TESTED) */
iforce2d 0:972874f31c98 48 static const uint8_t u8g_dev_ssd1306_128x32_adafruit1_init_seq[] PROGMEM = {
iforce2d 0:972874f31c98 49 U8G_ESC_CS(0), /* disable chip */
iforce2d 0:972874f31c98 50 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 51 U8G_ESC_RST(1), /* do reset low pulse with (1*16)+2 milliseconds */
iforce2d 0:972874f31c98 52 U8G_ESC_CS(1), /* enable chip */
iforce2d 0:972874f31c98 53
iforce2d 0:972874f31c98 54 0x0ae, /* display off, sleep mode */
iforce2d 0:972874f31c98 55 0x0d5, 0x080, /* clock divide ratio (0x00=1) and oscillator frequency (0x8) */
iforce2d 0:972874f31c98 56 0x0a8, 0x03f, /* */
iforce2d 0:972874f31c98 57
iforce2d 0:972874f31c98 58 0x0d3, 0x000, /* */
iforce2d 0:972874f31c98 59
iforce2d 0:972874f31c98 60 0x040, /* start line */
iforce2d 0:972874f31c98 61
iforce2d 0:972874f31c98 62 0x08d, 0x010, /* [1] charge pump setting (p62): 0x014 enable, 0x010 disable */
iforce2d 0:972874f31c98 63
iforce2d 0:972874f31c98 64 0x020, 0x000, /* */
iforce2d 0:972874f31c98 65 0x0a1, /* segment remap a0/a1*/
iforce2d 0:972874f31c98 66 0x0c8, /* c0: scan dir normal, c8: reverse */
iforce2d 0:972874f31c98 67 0x0da, 0x012, /* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5) */
iforce2d 0:972874f31c98 68 0x081, 0x09f, /* [1] set contrast control */
iforce2d 0:972874f31c98 69 0x0d9, 0x022, /* [1] pre-charge period 0x022/f1*/
iforce2d 0:972874f31c98 70 0x0db, 0x040, /* vcomh deselect level */
iforce2d 0:972874f31c98 71
iforce2d 0:972874f31c98 72 0x02e, /* 2012-05-27: Deactivate scroll */
iforce2d 0:972874f31c98 73 0x0a4, /* output ram to display */
iforce2d 0:972874f31c98 74 0x0a6, /* none inverted normal display mode */
iforce2d 0:972874f31c98 75 0x0af, /* display on */
iforce2d 0:972874f31c98 76
iforce2d 0:972874f31c98 77 U8G_ESC_CS(0), /* disable chip */
iforce2d 0:972874f31c98 78 U8G_ESC_END /* end of sequence */
iforce2d 0:972874f31c98 79 };
iforce2d 0:972874f31c98 80
iforce2d 0:972874f31c98 81
iforce2d 0:972874f31c98 82 /* init sequence adafruit 128x32 OLED (NOT TESTED) */
iforce2d 0:972874f31c98 83 static const uint8_t u8g_dev_ssd1306_128x32_adafruit2_init_seq[] PROGMEM = {
iforce2d 0:972874f31c98 84 U8G_ESC_CS(0), /* disable chip */
iforce2d 0:972874f31c98 85 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 86 U8G_ESC_RST(1), /* do reset low pulse with (1*16)+2 milliseconds */
iforce2d 0:972874f31c98 87 U8G_ESC_CS(1), /* enable chip */
iforce2d 0:972874f31c98 88
iforce2d 0:972874f31c98 89 0x0ae, /* display off, sleep mode */
iforce2d 0:972874f31c98 90 0x0d5, 0x080, /* clock divide ratio (0x00=1) and oscillator frequency (0x8) */
iforce2d 0:972874f31c98 91 0x0a8, 0x03f, /* */
iforce2d 0:972874f31c98 92
iforce2d 0:972874f31c98 93 0x0d3, 0x000, /* */
iforce2d 0:972874f31c98 94
iforce2d 0:972874f31c98 95 0x040, /* start line */
iforce2d 0:972874f31c98 96
iforce2d 0:972874f31c98 97 0x08d, 0x014, /* [2] charge pump setting (p62): 0x014 enable, 0x010 disable */
iforce2d 0:972874f31c98 98
iforce2d 0:972874f31c98 99 0x020, 0x000, /* */
iforce2d 0:972874f31c98 100 0x0a1, /* segment remap a0/a1*/
iforce2d 0:972874f31c98 101 0x0c8, /* c0: scan dir normal, c8: reverse */
iforce2d 0:972874f31c98 102 0x0da, 0x012, /* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5) */
iforce2d 0:972874f31c98 103 0x081, 0x0cf, /* [2] set contrast control */
iforce2d 0:972874f31c98 104 0x0d9, 0x0f1, /* [2] pre-charge period 0x022/f1*/
iforce2d 0:972874f31c98 105 0x0db, 0x040, /* vcomh deselect level */
iforce2d 0:972874f31c98 106
iforce2d 0:972874f31c98 107 0x02e, /* 2012-05-27: Deactivate scroll */
iforce2d 0:972874f31c98 108 0x0a4, /* output ram to display */
iforce2d 0:972874f31c98 109 0x0a6, /* none inverted normal display mode */
iforce2d 0:972874f31c98 110 0x0af, /* display on */
iforce2d 0:972874f31c98 111
iforce2d 0:972874f31c98 112 U8G_ESC_CS(0), /* disable chip */
iforce2d 0:972874f31c98 113 U8G_ESC_END /* end of sequence */
iforce2d 0:972874f31c98 114 };
iforce2d 0:972874f31c98 115
iforce2d 0:972874f31c98 116
iforce2d 0:972874f31c98 117 /* init sequence adafruit 128x32 OLED (TESTED - WORKING 23.02.13), like adafruit3, but with page addressing mode */
iforce2d 0:972874f31c98 118 static const uint8_t u8g_dev_ssd1306_128x32_adafruit3_init_seq[] PROGMEM = {
iforce2d 0:972874f31c98 119 U8G_ESC_CS(0), /* disable chip */
iforce2d 0:972874f31c98 120 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 121 U8G_ESC_RST(1), /* do reset low pulse with (1*16)+2 milliseconds */
iforce2d 0:972874f31c98 122 U8G_ESC_CS(1), /* enable chip */
iforce2d 0:972874f31c98 123
iforce2d 0:972874f31c98 124 0x0ae, /* display off, sleep mode */
iforce2d 0:972874f31c98 125 0x0d5, 0x080, /* clock divide ratio (0x00=1) and oscillator frequency (0x8) */
iforce2d 0:972874f31c98 126 0x0a8, 0x01f, /* Feb 23, 2013: 128x32 OLED: 0x01f, 128x32 OLED 0x03f */
iforce2d 0:972874f31c98 127
iforce2d 0:972874f31c98 128 0x0d3, 0x000, /* */
iforce2d 0:972874f31c98 129
iforce2d 0:972874f31c98 130 0x040, /* start line */
iforce2d 0:972874f31c98 131
iforce2d 0:972874f31c98 132 0x08d, 0x014, /* [2] charge pump setting (p62): 0x014 enable, 0x010 disable */
iforce2d 0:972874f31c98 133
iforce2d 0:972874f31c98 134 0x020, 0x002, /* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5), Feb 23, 2013: 128x32 OLED: 0x002, 128x32 OLED 0x012 */
iforce2d 0:972874f31c98 135 0x0a1, /* segment remap a0/a1*/
iforce2d 0:972874f31c98 136 0x0c8, /* c0: scan dir normal, c8: reverse */
iforce2d 0:972874f31c98 137 0x0da, 0x002, /* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5) */
iforce2d 0:972874f31c98 138 0x081, 0x0cf, /* [2] set contrast control */
iforce2d 0:972874f31c98 139 0x0d9, 0x0f1, /* [2] pre-charge period 0x022/f1*/
iforce2d 0:972874f31c98 140 0x0db, 0x040, /* vcomh deselect level */
iforce2d 0:972874f31c98 141
iforce2d 0:972874f31c98 142 0x02e, /* 2012-05-27: Deactivate scroll */
iforce2d 0:972874f31c98 143 0x0a4, /* output ram to display */
iforce2d 0:972874f31c98 144 0x0a6, /* none inverted normal display mode */
iforce2d 0:972874f31c98 145 0x0af, /* display on */
iforce2d 0:972874f31c98 146
iforce2d 0:972874f31c98 147 U8G_ESC_CS(0), /* disable chip */
iforce2d 0:972874f31c98 148 U8G_ESC_END /* end of sequence */
iforce2d 0:972874f31c98 149 };
iforce2d 0:972874f31c98 150
iforce2d 0:972874f31c98 151
iforce2d 0:972874f31c98 152 /* init sequence Univision datasheet (NOT TESTED) */
iforce2d 0:972874f31c98 153 static const uint8_t u8g_dev_ssd1306_128x32_univision_init_seq[] PROGMEM = {
iforce2d 0:972874f31c98 154 U8G_ESC_CS(0), /* disable chip */
iforce2d 0:972874f31c98 155 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 156 U8G_ESC_RST(1), /* do reset low pulse with (1*16)+2 milliseconds */
iforce2d 0:972874f31c98 157 U8G_ESC_CS(1), /* enable chip */
iforce2d 0:972874f31c98 158
iforce2d 0:972874f31c98 159 0x0ae, /* display off, sleep mode */
iforce2d 0:972874f31c98 160 0x0d5, 0x080, /* clock divide ratio (0x00=1) and oscillator frequency (0x8) */
iforce2d 0:972874f31c98 161 0x0a8, 0x03f, /* multiplex ratio */
iforce2d 0:972874f31c98 162 0x0d3, 0x000, /* display offset */
iforce2d 0:972874f31c98 163 0x040, /* start line */
iforce2d 0:972874f31c98 164 0x08d, 0x010, /* charge pump setting (p62): 0x014 enable, 0x010 disable */
iforce2d 0:972874f31c98 165 0x0a1, /* segment remap a0/a1*/
iforce2d 0:972874f31c98 166 0x0c8, /* c0: scan dir normal, c8: reverse */
iforce2d 0:972874f31c98 167 0x0da, 0x012, /* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5) */
iforce2d 0:972874f31c98 168 0x081, 0x09f, /* set contrast control */
iforce2d 0:972874f31c98 169 0x0d9, 0x022, /* pre-charge period */
iforce2d 0:972874f31c98 170 0x0db, 0x040, /* vcomh deselect level */
iforce2d 0:972874f31c98 171 0x022, 0x000, /* page addressing mode WRONG: 3 byte cmd! */
iforce2d 0:972874f31c98 172 0x0a4, /* output ram to display */
iforce2d 0:972874f31c98 173 0x0a6, /* none inverted normal display mode */
iforce2d 0:972874f31c98 174 0x0af, /* display on */
iforce2d 0:972874f31c98 175 U8G_ESC_CS(0), /* disable chip */
iforce2d 0:972874f31c98 176 U8G_ESC_END /* end of sequence */
iforce2d 0:972874f31c98 177 };
iforce2d 0:972874f31c98 178
iforce2d 0:972874f31c98 179
iforce2d 0:972874f31c98 180 /* select one init sequence here */
iforce2d 0:972874f31c98 181 //define u8g_dev_ssd1306_128x32_init_seq u8g_dev_ssd1306_128x32_univision_init_seq
iforce2d 0:972874f31c98 182 //define u8g_dev_ssd1306_128x32_init_seq u8g_dev_ssd1306_128x32_adafruit1_init_seq
iforce2d 0:972874f31c98 183 //define u8g_dev_ssd1306_128x32_init_seq u8g_dev_ssd1306_128x32_adafruit2_init_seq
iforce2d 0:972874f31c98 184 #define u8g_dev_ssd1306_128x32_init_seq u8g_dev_ssd1306_128x32_adafruit3_init_seq
iforce2d 0:972874f31c98 185
iforce2d 0:972874f31c98 186
iforce2d 0:972874f31c98 187 static const uint8_t u8g_dev_ssd1306_128x32_data_start[] PROGMEM = {
iforce2d 0:972874f31c98 188 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 189 U8G_ESC_CS(1), /* enable chip */
iforce2d 0:972874f31c98 190 0x010, /* set upper 4 bit of the col adr. to 0 */
iforce2d 0:972874f31c98 191 0x000, /* set lower 4 bit of the col adr. to 4 */
iforce2d 0:972874f31c98 192 U8G_ESC_END /* end of sequence */
iforce2d 0:972874f31c98 193 };
iforce2d 0:972874f31c98 194
iforce2d 0:972874f31c98 195 static const uint8_t u8g_dev_ssd13xx_sleep_on[] PROGMEM = {
iforce2d 0:972874f31c98 196 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 197 U8G_ESC_CS(1), /* enable chip */
iforce2d 0:972874f31c98 198 0x0ae, /* display off */
iforce2d 0:972874f31c98 199 U8G_ESC_CS(1), /* disable chip */
iforce2d 0:972874f31c98 200 U8G_ESC_END /* end of sequence */
iforce2d 0:972874f31c98 201 };
iforce2d 0:972874f31c98 202
iforce2d 0:972874f31c98 203 static const uint8_t u8g_dev_ssd13xx_sleep_off[] PROGMEM = {
iforce2d 0:972874f31c98 204 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 205 U8G_ESC_CS(1), /* enable chip */
iforce2d 0:972874f31c98 206 0x0af, /* display on */
iforce2d 0:972874f31c98 207 U8G_ESC_DLY(50), /* delay 50 ms */
iforce2d 0:972874f31c98 208 U8G_ESC_CS(1), /* disable chip */
iforce2d 0:972874f31c98 209 U8G_ESC_END /* end of sequence */
iforce2d 0:972874f31c98 210 };
iforce2d 0:972874f31c98 211
iforce2d 0:972874f31c98 212 uint8_t u8g_dev_ssd1306_128x32_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
iforce2d 0:972874f31c98 213 {
iforce2d 0:972874f31c98 214 switch(msg)
iforce2d 0:972874f31c98 215 {
iforce2d 0:972874f31c98 216 case U8G_DEV_MSG_INIT:
iforce2d 0:972874f31c98 217 u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
iforce2d 0:972874f31c98 218 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1306_128x32_init_seq);
iforce2d 0:972874f31c98 219 break;
iforce2d 0:972874f31c98 220 case U8G_DEV_MSG_STOP:
iforce2d 0:972874f31c98 221 break;
iforce2d 0:972874f31c98 222 case U8G_DEV_MSG_PAGE_NEXT:
iforce2d 0:972874f31c98 223 {
iforce2d 0:972874f31c98 224 u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
iforce2d 0:972874f31c98 225 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1306_128x32_data_start);
iforce2d 0:972874f31c98 226 u8g_WriteByte(u8g, dev, 0x0b0 | pb->p.page); /* select current page (SSD1306) */
iforce2d 0:972874f31c98 227 u8g_SetAddress(u8g, dev, 1); /* data mode */
iforce2d 0:972874f31c98 228 if ( u8g_pb_WriteBuffer(pb, u8g, dev) == 0 )
iforce2d 0:972874f31c98 229 return 0;
iforce2d 0:972874f31c98 230 u8g_SetChipSelect(u8g, dev, 0);
iforce2d 0:972874f31c98 231 }
iforce2d 0:972874f31c98 232 break;
iforce2d 0:972874f31c98 233 case U8G_DEV_MSG_SLEEP_ON:
iforce2d 0:972874f31c98 234 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_on);
iforce2d 0:972874f31c98 235 return 1;
iforce2d 0:972874f31c98 236 case U8G_DEV_MSG_SLEEP_OFF:
iforce2d 0:972874f31c98 237 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_off);
iforce2d 0:972874f31c98 238 return 1;
iforce2d 0:972874f31c98 239 }
iforce2d 0:972874f31c98 240
iforce2d 0:972874f31c98 241 return u8g_dev_pb8v1_base_fn(u8g, dev, msg, arg);
iforce2d 0:972874f31c98 242 }
iforce2d 0:972874f31c98 243
iforce2d 0:972874f31c98 244 uint8_t u8g_dev_ssd1306_128x32_2x_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
iforce2d 0:972874f31c98 245 {
iforce2d 0:972874f31c98 246 switch(msg)
iforce2d 0:972874f31c98 247 {
iforce2d 0:972874f31c98 248 case U8G_DEV_MSG_INIT:
iforce2d 0:972874f31c98 249 u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
iforce2d 0:972874f31c98 250 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1306_128x32_init_seq);
iforce2d 0:972874f31c98 251 break;
iforce2d 0:972874f31c98 252 case U8G_DEV_MSG_STOP:
iforce2d 0:972874f31c98 253 break;
iforce2d 0:972874f31c98 254 case U8G_DEV_MSG_PAGE_NEXT:
iforce2d 0:972874f31c98 255 {
iforce2d 0:972874f31c98 256 u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
iforce2d 0:972874f31c98 257
iforce2d 0:972874f31c98 258 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1306_128x32_data_start);
iforce2d 0:972874f31c98 259 u8g_WriteByte(u8g, dev, 0x0b0 | (pb->p.page*2)); /* select current page (SSD1306) */
iforce2d 0:972874f31c98 260 u8g_SetAddress(u8g, dev, 1); /* data mode */
iforce2d 0:972874f31c98 261 u8g_WriteSequence(u8g, dev, pb->width, pb->buf);
iforce2d 0:972874f31c98 262 u8g_SetChipSelect(u8g, dev, 0);
iforce2d 0:972874f31c98 263
iforce2d 0:972874f31c98 264 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1306_128x32_data_start);
iforce2d 0:972874f31c98 265 u8g_WriteByte(u8g, dev, 0x0b0 | (pb->p.page*2+1)); /* select current page (SSD1306) */
iforce2d 0:972874f31c98 266 u8g_SetAddress(u8g, dev, 1); /* data mode */
iforce2d 0:972874f31c98 267 u8g_WriteSequence(u8g, dev, pb->width, (uint8_t *)(pb->buf)+pb->width);
iforce2d 0:972874f31c98 268 u8g_SetChipSelect(u8g, dev, 0);
iforce2d 0:972874f31c98 269 }
iforce2d 0:972874f31c98 270 break;
iforce2d 0:972874f31c98 271 case U8G_DEV_MSG_SLEEP_ON:
iforce2d 0:972874f31c98 272 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_on);
iforce2d 0:972874f31c98 273 return 1;
iforce2d 0:972874f31c98 274 case U8G_DEV_MSG_SLEEP_OFF:
iforce2d 0:972874f31c98 275 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_off);
iforce2d 0:972874f31c98 276 return 1;
iforce2d 0:972874f31c98 277 }
iforce2d 0:972874f31c98 278 return u8g_dev_pb16v1_base_fn(u8g, dev, msg, arg);
iforce2d 0:972874f31c98 279 }
iforce2d 0:972874f31c98 280
iforce2d 0:972874f31c98 281 U8G_PB_DEV(u8g_dev_ssd1306_128x32_sw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_ssd1306_128x32_fn, U8G_COM_SW_SPI);
iforce2d 0:972874f31c98 282 U8G_PB_DEV(u8g_dev_ssd1306_128x32_hw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_ssd1306_128x32_fn, U8G_COM_HW_SPI);
iforce2d 0:972874f31c98 283 U8G_PB_DEV(u8g_dev_ssd1306_128x32_i2c, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_ssd1306_128x32_fn, U8G_COM_SSD_I2C);
iforce2d 0:972874f31c98 284
iforce2d 0:972874f31c98 285 uint8_t u8g_dev_ssd1306_128x32_2x_buf[WIDTH*2] U8G_NOCOMMON ;
iforce2d 0:972874f31c98 286 u8g_pb_t u8g_dev_ssd1306_128x32_2x_pb = { {16, HEIGHT, 0, 0, 0}, WIDTH, u8g_dev_ssd1306_128x32_2x_buf};
iforce2d 0:972874f31c98 287 u8g_dev_t u8g_dev_ssd1306_128x32_2x_sw_spi = { u8g_dev_ssd1306_128x32_2x_fn, &u8g_dev_ssd1306_128x32_2x_pb, U8G_COM_SW_SPI };
iforce2d 0:972874f31c98 288 u8g_dev_t u8g_dev_ssd1306_128x32_2x_hw_spi = { u8g_dev_ssd1306_128x32_2x_fn, &u8g_dev_ssd1306_128x32_2x_pb, U8G_COM_HW_SPI };
iforce2d 0:972874f31c98 289 u8g_dev_t u8g_dev_ssd1306_128x32_2x_i2c = { u8g_dev_ssd1306_128x32_2x_fn, &u8g_dev_ssd1306_128x32_2x_pb, U8G_COM_SSD_I2C };
iforce2d 0:972874f31c98 290