Displays distance to start location on OLED screen.

Dependencies:   mbed

Committer:
iforce2d
Date:
Wed Mar 07 12:49:14 2018 +0000
Revision:
0:972874f31c98
First commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
iforce2d 0:972874f31c98 1 /*
iforce2d 0:972874f31c98 2
iforce2d 0:972874f31c98 3 u8g_dev_ks0108_128x64.c
iforce2d 0:972874f31c98 4
iforce2d 0:972874f31c98 5 Universal 8bit Graphics Library
iforce2d 0:972874f31c98 6
iforce2d 0:972874f31c98 7 Copyright (c) 2011, olikraus@gmail.com
iforce2d 0:972874f31c98 8 All rights reserved.
iforce2d 0:972874f31c98 9
iforce2d 0:972874f31c98 10 Redistribution and use in source and binary forms, with or without modification,
iforce2d 0:972874f31c98 11 are permitted provided that the following conditions are met:
iforce2d 0:972874f31c98 12
iforce2d 0:972874f31c98 13 * Redistributions of source code must retain the above copyright notice, this list
iforce2d 0:972874f31c98 14 of conditions and the following disclaimer.
iforce2d 0:972874f31c98 15
iforce2d 0:972874f31c98 16 * Redistributions in binary form must reproduce the above copyright notice, this
iforce2d 0:972874f31c98 17 list of conditions and the following disclaimer in the documentation and/or other
iforce2d 0:972874f31c98 18 materials provided with the distribution.
iforce2d 0:972874f31c98 19
iforce2d 0:972874f31c98 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
iforce2d 0:972874f31c98 21 CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
iforce2d 0:972874f31c98 22 INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
iforce2d 0:972874f31c98 23 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
iforce2d 0:972874f31c98 24 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
iforce2d 0:972874f31c98 25 CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
iforce2d 0:972874f31c98 26 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
iforce2d 0:972874f31c98 27 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
iforce2d 0:972874f31c98 28 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
iforce2d 0:972874f31c98 29 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
iforce2d 0:972874f31c98 30 STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
iforce2d 0:972874f31c98 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
iforce2d 0:972874f31c98 32 ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
iforce2d 0:972874f31c98 33
iforce2d 0:972874f31c98 34
iforce2d 0:972874f31c98 35 ADDRESS = 0 (Command Mode)
iforce2d 0:972874f31c98 36 0x03f Display On
iforce2d 0:972874f31c98 37 0x0c0 Start Display at line 0
iforce2d 0:972874f31c98 38 0x040 | y write to y address (y:0..63)
iforce2d 0:972874f31c98 39 0x0b8 | x write to page [0..7]
iforce2d 0:972874f31c98 40
iforce2d 0:972874f31c98 41
iforce2d 0:972874f31c98 42 u8g_Init8Bit(u8g, dev, d0, d1, d2, d3, d4, d5, d6, d7, en, cs1, cs2, di, rw, reset)
iforce2d 0:972874f31c98 43 u8g_Init8Bit(u8g, dev, 8, 9, 10, 11, 4, 5, 6, 7, 18, 14, 15, 17, 16, U8G_PIN_NONE)
iforce2d 0:972874f31c98 44
iforce2d 0:972874f31c98 45 */
iforce2d 0:972874f31c98 46
iforce2d 0:972874f31c98 47 #include "u8g.h"
iforce2d 0:972874f31c98 48
iforce2d 0:972874f31c98 49 #define WIDTH 128
iforce2d 0:972874f31c98 50 #define HEIGHT 64
iforce2d 0:972874f31c98 51 #define PAGE_HEIGHT 8
iforce2d 0:972874f31c98 52
iforce2d 0:972874f31c98 53 static const uint8_t u8g_dev_ks0108_128x64_init_seq[] PROGMEM = {
iforce2d 0:972874f31c98 54 U8G_ESC_CS(0), /* disable chip */
iforce2d 0:972874f31c98 55 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 56 U8G_ESC_RST(1), /* do reset low pulse with (1*16)+2 milliseconds */
iforce2d 0:972874f31c98 57 U8G_ESC_CS(1), /* enable chip 1 */
iforce2d 0:972874f31c98 58 0x03f, /* display on */
iforce2d 0:972874f31c98 59 0x0c0, /* start at line 0 */
iforce2d 0:972874f31c98 60 U8G_ESC_DLY(20), /* delay 20 ms */
iforce2d 0:972874f31c98 61 U8G_ESC_CS(2), /* enable chip 2 */
iforce2d 0:972874f31c98 62 0x03f, /* display on */
iforce2d 0:972874f31c98 63 0x0c0, /* start at line 0 */
iforce2d 0:972874f31c98 64 U8G_ESC_DLY(20), /* delay 20 ms */
iforce2d 0:972874f31c98 65 U8G_ESC_CS(0), /* disable all chips */
iforce2d 0:972874f31c98 66 U8G_ESC_END /* end of sequence */
iforce2d 0:972874f31c98 67 };
iforce2d 0:972874f31c98 68
iforce2d 0:972874f31c98 69
iforce2d 0:972874f31c98 70 uint8_t u8g_dev_ks0108_128x64_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
iforce2d 0:972874f31c98 71 {
iforce2d 0:972874f31c98 72
iforce2d 0:972874f31c98 73 switch(msg)
iforce2d 0:972874f31c98 74 {
iforce2d 0:972874f31c98 75 case U8G_DEV_MSG_INIT:
iforce2d 0:972874f31c98 76 u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_NONE);
iforce2d 0:972874f31c98 77 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ks0108_128x64_init_seq);
iforce2d 0:972874f31c98 78 break;
iforce2d 0:972874f31c98 79 case U8G_DEV_MSG_STOP:
iforce2d 0:972874f31c98 80 break;
iforce2d 0:972874f31c98 81 case U8G_DEV_MSG_PAGE_NEXT:
iforce2d 0:972874f31c98 82 {
iforce2d 0:972874f31c98 83 u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
iforce2d 0:972874f31c98 84
iforce2d 0:972874f31c98 85 u8g_SetAddress(u8g, dev, 0); /* command mode */
iforce2d 0:972874f31c98 86 u8g_SetChipSelect(u8g, dev, 2);
iforce2d 0:972874f31c98 87 u8g_WriteByte(u8g, dev, 0x0b8 | pb->p.page); /* select current page (KS0108b) */
iforce2d 0:972874f31c98 88 u8g_WriteByte(u8g, dev, 0x040 ); /* set address 0 */
iforce2d 0:972874f31c98 89 u8g_SetAddress(u8g, dev, 1); /* data mode */
iforce2d 0:972874f31c98 90 u8g_WriteSequence(u8g, dev, 64, pb->buf);
iforce2d 0:972874f31c98 91 u8g_SetChipSelect(u8g, dev, 0);
iforce2d 0:972874f31c98 92
iforce2d 0:972874f31c98 93 u8g_SetAddress(u8g, dev, 0); /* command mode */
iforce2d 0:972874f31c98 94 u8g_SetChipSelect(u8g, dev, 1);
iforce2d 0:972874f31c98 95 u8g_WriteByte(u8g, dev, 0x0b8 | pb->p.page); /* select current page (KS0108b) */
iforce2d 0:972874f31c98 96 u8g_WriteByte(u8g, dev, 0x040 ); /* set address 0 */
iforce2d 0:972874f31c98 97 u8g_SetAddress(u8g, dev, 1); /* data mode */
iforce2d 0:972874f31c98 98 u8g_WriteSequence(u8g, dev, 64, 64+(uint8_t *)pb->buf);
iforce2d 0:972874f31c98 99 u8g_SetChipSelect(u8g, dev, 0);
iforce2d 0:972874f31c98 100
iforce2d 0:972874f31c98 101 }
iforce2d 0:972874f31c98 102 break;
iforce2d 0:972874f31c98 103 }
iforce2d 0:972874f31c98 104 return u8g_dev_pb8v1_base_fn(u8g, dev, msg, arg);
iforce2d 0:972874f31c98 105 }
iforce2d 0:972874f31c98 106
iforce2d 0:972874f31c98 107 U8G_PB_DEV(u8g_dev_ks0108_128x64, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_ks0108_128x64_fn, U8G_COM_PARALLEL);
iforce2d 0:972874f31c98 108 U8G_PB_DEV(u8g_dev_ks0108_128x64_fast, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_ks0108_128x64_fn, U8G_COM_FAST_PARALLEL);
iforce2d 0:972874f31c98 109
iforce2d 0:972874f31c98 110
iforce2d 0:972874f31c98 111