iforce2d Chris / Mbed 2 deprecated ubxDistanceMeter

Displays distance to start location on OLED screen.

Dependencies:   mbed

u8g_com_atmega_parallel.c@0:972874f31c98, 2018-03-07 (annotated)

Committer:
iforce2d
Date:
Wed Mar 07 12:49:14 2018 +0000
Revision:
0:972874f31c98
First commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
iforce2d 0:972874f31c98 1 /*
iforce2d 0:972874f31c98 2
iforce2d 0:972874f31c98 3 u8g_com_atmega_parallel.c
iforce2d 0:972874f31c98 4
iforce2d 0:972874f31c98 5 Universal 8bit Graphics Library
iforce2d 0:972874f31c98 6
iforce2d 0:972874f31c98 7 Copyright (c) 2012, olikraus@gmail.com
iforce2d 0:972874f31c98 8 All rights reserved.
iforce2d 0:972874f31c98 9
iforce2d 0:972874f31c98 10 Redistribution and use in source and binary forms, with or without modification,
iforce2d 0:972874f31c98 11 are permitted provided that the following conditions are met:
iforce2d 0:972874f31c98 12
iforce2d 0:972874f31c98 13 * Redistributions of source code must retain the above copyright notice, this list
iforce2d 0:972874f31c98 14 of conditions and the following disclaimer.
iforce2d 0:972874f31c98 15
iforce2d 0:972874f31c98 16 * Redistributions in binary form must reproduce the above copyright notice, this
iforce2d 0:972874f31c98 17 list of conditions and the following disclaimer in the documentation and/or other
iforce2d 0:972874f31c98 18 materials provided with the distribution.
iforce2d 0:972874f31c98 19
iforce2d 0:972874f31c98 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
iforce2d 0:972874f31c98 21 CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
iforce2d 0:972874f31c98 22 INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
iforce2d 0:972874f31c98 23 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
iforce2d 0:972874f31c98 24 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
iforce2d 0:972874f31c98 25 CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
iforce2d 0:972874f31c98 26 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
iforce2d 0:972874f31c98 27 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
iforce2d 0:972874f31c98 28 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
iforce2d 0:972874f31c98 29 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
iforce2d 0:972874f31c98 30 STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
iforce2d 0:972874f31c98 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
iforce2d 0:972874f31c98 32 ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
iforce2d 0:972874f31c98 33
iforce2d 0:972874f31c98 34
iforce2d 0:972874f31c98 35 PIN_D0 8
iforce2d 0:972874f31c98 36 PIN_D1 9
iforce2d 0:972874f31c98 37 PIN_D2 10
iforce2d 0:972874f31c98 38 PIN_D3 11
iforce2d 0:972874f31c98 39 PIN_D4 4
iforce2d 0:972874f31c98 40 PIN_D5 5
iforce2d 0:972874f31c98 41 PIN_D6 6
iforce2d 0:972874f31c98 42 PIN_D7 7
iforce2d 0:972874f31c98 43
iforce2d 0:972874f31c98 44 PIN_CS1 14
iforce2d 0:972874f31c98 45 PIN_CS2 15
iforce2d 0:972874f31c98 46 PIN_RW 16
iforce2d 0:972874f31c98 47 PIN_DI 17
iforce2d 0:972874f31c98 48 PIN_EN 18
iforce2d 0:972874f31c98 49
iforce2d 0:972874f31c98 50 u8g_Init8Bit(u8g, dev, d0, d1, d2, d3, d4, d5, d6, d7, en, cs1, cs2, di, rw, reset)
iforce2d 0:972874f31c98 51 u8g_Init8Bit(u8g, dev, 8, 9, 10, 11, 4, 5, 6, 7, 18, 14, 15, 17, 16, U8G_PIN_NONE)
iforce2d 0:972874f31c98 52
iforce2d 0:972874f31c98 53 */
iforce2d 0:972874f31c98 54
iforce2d 0:972874f31c98 55 #include "u8g.h"
iforce2d 0:972874f31c98 56
iforce2d 0:972874f31c98 57 #if defined(__AVR__)
iforce2d 0:972874f31c98 58
iforce2d 0:972874f31c98 59 static void u8g_com_atmega_parallel_write(u8g_t *u8g, uint8_t val) U8G_NOINLINE;
iforce2d 0:972874f31c98 60 static void u8g_com_atmega_parallel_write(u8g_t *u8g, uint8_t val)
iforce2d 0:972874f31c98 61 {
iforce2d 0:972874f31c98 62
iforce2d 0:972874f31c98 63 u8g_SetPILevel(u8g, U8G_PI_D0, val&1);
iforce2d 0:972874f31c98 64 val >>= 1;
iforce2d 0:972874f31c98 65 u8g_SetPILevel(u8g, U8G_PI_D1, val&1);
iforce2d 0:972874f31c98 66 val >>= 1;
iforce2d 0:972874f31c98 67 u8g_SetPILevel(u8g, U8G_PI_D2, val&1);
iforce2d 0:972874f31c98 68 val >>= 1;
iforce2d 0:972874f31c98 69 u8g_SetPILevel(u8g, U8G_PI_D3, val&1);
iforce2d 0:972874f31c98 70 val >>= 1;
iforce2d 0:972874f31c98 71 u8g_SetPILevel(u8g, U8G_PI_D4, val&1);
iforce2d 0:972874f31c98 72 val >>= 1;
iforce2d 0:972874f31c98 73 u8g_SetPILevel(u8g, U8G_PI_D5, val&1);
iforce2d 0:972874f31c98 74 val >>= 1;
iforce2d 0:972874f31c98 75 u8g_SetPILevel(u8g, U8G_PI_D6, val&1);
iforce2d 0:972874f31c98 76 val >>= 1;
iforce2d 0:972874f31c98 77 u8g_SetPILevel(u8g, U8G_PI_D7, val&1);
iforce2d 0:972874f31c98 78
iforce2d 0:972874f31c98 79 /* EN cycle time must be 1 micro second */
iforce2d 0:972874f31c98 80 u8g_SetPILevel(u8g, U8G_PI_EN, 1);
iforce2d 0:972874f31c98 81 u8g_MicroDelay(); /* delay by 1000ns, reference: ST7920: 140ns, SBN1661: 100ns */
iforce2d 0:972874f31c98 82 u8g_SetPILevel(u8g, U8G_PI_EN, 0);
iforce2d 0:972874f31c98 83 u8g_10MicroDelay(); /* ST7920 commands: 72us */
iforce2d 0:972874f31c98 84 u8g_10MicroDelay(); /* ST7920 commands: 72us */
iforce2d 0:972874f31c98 85 }
iforce2d 0:972874f31c98 86
iforce2d 0:972874f31c98 87
iforce2d 0:972874f31c98 88 uint8_t u8g_com_atmega_parallel_fn(u8g_t *u8g, uint8_t msg, uint8_t arg_val, void *arg_ptr)
iforce2d 0:972874f31c98 89 {
iforce2d 0:972874f31c98 90 switch(msg)
iforce2d 0:972874f31c98 91 {
iforce2d 0:972874f31c98 92 case U8G_COM_MSG_INIT:
iforce2d 0:972874f31c98 93 /* setup the RW pin as output and force it to low */
iforce2d 0:972874f31c98 94 u8g_SetPIOutput(u8g, U8G_PI_RW);
iforce2d 0:972874f31c98 95 u8g_SetPILevel(u8g, U8G_PI_RW, 0);
iforce2d 0:972874f31c98 96
iforce2d 0:972874f31c98 97 u8g_SetPIOutput(u8g, U8G_PI_D0);
iforce2d 0:972874f31c98 98 u8g_SetPIOutput(u8g, U8G_PI_D1);
iforce2d 0:972874f31c98 99 u8g_SetPIOutput(u8g, U8G_PI_D2);
iforce2d 0:972874f31c98 100 u8g_SetPIOutput(u8g, U8G_PI_D3);
iforce2d 0:972874f31c98 101 u8g_SetPIOutput(u8g, U8G_PI_D4);
iforce2d 0:972874f31c98 102 u8g_SetPIOutput(u8g, U8G_PI_D5);
iforce2d 0:972874f31c98 103 u8g_SetPIOutput(u8g, U8G_PI_D6);
iforce2d 0:972874f31c98 104 u8g_SetPIOutput(u8g, U8G_PI_D7);
iforce2d 0:972874f31c98 105 u8g_SetPIOutput(u8g, U8G_PI_EN);
iforce2d 0:972874f31c98 106 u8g_SetPIOutput(u8g, U8G_PI_CS1);
iforce2d 0:972874f31c98 107 u8g_SetPIOutput(u8g, U8G_PI_CS2);
iforce2d 0:972874f31c98 108 u8g_SetPIOutput(u8g, U8G_PI_DI);
iforce2d 0:972874f31c98 109 u8g_SetPILevel(u8g, U8G_PI_CS1, 1);
iforce2d 0:972874f31c98 110 u8g_SetPILevel(u8g, U8G_PI_CS2, 1);
iforce2d 0:972874f31c98 111
iforce2d 0:972874f31c98 112 break;
iforce2d 0:972874f31c98 113 case U8G_COM_MSG_STOP:
iforce2d 0:972874f31c98 114 break;
iforce2d 0:972874f31c98 115 case U8G_COM_MSG_CHIP_SELECT:
iforce2d 0:972874f31c98 116 if ( arg_val == 0 )
iforce2d 0:972874f31c98 117 {
iforce2d 0:972874f31c98 118 /* disable */
iforce2d 0:972874f31c98 119 u8g_SetPILevel(u8g, U8G_PI_CS1, 1);
iforce2d 0:972874f31c98 120 u8g_SetPILevel(u8g, U8G_PI_CS2, 1);
iforce2d 0:972874f31c98 121 }
iforce2d 0:972874f31c98 122 else if ( arg_val == 1 )
iforce2d 0:972874f31c98 123 {
iforce2d 0:972874f31c98 124 /* enable */
iforce2d 0:972874f31c98 125 u8g_SetPILevel(u8g, U8G_PI_CS1, 0);
iforce2d 0:972874f31c98 126 u8g_SetPILevel(u8g, U8G_PI_CS2, 1);
iforce2d 0:972874f31c98 127 }
iforce2d 0:972874f31c98 128 else if ( arg_val == 2 )
iforce2d 0:972874f31c98 129 {
iforce2d 0:972874f31c98 130 /* enable */
iforce2d 0:972874f31c98 131 u8g_SetPILevel(u8g, U8G_PI_CS1, 1);
iforce2d 0:972874f31c98 132 u8g_SetPILevel(u8g, U8G_PI_CS2, 0);
iforce2d 0:972874f31c98 133 }
iforce2d 0:972874f31c98 134 else
iforce2d 0:972874f31c98 135 {
iforce2d 0:972874f31c98 136 /* enable */
iforce2d 0:972874f31c98 137 u8g_SetPILevel(u8g, U8G_PI_CS1, 0);
iforce2d 0:972874f31c98 138 u8g_SetPILevel(u8g, U8G_PI_CS2, 0);
iforce2d 0:972874f31c98 139 }
iforce2d 0:972874f31c98 140 break;
iforce2d 0:972874f31c98 141 case U8G_COM_MSG_WRITE_BYTE:
iforce2d 0:972874f31c98 142 u8g_com_atmega_parallel_write(u8g, arg_val);
iforce2d 0:972874f31c98 143 break;
iforce2d 0:972874f31c98 144 case U8G_COM_MSG_WRITE_SEQ:
iforce2d 0:972874f31c98 145 {
iforce2d 0:972874f31c98 146 register uint8_t *ptr = arg_ptr;
iforce2d 0:972874f31c98 147 while( arg_val > 0 )
iforce2d 0:972874f31c98 148 {
iforce2d 0:972874f31c98 149 u8g_com_atmega_parallel_write(u8g, *ptr++);
iforce2d 0:972874f31c98 150 arg_val--;
iforce2d 0:972874f31c98 151 }
iforce2d 0:972874f31c98 152 }
iforce2d 0:972874f31c98 153 break;
iforce2d 0:972874f31c98 154 case U8G_COM_MSG_WRITE_SEQ_P:
iforce2d 0:972874f31c98 155 {
iforce2d 0:972874f31c98 156 register uint8_t *ptr = arg_ptr;
iforce2d 0:972874f31c98 157 while( arg_val > 0 )
iforce2d 0:972874f31c98 158 {
iforce2d 0:972874f31c98 159 u8g_com_atmega_parallel_write(u8g, u8g_pgm_read(ptr));
iforce2d 0:972874f31c98 160 ptr++;
iforce2d 0:972874f31c98 161 arg_val--;
iforce2d 0:972874f31c98 162 }
iforce2d 0:972874f31c98 163 }
iforce2d 0:972874f31c98 164 break;
iforce2d 0:972874f31c98 165 case U8G_COM_MSG_ADDRESS: /* define cmd (arg_val = 0) or data mode (arg_val = 1) */
iforce2d 0:972874f31c98 166 u8g_SetPILevel(u8g, U8G_PI_DI, arg_val);
iforce2d 0:972874f31c98 167 break;
iforce2d 0:972874f31c98 168 case U8G_COM_MSG_RESET:
iforce2d 0:972874f31c98 169 u8g_SetPILevel(u8g, U8G_PI_RESET, arg_val);
iforce2d 0:972874f31c98 170 break;
iforce2d 0:972874f31c98 171 }
iforce2d 0:972874f31c98 172 return 1;
iforce2d 0:972874f31c98 173 }
iforce2d 0:972874f31c98 174
iforce2d 0:972874f31c98 175 #else
iforce2d 0:972874f31c98 176
iforce2d 0:972874f31c98 177 uint8_t u8g_com_atmega_parallel_fn(u8g_t *u8g, uint8_t msg, uint8_t arg_val, void *arg_ptr)
iforce2d 0:972874f31c98 178 {
iforce2d 0:972874f31c98 179 return 1;
iforce2d 0:972874f31c98 180 }
iforce2d 0:972874f31c98 181
iforce2d 0:972874f31c98 182 #endif /* ARDUINO */
iforce2d 0:972874f31c98 183
iforce2d 0:972874f31c98 184