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This library is stripped down version of NetServices library. HTTP server and client function is NOT supported.

drv/usb/UsbInc.h@0:dcf3c92487ca, 2011-07-20 (annotated)

Committer:: idinor
Date:: Wed Jul 20 11:45:39 2011 +0000
Revision:: 0:dcf3c92487ca

Who changed what in which revision?

User	Revision	Line number	New contents of line
idinor	0:dcf3c92487ca	1
idinor	0:dcf3c92487ca	2	/*
idinor	0:dcf3c92487ca	3	Copyright (c) 2010 Donatien Garnier (donatiengar [at] gmail [dot] com)
idinor	0:dcf3c92487ca	4
idinor	0:dcf3c92487ca	5	Permission is hereby granted, free of charge, to any person obtaining a copy
idinor	0:dcf3c92487ca	6	of this software and associated documentation files (the "Software"), to deal
idinor	0:dcf3c92487ca	7	in the Software without restriction, including without limitation the rights
idinor	0:dcf3c92487ca	8	to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
idinor	0:dcf3c92487ca	9	copies of the Software, and to permit persons to whom the Software is
idinor	0:dcf3c92487ca	10	furnished to do so, subject to the following conditions:
idinor	0:dcf3c92487ca	11
idinor	0:dcf3c92487ca	12	The above copyright notice and this permission notice shall be included in
idinor	0:dcf3c92487ca	13	all copies or substantial portions of the Software.
idinor	0:dcf3c92487ca	14
idinor	0:dcf3c92487ca	15	THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
idinor	0:dcf3c92487ca	16	IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
idinor	0:dcf3c92487ca	17	FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
idinor	0:dcf3c92487ca	18	AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
idinor	0:dcf3c92487ca	19	LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
idinor	0:dcf3c92487ca	20	OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
idinor	0:dcf3c92487ca	21	THE SOFTWARE.
idinor	0:dcf3c92487ca	22	*/
idinor	0:dcf3c92487ca	23
idinor	0:dcf3c92487ca	24	#ifndef USB_INC_H
idinor	0:dcf3c92487ca	25	#define USB_INC_H
idinor	0:dcf3c92487ca	26
idinor	0:dcf3c92487ca	27	#include "mbed.h"
idinor	0:dcf3c92487ca	28
idinor	0:dcf3c92487ca	29	#define MIN(a,b) ((a)<(b)?(a):(b))
idinor	0:dcf3c92487ca	30	#define MAX(a,b) ((a)>(b)?(a):(b))
idinor	0:dcf3c92487ca	31
idinor	0:dcf3c92487ca	32	//typedef int32_t RC;
idinor	0:dcf3c92487ca	33
idinor	0:dcf3c92487ca	34	typedef uint8_t byte;
idinor	0:dcf3c92487ca	35	typedef uint16_t word;
idinor	0:dcf3c92487ca	36
idinor	0:dcf3c92487ca	37	enum UsbErr
idinor	0:dcf3c92487ca	38	{
idinor	0:dcf3c92487ca	39	__USBERR_MIN = -0xFFFF,
idinor	0:dcf3c92487ca	40	USBERR_DISCONNECTED,
idinor	0:dcf3c92487ca	41	USBERR_NOTFOUND,
idinor	0:dcf3c92487ca	42	USBERR_BADCONFIG,
idinor	0:dcf3c92487ca	43	USBERR_PROCESSING,
idinor	0:dcf3c92487ca	44	USBERR_HALTED, //Transfer on an ep is stalled
idinor	0:dcf3c92487ca	45	USBERR_BUSY,
idinor	0:dcf3c92487ca	46	USBERR_TDFAIL,
idinor	0:dcf3c92487ca	47	USBERR_ERROR,
idinor	0:dcf3c92487ca	48	USBERR_OK = 0
idinor	0:dcf3c92487ca	49	};
idinor	0:dcf3c92487ca	50
idinor	0:dcf3c92487ca	51
idinor	0:dcf3c92487ca	52	/* From NXP's USBHostLite stack's usbhost_lpc17xx.h */
idinor	0:dcf3c92487ca	53	/* Only the types names have been changed to avoid unecessary typedefs */
idinor	0:dcf3c92487ca	54
idinor	0:dcf3c92487ca	55
idinor	0:dcf3c92487ca	56	/*
idinor	0:dcf3c92487ca	57	**************************************************************************************************************
idinor	0:dcf3c92487ca	58	* NXP USB Host Stack
idinor	0:dcf3c92487ca	59	*
idinor	0:dcf3c92487ca	60	* (c) Copyright 2008, NXP SemiConductors
idinor	0:dcf3c92487ca	61	* (c) Copyright 2008, OnChip Technologies LLC
idinor	0:dcf3c92487ca	62	* All Rights Reserved
idinor	0:dcf3c92487ca	63	*
idinor	0:dcf3c92487ca	64	* www.nxp.com
idinor	0:dcf3c92487ca	65	* www.onchiptech.com
idinor	0:dcf3c92487ca	66	*
idinor	0:dcf3c92487ca	67	* File : usbhost_lpc17xx.h
idinor	0:dcf3c92487ca	68	* Programmer(s) : Ravikanth.P
idinor	0:dcf3c92487ca	69	* Version :
idinor	0:dcf3c92487ca	70	*
idinor	0:dcf3c92487ca	71	**************************************************************************************************************
idinor	0:dcf3c92487ca	72	*/
idinor	0:dcf3c92487ca	73
idinor	0:dcf3c92487ca	74
idinor	0:dcf3c92487ca	75
idinor	0:dcf3c92487ca	76	/*
idinor	0:dcf3c92487ca	77	**************************************************************************************************************
idinor	0:dcf3c92487ca	78	* OHCI OPERATIONAL REGISTER FIELD DEFINITIONS
idinor	0:dcf3c92487ca	79	**************************************************************************************************************
idinor	0:dcf3c92487ca	80	*/
idinor	0:dcf3c92487ca	81
idinor	0:dcf3c92487ca	82	/* ------------------ HcControl Register --------------------- */
idinor	0:dcf3c92487ca	83	#define OR_CONTROL_CLE 0x00000010
idinor	0:dcf3c92487ca	84	#define OR_CONTROL_BLE 0x00000020
idinor	0:dcf3c92487ca	85	#define OR_CONTROL_HCFS 0x000000C0
idinor	0:dcf3c92487ca	86	#define OR_CONTROL_HC_OPER 0x00000080
idinor	0:dcf3c92487ca	87	/* ----------------- HcCommandStatus Register ----------------- */
idinor	0:dcf3c92487ca	88	#define OR_CMD_STATUS_HCR 0x00000001
idinor	0:dcf3c92487ca	89	#define OR_CMD_STATUS_CLF 0x00000002
idinor	0:dcf3c92487ca	90	#define OR_CMD_STATUS_BLF 0x00000004
idinor	0:dcf3c92487ca	91	/* --------------- HcInterruptStatus Register ----------------- */
idinor	0:dcf3c92487ca	92	#define OR_INTR_STATUS_WDH 0x00000002
idinor	0:dcf3c92487ca	93	#define OR_INTR_STATUS_RHSC 0x00000040
idinor	0:dcf3c92487ca	94	#define OR_INTR_STATUS_UE 0x00000010
idinor	0:dcf3c92487ca	95	/* --------------- HcInterruptEnable Register ----------------- */
idinor	0:dcf3c92487ca	96	#define OR_INTR_ENABLE_WDH 0x00000002
idinor	0:dcf3c92487ca	97	#define OR_INTR_ENABLE_RHSC 0x00000040
idinor	0:dcf3c92487ca	98	#define OR_INTR_ENABLE_MIE 0x80000000
idinor	0:dcf3c92487ca	99	/* ---------------- HcRhDescriptorA Register ------------------ */
idinor	0:dcf3c92487ca	100	#define OR_RH_STATUS_LPSC 0x00010000
idinor	0:dcf3c92487ca	101	#define OR_RH_STATUS_DRWE 0x00008000
idinor	0:dcf3c92487ca	102	/* -------------- HcRhPortStatus[1:NDP] Register -------------- */
idinor	0:dcf3c92487ca	103	#define OR_RH_PORT_CCS 0x00000001
idinor	0:dcf3c92487ca	104	#define OR_RH_PORT_PRS 0x00000010
idinor	0:dcf3c92487ca	105	#define OR_RH_PORT_CSC 0x00010000
idinor	0:dcf3c92487ca	106	#define OR_RH_PORT_PRSC 0x00100000
idinor	0:dcf3c92487ca	107
idinor	0:dcf3c92487ca	108
idinor	0:dcf3c92487ca	109	/*
idinor	0:dcf3c92487ca	110	**************************************************************************************************************
idinor	0:dcf3c92487ca	111	* FRAME INTERVAL
idinor	0:dcf3c92487ca	112	**************************************************************************************************************
idinor	0:dcf3c92487ca	113	*/
idinor	0:dcf3c92487ca	114
idinor	0:dcf3c92487ca	115	#define FI 0x2EDF /* 12000 bits per frame (-1) */
idinor	0:dcf3c92487ca	116	#define DEFAULT_FMINTERVAL ((((6 * (FI - 210)) / 7) << 16) \| FI)
idinor	0:dcf3c92487ca	117
idinor	0:dcf3c92487ca	118	/*
idinor	0:dcf3c92487ca	119	**************************************************************************************************************
idinor	0:dcf3c92487ca	120	* ENDPOINT DESCRIPTOR CONTROL FIELDS
idinor	0:dcf3c92487ca	121	**************************************************************************************************************
idinor	0:dcf3c92487ca	122	*/
idinor	0:dcf3c92487ca	123
idinor	0:dcf3c92487ca	124	#define ED_SKIP (uint32_t) (0x00001000) /* Skip this ep in queue */
idinor	0:dcf3c92487ca	125
idinor	0:dcf3c92487ca	126	/*
idinor	0:dcf3c92487ca	127	**************************************************************************************************************
idinor	0:dcf3c92487ca	128	* TRANSFER DESCRIPTOR CONTROL FIELDS
idinor	0:dcf3c92487ca	129	**************************************************************************************************************
idinor	0:dcf3c92487ca	130	*/
idinor	0:dcf3c92487ca	131
idinor	0:dcf3c92487ca	132	#define TD_ROUNDING (uint32_t) (0x00040000) /* Buffer Rounding */
idinor	0:dcf3c92487ca	133	#define TD_SETUP (uint32_t)(0) /* Direction of Setup Packet */
idinor	0:dcf3c92487ca	134	#define TD_IN (uint32_t)(0x00100000) /* Direction In */
idinor	0:dcf3c92487ca	135	#define TD_OUT (uint32_t)(0x00080000) /* Direction Out */
idinor	0:dcf3c92487ca	136	#define TD_DELAY_INT(x) (uint32_t)((x) << 21) /* Delay Interrupt */
idinor	0:dcf3c92487ca	137	#define TD_TOGGLE_0 (uint32_t)(0x02000000) /* Toggle 0 */
idinor	0:dcf3c92487ca	138	#define TD_TOGGLE_1 (uint32_t)(0x03000000) /* Toggle 1 */
idinor	0:dcf3c92487ca	139	#define TD_CC (uint32_t)(0xF0000000) /* Completion Code */
idinor	0:dcf3c92487ca	140
idinor	0:dcf3c92487ca	141	/*
idinor	0:dcf3c92487ca	142	**************************************************************************************************************
idinor	0:dcf3c92487ca	143	* USB STANDARD REQUEST DEFINITIONS
idinor	0:dcf3c92487ca	144	**************************************************************************************************************
idinor	0:dcf3c92487ca	145	*/
idinor	0:dcf3c92487ca	146
idinor	0:dcf3c92487ca	147	#define USB_DESCRIPTOR_TYPE_DEVICE 1
idinor	0:dcf3c92487ca	148	#define USB_DESCRIPTOR_TYPE_CONFIGURATION 2
idinor	0:dcf3c92487ca	149	#define USB_DESCRIPTOR_TYPE_INTERFACE 4
idinor	0:dcf3c92487ca	150	#define USB_DESCRIPTOR_TYPE_ENDPOINT 5
idinor	0:dcf3c92487ca	151	/* ----------- Control RequestType Fields ----------- */
idinor	0:dcf3c92487ca	152	#define USB_DEVICE_TO_HOST 0x80
idinor	0:dcf3c92487ca	153	#define USB_HOST_TO_DEVICE 0x00
idinor	0:dcf3c92487ca	154	#define USB_REQUEST_TYPE_CLASS 0x20
idinor	0:dcf3c92487ca	155	#define USB_RECIPIENT_DEVICE 0x00
idinor	0:dcf3c92487ca	156	#define USB_RECIPIENT_INTERFACE 0x01
idinor	0:dcf3c92487ca	157	/* -------------- USB Standard Requests -------------- */
idinor	0:dcf3c92487ca	158	#define SET_ADDRESS 5
idinor	0:dcf3c92487ca	159	#define GET_DESCRIPTOR 6
idinor	0:dcf3c92487ca	160	#define SET_CONFIGURATION 9
idinor	0:dcf3c92487ca	161	#define SET_INTERFACE 11
idinor	0:dcf3c92487ca	162
idinor	0:dcf3c92487ca	163	/*
idinor	0:dcf3c92487ca	164	**************************************************************************************************************
idinor	0:dcf3c92487ca	165	* TYPE DEFINITIONS
idinor	0:dcf3c92487ca	166	**************************************************************************************************************
idinor	0:dcf3c92487ca	167	*/
idinor	0:dcf3c92487ca	168
idinor	0:dcf3c92487ca	169	typedef struct hcEd { /* ----------- HostController EndPoint Descriptor ------------- */
idinor	0:dcf3c92487ca	170	volatile uint32_t Control; /* Endpoint descriptor control */
idinor	0:dcf3c92487ca	171	volatile uint32_t TailTd; /* Physical address of tail in Transfer descriptor list */
idinor	0:dcf3c92487ca	172	volatile uint32_t HeadTd; /* Physcial address of head in Transfer descriptor list */
idinor	0:dcf3c92487ca	173	volatile uint32_t Next; /* Physical address of next Endpoint descriptor */
idinor	0:dcf3c92487ca	174	} HCED;
idinor	0:dcf3c92487ca	175
idinor	0:dcf3c92487ca	176	typedef struct hcTd { /* ------------ HostController Transfer Descriptor ------------ */
idinor	0:dcf3c92487ca	177	volatile uint32_t Control; /* Transfer descriptor control */
idinor	0:dcf3c92487ca	178	volatile uint32_t CurrBufPtr; /* Physical address of current buffer pointer */
idinor	0:dcf3c92487ca	179	volatile uint32_t Next; /* Physical pointer to next Transfer Descriptor */
idinor	0:dcf3c92487ca	180	volatile uint32_t BufEnd; /* Physical address of end of buffer */
idinor	0:dcf3c92487ca	181	} HCTD;
idinor	0:dcf3c92487ca	182
idinor	0:dcf3c92487ca	183	typedef struct hcca { /* ----------- Host Controller Communication Area ------------ */
idinor	0:dcf3c92487ca	184	volatile uint32_t IntTable[32]; /* Interrupt Table */
idinor	0:dcf3c92487ca	185	volatile uint32_t FrameNumber; /* Frame Number */
idinor	0:dcf3c92487ca	186	volatile uint32_t DoneHead; /* Done Head */
idinor	0:dcf3c92487ca	187	volatile uint8_t Reserved[116]; /* Reserved for future use */
idinor	0:dcf3c92487ca	188	volatile uint8_t Unknown[4]; /* Unused */
idinor	0:dcf3c92487ca	189	} HCCA;
idinor	0:dcf3c92487ca	190
idinor	0:dcf3c92487ca	191
idinor	0:dcf3c92487ca	192
idinor	0:dcf3c92487ca	193	#endif

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Type:	Library
Created:	20 Jul 2011
Imports:	35
Forks:	0
Commits:	1
Dependents:	1
Dependencies:	0
Followers:	1

drv/usb/UsbInc.h@0:dcf3c92487ca, 2011-07-20 (annotated)

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