mbed library sources: Modified to operate FRDM-KL25Z at 48MHz from internal 32kHz oscillator (nothing else changed).
Fork of mbed-src by
The only file that changed is: mbed-src-FLL48/targets/cmsis/TARGET_Freescale/TARGET_KL25Z/system_MKL25Z4.h
vendor/Freescale/KL25Z/cmsis/system_MKL25Z4.c@10:3bc89ef62ce7, 2013-06-14 (annotated)
- Committer:
- emilmont
- Date:
- Fri Jun 14 17:49:17 2013 +0100
- Revision:
- 10:3bc89ef62ce7
Unify mbed library sources
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
emilmont | 10:3bc89ef62ce7 | 1 | /* |
emilmont | 10:3bc89ef62ce7 | 2 | ** ################################################################### |
emilmont | 10:3bc89ef62ce7 | 3 | ** Processor: MKL25Z128VLK4 |
emilmont | 10:3bc89ef62ce7 | 4 | ** Compilers: ARM Compiler |
emilmont | 10:3bc89ef62ce7 | 5 | ** Freescale C/C++ for Embedded ARM |
emilmont | 10:3bc89ef62ce7 | 6 | ** GNU C Compiler |
emilmont | 10:3bc89ef62ce7 | 7 | ** IAR ANSI C/C++ Compiler for ARM |
emilmont | 10:3bc89ef62ce7 | 8 | ** |
emilmont | 10:3bc89ef62ce7 | 9 | ** Reference manual: KL25RM, Rev.1, Jun 2012 |
emilmont | 10:3bc89ef62ce7 | 10 | ** Version: rev. 1.1, 2012-06-21 |
emilmont | 10:3bc89ef62ce7 | 11 | ** |
emilmont | 10:3bc89ef62ce7 | 12 | ** Abstract: |
emilmont | 10:3bc89ef62ce7 | 13 | ** Provides a system configuration function and a global variable that |
emilmont | 10:3bc89ef62ce7 | 14 | ** contains the system frequency. It configures the device and initializes |
emilmont | 10:3bc89ef62ce7 | 15 | ** the oscillator (PLL) that is part of the microcontroller device. |
emilmont | 10:3bc89ef62ce7 | 16 | ** |
emilmont | 10:3bc89ef62ce7 | 17 | ** Copyright: 2012 Freescale Semiconductor, Inc. All Rights Reserved. |
emilmont | 10:3bc89ef62ce7 | 18 | ** |
emilmont | 10:3bc89ef62ce7 | 19 | ** http: www.freescale.com |
emilmont | 10:3bc89ef62ce7 | 20 | ** mail: support@freescale.com |
emilmont | 10:3bc89ef62ce7 | 21 | ** |
emilmont | 10:3bc89ef62ce7 | 22 | ** Revisions: |
emilmont | 10:3bc89ef62ce7 | 23 | ** - rev. 1.0 (2012-06-13) |
emilmont | 10:3bc89ef62ce7 | 24 | ** Initial version. |
emilmont | 10:3bc89ef62ce7 | 25 | ** - rev. 1.1 (2012-06-21) |
emilmont | 10:3bc89ef62ce7 | 26 | ** Update according to reference manual rev. 1. |
emilmont | 10:3bc89ef62ce7 | 27 | ** |
emilmont | 10:3bc89ef62ce7 | 28 | ** ################################################################### |
emilmont | 10:3bc89ef62ce7 | 29 | */ |
emilmont | 10:3bc89ef62ce7 | 30 | |
emilmont | 10:3bc89ef62ce7 | 31 | /** |
emilmont | 10:3bc89ef62ce7 | 32 | * @file MKL25Z4 |
emilmont | 10:3bc89ef62ce7 | 33 | * @version 1.1 |
emilmont | 10:3bc89ef62ce7 | 34 | * @date 2012-06-21 |
emilmont | 10:3bc89ef62ce7 | 35 | * @brief Device specific configuration file for MKL25Z4 (implementation file) |
emilmont | 10:3bc89ef62ce7 | 36 | * |
emilmont | 10:3bc89ef62ce7 | 37 | * Provides a system configuration function and a global variable that contains |
emilmont | 10:3bc89ef62ce7 | 38 | * the system frequency. It configures the device and initializes the oscillator |
emilmont | 10:3bc89ef62ce7 | 39 | * (PLL) that is part of the microcontroller device. |
emilmont | 10:3bc89ef62ce7 | 40 | */ |
emilmont | 10:3bc89ef62ce7 | 41 | |
emilmont | 10:3bc89ef62ce7 | 42 | #include <stdint.h> |
emilmont | 10:3bc89ef62ce7 | 43 | #include "MKL25Z4.h" |
emilmont | 10:3bc89ef62ce7 | 44 | |
emilmont | 10:3bc89ef62ce7 | 45 | #define DISABLE_WDOG 1 |
emilmont | 10:3bc89ef62ce7 | 46 | |
emilmont | 10:3bc89ef62ce7 | 47 | #define CLOCK_SETUP 1 |
emilmont | 10:3bc89ef62ce7 | 48 | /* Predefined clock setups |
emilmont | 10:3bc89ef62ce7 | 49 | 0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode |
emilmont | 10:3bc89ef62ce7 | 50 | Reference clock source for MCG module is the slow internal clock source 32.768kHz |
emilmont | 10:3bc89ef62ce7 | 51 | Core clock = 41.94MHz, BusClock = 13.98MHz |
emilmont | 10:3bc89ef62ce7 | 52 | 1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode |
emilmont | 10:3bc89ef62ce7 | 53 | Reference clock source for MCG module is an external crystal 8MHz |
emilmont | 10:3bc89ef62ce7 | 54 | Core clock = 48MHz, BusClock = 24MHz |
emilmont | 10:3bc89ef62ce7 | 55 | 2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode |
emilmont | 10:3bc89ef62ce7 | 56 | Core clock/Bus clock derived directly from an external crystal 8MHz with no multiplication |
emilmont | 10:3bc89ef62ce7 | 57 | Core clock = 8MHz, BusClock = 8MHz |
emilmont | 10:3bc89ef62ce7 | 58 | */ |
emilmont | 10:3bc89ef62ce7 | 59 | |
emilmont | 10:3bc89ef62ce7 | 60 | /*---------------------------------------------------------------------------- |
emilmont | 10:3bc89ef62ce7 | 61 | Define clock source values |
emilmont | 10:3bc89ef62ce7 | 62 | *----------------------------------------------------------------------------*/ |
emilmont | 10:3bc89ef62ce7 | 63 | #if (CLOCK_SETUP == 0) |
emilmont | 10:3bc89ef62ce7 | 64 | #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */ |
emilmont | 10:3bc89ef62ce7 | 65 | #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ |
emilmont | 10:3bc89ef62ce7 | 66 | #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ |
emilmont | 10:3bc89ef62ce7 | 67 | #define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value */ |
emilmont | 10:3bc89ef62ce7 | 68 | #elif (CLOCK_SETUP == 1) |
emilmont | 10:3bc89ef62ce7 | 69 | #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */ |
emilmont | 10:3bc89ef62ce7 | 70 | #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ |
emilmont | 10:3bc89ef62ce7 | 71 | #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ |
emilmont | 10:3bc89ef62ce7 | 72 | #define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */ |
emilmont | 10:3bc89ef62ce7 | 73 | #elif (CLOCK_SETUP == 2) |
emilmont | 10:3bc89ef62ce7 | 74 | #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */ |
emilmont | 10:3bc89ef62ce7 | 75 | #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ |
emilmont | 10:3bc89ef62ce7 | 76 | #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ |
emilmont | 10:3bc89ef62ce7 | 77 | #define DEFAULT_SYSTEM_CLOCK 8000000u /* Default System clock value */ |
emilmont | 10:3bc89ef62ce7 | 78 | #endif /* (CLOCK_SETUP == 2) */ |
emilmont | 10:3bc89ef62ce7 | 79 | |
emilmont | 10:3bc89ef62ce7 | 80 | |
emilmont | 10:3bc89ef62ce7 | 81 | /* ---------------------------------------------------------------------------- |
emilmont | 10:3bc89ef62ce7 | 82 | -- Core clock |
emilmont | 10:3bc89ef62ce7 | 83 | ---------------------------------------------------------------------------- */ |
emilmont | 10:3bc89ef62ce7 | 84 | |
emilmont | 10:3bc89ef62ce7 | 85 | uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; |
emilmont | 10:3bc89ef62ce7 | 86 | |
emilmont | 10:3bc89ef62ce7 | 87 | /* ---------------------------------------------------------------------------- |
emilmont | 10:3bc89ef62ce7 | 88 | -- SystemInit() |
emilmont | 10:3bc89ef62ce7 | 89 | ---------------------------------------------------------------------------- */ |
emilmont | 10:3bc89ef62ce7 | 90 | |
emilmont | 10:3bc89ef62ce7 | 91 | void SystemInit (void) { |
emilmont | 10:3bc89ef62ce7 | 92 | #if (DISABLE_WDOG) |
emilmont | 10:3bc89ef62ce7 | 93 | /* Disable the WDOG module */ |
emilmont | 10:3bc89ef62ce7 | 94 | /* SIM_COPC: COPT=0,COPCLKS=0,COPW=0 */ |
emilmont | 10:3bc89ef62ce7 | 95 | SIM->COPC = (uint32_t)0x00u; |
emilmont | 10:3bc89ef62ce7 | 96 | #endif /* (DISABLE_WDOG) */ |
emilmont | 10:3bc89ef62ce7 | 97 | #if (CLOCK_SETUP == 0) |
emilmont | 10:3bc89ef62ce7 | 98 | /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=2,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ |
emilmont | 10:3bc89ef62ce7 | 99 | SIM->CLKDIV1 = (uint32_t)0x00020000UL; /* Update system prescalers */ |
emilmont | 10:3bc89ef62ce7 | 100 | /* Switch to FEI Mode */ |
emilmont | 10:3bc89ef62ce7 | 101 | /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */ |
emilmont | 10:3bc89ef62ce7 | 102 | MCG->C1 = (uint8_t)0x06U; |
emilmont | 10:3bc89ef62ce7 | 103 | /* MCG_C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */ |
emilmont | 10:3bc89ef62ce7 | 104 | MCG->C2 = (uint8_t)0x00U; |
emilmont | 10:3bc89ef62ce7 | 105 | /* MCG->C4: DMX32=0,DRST_DRS=1 */ |
emilmont | 10:3bc89ef62ce7 | 106 | MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0U) | (uint8_t)0x20U); |
emilmont | 10:3bc89ef62ce7 | 107 | /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ |
emilmont | 10:3bc89ef62ce7 | 108 | OSC0->CR = (uint8_t)0x80U; |
emilmont | 10:3bc89ef62ce7 | 109 | /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */ |
emilmont | 10:3bc89ef62ce7 | 110 | MCG->C5 = (uint8_t)0x00U; |
emilmont | 10:3bc89ef62ce7 | 111 | /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */ |
emilmont | 10:3bc89ef62ce7 | 112 | MCG->C6 = (uint8_t)0x00U; |
emilmont | 10:3bc89ef62ce7 | 113 | while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */ |
emilmont | 10:3bc89ef62ce7 | 114 | } |
emilmont | 10:3bc89ef62ce7 | 115 | while((MCG->S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */ |
emilmont | 10:3bc89ef62ce7 | 116 | } |
emilmont | 10:3bc89ef62ce7 | 117 | #elif (CLOCK_SETUP == 1) |
emilmont | 10:3bc89ef62ce7 | 118 | /* SIM->SCGC5: PORTA=1 */ |
emilmont | 10:3bc89ef62ce7 | 119 | SIM->SCGC5 |= (uint32_t)0x0200UL; /* Enable clock gate for ports to enable pin routing */ |
emilmont | 10:3bc89ef62ce7 | 120 | /* SIM->CLKDIV1: OUTDIV1=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ |
emilmont | 10:3bc89ef62ce7 | 121 | SIM->CLKDIV1 = (uint32_t)0x10010000UL; /* Update system prescalers */ |
emilmont | 10:3bc89ef62ce7 | 122 | /* PORTA->PCR18: ISF=0,MUX=0 */ |
emilmont | 10:3bc89ef62ce7 | 123 | PORTA->PCR[18] &= (uint32_t)~0x01000700UL; |
emilmont | 10:3bc89ef62ce7 | 124 | /* PORTA->PCR19: ISF=0,MUX=0 */ |
emilmont | 10:3bc89ef62ce7 | 125 | PORTA->PCR[19] &= (uint32_t)~0x01000700UL; |
emilmont | 10:3bc89ef62ce7 | 126 | /* Switch to FBE Mode */ |
emilmont | 10:3bc89ef62ce7 | 127 | /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=1,SC4P=0,SC8P=0,SC16P=1 */ |
emilmont | 10:3bc89ef62ce7 | 128 | OSC0->CR = (uint8_t)0x89U; |
emilmont | 10:3bc89ef62ce7 | 129 | /* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */ |
emilmont | 10:3bc89ef62ce7 | 130 | MCG->C2 = (uint8_t)0x24U; |
emilmont | 10:3bc89ef62ce7 | 131 | /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ |
emilmont | 10:3bc89ef62ce7 | 132 | MCG->C1 = (uint8_t)0x9AU; |
emilmont | 10:3bc89ef62ce7 | 133 | /* MCG->C4: DMX32=0,DRST_DRS=0 */ |
emilmont | 10:3bc89ef62ce7 | 134 | MCG->C4 &= (uint8_t)~(uint8_t)0xE0U; |
emilmont | 10:3bc89ef62ce7 | 135 | /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */ |
emilmont | 10:3bc89ef62ce7 | 136 | MCG->C5 = (uint8_t)0x01U; |
emilmont | 10:3bc89ef62ce7 | 137 | /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */ |
emilmont | 10:3bc89ef62ce7 | 138 | MCG->C6 = (uint8_t)0x00U; |
emilmont | 10:3bc89ef62ce7 | 139 | while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */ |
emilmont | 10:3bc89ef62ce7 | 140 | } |
emilmont | 10:3bc89ef62ce7 | 141 | while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */ |
emilmont | 10:3bc89ef62ce7 | 142 | } |
emilmont | 10:3bc89ef62ce7 | 143 | /* Switch to PBE Mode */ |
emilmont | 10:3bc89ef62ce7 | 144 | /* MCG->C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0 */ |
emilmont | 10:3bc89ef62ce7 | 145 | MCG->C6 = (uint8_t)0x40U; |
emilmont | 10:3bc89ef62ce7 | 146 | while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */ |
emilmont | 10:3bc89ef62ce7 | 147 | } |
emilmont | 10:3bc89ef62ce7 | 148 | while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until locked */ |
emilmont | 10:3bc89ef62ce7 | 149 | } |
emilmont | 10:3bc89ef62ce7 | 150 | /* Switch to PEE Mode */ |
emilmont | 10:3bc89ef62ce7 | 151 | /* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ |
emilmont | 10:3bc89ef62ce7 | 152 | MCG->C1 = (uint8_t)0x1AU; |
emilmont | 10:3bc89ef62ce7 | 153 | while((MCG->S & 0x0CU) != 0x0CU) { /* Wait until output of the PLL is selected */ |
emilmont | 10:3bc89ef62ce7 | 154 | } |
emilmont | 10:3bc89ef62ce7 | 155 | #elif (CLOCK_SETUP == 2) |
emilmont | 10:3bc89ef62ce7 | 156 | /* SIM->SCGC5: PORTA=1 */ |
emilmont | 10:3bc89ef62ce7 | 157 | SIM->SCGC5 |= (uint32_t)0x0200UL; /* Enable clock gate for ports to enable pin routing */ |
emilmont | 10:3bc89ef62ce7 | 158 | /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ |
emilmont | 10:3bc89ef62ce7 | 159 | SIM->CLKDIV1 = (uint32_t)0x00000000UL; /* Update system prescalers */ |
emilmont | 10:3bc89ef62ce7 | 160 | /* PORTA->PCR18: ISF=0,MUX=0 */ |
emilmont | 10:3bc89ef62ce7 | 161 | PORTA->PCR[18] &= (uint32_t)~0x01000700UL; |
emilmont | 10:3bc89ef62ce7 | 162 | /* PORTA->PCR19: ISF=0,MUX=0 */ |
emilmont | 10:3bc89ef62ce7 | 163 | PORTA->PCR[19] &= (uint32_t)~0x01000700UL; |
emilmont | 10:3bc89ef62ce7 | 164 | /* Switch to FBE Mode */ |
emilmont | 10:3bc89ef62ce7 | 165 | /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=1,SC4P=0,SC8P=0,SC16P=1 */ |
emilmont | 10:3bc89ef62ce7 | 166 | OSC0->CR = (uint8_t)0x89U; |
emilmont | 10:3bc89ef62ce7 | 167 | /* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */ |
emilmont | 10:3bc89ef62ce7 | 168 | MCG->C2 = (uint8_t)0x24U; |
emilmont | 10:3bc89ef62ce7 | 169 | /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ |
emilmont | 10:3bc89ef62ce7 | 170 | MCG->C1 = (uint8_t)0x9AU; |
emilmont | 10:3bc89ef62ce7 | 171 | /* MCG->C4: DMX32=0,DRST_DRS=0 */ |
emilmont | 10:3bc89ef62ce7 | 172 | MCG->C4 &= (uint8_t)~(uint8_t)0xE0U; |
emilmont | 10:3bc89ef62ce7 | 173 | /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */ |
emilmont | 10:3bc89ef62ce7 | 174 | MCG->C5 = (uint8_t)0x00U; |
emilmont | 10:3bc89ef62ce7 | 175 | /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */ |
emilmont | 10:3bc89ef62ce7 | 176 | MCG->C6 = (uint8_t)0x00U; |
emilmont | 10:3bc89ef62ce7 | 177 | while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */ |
emilmont | 10:3bc89ef62ce7 | 178 | } |
emilmont | 10:3bc89ef62ce7 | 179 | while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */ |
emilmont | 10:3bc89ef62ce7 | 180 | } |
emilmont | 10:3bc89ef62ce7 | 181 | /* Switch to BLPE Mode */ |
emilmont | 10:3bc89ef62ce7 | 182 | /* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=1,IRCS=0 */ |
emilmont | 10:3bc89ef62ce7 | 183 | MCG->C2 = (uint8_t)0x26U; |
emilmont | 10:3bc89ef62ce7 | 184 | while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */ |
emilmont | 10:3bc89ef62ce7 | 185 | } |
emilmont | 10:3bc89ef62ce7 | 186 | #endif /* (CLOCK_SETUP == 2) */ |
emilmont | 10:3bc89ef62ce7 | 187 | } |
emilmont | 10:3bc89ef62ce7 | 188 | |
emilmont | 10:3bc89ef62ce7 | 189 | /* ---------------------------------------------------------------------------- |
emilmont | 10:3bc89ef62ce7 | 190 | -- SystemCoreClockUpdate() |
emilmont | 10:3bc89ef62ce7 | 191 | ---------------------------------------------------------------------------- */ |
emilmont | 10:3bc89ef62ce7 | 192 | |
emilmont | 10:3bc89ef62ce7 | 193 | void SystemCoreClockUpdate (void) { |
emilmont | 10:3bc89ef62ce7 | 194 | uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */ |
emilmont | 10:3bc89ef62ce7 | 195 | uint8_t Divider; |
emilmont | 10:3bc89ef62ce7 | 196 | |
emilmont | 10:3bc89ef62ce7 | 197 | if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) { |
emilmont | 10:3bc89ef62ce7 | 198 | /* Output of FLL or PLL is selected */ |
emilmont | 10:3bc89ef62ce7 | 199 | if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { |
emilmont | 10:3bc89ef62ce7 | 200 | /* FLL is selected */ |
emilmont | 10:3bc89ef62ce7 | 201 | if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) { |
emilmont | 10:3bc89ef62ce7 | 202 | /* External reference clock is selected */ |
emilmont | 10:3bc89ef62ce7 | 203 | MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */ |
emilmont | 10:3bc89ef62ce7 | 204 | Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); |
emilmont | 10:3bc89ef62ce7 | 205 | MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ |
emilmont | 10:3bc89ef62ce7 | 206 | if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) { |
emilmont | 10:3bc89ef62ce7 | 207 | MCGOUTClock /= 32u; /* If high range is enabled, additional 32 divider is active */ |
emilmont | 10:3bc89ef62ce7 | 208 | } /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) */ |
emilmont | 10:3bc89ef62ce7 | 209 | } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */ |
emilmont | 10:3bc89ef62ce7 | 210 | MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */ |
emilmont | 10:3bc89ef62ce7 | 211 | } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */ |
emilmont | 10:3bc89ef62ce7 | 212 | /* Select correct multiplier to calculate the MCG output clock */ |
emilmont | 10:3bc89ef62ce7 | 213 | switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) { |
emilmont | 10:3bc89ef62ce7 | 214 | case 0x0u: |
emilmont | 10:3bc89ef62ce7 | 215 | MCGOUTClock *= 640u; |
emilmont | 10:3bc89ef62ce7 | 216 | break; |
emilmont | 10:3bc89ef62ce7 | 217 | case 0x20u: |
emilmont | 10:3bc89ef62ce7 | 218 | MCGOUTClock *= 1280u; |
emilmont | 10:3bc89ef62ce7 | 219 | break; |
emilmont | 10:3bc89ef62ce7 | 220 | case 0x40u: |
emilmont | 10:3bc89ef62ce7 | 221 | MCGOUTClock *= 1920u; |
emilmont | 10:3bc89ef62ce7 | 222 | break; |
emilmont | 10:3bc89ef62ce7 | 223 | case 0x60u: |
emilmont | 10:3bc89ef62ce7 | 224 | MCGOUTClock *= 2560u; |
emilmont | 10:3bc89ef62ce7 | 225 | break; |
emilmont | 10:3bc89ef62ce7 | 226 | case 0x80u: |
emilmont | 10:3bc89ef62ce7 | 227 | MCGOUTClock *= 732u; |
emilmont | 10:3bc89ef62ce7 | 228 | break; |
emilmont | 10:3bc89ef62ce7 | 229 | case 0xA0u: |
emilmont | 10:3bc89ef62ce7 | 230 | MCGOUTClock *= 1464u; |
emilmont | 10:3bc89ef62ce7 | 231 | break; |
emilmont | 10:3bc89ef62ce7 | 232 | case 0xC0u: |
emilmont | 10:3bc89ef62ce7 | 233 | MCGOUTClock *= 2197u; |
emilmont | 10:3bc89ef62ce7 | 234 | break; |
emilmont | 10:3bc89ef62ce7 | 235 | case 0xE0u: |
emilmont | 10:3bc89ef62ce7 | 236 | MCGOUTClock *= 2929u; |
emilmont | 10:3bc89ef62ce7 | 237 | break; |
emilmont | 10:3bc89ef62ce7 | 238 | default: |
emilmont | 10:3bc89ef62ce7 | 239 | break; |
emilmont | 10:3bc89ef62ce7 | 240 | } |
emilmont | 10:3bc89ef62ce7 | 241 | } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */ |
emilmont | 10:3bc89ef62ce7 | 242 | /* PLL is selected */ |
emilmont | 10:3bc89ef62ce7 | 243 | Divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK)); |
emilmont | 10:3bc89ef62ce7 | 244 | MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */ |
emilmont | 10:3bc89ef62ce7 | 245 | Divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u); |
emilmont | 10:3bc89ef62ce7 | 246 | MCGOUTClock *= Divider; /* Calculate the MCG output clock */ |
emilmont | 10:3bc89ef62ce7 | 247 | } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */ |
emilmont | 10:3bc89ef62ce7 | 248 | } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) { |
emilmont | 10:3bc89ef62ce7 | 249 | /* Internal reference clock is selected */ |
emilmont | 10:3bc89ef62ce7 | 250 | if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) { |
emilmont | 10:3bc89ef62ce7 | 251 | MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */ |
emilmont | 10:3bc89ef62ce7 | 252 | } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */ |
emilmont | 10:3bc89ef62ce7 | 253 | MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */ |
emilmont | 10:3bc89ef62ce7 | 254 | } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */ |
emilmont | 10:3bc89ef62ce7 | 255 | } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) { |
emilmont | 10:3bc89ef62ce7 | 256 | /* External reference clock is selected */ |
emilmont | 10:3bc89ef62ce7 | 257 | MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */ |
emilmont | 10:3bc89ef62ce7 | 258 | } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */ |
emilmont | 10:3bc89ef62ce7 | 259 | /* Reserved value */ |
emilmont | 10:3bc89ef62ce7 | 260 | return; |
emilmont | 10:3bc89ef62ce7 | 261 | } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */ |
emilmont | 10:3bc89ef62ce7 | 262 | SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT))); |
emilmont | 10:3bc89ef62ce7 | 263 | } |