david dicarlo / mbed-src-FLL48

mbed library sources: Modified to operate FRDM-KL25Z at 48MHz from internal 32kHz oscillator (nothing else changed).

Fork of mbed-src by mbed official

The only file that changed is: mbed-src-FLL48/targets/cmsis/TARGET_Freescale/TARGET_KL25Z/system_MKL25Z4.h

targets/hal/TARGET_Freescale/TARGET_KL05Z/analogin_api.c@30:7ca55132b805, 2013-10-26 (annotated)

Committer:
icenyne
Date:
Sat Oct 26 13:59:14 2013 +0000
Revision:
30:7ca55132b805
Parent:
20:4263a77256ae 
mbed library source for KL25Z updated to operate using internal oscillator at 48MHz as the default.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 20:4263a77256ae 1 /* mbed Microcontroller Library
bogdanm 20:4263a77256ae 2 * Copyright (c) 2006-2013 ARM Limited
bogdanm 20:4263a77256ae 3 *
bogdanm 20:4263a77256ae 4 * Licensed under the Apache License, Version 2.0 (the "License");
bogdanm 20:4263a77256ae 5 * you may not use this file except in compliance with the License.
bogdanm 20:4263a77256ae 6 * You may obtain a copy of the License at
bogdanm 20:4263a77256ae 7 *
bogdanm 20:4263a77256ae 8 * http://www.apache.org/licenses/LICENSE-2.0
bogdanm 20:4263a77256ae 9 *
bogdanm 20:4263a77256ae 10 * Unless required by applicable law or agreed to in writing, software
bogdanm 20:4263a77256ae 11 * distributed under the License is distributed on an "AS IS" BASIS,
bogdanm 20:4263a77256ae 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
bogdanm 20:4263a77256ae 13 * See the License for the specific language governing permissions and
bogdanm 20:4263a77256ae 14 * limitations under the License.
bogdanm 20:4263a77256ae 15 */
bogdanm 20:4263a77256ae 16 #include "analogin_api.h"
bogdanm 20:4263a77256ae 17
bogdanm 20:4263a77256ae 18 #include "cmsis.h"
bogdanm 20:4263a77256ae 19 #include "pinmap.h"
bogdanm 20:4263a77256ae 20 #include "error.h"
bogdanm 20:4263a77256ae 21
bogdanm 20:4263a77256ae 22 static const PinMap PinMap_ADC[] = {
bogdanm 20:4263a77256ae 23 /* A0-A5 pins */
bogdanm 20:4263a77256ae 24 {PTA0, ADC0_SE12, 0},
bogdanm 20:4263a77256ae 25 {PTA8, ADC0_SE3, 0},
bogdanm 20:4263a77256ae 26 {PTA9, ADC0_SE2, 0},
bogdanm 20:4263a77256ae 27 {PTB8, ADC0_SE11, 0},
bogdanm 20:4263a77256ae 28 {PTB9, ADC0_SE10, 0},
bogdanm 20:4263a77256ae 29 {PTB13, ADC0_SE13, 0},
bogdanm 20:4263a77256ae 30 /* Rest of pins ADC Mux */
bogdanm 20:4263a77256ae 31 {PTB2, ADC0_SE4, 0},
bogdanm 20:4263a77256ae 32 {PTB1, ADC0_SE5, 0},
bogdanm 20:4263a77256ae 33 {PTB5, ADC0_SE1, 0},
bogdanm 20:4263a77256ae 34 {PTA12, ADC0_SE0, 0},
bogdanm 20:4263a77256ae 35 {PTB10, ADC0_SE9, 0},
bogdanm 20:4263a77256ae 36 {PTB11, ADC0_SE8, 0},
bogdanm 20:4263a77256ae 37 {PTB7, ADC0_SE7, 0},
bogdanm 20:4263a77256ae 38 {PTB0, ADC0_SE6, 0},
bogdanm 20:4263a77256ae 39 {NC, NC, 0}
bogdanm 20:4263a77256ae 40 };
bogdanm 20:4263a77256ae 41
bogdanm 20:4263a77256ae 42 void analogin_init(analogin_t *obj, PinName pin) {
bogdanm 20:4263a77256ae 43 obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
bogdanm 20:4263a77256ae 44 if (obj->adc == (uint32_t)NC) {
bogdanm 20:4263a77256ae 45 error("ADC pin mapping failed");
bogdanm 20:4263a77256ae 46 }
bogdanm 20:4263a77256ae 47
bogdanm 20:4263a77256ae 48 SIM->SCGC6 |= SIM_SCGC6_ADC0_MASK;
bogdanm 20:4263a77256ae 49
bogdanm 20:4263a77256ae 50 uint32_t port = (uint32_t)pin >> PORT_SHIFT;
bogdanm 20:4263a77256ae 51 SIM->SCGC5 |= 1 << (SIM_SCGC5_PORTA_SHIFT + port);
bogdanm 20:4263a77256ae 52
bogdanm 20:4263a77256ae 53 ADC0->SC1[1] = ADC_SC1_ADCH(obj->adc);
bogdanm 20:4263a77256ae 54
bogdanm 20:4263a77256ae 55 ADC0->CFG1 = ADC_CFG1_ADLPC_MASK // Low-Power Configuration
bogdanm 20:4263a77256ae 56 | ADC_CFG1_ADIV(3) // Clock Divide Select: (Input Clock)/8
bogdanm 20:4263a77256ae 57 | ADC_CFG1_ADLSMP_MASK // Long Sample Time
bogdanm 20:4263a77256ae 58 | ADC_CFG1_MODE(1) // (12)bits Resolution
bogdanm 20:4263a77256ae 59 | ADC_CFG1_ADICLK(1); // Input Clock: (Bus Clock)/2
bogdanm 20:4263a77256ae 60
bogdanm 20:4263a77256ae 61 ADC0->CFG2 = ADC_CFG2_MUXSEL_MASK // ADxxb channels are selected
bogdanm 20:4263a77256ae 62 | ADC_CFG2_ADACKEN_MASK // Asynchronous Clock Output Enable
bogdanm 20:4263a77256ae 63 | ADC_CFG2_ADHSC_MASK // High-Speed Configuration
bogdanm 20:4263a77256ae 64 | ADC_CFG2_ADLSTS(0); // Long Sample Time Select
bogdanm 20:4263a77256ae 65
bogdanm 20:4263a77256ae 66 ADC0->SC2 = ADC_SC2_REFSEL(0); // Default Voltage Reference
bogdanm 20:4263a77256ae 67
bogdanm 20:4263a77256ae 68 ADC0->SC3 = ADC_SC3_AVGE_MASK // Hardware Average Enable
bogdanm 20:4263a77256ae 69 | ADC_SC3_AVGS(0); // 4 Samples Averaged
bogdanm 20:4263a77256ae 70
bogdanm 20:4263a77256ae 71 pinmap_pinout(pin, PinMap_ADC);
bogdanm 20:4263a77256ae 72 }
bogdanm 20:4263a77256ae 73
bogdanm 20:4263a77256ae 74 uint16_t analogin_read_u16(analogin_t *obj) {
bogdanm 20:4263a77256ae 75 // start conversion
bogdanm 20:4263a77256ae 76 ADC0->SC1[0] = ADC_SC1_ADCH(obj->adc);
bogdanm 20:4263a77256ae 77
bogdanm 20:4263a77256ae 78 // Wait Conversion Complete
bogdanm 20:4263a77256ae 79 while ((ADC0->SC1[0] & ADC_SC1_COCO_MASK) != ADC_SC1_COCO_MASK);
bogdanm 20:4263a77256ae 80
bogdanm 20:4263a77256ae 81 // Return value (12bit)
bogdanm 20:4263a77256ae 82 return (uint16_t)ADC0->R[0];
bogdanm 20:4263a77256ae 83 }
bogdanm 20:4263a77256ae 84
bogdanm 20:4263a77256ae 85 float analogin_read(analogin_t *obj) {
bogdanm 20:4263a77256ae 86 uint16_t value = analogin_read_u16(obj);
bogdanm 20:4263a77256ae 87 return (float)value * (1.0f / (float)0xFFFF);
bogdanm 20:4263a77256ae 88 }
bogdanm 20:4263a77256ae 89