david dicarlo / mbed-src-FLL48

mbed library sources: Modified to operate FRDM-KL25Z at 48MHz from internal 32kHz oscillator (nothing else changed).

Fork of mbed-src by mbed official

The only file that changed is: mbed-src-FLL48/targets/cmsis/TARGET_Freescale/TARGET_KL25Z/system_MKL25Z4.h

targets/hal/TARGET_NXP/TARGET_LPC11CXX/gpio_irq_api.c@20:4263a77256ae, 2013-09-10 (annotated)

Committer:
bogdanm
Date:
Tue Sep 10 15:14:19 2013 +0300
Revision:
20:4263a77256ae
Sync with git revision 171dda705c947bf910926a0b73d6a4797802554d

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 20:4263a77256ae 1 /* mbed Microcontroller Library
bogdanm 20:4263a77256ae 2 * Copyright (c) 2006-2013 ARM Limited
bogdanm 20:4263a77256ae 3 *
bogdanm 20:4263a77256ae 4 * Licensed under the Apache License, Version 2.0 (the "License");
bogdanm 20:4263a77256ae 5 * you may not use this file except in compliance with the License.
bogdanm 20:4263a77256ae 6 * You may obtain a copy of the License at
bogdanm 20:4263a77256ae 7 *
bogdanm 20:4263a77256ae 8 * http://www.apache.org/licenses/LICENSE-2.0
bogdanm 20:4263a77256ae 9 *
bogdanm 20:4263a77256ae 10 * Unless required by applicable law or agreed to in writing, software
bogdanm 20:4263a77256ae 11 * distributed under the License is distributed on an "AS IS" BASIS,
bogdanm 20:4263a77256ae 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
bogdanm 20:4263a77256ae 13 * See the License for the specific language governing permissions and
bogdanm 20:4263a77256ae 14 * limitations under the License.
bogdanm 20:4263a77256ae 15 */
bogdanm 20:4263a77256ae 16 #include <stddef.h>
bogdanm 20:4263a77256ae 17 #include "cmsis.h"
bogdanm 20:4263a77256ae 18 #include "gpio_irq_api.h"
bogdanm 20:4263a77256ae 19 #include "error.h"
bogdanm 20:4263a77256ae 20 #include "gpio_api.h"
bogdanm 20:4263a77256ae 21
bogdanm 20:4263a77256ae 22 // The chip is capable of 4 external interrupts.
bogdanm 20:4263a77256ae 23 #define CHANNEL_NUM 4
bogdanm 20:4263a77256ae 24
bogdanm 20:4263a77256ae 25 static uint32_t channel_ids[CHANNEL_NUM] = {0};
bogdanm 20:4263a77256ae 26 static gpio_irq_handler irq_handler;
bogdanm 20:4263a77256ae 27 static PinName pin_names[CHANNEL_NUM] = {};
bogdanm 20:4263a77256ae 28 static uint8_t trigger_events[CHANNEL_NUM] = {};
bogdanm 20:4263a77256ae 29
bogdanm 20:4263a77256ae 30 static inline void handle_interrupt_in(uint32_t channel) {
bogdanm 20:4263a77256ae 31 // Find out whether the interrupt has been triggered by a high or low value...
bogdanm 20:4263a77256ae 32 // As the LPC1114 doesn't have a specific register for this, we'll just have to read
bogdanm 20:4263a77256ae 33 // the level of the pin as if it were just a normal input...
bogdanm 20:4263a77256ae 34
bogdanm 20:4263a77256ae 35 // Get the number of the pin being used and the port typedef
bogdanm 20:4263a77256ae 36 LPC_GPIO_TypeDef *port_reg = ((LPC_GPIO_TypeDef *) (LPC_GPIO0_BASE + (((pin_names[channel] & 0xF000) >> PORT_SHIFT) * 0x10000)));
bogdanm 20:4263a77256ae 37 uint8_t pin_num = (pin_names[channel] & (0x0f << PIN_SHIFT)) >> PIN_SHIFT;
bogdanm 20:4263a77256ae 38 uint8_t trigger_event = trigger_events[channel];
bogdanm 20:4263a77256ae 39
bogdanm 20:4263a77256ae 40 if (trigger_event == 1)
bogdanm 20:4263a77256ae 41 irq_handler(channel_ids[channel], IRQ_RISE);
bogdanm 20:4263a77256ae 42 else if (trigger_event == 2)
bogdanm 20:4263a77256ae 43 irq_handler(channel_ids[channel], IRQ_FALL);
bogdanm 20:4263a77256ae 44 else {
bogdanm 20:4263a77256ae 45 // In order to get an idea of which kind of event it is,
bogdanm 20:4263a77256ae 46 // We need to read the logic level of the pin...
bogdanm 20:4263a77256ae 47
bogdanm 20:4263a77256ae 48 uint8_t logic = (port_reg->DATA & (1 << pin_num)) >> pin_num;
bogdanm 20:4263a77256ae 49
bogdanm 20:4263a77256ae 50 if (logic == 1)
bogdanm 20:4263a77256ae 51 irq_handler(channel_ids[channel], IRQ_RISE);
bogdanm 20:4263a77256ae 52 else
bogdanm 20:4263a77256ae 53 irq_handler(channel_ids[channel], IRQ_FALL);
bogdanm 20:4263a77256ae 54 }
bogdanm 20:4263a77256ae 55
bogdanm 20:4263a77256ae 56 // Clear the interrupt...
bogdanm 20:4263a77256ae 57 port_reg->IC |= 1 << pin_num;
bogdanm 20:4263a77256ae 58 }
bogdanm 20:4263a77256ae 59
bogdanm 20:4263a77256ae 60 void gpio_irq0(void) {handle_interrupt_in(0);}
bogdanm 20:4263a77256ae 61 void gpio_irq1(void) {handle_interrupt_in(1);}
bogdanm 20:4263a77256ae 62 void gpio_irq2(void) {handle_interrupt_in(2);}
bogdanm 20:4263a77256ae 63 void gpio_irq3(void) {handle_interrupt_in(3);}
bogdanm 20:4263a77256ae 64
bogdanm 20:4263a77256ae 65 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
bogdanm 20:4263a77256ae 66 if (pin == NC) return -1;
bogdanm 20:4263a77256ae 67
bogdanm 20:4263a77256ae 68 // Firstly, we'll put some data in *obj so we can keep track of stuff.
bogdanm 20:4263a77256ae 69 obj->pin = pin;
bogdanm 20:4263a77256ae 70
bogdanm 20:4263a77256ae 71 // Set the handler to be the pointer at the top...
bogdanm 20:4263a77256ae 72 irq_handler = handler;
bogdanm 20:4263a77256ae 73
bogdanm 20:4263a77256ae 74 // Which port are we using?
bogdanm 20:4263a77256ae 75 int channel;
bogdanm 20:4263a77256ae 76 uint32_t port_reg = (LPC_GPIO0_BASE + (((pin & 0xF000) >> PORT_SHIFT) * 0x10000));
bogdanm 20:4263a77256ae 77
bogdanm 20:4263a77256ae 78 switch (port_reg) {
bogdanm 20:4263a77256ae 79 case LPC_GPIO0_BASE:
bogdanm 20:4263a77256ae 80 NVIC_SetVector(EINT0_IRQn, (uint32_t)gpio_irq0);
bogdanm 20:4263a77256ae 81 NVIC_EnableIRQ(EINT0_IRQn);
bogdanm 20:4263a77256ae 82 channel = 0;
bogdanm 20:4263a77256ae 83 break;
bogdanm 20:4263a77256ae 84 case LPC_GPIO1_BASE:
bogdanm 20:4263a77256ae 85 NVIC_SetVector(EINT1_IRQn, (uint32_t)gpio_irq1);
bogdanm 20:4263a77256ae 86 NVIC_EnableIRQ(EINT1_IRQn);
bogdanm 20:4263a77256ae 87 channel = 1;
bogdanm 20:4263a77256ae 88 break;
bogdanm 20:4263a77256ae 89 case LPC_GPIO2_BASE:
bogdanm 20:4263a77256ae 90 NVIC_SetVector(EINT2_IRQn, (uint32_t)gpio_irq2);
bogdanm 20:4263a77256ae 91 NVIC_EnableIRQ(EINT2_IRQn);
bogdanm 20:4263a77256ae 92 channel = 2;
bogdanm 20:4263a77256ae 93 break;
bogdanm 20:4263a77256ae 94 case LPC_GPIO3_BASE:
bogdanm 20:4263a77256ae 95 NVIC_SetVector(EINT3_IRQn, (uint32_t)gpio_irq3);
bogdanm 20:4263a77256ae 96 NVIC_EnableIRQ(EINT3_IRQn);
bogdanm 20:4263a77256ae 97 channel = 3;
bogdanm 20:4263a77256ae 98 break;
bogdanm 20:4263a77256ae 99 default:
bogdanm 20:4263a77256ae 100 channel = -1;
bogdanm 20:4263a77256ae 101 error("Invalid interrupt choice.");
bogdanm 20:4263a77256ae 102 break;
bogdanm 20:4263a77256ae 103 }
bogdanm 20:4263a77256ae 104
bogdanm 20:4263a77256ae 105 channel_ids[channel] = id;
bogdanm 20:4263a77256ae 106 pin_names[channel] = pin;
bogdanm 20:4263a77256ae 107 obj->ch = channel;
bogdanm 20:4263a77256ae 108 return 0;
bogdanm 20:4263a77256ae 109 }
bogdanm 20:4263a77256ae 110
bogdanm 20:4263a77256ae 111 void gpio_irq_free(gpio_irq_t *obj) {
bogdanm 20:4263a77256ae 112 channel_ids[obj->ch] = 0;
bogdanm 20:4263a77256ae 113 }
bogdanm 20:4263a77256ae 114
bogdanm 20:4263a77256ae 115 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
bogdanm 20:4263a77256ae 116 // Firstly, check if there is an existing event stored...
bogdanm 20:4263a77256ae 117
bogdanm 20:4263a77256ae 118 LPC_GPIO_TypeDef *port_reg = ((LPC_GPIO_TypeDef *) (LPC_GPIO0_BASE + (((obj->pin & 0xF000) >> PORT_SHIFT) * 0x10000)));
bogdanm 20:4263a77256ae 119
bogdanm 20:4263a77256ae 120 // Need to get the pin number of the pin, not the value of the enum
bogdanm 20:4263a77256ae 121 uint8_t pin_num = (obj->pin & (0x0f << PIN_SHIFT)) >> PIN_SHIFT;
bogdanm 20:4263a77256ae 122
bogdanm 20:4263a77256ae 123
bogdanm 20:4263a77256ae 124 if (trigger_events[obj->ch] != 0) {
bogdanm 20:4263a77256ae 125 // We have an event.
bogdanm 20:4263a77256ae 126 // Enable both edge interrupts.
bogdanm 20:4263a77256ae 127
bogdanm 20:4263a77256ae 128 if (enable) {
bogdanm 20:4263a77256ae 129 trigger_events[obj->ch] = 3;
bogdanm 20:4263a77256ae 130 port_reg->IBE |= 1 << pin_num;
bogdanm 20:4263a77256ae 131 port_reg->IE |= 1 << pin_num;
bogdanm 20:4263a77256ae 132 }
bogdanm 20:4263a77256ae 133 else {
bogdanm 20:4263a77256ae 134 // These all need to be opposite, to reenable the other one.
bogdanm 20:4263a77256ae 135 trigger_events[obj->ch] = event == IRQ_RISE ? 2 : 1;
bogdanm 20:4263a77256ae 136
bogdanm 20:4263a77256ae 137 port_reg->IBE &= ~(1 << pin_num);
bogdanm 20:4263a77256ae 138
bogdanm 20:4263a77256ae 139 if (event == IRQ_RISE)
bogdanm 20:4263a77256ae 140 port_reg->IEV &= ~(1 << pin_num);
bogdanm 20:4263a77256ae 141 else
bogdanm 20:4263a77256ae 142 port_reg->IEV |= 1 << pin_num;
bogdanm 20:4263a77256ae 143
bogdanm 20:4263a77256ae 144 port_reg->IE |= 1 << pin_num;
bogdanm 20:4263a77256ae 145 }
bogdanm 20:4263a77256ae 146 }
bogdanm 20:4263a77256ae 147 else {
bogdanm 20:4263a77256ae 148 if (enable) {
bogdanm 20:4263a77256ae 149 trigger_events[obj->ch] = event == IRQ_RISE ? 1 : 2;
bogdanm 20:4263a77256ae 150 port_reg->IE |= 1 << pin_num;
bogdanm 20:4263a77256ae 151 }
bogdanm 20:4263a77256ae 152 // One edge
bogdanm 20:4263a77256ae 153 port_reg->IBE &= ~(1 << pin_num);
bogdanm 20:4263a77256ae 154 // Rising/falling?
bogdanm 20:4263a77256ae 155 if (event == IRQ_RISE)
bogdanm 20:4263a77256ae 156 port_reg->IEV |= 1 << pin_num;
bogdanm 20:4263a77256ae 157 else
bogdanm 20:4263a77256ae 158 port_reg->IEV &= ~(1 << pin_num);
bogdanm 20:4263a77256ae 159 }
bogdanm 20:4263a77256ae 160
bogdanm 20:4263a77256ae 161 // Clear
bogdanm 20:4263a77256ae 162 port_reg->IC |= 1 << pin_num;
bogdanm 20:4263a77256ae 163
bogdanm 20:4263a77256ae 164 // Make it edge sensitive.
bogdanm 20:4263a77256ae 165 port_reg->IS &= ~(1 << pin_num);
bogdanm 20:4263a77256ae 166 }