david dicarlo / mbed-src-FLL48

mbed library sources: Modified to operate FRDM-KL25Z at 48MHz from internal 32kHz oscillator (nothing else changed).

Fork of mbed-src by mbed official

The only file that changed is: mbed-src-FLL48/targets/cmsis/TARGET_Freescale/TARGET_KL25Z/system_MKL25Z4.h

targets/hal/TARGET_Freescale/TARGET_KL05Z/rtc_api.c@20:4263a77256ae, 2013-09-10 (annotated)

Committer:
bogdanm
Date:
Tue Sep 10 15:14:19 2013 +0300
Revision:
20:4263a77256ae
Sync with git revision 171dda705c947bf910926a0b73d6a4797802554d

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 20:4263a77256ae 1 /* mbed Microcontroller Library
bogdanm 20:4263a77256ae 2 * Copyright (c) 2006-2013 ARM Limited
bogdanm 20:4263a77256ae 3 *
bogdanm 20:4263a77256ae 4 * Licensed under the Apache License, Version 2.0 (the "License");
bogdanm 20:4263a77256ae 5 * you may not use this file except in compliance with the License.
bogdanm 20:4263a77256ae 6 * You may obtain a copy of the License at
bogdanm 20:4263a77256ae 7 *
bogdanm 20:4263a77256ae 8 * http://www.apache.org/licenses/LICENSE-2.0
bogdanm 20:4263a77256ae 9 *
bogdanm 20:4263a77256ae 10 * Unless required by applicable law or agreed to in writing, software
bogdanm 20:4263a77256ae 11 * distributed under the License is distributed on an "AS IS" BASIS,
bogdanm 20:4263a77256ae 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
bogdanm 20:4263a77256ae 13 * See the License for the specific language governing permissions and
bogdanm 20:4263a77256ae 14 * limitations under the License.
bogdanm 20:4263a77256ae 15 */
bogdanm 20:4263a77256ae 16 #include "rtc_api.h"
bogdanm 20:4263a77256ae 17
bogdanm 20:4263a77256ae 18 static void init(void) {
bogdanm 20:4263a77256ae 19 // enable RTC clock
bogdanm 20:4263a77256ae 20 SIM->SCGC6 |= SIM_SCGC6_RTC_MASK;
bogdanm 20:4263a77256ae 21
bogdanm 20:4263a77256ae 22 // select OSC32 as RTC clock source
bogdanm 20:4263a77256ae 23 SIM->SOPT1 &= ~SIM_SOPT1_OSC32KSEL_MASK;
bogdanm 20:4263a77256ae 24
bogdanm 20:4263a77256ae 25 }
bogdanm 20:4263a77256ae 26
bogdanm 20:4263a77256ae 27 void rtc_init(void) {
bogdanm 20:4263a77256ae 28 uint32_t i;
bogdanm 20:4263a77256ae 29 init();
bogdanm 20:4263a77256ae 30
bogdanm 20:4263a77256ae 31 //Configure the TSR. default value: 1
bogdanm 20:4263a77256ae 32 RTC->TSR = 1;
bogdanm 20:4263a77256ae 33
bogdanm 20:4263a77256ae 34 RTC->CR |= RTC_CR_OSCE_MASK;
bogdanm 20:4263a77256ae 35
bogdanm 20:4263a77256ae 36 //delay for OSCE stabilization
bogdanm 20:4263a77256ae 37 for(i=0; i<0x1000; i++) __NOP();
bogdanm 20:4263a77256ae 38
bogdanm 20:4263a77256ae 39 // enable counter
bogdanm 20:4263a77256ae 40 RTC->SR |= RTC_SR_TCE_MASK;
bogdanm 20:4263a77256ae 41 }
bogdanm 20:4263a77256ae 42
bogdanm 20:4263a77256ae 43 void rtc_free(void) {
bogdanm 20:4263a77256ae 44 // [TODO]
bogdanm 20:4263a77256ae 45 }
bogdanm 20:4263a77256ae 46
bogdanm 20:4263a77256ae 47
bogdanm 20:4263a77256ae 48 int rtc_isenabled(void) {
bogdanm 20:4263a77256ae 49 // even if the RTC module is enabled,
bogdanm 20:4263a77256ae 50 // as we use RTC_CLKIN and an external clock,
bogdanm 20:4263a77256ae 51 // we need to reconfigure the pins. That is why we
bogdanm 20:4263a77256ae 52 // call init() if the rtc is enabled
bogdanm 20:4263a77256ae 53
bogdanm 20:4263a77256ae 54 // if RTC not enabled return 0
bogdanm 20:4263a77256ae 55 SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK;
bogdanm 20:4263a77256ae 56 SIM->SCGC6 |= SIM_SCGC6_RTC_MASK;
bogdanm 20:4263a77256ae 57 if ((RTC->SR & RTC_SR_TCE_MASK) == 0) {
bogdanm 20:4263a77256ae 58 return 0;
bogdanm 20:4263a77256ae 59 }
bogdanm 20:4263a77256ae 60
bogdanm 20:4263a77256ae 61 init();
bogdanm 20:4263a77256ae 62 return 1;
bogdanm 20:4263a77256ae 63 }
bogdanm 20:4263a77256ae 64
bogdanm 20:4263a77256ae 65 time_t rtc_read(void) {
bogdanm 20:4263a77256ae 66 return RTC->TSR;
bogdanm 20:4263a77256ae 67 }
bogdanm 20:4263a77256ae 68
bogdanm 20:4263a77256ae 69 void rtc_write(time_t t) {
bogdanm 20:4263a77256ae 70 // disable counter
bogdanm 20:4263a77256ae 71 RTC->SR &= ~RTC_SR_TCE_MASK;
bogdanm 20:4263a77256ae 72
bogdanm 20:4263a77256ae 73 // we do not write 0 into TSR
bogdanm 20:4263a77256ae 74 // to avoid invalid time
bogdanm 20:4263a77256ae 75 if (t == 0) {
bogdanm 20:4263a77256ae 76 t = 1;
bogdanm 20:4263a77256ae 77 }
bogdanm 20:4263a77256ae 78
bogdanm 20:4263a77256ae 79 // write seconds
bogdanm 20:4263a77256ae 80 RTC->TSR = t;
bogdanm 20:4263a77256ae 81
bogdanm 20:4263a77256ae 82 // re-enable counter
bogdanm 20:4263a77256ae 83 RTC->SR |= RTC_SR_TCE_MASK;
bogdanm 20:4263a77256ae 84 }