mbed library sources: Modified to operate FRDM-KL25Z at 48MHz from internal 32kHz oscillator (nothing else changed).
Fork of mbed-src by
The only file that changed is: mbed-src-FLL48/targets/cmsis/TARGET_Freescale/TARGET_KL25Z/system_MKL25Z4.h
targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC810/system_LPC8xx.c@20:4263a77256ae, 2013-09-10 (annotated)
- Committer:
- bogdanm
- Date:
- Tue Sep 10 15:14:19 2013 +0300
- Revision:
- 20:4263a77256ae
Sync with git revision 171dda705c947bf910926a0b73d6a4797802554d
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
bogdanm | 20:4263a77256ae | 1 | /****************************************************************************** |
bogdanm | 20:4263a77256ae | 2 | * @file: system_LPC8xx.c |
bogdanm | 20:4263a77256ae | 3 | * @purpose: CMSIS Cortex-M0+ Device Peripheral Access Layer Source File |
bogdanm | 20:4263a77256ae | 4 | * for the NXP LPC8xx Device Series |
bogdanm | 20:4263a77256ae | 5 | * @version: V1.0 |
bogdanm | 20:4263a77256ae | 6 | * @date: 16. Aug. 2012 |
bogdanm | 20:4263a77256ae | 7 | *---------------------------------------------------------------------------- |
bogdanm | 20:4263a77256ae | 8 | * |
bogdanm | 20:4263a77256ae | 9 | * Copyright (C) 2012 ARM Limited. All rights reserved. |
bogdanm | 20:4263a77256ae | 10 | * |
bogdanm | 20:4263a77256ae | 11 | * ARM Limited (ARM) is supplying this software for use with Cortex-M0+ |
bogdanm | 20:4263a77256ae | 12 | * processor based microcontrollers. This file can be freely distributed |
bogdanm | 20:4263a77256ae | 13 | * within development tools that are supporting such ARM based processors. |
bogdanm | 20:4263a77256ae | 14 | * |
bogdanm | 20:4263a77256ae | 15 | * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
bogdanm | 20:4263a77256ae | 16 | * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
bogdanm | 20:4263a77256ae | 17 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
bogdanm | 20:4263a77256ae | 18 | * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
bogdanm | 20:4263a77256ae | 19 | * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
bogdanm | 20:4263a77256ae | 20 | * |
bogdanm | 20:4263a77256ae | 21 | ******************************************************************************/ |
bogdanm | 20:4263a77256ae | 22 | #include <stdint.h> |
bogdanm | 20:4263a77256ae | 23 | #include "LPC8xx.h" |
bogdanm | 20:4263a77256ae | 24 | |
bogdanm | 20:4263a77256ae | 25 | /* |
bogdanm | 20:4263a77256ae | 26 | //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ |
bogdanm | 20:4263a77256ae | 27 | */ |
bogdanm | 20:4263a77256ae | 28 | |
bogdanm | 20:4263a77256ae | 29 | /*--------------------- Clock Configuration ---------------------------------- |
bogdanm | 20:4263a77256ae | 30 | // |
bogdanm | 20:4263a77256ae | 31 | // <e> Clock Configuration |
bogdanm | 20:4263a77256ae | 32 | // <h> System Oscillator Control Register (SYSOSCCTRL) |
bogdanm | 20:4263a77256ae | 33 | // <o1.0> BYPASS: System Oscillator Bypass Enable |
bogdanm | 20:4263a77256ae | 34 | // <i> If enabled then PLL input (sys_osc_clk) is fed |
bogdanm | 20:4263a77256ae | 35 | // <i> directly from XTALIN and XTALOUT pins. |
bogdanm | 20:4263a77256ae | 36 | // <o1.9> FREQRANGE: System Oscillator Frequency Range |
bogdanm | 20:4263a77256ae | 37 | // <i> Determines frequency range for Low-power oscillator. |
bogdanm | 20:4263a77256ae | 38 | // <0=> 1 - 20 MHz |
bogdanm | 20:4263a77256ae | 39 | // <1=> 15 - 25 MHz |
bogdanm | 20:4263a77256ae | 40 | // </h> |
bogdanm | 20:4263a77256ae | 41 | // |
bogdanm | 20:4263a77256ae | 42 | // <h> Watchdog Oscillator Control Register (WDTOSCCTRL) |
bogdanm | 20:4263a77256ae | 43 | // <o2.0..4> DIVSEL: Select Divider for Fclkana |
bogdanm | 20:4263a77256ae | 44 | // <i> wdt_osc_clk = Fclkana/ (2 * (1 + DIVSEL)) |
bogdanm | 20:4263a77256ae | 45 | // <0-31> |
bogdanm | 20:4263a77256ae | 46 | // <o2.5..8> FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana) |
bogdanm | 20:4263a77256ae | 47 | // <0=> Undefined |
bogdanm | 20:4263a77256ae | 48 | // <1=> 0.5 MHz |
bogdanm | 20:4263a77256ae | 49 | // <2=> 0.8 MHz |
bogdanm | 20:4263a77256ae | 50 | // <3=> 1.1 MHz |
bogdanm | 20:4263a77256ae | 51 | // <4=> 1.4 MHz |
bogdanm | 20:4263a77256ae | 52 | // <5=> 1.6 MHz |
bogdanm | 20:4263a77256ae | 53 | // <6=> 1.8 MHz |
bogdanm | 20:4263a77256ae | 54 | // <7=> 2.0 MHz |
bogdanm | 20:4263a77256ae | 55 | // <8=> 2.2 MHz |
bogdanm | 20:4263a77256ae | 56 | // <9=> 2.4 MHz |
bogdanm | 20:4263a77256ae | 57 | // <10=> 2.6 MHz |
bogdanm | 20:4263a77256ae | 58 | // <11=> 2.7 MHz |
bogdanm | 20:4263a77256ae | 59 | // <12=> 2.9 MHz |
bogdanm | 20:4263a77256ae | 60 | // <13=> 3.1 MHz |
bogdanm | 20:4263a77256ae | 61 | // <14=> 3.2 MHz |
bogdanm | 20:4263a77256ae | 62 | // <15=> 3.4 MHz |
bogdanm | 20:4263a77256ae | 63 | // </h> |
bogdanm | 20:4263a77256ae | 64 | // |
bogdanm | 20:4263a77256ae | 65 | // <h> System PLL Control Register (SYSPLLCTRL) |
bogdanm | 20:4263a77256ae | 66 | // <i> F_clkout = M * F_clkin = F_CCO / (2 * P) |
bogdanm | 20:4263a77256ae | 67 | // <i> F_clkin must be in the range of 10 MHz to 25 MHz |
bogdanm | 20:4263a77256ae | 68 | // <i> F_CCO must be in the range of 156 MHz to 320 MHz |
bogdanm | 20:4263a77256ae | 69 | // <o3.0..4> MSEL: Feedback Divider Selection |
bogdanm | 20:4263a77256ae | 70 | // <i> M = MSEL + 1 |
bogdanm | 20:4263a77256ae | 71 | // <0-31> |
bogdanm | 20:4263a77256ae | 72 | // <o3.5..6> PSEL: Post Divider Selection |
bogdanm | 20:4263a77256ae | 73 | // <0=> P = 1 |
bogdanm | 20:4263a77256ae | 74 | // <1=> P = 2 |
bogdanm | 20:4263a77256ae | 75 | // <2=> P = 4 |
bogdanm | 20:4263a77256ae | 76 | // <3=> P = 8 |
bogdanm | 20:4263a77256ae | 77 | // </h> |
bogdanm | 20:4263a77256ae | 78 | // |
bogdanm | 20:4263a77256ae | 79 | // <h> System PLL Clock Source Select Register (SYSPLLCLKSEL) |
bogdanm | 20:4263a77256ae | 80 | // <o4.0..1> SEL: System PLL Clock Source |
bogdanm | 20:4263a77256ae | 81 | // <0=> IRC Oscillator |
bogdanm | 20:4263a77256ae | 82 | // <1=> System Oscillator |
bogdanm | 20:4263a77256ae | 83 | // <2=> Reserved |
bogdanm | 20:4263a77256ae | 84 | // <3=> CLKIN pin |
bogdanm | 20:4263a77256ae | 85 | // </h> |
bogdanm | 20:4263a77256ae | 86 | // |
bogdanm | 20:4263a77256ae | 87 | // <h> Main Clock Source Select Register (MAINCLKSEL) |
bogdanm | 20:4263a77256ae | 88 | // <o5.0..1> SEL: Clock Source for Main Clock |
bogdanm | 20:4263a77256ae | 89 | // <0=> IRC Oscillator |
bogdanm | 20:4263a77256ae | 90 | // <1=> Input Clock to System PLL |
bogdanm | 20:4263a77256ae | 91 | // <2=> WDT Oscillator |
bogdanm | 20:4263a77256ae | 92 | // <3=> System PLL Clock Out |
bogdanm | 20:4263a77256ae | 93 | // </h> |
bogdanm | 20:4263a77256ae | 94 | // |
bogdanm | 20:4263a77256ae | 95 | // <h> System AHB Clock Divider Register (SYSAHBCLKDIV) |
bogdanm | 20:4263a77256ae | 96 | // <o6.0..7> DIV: System AHB Clock Divider |
bogdanm | 20:4263a77256ae | 97 | // <i> Divides main clock to provide system clock to core, memories, and peripherals. |
bogdanm | 20:4263a77256ae | 98 | // <i> 0 = is disabled |
bogdanm | 20:4263a77256ae | 99 | // <0-255> |
bogdanm | 20:4263a77256ae | 100 | // </h> |
bogdanm | 20:4263a77256ae | 101 | // </e> |
bogdanm | 20:4263a77256ae | 102 | */ |
bogdanm | 20:4263a77256ae | 103 | #define CLOCK_SETUP 1 |
bogdanm | 20:4263a77256ae | 104 | #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000 |
bogdanm | 20:4263a77256ae | 105 | #define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000 |
bogdanm | 20:4263a77256ae | 106 | #define SYSPLLCTRL_Val 0x00000041 // Reset: 0x000 |
bogdanm | 20:4263a77256ae | 107 | #define SYSPLLCLKSEL_Val 0x00000000 // Reset: 0x000 |
bogdanm | 20:4263a77256ae | 108 | #define MAINCLKSEL_Val 0x00000003 // Reset: 0x000 |
bogdanm | 20:4263a77256ae | 109 | #define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001 |
bogdanm | 20:4263a77256ae | 110 | |
bogdanm | 20:4263a77256ae | 111 | /* |
bogdanm | 20:4263a77256ae | 112 | //-------- <<< end of configuration section >>> ------------------------------ |
bogdanm | 20:4263a77256ae | 113 | */ |
bogdanm | 20:4263a77256ae | 114 | |
bogdanm | 20:4263a77256ae | 115 | /*---------------------------------------------------------------------------- |
bogdanm | 20:4263a77256ae | 116 | Check the register settings |
bogdanm | 20:4263a77256ae | 117 | *----------------------------------------------------------------------------*/ |
bogdanm | 20:4263a77256ae | 118 | #define CHECK_RANGE(val, min, max) ((val < min) || (val > max)) |
bogdanm | 20:4263a77256ae | 119 | #define CHECK_RSVD(val, mask) (val & mask) |
bogdanm | 20:4263a77256ae | 120 | |
bogdanm | 20:4263a77256ae | 121 | /* Clock Configuration -------------------------------------------------------*/ |
bogdanm | 20:4263a77256ae | 122 | #if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003)) |
bogdanm | 20:4263a77256ae | 123 | #error "SYSOSCCTRL: Invalid values of reserved bits!" |
bogdanm | 20:4263a77256ae | 124 | #endif |
bogdanm | 20:4263a77256ae | 125 | |
bogdanm | 20:4263a77256ae | 126 | #if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF)) |
bogdanm | 20:4263a77256ae | 127 | #error "WDTOSCCTRL: Invalid values of reserved bits!" |
bogdanm | 20:4263a77256ae | 128 | #endif |
bogdanm | 20:4263a77256ae | 129 | |
bogdanm | 20:4263a77256ae | 130 | #if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 3)) |
bogdanm | 20:4263a77256ae | 131 | #error "SYSPLLCLKSEL: Value out of range!" |
bogdanm | 20:4263a77256ae | 132 | #endif |
bogdanm | 20:4263a77256ae | 133 | |
bogdanm | 20:4263a77256ae | 134 | #if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF)) |
bogdanm | 20:4263a77256ae | 135 | #error "SYSPLLCTRL: Invalid values of reserved bits!" |
bogdanm | 20:4263a77256ae | 136 | #endif |
bogdanm | 20:4263a77256ae | 137 | |
bogdanm | 20:4263a77256ae | 138 | #if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003)) |
bogdanm | 20:4263a77256ae | 139 | #error "MAINCLKSEL: Invalid values of reserved bits!" |
bogdanm | 20:4263a77256ae | 140 | #endif |
bogdanm | 20:4263a77256ae | 141 | |
bogdanm | 20:4263a77256ae | 142 | #if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255)) |
bogdanm | 20:4263a77256ae | 143 | #error "SYSAHBCLKDIV: Value out of range!" |
bogdanm | 20:4263a77256ae | 144 | #endif |
bogdanm | 20:4263a77256ae | 145 | |
bogdanm | 20:4263a77256ae | 146 | |
bogdanm | 20:4263a77256ae | 147 | /*---------------------------------------------------------------------------- |
bogdanm | 20:4263a77256ae | 148 | DEFINES |
bogdanm | 20:4263a77256ae | 149 | *----------------------------------------------------------------------------*/ |
bogdanm | 20:4263a77256ae | 150 | |
bogdanm | 20:4263a77256ae | 151 | /*---------------------------------------------------------------------------- |
bogdanm | 20:4263a77256ae | 152 | Define clocks |
bogdanm | 20:4263a77256ae | 153 | *----------------------------------------------------------------------------*/ |
bogdanm | 20:4263a77256ae | 154 | #define __XTAL (12000000UL) /* Oscillator frequency */ |
bogdanm | 20:4263a77256ae | 155 | #define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */ |
bogdanm | 20:4263a77256ae | 156 | #define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */ |
bogdanm | 20:4263a77256ae | 157 | #define __CLKIN_CLK (12000000UL) /* CLKIN pin frequency */ |
bogdanm | 20:4263a77256ae | 158 | |
bogdanm | 20:4263a77256ae | 159 | |
bogdanm | 20:4263a77256ae | 160 | #define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F) |
bogdanm | 20:4263a77256ae | 161 | #define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2) |
bogdanm | 20:4263a77256ae | 162 | |
bogdanm | 20:4263a77256ae | 163 | #if (CLOCK_SETUP) /* Clock Setup */ |
bogdanm | 20:4263a77256ae | 164 | #if (__FREQSEL == 0) |
bogdanm | 20:4263a77256ae | 165 | #define __WDT_OSC_CLK ( 0) /* undefined */ |
bogdanm | 20:4263a77256ae | 166 | #elif (__FREQSEL == 1) |
bogdanm | 20:4263a77256ae | 167 | #define __WDT_OSC_CLK ( 500000 / __DIVSEL) |
bogdanm | 20:4263a77256ae | 168 | #elif (__FREQSEL == 2) |
bogdanm | 20:4263a77256ae | 169 | #define __WDT_OSC_CLK ( 800000 / __DIVSEL) |
bogdanm | 20:4263a77256ae | 170 | #elif (__FREQSEL == 3) |
bogdanm | 20:4263a77256ae | 171 | #define __WDT_OSC_CLK (1100000 / __DIVSEL) |
bogdanm | 20:4263a77256ae | 172 | #elif (__FREQSEL == 4) |
bogdanm | 20:4263a77256ae | 173 | #define __WDT_OSC_CLK (1400000 / __DIVSEL) |
bogdanm | 20:4263a77256ae | 174 | #elif (__FREQSEL == 5) |
bogdanm | 20:4263a77256ae | 175 | #define __WDT_OSC_CLK (1600000 / __DIVSEL) |
bogdanm | 20:4263a77256ae | 176 | #elif (__FREQSEL == 6) |
bogdanm | 20:4263a77256ae | 177 | #define __WDT_OSC_CLK (1800000 / __DIVSEL) |
bogdanm | 20:4263a77256ae | 178 | #elif (__FREQSEL == 7) |
bogdanm | 20:4263a77256ae | 179 | #define __WDT_OSC_CLK (2000000 / __DIVSEL) |
bogdanm | 20:4263a77256ae | 180 | #elif (__FREQSEL == 8) |
bogdanm | 20:4263a77256ae | 181 | #define __WDT_OSC_CLK (2200000 / __DIVSEL) |
bogdanm | 20:4263a77256ae | 182 | #elif (__FREQSEL == 9) |
bogdanm | 20:4263a77256ae | 183 | #define __WDT_OSC_CLK (2400000 / __DIVSEL) |
bogdanm | 20:4263a77256ae | 184 | #elif (__FREQSEL == 10) |
bogdanm | 20:4263a77256ae | 185 | #define __WDT_OSC_CLK (2600000 / __DIVSEL) |
bogdanm | 20:4263a77256ae | 186 | #elif (__FREQSEL == 11) |
bogdanm | 20:4263a77256ae | 187 | #define __WDT_OSC_CLK (2700000 / __DIVSEL) |
bogdanm | 20:4263a77256ae | 188 | #elif (__FREQSEL == 12) |
bogdanm | 20:4263a77256ae | 189 | #define __WDT_OSC_CLK (2900000 / __DIVSEL) |
bogdanm | 20:4263a77256ae | 190 | #elif (__FREQSEL == 13) |
bogdanm | 20:4263a77256ae | 191 | #define __WDT_OSC_CLK (3100000 / __DIVSEL) |
bogdanm | 20:4263a77256ae | 192 | #elif (__FREQSEL == 14) |
bogdanm | 20:4263a77256ae | 193 | #define __WDT_OSC_CLK (3200000 / __DIVSEL) |
bogdanm | 20:4263a77256ae | 194 | #else |
bogdanm | 20:4263a77256ae | 195 | #define __WDT_OSC_CLK (3400000 / __DIVSEL) |
bogdanm | 20:4263a77256ae | 196 | #endif |
bogdanm | 20:4263a77256ae | 197 | |
bogdanm | 20:4263a77256ae | 198 | /* sys_pllclkin calculation */ |
bogdanm | 20:4263a77256ae | 199 | #if ((SYSPLLCLKSEL_Val & 0x03) == 0) |
bogdanm | 20:4263a77256ae | 200 | #define __SYS_PLLCLKIN (__IRC_OSC_CLK) |
bogdanm | 20:4263a77256ae | 201 | #elif ((SYSPLLCLKSEL_Val & 0x03) == 1) |
bogdanm | 20:4263a77256ae | 202 | #define __SYS_PLLCLKIN (__SYS_OSC_CLK) |
bogdanm | 20:4263a77256ae | 203 | #elif ((SYSPLLCLKSEL_Val & 0x03) == 3) |
bogdanm | 20:4263a77256ae | 204 | #define __SYS_PLLCLKIN (__CLKIN_CLK) |
bogdanm | 20:4263a77256ae | 205 | #else |
bogdanm | 20:4263a77256ae | 206 | #define __SYS_PLLCLKIN (0) |
bogdanm | 20:4263a77256ae | 207 | #endif |
bogdanm | 20:4263a77256ae | 208 | |
bogdanm | 20:4263a77256ae | 209 | #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1)) |
bogdanm | 20:4263a77256ae | 210 | |
bogdanm | 20:4263a77256ae | 211 | /* main clock calculation */ |
bogdanm | 20:4263a77256ae | 212 | #if ((MAINCLKSEL_Val & 0x03) == 0) |
bogdanm | 20:4263a77256ae | 213 | #define __MAIN_CLOCK (__IRC_OSC_CLK) |
bogdanm | 20:4263a77256ae | 214 | #elif ((MAINCLKSEL_Val & 0x03) == 1) |
bogdanm | 20:4263a77256ae | 215 | #define __MAIN_CLOCK (__SYS_PLLCLKIN) |
bogdanm | 20:4263a77256ae | 216 | #elif ((MAINCLKSEL_Val & 0x03) == 2) |
bogdanm | 20:4263a77256ae | 217 | #if (__FREQSEL == 0) |
bogdanm | 20:4263a77256ae | 218 | #error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!" |
bogdanm | 20:4263a77256ae | 219 | #else |
bogdanm | 20:4263a77256ae | 220 | #define __MAIN_CLOCK (__WDT_OSC_CLK) |
bogdanm | 20:4263a77256ae | 221 | #endif |
bogdanm | 20:4263a77256ae | 222 | #elif ((MAINCLKSEL_Val & 0x03) == 3) |
bogdanm | 20:4263a77256ae | 223 | #define __MAIN_CLOCK (__SYS_PLLCLKOUT) |
bogdanm | 20:4263a77256ae | 224 | #else |
bogdanm | 20:4263a77256ae | 225 | #define __MAIN_CLOCK (0) |
bogdanm | 20:4263a77256ae | 226 | #endif |
bogdanm | 20:4263a77256ae | 227 | |
bogdanm | 20:4263a77256ae | 228 | #define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val) |
bogdanm | 20:4263a77256ae | 229 | |
bogdanm | 20:4263a77256ae | 230 | #else |
bogdanm | 20:4263a77256ae | 231 | #define __SYSTEM_CLOCK (__IRC_OSC_CLK) |
bogdanm | 20:4263a77256ae | 232 | #endif // CLOCK_SETUP |
bogdanm | 20:4263a77256ae | 233 | |
bogdanm | 20:4263a77256ae | 234 | |
bogdanm | 20:4263a77256ae | 235 | /*---------------------------------------------------------------------------- |
bogdanm | 20:4263a77256ae | 236 | Clock Variable definitions |
bogdanm | 20:4263a77256ae | 237 | *----------------------------------------------------------------------------*/ |
bogdanm | 20:4263a77256ae | 238 | uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ |
bogdanm | 20:4263a77256ae | 239 | |
bogdanm | 20:4263a77256ae | 240 | |
bogdanm | 20:4263a77256ae | 241 | /*---------------------------------------------------------------------------- |
bogdanm | 20:4263a77256ae | 242 | Clock functions |
bogdanm | 20:4263a77256ae | 243 | *----------------------------------------------------------------------------*/ |
bogdanm | 20:4263a77256ae | 244 | void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ |
bogdanm | 20:4263a77256ae | 245 | { |
bogdanm | 20:4263a77256ae | 246 | uint32_t wdt_osc = 0; |
bogdanm | 20:4263a77256ae | 247 | |
bogdanm | 20:4263a77256ae | 248 | /* Determine clock frequency according to clock register values */ |
bogdanm | 20:4263a77256ae | 249 | switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) { |
bogdanm | 20:4263a77256ae | 250 | case 0: wdt_osc = 0; break; |
bogdanm | 20:4263a77256ae | 251 | case 1: wdt_osc = 500000; break; |
bogdanm | 20:4263a77256ae | 252 | case 2: wdt_osc = 800000; break; |
bogdanm | 20:4263a77256ae | 253 | case 3: wdt_osc = 1100000; break; |
bogdanm | 20:4263a77256ae | 254 | case 4: wdt_osc = 1400000; break; |
bogdanm | 20:4263a77256ae | 255 | case 5: wdt_osc = 1600000; break; |
bogdanm | 20:4263a77256ae | 256 | case 6: wdt_osc = 1800000; break; |
bogdanm | 20:4263a77256ae | 257 | case 7: wdt_osc = 2000000; break; |
bogdanm | 20:4263a77256ae | 258 | case 8: wdt_osc = 2200000; break; |
bogdanm | 20:4263a77256ae | 259 | case 9: wdt_osc = 2400000; break; |
bogdanm | 20:4263a77256ae | 260 | case 10: wdt_osc = 2600000; break; |
bogdanm | 20:4263a77256ae | 261 | case 11: wdt_osc = 2700000; break; |
bogdanm | 20:4263a77256ae | 262 | case 12: wdt_osc = 2900000; break; |
bogdanm | 20:4263a77256ae | 263 | case 13: wdt_osc = 3100000; break; |
bogdanm | 20:4263a77256ae | 264 | case 14: wdt_osc = 3200000; break; |
bogdanm | 20:4263a77256ae | 265 | case 15: wdt_osc = 3400000; break; |
bogdanm | 20:4263a77256ae | 266 | } |
bogdanm | 20:4263a77256ae | 267 | wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2; |
bogdanm | 20:4263a77256ae | 268 | |
bogdanm | 20:4263a77256ae | 269 | switch (LPC_SYSCON->MAINCLKSEL & 0x03) { |
bogdanm | 20:4263a77256ae | 270 | case 0: /* Internal RC oscillator */ |
bogdanm | 20:4263a77256ae | 271 | SystemCoreClock = __IRC_OSC_CLK; |
bogdanm | 20:4263a77256ae | 272 | break; |
bogdanm | 20:4263a77256ae | 273 | case 1: /* Input Clock to System PLL */ |
bogdanm | 20:4263a77256ae | 274 | switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) { |
bogdanm | 20:4263a77256ae | 275 | case 0: /* Internal RC oscillator */ |
bogdanm | 20:4263a77256ae | 276 | SystemCoreClock = __IRC_OSC_CLK; |
bogdanm | 20:4263a77256ae | 277 | break; |
bogdanm | 20:4263a77256ae | 278 | case 1: /* System oscillator */ |
bogdanm | 20:4263a77256ae | 279 | SystemCoreClock = __SYS_OSC_CLK; |
bogdanm | 20:4263a77256ae | 280 | break; |
bogdanm | 20:4263a77256ae | 281 | case 2: /* Reserved */ |
bogdanm | 20:4263a77256ae | 282 | SystemCoreClock = 0; |
bogdanm | 20:4263a77256ae | 283 | break; |
bogdanm | 20:4263a77256ae | 284 | case 3: /* CLKIN pin */ |
bogdanm | 20:4263a77256ae | 285 | SystemCoreClock = __CLKIN_CLK; |
bogdanm | 20:4263a77256ae | 286 | break; |
bogdanm | 20:4263a77256ae | 287 | } |
bogdanm | 20:4263a77256ae | 288 | break; |
bogdanm | 20:4263a77256ae | 289 | case 2: /* WDT Oscillator */ |
bogdanm | 20:4263a77256ae | 290 | SystemCoreClock = wdt_osc; |
bogdanm | 20:4263a77256ae | 291 | break; |
bogdanm | 20:4263a77256ae | 292 | case 3: /* System PLL Clock Out */ |
bogdanm | 20:4263a77256ae | 293 | switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) { |
bogdanm | 20:4263a77256ae | 294 | case 0: /* Internal RC oscillator */ |
bogdanm | 20:4263a77256ae | 295 | SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); |
bogdanm | 20:4263a77256ae | 296 | break; |
bogdanm | 20:4263a77256ae | 297 | case 1: /* System oscillator */ |
bogdanm | 20:4263a77256ae | 298 | SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); |
bogdanm | 20:4263a77256ae | 299 | break; |
bogdanm | 20:4263a77256ae | 300 | case 2: /* Reserved */ |
bogdanm | 20:4263a77256ae | 301 | SystemCoreClock = 0; |
bogdanm | 20:4263a77256ae | 302 | break; |
bogdanm | 20:4263a77256ae | 303 | case 3: /* CLKIN pin */ |
bogdanm | 20:4263a77256ae | 304 | SystemCoreClock = __CLKIN_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); |
bogdanm | 20:4263a77256ae | 305 | break; |
bogdanm | 20:4263a77256ae | 306 | } |
bogdanm | 20:4263a77256ae | 307 | break; |
bogdanm | 20:4263a77256ae | 308 | } |
bogdanm | 20:4263a77256ae | 309 | |
bogdanm | 20:4263a77256ae | 310 | SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV; |
bogdanm | 20:4263a77256ae | 311 | |
bogdanm | 20:4263a77256ae | 312 | } |
bogdanm | 20:4263a77256ae | 313 | |
bogdanm | 20:4263a77256ae | 314 | /** |
bogdanm | 20:4263a77256ae | 315 | * Initialize the system |
bogdanm | 20:4263a77256ae | 316 | * |
bogdanm | 20:4263a77256ae | 317 | * @param none |
bogdanm | 20:4263a77256ae | 318 | * @return none |
bogdanm | 20:4263a77256ae | 319 | * |
bogdanm | 20:4263a77256ae | 320 | * @brief Setup the microcontroller system. |
bogdanm | 20:4263a77256ae | 321 | * Initialize the System. |
bogdanm | 20:4263a77256ae | 322 | */ |
bogdanm | 20:4263a77256ae | 323 | void SystemInit (void) { |
bogdanm | 20:4263a77256ae | 324 | volatile uint32_t i; |
bogdanm | 20:4263a77256ae | 325 | |
bogdanm | 20:4263a77256ae | 326 | /* System clock to the IOCON & the SWM need to be enabled or |
bogdanm | 20:4263a77256ae | 327 | most of the I/O related peripherals won't work. */ |
bogdanm | 20:4263a77256ae | 328 | LPC_SYSCON->SYSAHBCLKCTRL |= ( (0x1 << 7) | (0x1 << 18) ); |
bogdanm | 20:4263a77256ae | 329 | |
bogdanm | 20:4263a77256ae | 330 | #if (CLOCK_SETUP) /* Clock Setup */ |
bogdanm | 20:4263a77256ae | 331 | |
bogdanm | 20:4263a77256ae | 332 | #if ((SYSPLLCLKSEL_Val & 0x03) == 1) |
bogdanm | 20:4263a77256ae | 333 | LPC_IOCON->PIO0_8 &= ~(0x3 << 3); |
bogdanm | 20:4263a77256ae | 334 | LPC_IOCON->PIO0_9 &= ~(0x3 << 3); |
bogdanm | 20:4263a77256ae | 335 | LPC_SWM->PINENABLE0 &= ~(0x3 << 4); |
bogdanm | 20:4263a77256ae | 336 | LPC_SYSCON->PDRUNCFG &= ~(0x1 << 5); /* Power-up System Osc */ |
bogdanm | 20:4263a77256ae | 337 | LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val; |
bogdanm | 20:4263a77256ae | 338 | for (i = 0; i < 200; i++) __NOP(); |
bogdanm | 20:4263a77256ae | 339 | #endif |
bogdanm | 20:4263a77256ae | 340 | #if ((SYSPLLCLKSEL_Val & 0x03) == 3) |
bogdanm | 20:4263a77256ae | 341 | LPC_IOCON->PIO0_1 &= ~(0x3 << 3); |
bogdanm | 20:4263a77256ae | 342 | LPC_SWM->PINENABLE0 &= ~(0x1 << 7); |
bogdanm | 20:4263a77256ae | 343 | for (i = 0; i < 200; i++) __NOP(); |
bogdanm | 20:4263a77256ae | 344 | #endif |
bogdanm | 20:4263a77256ae | 345 | |
bogdanm | 20:4263a77256ae | 346 | LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */ |
bogdanm | 20:4263a77256ae | 347 | LPC_SYSCON->SYSPLLCLKUEN = 0x01; /* Update Clock Source */ |
bogdanm | 20:4263a77256ae | 348 | while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */ |
bogdanm | 20:4263a77256ae | 349 | #if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */ |
bogdanm | 20:4263a77256ae | 350 | LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val; |
bogdanm | 20:4263a77256ae | 351 | LPC_SYSCON->PDRUNCFG &= ~(0x1 << 7); /* Power-up SYSPLL */ |
bogdanm | 20:4263a77256ae | 352 | while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */ |
bogdanm | 20:4263a77256ae | 353 | #endif |
bogdanm | 20:4263a77256ae | 354 | |
bogdanm | 20:4263a77256ae | 355 | #if (((MAINCLKSEL_Val & 0x03) == 2) ) |
bogdanm | 20:4263a77256ae | 356 | LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val; |
bogdanm | 20:4263a77256ae | 357 | LPC_SYSCON->PDRUNCFG &= ~(0x1 << 6); /* Power-up WDT Clock */ |
bogdanm | 20:4263a77256ae | 358 | for (i = 0; i < 200; i++) __NOP(); |
bogdanm | 20:4263a77256ae | 359 | #endif |
bogdanm | 20:4263a77256ae | 360 | |
bogdanm | 20:4263a77256ae | 361 | LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */ |
bogdanm | 20:4263a77256ae | 362 | LPC_SYSCON->MAINCLKUEN = 0x01; /* Update MCLK Clock Source */ |
bogdanm | 20:4263a77256ae | 363 | while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */ |
bogdanm | 20:4263a77256ae | 364 | |
bogdanm | 20:4263a77256ae | 365 | LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val; |
bogdanm | 20:4263a77256ae | 366 | #endif |
bogdanm | 20:4263a77256ae | 367 | } |