david dicarlo / mbed-src-FLL48

mbed library sources: Modified to operate FRDM-KL25Z at 48MHz from internal 32kHz oscillator (nothing else changed).

Fork of mbed-src by mbed official

The only file that changed is: mbed-src-FLL48/targets/cmsis/TARGET_Freescale/TARGET_KL25Z/system_MKL25Z4.h

targets/cmsis/TARGET_NXP/TARGET_LPC11XX/system_LPC11xx.c@20:4263a77256ae, 2013-09-10 (annotated)

Committer:
bogdanm
Date:
Tue Sep 10 15:14:19 2013 +0300
Revision:
20:4263a77256ae
Parent:
19:398f4c622e1b 
Sync with git revision 171dda705c947bf910926a0b73d6a4797802554d

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 19:398f4c622e1b 1 /**************************************************************************//**
bogdanm 19:398f4c622e1b 2 * @file system_LPC11xx.c
bogdanm 19:398f4c622e1b 3 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Source File
bogdanm 19:398f4c622e1b 4 * for the NXP LPC11xx/LPC11Cxx Devices
bogdanm 19:398f4c622e1b 5 * @version V1.10
bogdanm 19:398f4c622e1b 6 * @date 24. November 2010
bogdanm 19:398f4c622e1b 7 *
bogdanm 19:398f4c622e1b 8 * @note
bogdanm 19:398f4c622e1b 9 * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
bogdanm 19:398f4c622e1b 10 *
bogdanm 19:398f4c622e1b 11 * @par
bogdanm 19:398f4c622e1b 12 * ARM Limited (ARM) is supplying this software for use with Cortex-M
bogdanm 19:398f4c622e1b 13 * processor based microcontrollers. This file can be freely distributed
bogdanm 19:398f4c622e1b 14 * within development tools that are supporting such ARM based processors.
bogdanm 19:398f4c622e1b 15 *
bogdanm 19:398f4c622e1b 16 * @par
bogdanm 19:398f4c622e1b 17 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
bogdanm 19:398f4c622e1b 18 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
bogdanm 19:398f4c622e1b 19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
bogdanm 19:398f4c622e1b 20 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
bogdanm 19:398f4c622e1b 21 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
bogdanm 19:398f4c622e1b 22 *
bogdanm 19:398f4c622e1b 23 ******************************************************************************/
bogdanm 19:398f4c622e1b 24
bogdanm 19:398f4c622e1b 25
bogdanm 19:398f4c622e1b 26 #include <stdint.h>
bogdanm 19:398f4c622e1b 27 #include "LPC11xx.h"
bogdanm 19:398f4c622e1b 28
bogdanm 19:398f4c622e1b 29 /*
bogdanm 19:398f4c622e1b 30 //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
bogdanm 19:398f4c622e1b 31 */
bogdanm 19:398f4c622e1b 32
bogdanm 19:398f4c622e1b 33 /*--------------------- Clock Configuration ----------------------------------
bogdanm 19:398f4c622e1b 34 //
bogdanm 19:398f4c622e1b 35 // <e> Clock Configuration
bogdanm 19:398f4c622e1b 36 // <h> System Oscillator Control Register (SYSOSCCTRL)
bogdanm 19:398f4c622e1b 37 // <o1.0> BYPASS: System Oscillator Bypass Enable
bogdanm 19:398f4c622e1b 38 // <i> If enabled then PLL input (sys_osc_clk) is fed
bogdanm 19:398f4c622e1b 39 // <i> directly from XTALIN and XTALOUT pins.
bogdanm 19:398f4c622e1b 40 // <o1.9> FREQRANGE: System Oscillator Frequency Range
bogdanm 19:398f4c622e1b 41 // <i> Determines frequency range for Low-power oscillator.
bogdanm 19:398f4c622e1b 42 // <0=> 1 - 20 MHz
bogdanm 19:398f4c622e1b 43 // <1=> 15 - 25 MHz
bogdanm 19:398f4c622e1b 44 // </h>
bogdanm 19:398f4c622e1b 45 //
bogdanm 19:398f4c622e1b 46 // <h> Watchdog Oscillator Control Register (WDTOSCCTRL)
bogdanm 19:398f4c622e1b 47 // <o2.0..4> DIVSEL: Select Divider for Fclkana
bogdanm 19:398f4c622e1b 48 // <i> wdt_osc_clk = Fclkana/ (2 * (1 + DIVSEL))
bogdanm 19:398f4c622e1b 49 // <0-31>
bogdanm 19:398f4c622e1b 50 // <o2.5..8> FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana)
bogdanm 19:398f4c622e1b 51 // <0=> Undefined
bogdanm 19:398f4c622e1b 52 // <1=> 0.5 MHz
bogdanm 19:398f4c622e1b 53 // <2=> 0.8 MHz
bogdanm 19:398f4c622e1b 54 // <3=> 1.1 MHz
bogdanm 19:398f4c622e1b 55 // <4=> 1.4 MHz
bogdanm 19:398f4c622e1b 56 // <5=> 1.6 MHz
bogdanm 19:398f4c622e1b 57 // <6=> 1.8 MHz
bogdanm 19:398f4c622e1b 58 // <7=> 2.0 MHz
bogdanm 19:398f4c622e1b 59 // <8=> 2.2 MHz
bogdanm 19:398f4c622e1b 60 // <9=> 2.4 MHz
bogdanm 19:398f4c622e1b 61 // <10=> 2.6 MHz
bogdanm 19:398f4c622e1b 62 // <11=> 2.7 MHz
bogdanm 19:398f4c622e1b 63 // <12=> 2.9 MHz
bogdanm 19:398f4c622e1b 64 // <13=> 3.1 MHz
bogdanm 19:398f4c622e1b 65 // <14=> 3.2 MHz
bogdanm 19:398f4c622e1b 66 // <15=> 3.4 MHz
bogdanm 19:398f4c622e1b 67 // </h>
bogdanm 19:398f4c622e1b 68 //
bogdanm 19:398f4c622e1b 69 // <h> System PLL Control Register (SYSPLLCTRL)
bogdanm 19:398f4c622e1b 70 // <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
bogdanm 19:398f4c622e1b 71 // <i> F_clkin must be in the range of 10 MHz to 25 MHz
bogdanm 19:398f4c622e1b 72 // <i> F_CCO must be in the range of 156 MHz to 320 MHz
bogdanm 19:398f4c622e1b 73 // <o3.0..4> MSEL: Feedback Divider Selection
bogdanm 19:398f4c622e1b 74 // <i> M = MSEL + 1
bogdanm 19:398f4c622e1b 75 // <0-31>
bogdanm 19:398f4c622e1b 76 // <o3.5..6> PSEL: Post Divider Selection
bogdanm 19:398f4c622e1b 77 // <0=> P = 1
bogdanm 19:398f4c622e1b 78 // <1=> P = 2
bogdanm 19:398f4c622e1b 79 // <2=> P = 4
bogdanm 19:398f4c622e1b 80 // <3=> P = 8
bogdanm 19:398f4c622e1b 81 // </h>
bogdanm 19:398f4c622e1b 82 //
bogdanm 19:398f4c622e1b 83 // <h> System PLL Clock Source Select Register (SYSPLLCLKSEL)
bogdanm 19:398f4c622e1b 84 // <o4.0..1> SEL: System PLL Clock Source
bogdanm 19:398f4c622e1b 85 // <0=> IRC Oscillator
bogdanm 19:398f4c622e1b 86 // <1=> System Oscillator
bogdanm 19:398f4c622e1b 87 // <2=> Reserved
bogdanm 19:398f4c622e1b 88 // <3=> Reserved
bogdanm 19:398f4c622e1b 89 // </h>
bogdanm 19:398f4c622e1b 90 //
bogdanm 19:398f4c622e1b 91 // <h> Main Clock Source Select Register (MAINCLKSEL)
bogdanm 19:398f4c622e1b 92 // <o5.0..1> SEL: Clock Source for Main Clock
bogdanm 19:398f4c622e1b 93 // <0=> IRC Oscillator
bogdanm 19:398f4c622e1b 94 // <1=> Input Clock to System PLL
bogdanm 19:398f4c622e1b 95 // <2=> WDT Oscillator
bogdanm 19:398f4c622e1b 96 // <3=> System PLL Clock Out
bogdanm 19:398f4c622e1b 97 // </h>
bogdanm 19:398f4c622e1b 98 //
bogdanm 19:398f4c622e1b 99 // <h> System AHB Clock Divider Register (SYSAHBCLKDIV)
bogdanm 19:398f4c622e1b 100 // <o6.0..7> DIV: System AHB Clock Divider
bogdanm 19:398f4c622e1b 101 // <i> Divides main clock to provide system clock to core, memories, and peripherals.
bogdanm 19:398f4c622e1b 102 // <i> 0 = is disabled
bogdanm 19:398f4c622e1b 103 // <0-255>
bogdanm 19:398f4c622e1b 104 // </h>
bogdanm 19:398f4c622e1b 105 // </e>
bogdanm 19:398f4c622e1b 106 */
bogdanm 19:398f4c622e1b 107 #define CLOCK_SETUP 1
bogdanm 19:398f4c622e1b 108 #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
bogdanm 19:398f4c622e1b 109 #define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000
bogdanm 19:398f4c622e1b 110 #define SYSPLLCTRL_Val 0x00000023 // Reset: 0x000
bogdanm 20:4263a77256ae 111 #define SYSPLLCLKSEL_Val 0x00000000 // Reset: 0x000 // Define as using IRC
bogdanm 20:4263a77256ae 112 #define MAINCLKSEL_Val 0x00000003 // Reset: 0x000 // Define as using System PLL clock out
bogdanm 19:398f4c622e1b 113 #define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001
bogdanm 19:398f4c622e1b 114
bogdanm 19:398f4c622e1b 115 /*
bogdanm 19:398f4c622e1b 116 //-------- <<< end of configuration section >>> ------------------------------
bogdanm 19:398f4c622e1b 117 */
bogdanm 19:398f4c622e1b 118
bogdanm 19:398f4c622e1b 119 /*----------------------------------------------------------------------------
bogdanm 19:398f4c622e1b 120 Check the register settings
bogdanm 19:398f4c622e1b 121 *----------------------------------------------------------------------------*/
bogdanm 19:398f4c622e1b 122 #define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
bogdanm 19:398f4c622e1b 123 #define CHECK_RSVD(val, mask) (val & mask)
bogdanm 19:398f4c622e1b 124
bogdanm 19:398f4c622e1b 125 /* Clock Configuration -------------------------------------------------------*/
bogdanm 19:398f4c622e1b 126 #if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003))
bogdanm 19:398f4c622e1b 127 #error "SYSOSCCTRL: Invalid values of reserved bits!"
bogdanm 19:398f4c622e1b 128 #endif
bogdanm 19:398f4c622e1b 129
bogdanm 19:398f4c622e1b 130 #if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF))
bogdanm 19:398f4c622e1b 131 #error "WDTOSCCTRL: Invalid values of reserved bits!"
bogdanm 19:398f4c622e1b 132 #endif
bogdanm 19:398f4c622e1b 133
bogdanm 19:398f4c622e1b 134 #if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 2))
bogdanm 19:398f4c622e1b 135 #error "SYSPLLCLKSEL: Value out of range!"
bogdanm 19:398f4c622e1b 136 #endif
bogdanm 19:398f4c622e1b 137
bogdanm 19:398f4c622e1b 138 #if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF))
bogdanm 19:398f4c622e1b 139 #error "SYSPLLCTRL: Invalid values of reserved bits!"
bogdanm 19:398f4c622e1b 140 #endif
bogdanm 19:398f4c622e1b 141
bogdanm 19:398f4c622e1b 142 #if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003))
bogdanm 19:398f4c622e1b 143 #error "MAINCLKSEL: Invalid values of reserved bits!"
bogdanm 19:398f4c622e1b 144 #endif
bogdanm 19:398f4c622e1b 145
bogdanm 19:398f4c622e1b 146 #if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
bogdanm 19:398f4c622e1b 147 #error "SYSAHBCLKDIV: Value out of range!"
bogdanm 19:398f4c622e1b 148 #endif
bogdanm 19:398f4c622e1b 149
bogdanm 19:398f4c622e1b 150
bogdanm 19:398f4c622e1b 151 /*----------------------------------------------------------------------------
bogdanm 19:398f4c622e1b 152 DEFINES
bogdanm 19:398f4c622e1b 153 *----------------------------------------------------------------------------*/
bogdanm 19:398f4c622e1b 154
bogdanm 19:398f4c622e1b 155 /*----------------------------------------------------------------------------
bogdanm 19:398f4c622e1b 156 Define clocks
bogdanm 19:398f4c622e1b 157 *----------------------------------------------------------------------------*/
bogdanm 19:398f4c622e1b 158 #define __XTAL (12000000UL) /* Oscillator frequency */
bogdanm 19:398f4c622e1b 159 #define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */
bogdanm 19:398f4c622e1b 160 #define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */
bogdanm 19:398f4c622e1b 161
bogdanm 19:398f4c622e1b 162
bogdanm 19:398f4c622e1b 163 #define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F)
bogdanm 19:398f4c622e1b 164 #define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
bogdanm 19:398f4c622e1b 165
bogdanm 19:398f4c622e1b 166 #if (CLOCK_SETUP) /* Clock Setup */
bogdanm 19:398f4c622e1b 167 #if (__FREQSEL == 0)
bogdanm 19:398f4c622e1b 168 #define __WDT_OSC_CLK ( 0) /* undefined */
bogdanm 19:398f4c622e1b 169 #elif (__FREQSEL == 1)
bogdanm 19:398f4c622e1b 170 #define __WDT_OSC_CLK ( 500000 / __DIVSEL)
bogdanm 19:398f4c622e1b 171 #elif (__FREQSEL == 2)
bogdanm 19:398f4c622e1b 172 #define __WDT_OSC_CLK ( 800000 / __DIVSEL)
bogdanm 19:398f4c622e1b 173 #elif (__FREQSEL == 3)
bogdanm 19:398f4c622e1b 174 #define __WDT_OSC_CLK (1100000 / __DIVSEL)
bogdanm 19:398f4c622e1b 175 #elif (__FREQSEL == 4)
bogdanm 19:398f4c622e1b 176 #define __WDT_OSC_CLK (1400000 / __DIVSEL)
bogdanm 19:398f4c622e1b 177 #elif (__FREQSEL == 5)
bogdanm 19:398f4c622e1b 178 #define __WDT_OSC_CLK (1600000 / __DIVSEL)
bogdanm 19:398f4c622e1b 179 #elif (__FREQSEL == 6)
bogdanm 19:398f4c622e1b 180 #define __WDT_OSC_CLK (1800000 / __DIVSEL)
bogdanm 19:398f4c622e1b 181 #elif (__FREQSEL == 7)
bogdanm 19:398f4c622e1b 182 #define __WDT_OSC_CLK (2000000 / __DIVSEL)
bogdanm 19:398f4c622e1b 183 #elif (__FREQSEL == 8)
bogdanm 19:398f4c622e1b 184 #define __WDT_OSC_CLK (2200000 / __DIVSEL)
bogdanm 19:398f4c622e1b 185 #elif (__FREQSEL == 9)
bogdanm 19:398f4c622e1b 186 #define __WDT_OSC_CLK (2400000 / __DIVSEL)
bogdanm 19:398f4c622e1b 187 #elif (__FREQSEL == 10)
bogdanm 19:398f4c622e1b 188 #define __WDT_OSC_CLK (2600000 / __DIVSEL)
bogdanm 19:398f4c622e1b 189 #elif (__FREQSEL == 11)
bogdanm 19:398f4c622e1b 190 #define __WDT_OSC_CLK (2700000 / __DIVSEL)
bogdanm 19:398f4c622e1b 191 #elif (__FREQSEL == 12)
bogdanm 19:398f4c622e1b 192 #define __WDT_OSC_CLK (2900000 / __DIVSEL)
bogdanm 19:398f4c622e1b 193 #elif (__FREQSEL == 13)
bogdanm 19:398f4c622e1b 194 #define __WDT_OSC_CLK (3100000 / __DIVSEL)
bogdanm 19:398f4c622e1b 195 #elif (__FREQSEL == 14)
bogdanm 19:398f4c622e1b 196 #define __WDT_OSC_CLK (3200000 / __DIVSEL)
bogdanm 19:398f4c622e1b 197 #else
bogdanm 19:398f4c622e1b 198 #define __WDT_OSC_CLK (3400000 / __DIVSEL)
bogdanm 19:398f4c622e1b 199 #endif
bogdanm 19:398f4c622e1b 200
bogdanm 19:398f4c622e1b 201 /* sys_pllclkin calculation */
bogdanm 19:398f4c622e1b 202 #if ((SYSPLLCLKSEL_Val & 0x03) == 0)
bogdanm 19:398f4c622e1b 203 #define __SYS_PLLCLKIN (__IRC_OSC_CLK)
bogdanm 19:398f4c622e1b 204 #elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
bogdanm 19:398f4c622e1b 205 #define __SYS_PLLCLKIN (__SYS_OSC_CLK)
bogdanm 19:398f4c622e1b 206 #else
bogdanm 19:398f4c622e1b 207 #define __SYS_PLLCLKIN (0)
bogdanm 19:398f4c622e1b 208 #endif
bogdanm 19:398f4c622e1b 209
bogdanm 19:398f4c622e1b 210 #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
bogdanm 19:398f4c622e1b 211
bogdanm 19:398f4c622e1b 212 /* main clock calculation */
bogdanm 19:398f4c622e1b 213 #if ((MAINCLKSEL_Val & 0x03) == 0)
bogdanm 19:398f4c622e1b 214 #define __MAIN_CLOCK (__IRC_OSC_CLK)
bogdanm 19:398f4c622e1b 215 #elif ((MAINCLKSEL_Val & 0x03) == 1)
bogdanm 19:398f4c622e1b 216 #define __MAIN_CLOCK (__SYS_PLLCLKIN)
bogdanm 19:398f4c622e1b 217 #elif ((MAINCLKSEL_Val & 0x03) == 2)
bogdanm 19:398f4c622e1b 218 #if (__FREQSEL == 0)
bogdanm 19:398f4c622e1b 219 #error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!"
bogdanm 19:398f4c622e1b 220 #else
bogdanm 19:398f4c622e1b 221 #define __MAIN_CLOCK (__WDT_OSC_CLK)
bogdanm 19:398f4c622e1b 222 #endif
bogdanm 19:398f4c622e1b 223 #elif ((MAINCLKSEL_Val & 0x03) == 3)
bogdanm 19:398f4c622e1b 224 #define __MAIN_CLOCK (__SYS_PLLCLKOUT)
bogdanm 19:398f4c622e1b 225 #else
bogdanm 19:398f4c622e1b 226 #define __MAIN_CLOCK (0)
bogdanm 19:398f4c622e1b 227 #endif
bogdanm 19:398f4c622e1b 228
bogdanm 19:398f4c622e1b 229 #define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
bogdanm 19:398f4c622e1b 230
bogdanm 19:398f4c622e1b 231 #else
bogdanm 19:398f4c622e1b 232 #define __SYSTEM_CLOCK (__IRC_OSC_CLK)
bogdanm 19:398f4c622e1b 233 #endif // CLOCK_SETUP
bogdanm 19:398f4c622e1b 234
bogdanm 19:398f4c622e1b 235
bogdanm 19:398f4c622e1b 236 /*----------------------------------------------------------------------------
bogdanm 19:398f4c622e1b 237 Clock Variable definitions
bogdanm 19:398f4c622e1b 238 *----------------------------------------------------------------------------*/
bogdanm 19:398f4c622e1b 239 uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
bogdanm 19:398f4c622e1b 240
bogdanm 19:398f4c622e1b 241
bogdanm 19:398f4c622e1b 242 /*----------------------------------------------------------------------------
bogdanm 19:398f4c622e1b 243 Clock functions
bogdanm 19:398f4c622e1b 244 *----------------------------------------------------------------------------*/
bogdanm 19:398f4c622e1b 245 void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
bogdanm 19:398f4c622e1b 246 {
bogdanm 19:398f4c622e1b 247 uint32_t wdt_osc = 0;
bogdanm 19:398f4c622e1b 248
bogdanm 19:398f4c622e1b 249 /* Determine clock frequency according to clock register values */
bogdanm 19:398f4c622e1b 250 switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
bogdanm 19:398f4c622e1b 251 case 0: wdt_osc = 0; break;
bogdanm 19:398f4c622e1b 252 case 1: wdt_osc = 500000; break;
bogdanm 19:398f4c622e1b 253 case 2: wdt_osc = 800000; break;
bogdanm 19:398f4c622e1b 254 case 3: wdt_osc = 1100000; break;
bogdanm 19:398f4c622e1b 255 case 4: wdt_osc = 1400000; break;
bogdanm 19:398f4c622e1b 256 case 5: wdt_osc = 1600000; break;
bogdanm 19:398f4c622e1b 257 case 6: wdt_osc = 1800000; break;
bogdanm 19:398f4c622e1b 258 case 7: wdt_osc = 2000000; break;
bogdanm 19:398f4c622e1b 259 case 8: wdt_osc = 2200000; break;
bogdanm 19:398f4c622e1b 260 case 9: wdt_osc = 2400000; break;
bogdanm 19:398f4c622e1b 261 case 10: wdt_osc = 2600000; break;
bogdanm 19:398f4c622e1b 262 case 11: wdt_osc = 2700000; break;
bogdanm 19:398f4c622e1b 263 case 12: wdt_osc = 2900000; break;
bogdanm 19:398f4c622e1b 264 case 13: wdt_osc = 3100000; break;
bogdanm 19:398f4c622e1b 265 case 14: wdt_osc = 3200000; break;
bogdanm 19:398f4c622e1b 266 case 15: wdt_osc = 3400000; break;
bogdanm 19:398f4c622e1b 267 }
bogdanm 19:398f4c622e1b 268 wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
bogdanm 19:398f4c622e1b 269
bogdanm 19:398f4c622e1b 270 switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
bogdanm 19:398f4c622e1b 271 case 0: /* Internal RC oscillator */
bogdanm 19:398f4c622e1b 272 SystemCoreClock = __IRC_OSC_CLK;
bogdanm 19:398f4c622e1b 273 break;
bogdanm 19:398f4c622e1b 274 case 1: /* Input Clock to System PLL */
bogdanm 19:398f4c622e1b 275 switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
bogdanm 19:398f4c622e1b 276 case 0: /* Internal RC oscillator */
bogdanm 19:398f4c622e1b 277 SystemCoreClock = __IRC_OSC_CLK;
bogdanm 19:398f4c622e1b 278 break;
bogdanm 19:398f4c622e1b 279 case 1: /* System oscillator */
bogdanm 19:398f4c622e1b 280 SystemCoreClock = __SYS_OSC_CLK;
bogdanm 19:398f4c622e1b 281 break;
bogdanm 19:398f4c622e1b 282 case 2: /* Reserved */
bogdanm 19:398f4c622e1b 283 case 3: /* Reserved */
bogdanm 19:398f4c622e1b 284 SystemCoreClock = 0;
bogdanm 19:398f4c622e1b 285 break;
bogdanm 19:398f4c622e1b 286 }
bogdanm 19:398f4c622e1b 287 break;
bogdanm 19:398f4c622e1b 288 case 2: /* WDT Oscillator */
bogdanm 19:398f4c622e1b 289 SystemCoreClock = wdt_osc;
bogdanm 19:398f4c622e1b 290 break;
bogdanm 19:398f4c622e1b 291 case 3: /* System PLL Clock Out */
bogdanm 19:398f4c622e1b 292 switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
bogdanm 19:398f4c622e1b 293 case 0: /* Internal RC oscillator */
bogdanm 19:398f4c622e1b 294 if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
bogdanm 19:398f4c622e1b 295 SystemCoreClock = __IRC_OSC_CLK;
bogdanm 19:398f4c622e1b 296 } else {
bogdanm 19:398f4c622e1b 297 SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
bogdanm 19:398f4c622e1b 298 }
bogdanm 19:398f4c622e1b 299 break;
bogdanm 19:398f4c622e1b 300 case 1: /* System oscillator */
bogdanm 19:398f4c622e1b 301 if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
bogdanm 19:398f4c622e1b 302 SystemCoreClock = __SYS_OSC_CLK;
bogdanm 19:398f4c622e1b 303 } else {
bogdanm 19:398f4c622e1b 304 SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
bogdanm 19:398f4c622e1b 305 }
bogdanm 19:398f4c622e1b 306 break;
bogdanm 19:398f4c622e1b 307 case 2: /* Reserved */
bogdanm 19:398f4c622e1b 308 case 3: /* Reserved */
bogdanm 19:398f4c622e1b 309 SystemCoreClock = 0;
bogdanm 19:398f4c622e1b 310 break;
bogdanm 19:398f4c622e1b 311 }
bogdanm 19:398f4c622e1b 312 break;
bogdanm 19:398f4c622e1b 313 }
bogdanm 19:398f4c622e1b 314
bogdanm 19:398f4c622e1b 315 SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
bogdanm 19:398f4c622e1b 316
bogdanm 19:398f4c622e1b 317 }
bogdanm 19:398f4c622e1b 318
bogdanm 19:398f4c622e1b 319 /**
bogdanm 19:398f4c622e1b 320 * Initialize the system
bogdanm 19:398f4c622e1b 321 *
bogdanm 19:398f4c622e1b 322 * @param none
bogdanm 19:398f4c622e1b 323 * @return none
bogdanm 19:398f4c622e1b 324 *
bogdanm 19:398f4c622e1b 325 * @brief Setup the microcontroller system.
bogdanm 19:398f4c622e1b 326 * Initialize the System.
bogdanm 19:398f4c622e1b 327 */
bogdanm 19:398f4c622e1b 328 void SystemInit (void) {
bogdanm 19:398f4c622e1b 329 volatile uint32_t i;
bogdanm 19:398f4c622e1b 330
bogdanm 19:398f4c622e1b 331 #if (CLOCK_SETUP) /* Clock Setup */
bogdanm 19:398f4c622e1b 332
bogdanm 19:398f4c622e1b 333 #if ((SYSPLLCLKSEL_Val & 0x03) == 1)
bogdanm 19:398f4c622e1b 334 LPC_SYSCON->PDRUNCFG &= ~(1 << 5); /* Power-up System Osc */
bogdanm 19:398f4c622e1b 335 LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
bogdanm 19:398f4c622e1b 336 for (i = 0; i < 200; i++) __NOP();
bogdanm 19:398f4c622e1b 337 #endif
bogdanm 19:398f4c622e1b 338
bogdanm 19:398f4c622e1b 339 LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */
bogdanm 19:398f4c622e1b 340 LPC_SYSCON->SYSPLLCLKUEN = 0x01; /* Update Clock Source */
bogdanm 19:398f4c622e1b 341 LPC_SYSCON->SYSPLLCLKUEN = 0x00; /* Toggle Update Register */
bogdanm 19:398f4c622e1b 342 LPC_SYSCON->SYSPLLCLKUEN = 0x01;
bogdanm 19:398f4c622e1b 343 while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */
bogdanm 19:398f4c622e1b 344 #if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */
bogdanm 19:398f4c622e1b 345 LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
bogdanm 19:398f4c622e1b 346 LPC_SYSCON->PDRUNCFG &= ~(1 << 7); /* Power-up SYSPLL */
bogdanm 19:398f4c622e1b 347 while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */
bogdanm 19:398f4c622e1b 348 #endif
bogdanm 19:398f4c622e1b 349
bogdanm 19:398f4c622e1b 350 #if (((MAINCLKSEL_Val & 0x03) == 2) )
bogdanm 19:398f4c622e1b 351 LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val;
bogdanm 19:398f4c622e1b 352 LPC_SYSCON->PDRUNCFG &= ~(1 << 6); /* Power-up WDT Clock */
bogdanm 19:398f4c622e1b 353 for (i = 0; i < 200; i++) __NOP();
bogdanm 19:398f4c622e1b 354 #endif
bogdanm 19:398f4c622e1b 355
bogdanm 19:398f4c622e1b 356 LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */
bogdanm 19:398f4c622e1b 357 LPC_SYSCON->MAINCLKUEN = 0x01; /* Update MCLK Clock Source */
bogdanm 19:398f4c622e1b 358 LPC_SYSCON->MAINCLKUEN = 0x00; /* Toggle Update Register */
bogdanm 19:398f4c622e1b 359 LPC_SYSCON->MAINCLKUEN = 0x01;
bogdanm 19:398f4c622e1b 360 while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */
bogdanm 19:398f4c622e1b 361
bogdanm 19:398f4c622e1b 362 LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;
bogdanm 19:398f4c622e1b 363 #endif
bogdanm 19:398f4c622e1b 364 /* System clock to the IOCON needs to be enabled or
bogdanm 19:398f4c622e1b 365 most of the I/O related peripherals won't work. */
bogdanm 19:398f4c622e1b 366 LPC_SYSCON->SYSAHBCLKCTRL |= (1<<16);
bogdanm 19:398f4c622e1b 367 }